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Differential D82571

[ARM] Allow the usub_sat and ssub_sat intrinsics to be tail predicated
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Authored by samtebbs on Jun 25 2020, 9:00 AM.

Details

Reviewers
samparker
SjoerdMeijer
dmgreen
olista01
simon_tatham
t.p.northover
Commits
rG66fa31399992: [ARM] Allow the usub_sat and ssub_sat intrinsics to be tail predicated
Summary

This patch stops the usub_sat and ssub_sat intrinsics from blocking tail predication.

Diff Detail

Event Timeline

samtebbs created this revision.Jun 25 2020, 9:00 AM
Herald added subscribers: llvm-commits, danielkiss, hiraditya, kristof.beyls. · View Herald TranscriptJun 25 2020, 9:00 AM
Harbormaster failed remote builds in B61758: Diff 273395!Jun 25 2020, 9:09 AM
dmgreen accepted this revision.Jun 25 2020, 9:18 AM

Oh yeah. LGTM

This revision is now accepted and ready to land.Jun 25 2020, 9:18 AM
Closed by commit rG66fa31399992: [ARM] Allow the usub_sat and ssub_sat intrinsics to be tail predicated (authored by Samuel Tebbs <samteb02@e124480.cambridge.arm.com>). · Explain WhyJun 30 2020, 9:44 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
2 lines
test/
CodeGen/
Thumb2/
LowOverheadLoops/
109 lines

Diff 274521

llvm/lib/Target/ARM/MVETailPredication.cpp

Show First 20 Lines • Show All 239 Lines • ▼ Show 20 Lines for (auto &I : *BB) {
continue; continue;
switch (Int->getIntrinsicID()) { switch (Int->getIntrinsicID()) {
case Intrinsic::get_active_lane_mask: case Intrinsic::get_active_lane_mask:
ActiveLaneMask = true; ActiveLaneMask = true;
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case Intrinsic::sadd_sat: case Intrinsic::sadd_sat:
case Intrinsic::uadd_sat: case Intrinsic::uadd_sat:
case Intrinsic::ssub_sat:
case Intrinsic::usub_sat:
continue; continue;
case Intrinsic::fma: case Intrinsic::fma:
case Intrinsic::trunc: case Intrinsic::trunc:
case Intrinsic::rint: case Intrinsic::rint:
case Intrinsic::round: case Intrinsic::round:
case Intrinsic::floor: case Intrinsic::floor:
case Intrinsic::ceil: case Intrinsic::ceil:
if (ST->hasMVEFloatOps()) if (ST->hasMVEFloatOps())
▲ Show 20 Lines • Show All 345 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-sub-sat.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs -disable-mve-tail-predication=false -o - %s | FileCheck %s
define arm_aapcs_vfpcc void @usub_sat(i16* noalias nocapture readonly %pSrcA, i16* noalias nocapture readonly %pSrcB, i16* noalias nocapture %pDst, i32 %blockSize) {
; CHECK-LABEL: usub_sat:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: it eq
; CHECK-NEXT: popeq {r7, pc}
; CHECK-NEXT: dlstp.16 lr, r3
; CHECK-NEXT: .LBB0_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrh.u16 q0, [r1], #16
; CHECK-NEXT: vldrh.u16 q1, [r0], #16
; CHECK-NEXT: vqsub.u16 q0, q1, q0
; CHECK-NEXT: vstrh.16 q0, [r2], #16
; CHECK-NEXT: letp lr, .LBB0_1
; CHECK-NEXT: @ %bb.2: @ %while.end
; CHECK-NEXT: pop {r7, pc}
entry:
%cmp7 = icmp eq i32 %blockSize, 0
br i1 %cmp7, label %while.end, label %vector.ph
vector.ph: ; preds = %entry
%n.rnd.up = add i32 %blockSize, 7
%n.vec = and i32 %n.rnd.up, -8
%trip.count.minus.1 = add i32 %blockSize, -1
br label %vector.body
vector.body: ; preds = %vector.body, %vector.ph
%index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
%next.gep = getelementptr i16, i16* %pSrcA, i32 %index
%next.gep20 = getelementptr i16, i16* %pDst, i32 %index
%next.gep21 = getelementptr i16, i16* %pSrcB, i32 %index
%active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %trip.count.minus.1)
%0 = bitcast i16* %next.gep to <8 x i16>*
%wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %0, i32 2, <8 x i1> %active.lane.mask, <8 x i16> undef)
%1 = bitcast i16* %next.gep21 to <8 x i16>*
%wide.masked.load24 = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %1, i32 2, <8 x i1> %active.lane.mask, <8 x i16> undef)
%2 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %wide.masked.load, <8 x i16> %wide.masked.load24)
%3 = bitcast i16* %next.gep20 to <8 x i16>*
call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %2, <8 x i16>* %3, i32 2, <8 x i1> %active.lane.mask)
%index.next = add i32 %index, 8
%4 = icmp eq i32 %index.next, %n.vec
br i1 %4, label %while.end, label %vector.body
while.end: ; preds = %vector.body, %entry
ret void
}
define arm_aapcs_vfpcc void @ssub_sat(i16* noalias nocapture readonly %pSrcA, i16* noalias nocapture readonly %pSrcB, i16* noalias nocapture %pDst, i32 %blockSize) {
; CHECK-LABEL: ssub_sat:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: it eq
; CHECK-NEXT: popeq {r7, pc}
; CHECK-NEXT: dlstp.16 lr, r3
; CHECK-NEXT: .LBB1_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrh.u16 q0, [r1], #16
; CHECK-NEXT: vldrh.u16 q1, [r0], #16
; CHECK-NEXT: vqsub.s16 q0, q1, q0
; CHECK-NEXT: vstrh.16 q0, [r2], #16
; CHECK-NEXT: letp lr, .LBB1_1
; CHECK-NEXT: @ %bb.2: @ %while.end
; CHECK-NEXT: pop {r7, pc}
entry:
%cmp7 = icmp eq i32 %blockSize, 0
br i1 %cmp7, label %while.end, label %vector.ph
vector.ph: ; preds = %entry
%n.rnd.up = add i32 %blockSize, 7
%n.vec = and i32 %n.rnd.up, -8
%trip.count.minus.1 = add i32 %blockSize, -1
br label %vector.body
vector.body: ; preds = %vector.body, %vector.ph
%index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
%next.gep = getelementptr i16, i16* %pSrcA, i32 %index
%next.gep20 = getelementptr i16, i16* %pDst, i32 %index
%next.gep21 = getelementptr i16, i16* %pSrcB, i32 %index
%active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %trip.count.minus.1)
%0 = bitcast i16* %next.gep to <8 x i16>*
%wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %0, i32 2, <8 x i1> %active.lane.mask, <8 x i16> undef)
%1 = bitcast i16* %next.gep21 to <8 x i16>*
%wide.masked.load24 = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %1, i32 2, <8 x i1> %active.lane.mask, <8 x i16> undef)
%2 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %wide.masked.load, <8 x i16> %wide.masked.load24)
%3 = bitcast i16* %next.gep20 to <8 x i16>*
call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %2, <8 x i16>* %3, i32 2, <8 x i1> %active.lane.mask)
%index.next = add i32 %index, 8
%4 = icmp eq i32 %index.next, %n.vec
br i1 %4, label %while.end, label %vector.body
while.end: ; preds = %vector.body, %entry
ret void
}
declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)
declare <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>*, i32 immarg, <8 x i1>, <8 x i16>)
declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>)
declare <8 x i16> @llvm.usub.sat.v8i16(<8 x i16>, <8 x i16>)
declare void @llvm.masked.store.v8i16.p0v8i16(<8 x i16>, <8 x i16>*, i32 immarg, <8 x i1>)