[MLIR][NFC] Adopt variadic isa<>

[rriddle]

mlir/lib/Transforms/PipelineDataTransfer.cpp

51

Why did you add additional parentheses?

[jurahul]

mlir/lib/Transforms/PipelineDataTransfer.cpp

51

I should have anticipated this question. I get compile failures otherwise. See https://stackoverflow.com/questions/35957357/getting-too-many-arguments-provided-to-function-like-macro-invocation-compile-er

[rriddle]

mlir/lib/Transforms/PipelineDataTransfer.cpp

51

Fun. SGTM.

mlir/lib/Analysis/AffineAnalysis.cpp

 /// Gathers dependence components for dependences between all ops in loop nest
 /// rooted at 'forOp' at loop depths in range [1, maxLoopDepth].
 void mlir::getDependenceComponents(
     AffineForOp forOp, unsigned maxLoopDepth,
     std::vector<SmallVector<DependenceComponent, 2>> *depCompsVec) {
   // Collect all load and store ops in loop nest rooted at 'forOp'.
   SmallVector<Operation *, 8> loadAndStoreOpInsts;
   forOp.getOperation()->walk([&](Operation *opInst) {
-    if (isa<AffineReadOpInterface>(opInst) ||
-        isa<AffineWriteOpInterface>(opInst))
+    if (isa<AffineReadOpInterface, AffineWriteOpInterface>(opInst))
       loadAndStoreOpInsts.push_back(opInst);
   });
 
   unsigned numOps = loadAndStoreOpInsts.size();
   for (unsigned d = 1; d <= maxLoopDepth; ++d) {
     for (unsigned i = 0; i < numOps; ++i) {
       auto *srcOpInst = loadAndStoreOpInsts[i];
       MemRefAccess srcAccess(srcOpInst);

mlir/lib/Analysis/LoopAnalysis.cpp

isVectorizableLoopBodyWithOpCond(AffineForOp loop,
   SmallVector<NestedMatch, 8> conditionalsMatched;
   conditionals.match(forOp, &conditionalsMatched);
   if (!conditionalsMatched.empty()) {
     return false;
   }
 
   // No vectorization across unknown regions.
   auto regions = matcher::Op([](Operation &op) -> bool {
-    return op.getNumRegions() != 0 &&
-           !(isa<AffineIfOp>(op) || isa<AffineForOp>(op));
+    return op.getNumRegions() != 0 && !isa<AffineIfOp, AffineForOp>(op);
   });
   SmallVector<NestedMatch, 8> regionsMatched;
   regions.match(forOp, &regionsMatched);
   if (!regionsMatched.empty()) {
     return false;
   }
 
   SmallVector<NestedMatch, 8> vectorTransfersMatched;

mlir/lib/Analysis/NestedMatcher.cpp

NestedPattern For(ArrayRef<NestedPattern> nested) {
   return NestedPattern(nested, isAffineForOp);
 }
 NestedPattern For(FilterFunctionType filter, ArrayRef<NestedPattern> nested) {
   return NestedPattern(
       nested, [=](Operation &op) { return isAffineForOp(op) && filter(op); });
 }
 
 bool isLoadOrStore(Operation &op) {
-  return isa<AffineLoadOp>(op) || isa<AffineStoreOp>(op);
+  return isa<AffineLoadOp, AffineStoreOp>(op);
 }
 
 } // end namespace matcher
 } // end namespace mlir

mlir/lib/Analysis/SliceAnalysis.cpp

 }
 
 static void getBackwardSliceImpl(Operation *op,
                                  SetVector<Operation *> *backwardSlice,
                                  TransitiveFilter filter) {
   if (!op)
     return;
 
-  assert((op->getNumRegions() == 0 || isa<AffineForOp>(op) ||
-          isa<scf::ForOp>(op)) &&
+  assert((op->getNumRegions() == 0 || isa<AffineForOp, scf::ForOp>(op)) &&
          "unexpected generic op with regions");
 
   // Evaluate whether we should keep this def.
   // This is useful in particular to implement scoping; i.e. return the
   // transitive forwardSlice in the current scope.
   if (!filter(op)) {
     return;
   }

mlir/lib/Analysis/Utils.cpp

 // region:  {memref = %A, write = false, {%i <= m0 <= %i + 7} }
 // The last field is a 2-d FlatAffineConstraints symbolic in %i.
 //
 // TODO(bondhugula): extend this to any other memref dereferencing ops
 // (dma_start, dma_wait).
 LogicalResult MemRefRegion::compute(Operation *op, unsigned loopDepth,
                                     ComputationSliceState *sliceState,
                                     bool addMemRefDimBounds) {
-  assert((isa<AffineReadOpInterface>(op) || isa<AffineWriteOpInterface>(op)) &&
+  assert((isa<AffineReadOpInterface, AffineWriteOpInterface>(op)) &&
          "affine read/write op expected");
 
   MemRefAccess access(op);
   memref = access.memref;
   write = access.isStore();
 
   unsigned rank = access.getRank();
 

mlir/lib/Dialect/Affine/IR/AffineOps.cpp

if (!value.getType().isIndex())
     return false;
 
   if (auto *defOp = value.getDefiningOp())
     return isValidDim(value, getAffineScope(defOp));
 
   // This value has to be a block argument for an op that has the
   // `AffineScope` trait or for an affine.for or affine.parallel.
   auto *parentOp = value.cast<BlockArgument>().getOwner()->getParentOp();
-  return parentOp &&
-         (parentOp->hasTrait<OpTrait::AffineScope>() ||
-          isa<AffineForOp>(parentOp) || isa<AffineParallelOp>(parentOp));
+  return parentOp && (parentOp->hasTrait<OpTrait::AffineScope>() ||
+                      isa<AffineForOp, AffineParallelOp>(parentOp));
 }
 
 // Value can be used as a dimension id iff it meets one of the following
 // conditions:
 // *) It is valid as a symbol.
 // *) It is an induction variable.
 // *) It is the result of an affine apply operation with dimension id operands.
 bool mlir::isValidDim(Value value, Region *region) {
   // The value must be an index type.
   if (!value.getType().isIndex())
     return false;
 
   // All valid symbols are okay.
   if (isValidSymbol(value, region))
     return true;
 
   auto *op = value.getDefiningOp();
   if (!op) {
     // This value has to be a block argument for an affine.for or an
     // affine.parallel.
     auto *parentOp = value.cast<BlockArgument>().getOwner()->getParentOp();
-    return isa<AffineForOp>(parentOp) || isa<AffineParallelOp>(parentOp);
+    return isa<AffineForOp, AffineParallelOp>(parentOp);
   }
 
   // Affine apply operation is ok if all of its operands are ok.
   if (auto applyOp = dyn_cast<AffineApplyOp>(op))
     return applyOp.isValidDim(region);
   // The dim op is okay if its operand memref/tensor is defined at the top
   // level.
   if (auto dimOp = dyn_cast<DimOp>(op))

mlir/lib/Dialect/Affine/Transforms/AffineDataCopyGeneration.cpp

AffineDataCopyGeneration::runOnBlock(Block *block,
   // moment; we do a check later and report an error with location info.
   // TODO(bondhugula): An 'affine.if' operation is being treated similar to an
   // operation. 'affine.if''s could have 'affine.for's in them;
   // treat them separately.
 
   // Get to the first load, store, or for op (that is not a copy nest itself).
   auto curBegin =
       std::find_if(block->begin(), block->end(), [&](Operation &op) {
-        return (isa<AffineLoadOp>(op) || isa<AffineStoreOp>(op) ||
-                isa<AffineForOp>(op)) &&
+        return isa<AffineLoadOp, AffineStoreOp, AffineForOp>(op) &&
                copyNests.count(&op) == 0;
       });
 
   // Create [begin, end) ranges.
   auto it = curBegin;
   while (it != block->end()) {
     AffineForOp forOp;
     // If you hit a non-copy for loop, we will split there.
if ((forOp = dyn_cast<AffineForOp>(&*it)) && copyNests.count(forOp) == 0) {
         // Inner loop copies have their own scope - we don't thus update
         // consumed capacity. The footprint check above guarantees this inner
         // loop's footprint fits.
         affineDataCopyGenerate(/*begin=*/it, /*end=*/std::next(it), copyOptions,
                                /*filterMemRef=*/llvm::None, copyNests);
       }
       // Get to the next load or store op after 'forOp'.
       curBegin = std::find_if(std::next(it), block->end(), [&](Operation &op) {
-        return (isa<AffineLoadOp>(op) || isa<AffineStoreOp>(op) ||
-                isa<AffineForOp>(op)) &&
+        return isa<AffineLoadOp, AffineStoreOp, AffineForOp>(op) &&
                copyNests.count(&op) == 0;
       });
       it = curBegin;
     } else {
       assert(copyNests.count(&*it) == 0 &&
              "all copy nests generated should have been skipped above");
       // We simply include this op in the current range and continue for more.
       ++it;

mlir/lib/Dialect/Affine/Transforms/AffineLoopInvariantCodeMotion.cpp

 
 static bool
 areAllOpsInTheBlockListInvariant(Region &blockList, Value indVar,
                                  SmallPtrSetImpl<Operation *> &definedOps,
                                  SmallPtrSetImpl<Operation *> &opsToHoist);
 
 static bool isMemRefDereferencingOp(Operation &op) {
   // TODO(asabne): Support DMA Ops.
-  if (isa<AffineLoadOp>(op) || isa<AffineStoreOp>(op)) {
-    return true;
-  }
-  return false;
+  return isa<AffineLoadOp, AffineStoreOp>(op);
 }
 
 // Returns true if the individual op is loop invariant.
 bool isOpLoopInvariant(Operation &op, Value indVar,
                        SmallPtrSetImpl<Operation *> &definedOps,
                        SmallPtrSetImpl<Operation *> &opsToHoist) {
   LLVM_DEBUG(llvm::dbgs() << "iterating on op: " << op;);
 

mlir/lib/Dialect/Affine/Transforms/SimplifyAffineStructures.cpp

for (auto attr : op->getAttrs()) {
       if (auto mapAttr = attr.second.dyn_cast<AffineMapAttr>())
         simplifyAndUpdateAttribute(op, attr.first, mapAttr);
       else if (auto setAttr = attr.second.dyn_cast<IntegerSetAttr>())
         simplifyAndUpdateAttribute(op, attr.first, setAttr);
     }
 
     // The simplification of the attribute will likely simplify the op. Try to
     // fold / apply canonicalization patterns when we have affine dialect ops.
-    if (isa<AffineForOp>(op) || isa<AffineIfOp>(op) || isa<AffineApplyOp>(op))
+    if (isa<AffineForOp, AffineIfOp, AffineApplyOp>(op))
       applyOpPatternsAndFold(op, patterns);
   });
 
   // Turn memrefs' non-identity layouts maps into ones with identity. Collect
   // alloc ops first and then process since normalizeMemRef replaces/erases ops
   // during memref rewriting.
   SmallVector<AllocOp, 4> allocOps;
   func.walk([&](AllocOp op) { allocOps.push_back(op); });
   for (auto allocOp : allocOps) {
     normalizeMemRef(allocOp);
   }
 }

mlir/lib/Dialect/Affine/Transforms/SuperVectorize.cpp

makePatterns(const DenseSet<Operation *> &parallelLoops, int vectorRank,
   default: {
     return std::vector<NestedPattern>();
   }
   }
 }
 
 static NestedPattern &vectorTransferPattern() {
   static auto pattern = matcher::Op([](Operation &op) {
-    return isa<vector::TransferReadOp>(op) || isa<vector::TransferWriteOp>(op);
+    return isa<vector::TransferReadOp, vector::TransferWriteOp>(op);
   });
   return pattern;
 }
 
 namespace {
 
 /// Base state for the vectorize pass.
 /// Command line arguments are preempted by non-empty pass arguments.

mlir/lib/Dialect/GPU/Transforms/KernelOutlining.cpp

static void injectGpuIndexOperations(Location loc, Region &launchFuncOpBody,
   createForAllDimensions<gpu::BlockDimOp>(builder, loc, indexOps);
   // Replace the leading 12 function args with the respective thread/block index
   // operations. Iterate backwards since args are erased and indices change.
   for (auto indexOp : enumerate(indexOps))
     map.map(firstBlock.getArgument(indexOp.index()), indexOp.value());
 }
 
 static bool isSinkingBeneficiary(Operation *op) {
-  return isa<ConstantOp>(op) || isa<DimOp>(op);
+  return isa<ConstantOp, DimOp>(op);
 }
 
 LogicalResult mlir::sinkOperationsIntoLaunchOp(gpu::LaunchOp launchOp) {
   Region &launchOpBody = launchOp.body();
 
   // Identify uses from values defined outside of the scope of the launch
   // operation.
   llvm::SetVector<Value> sinkCandidates;

mlir/lib/Dialect/Linalg/Transforms/Hoisting.cpp

 
 using llvm::dbgs;
 
 void mlir::linalg::hoistViewAllocOps(FuncOp func) {
   bool changed = true;
   while (changed) {
     changed = false;
     func.walk([&changed](Operation *op) {
-      if (!isa<AllocOp>(op) && !isa<AllocaOp>(op) && !isa<DeallocOp>(op))
+      if (!isa<AllocOp, AllocaOp, DeallocOp>(op))
         return;
 
       LLVM_DEBUG(DBGS() << "Candidate for hoisting: " << *op << "\n");
       auto loop = dyn_cast<scf::ForOp>(op->getParentOp());
       LLVM_DEBUG(DBGS() << "Parent op: " << *op->getParentOp() << "\n");
 
       // Only hoist out of immediately enclosing scf::ForOp.
       if (!loop)
func.walk([&changed](Operation *op) {
 
       // If alloc has other uses than ViewLikeOp and DeallocOp don't hoist.
       Value v;
       if (op->getNumResults() > 0) {
         assert(op->getNumResults() == 1 && "Unexpected multi-result alloc");
         v = op->getResult(0);
       }
       if (v && !llvm::all_of(v.getUses(), [&](OpOperand &operand) {
-            return isa<ViewLikeOpInterface>(operand.getOwner()) ||
-                   isa<DeallocOp>(operand.getOwner());
+            return isa<ViewLikeOpInterface, DeallocOp>(operand.getOwner());
           })) {
         LLVM_DEBUG(DBGS() << "Found non view-like or dealloc use: bail\n");
         return;
       }
 
       // Move AllocOp before the loop.
-      if (isa<AllocOp>(op) || isa<AllocaOp>(op))
+      if (isa<AllocOp, AllocaOp>(op))
         loop.moveOutOfLoop({op});
       else // Move DeallocOp outside of the loop.
         op->moveAfter(loop);
       changed = true;
     });
   }
 }
 

mlir/lib/Dialect/Linalg/Transforms/Interchange.cpp

 using namespace mlir;
 using namespace mlir::linalg;
 
 LogicalResult mlir::linalg::interchangeGenericLinalgOpPrecondition(
     Operation *op, ArrayRef<unsigned> interchangeVector) {
   if (interchangeVector.empty())
     return failure();
   // Transformation applies to generic ops only.
-  if (!isa<GenericOp>(op) && !isa<IndexedGenericOp>(op))
+  if (!isa<GenericOp, IndexedGenericOp>(op))
     return failure();
   LinalgOp linOp = cast<LinalgOp>(op);
   // Transformation applies to buffers only.
   if (!linOp.hasBufferSemantics())
     return failure();
   // Permutation must be applicable.
   if (linOp.getIndexingMap(0).getNumInputs() != interchangeVector.size())
     return failure();

mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp

LogicalResult mlir::linalg::vectorizeLinalgOpPrecondition(Operation *op) {
   auto linalgOp = cast<linalg::LinalgOp>(op);
   // All types must be static shape to go to vector.
   for (Value operand : linalgOp.getInputsAndOutputBuffers())
     if (!operand.getType().cast<ShapedType>().hasStaticShape())
       return failure();
   for (Type outputTensorType : linalgOp.getOutputTensorTypes())
     if (!outputTensorType.cast<ShapedType>().hasStaticShape())
       return failure();
-  if (isa<linalg::MatmulOp>(op) || isa<linalg::FillOp>(op))
+  if (isa<linalg::MatmulOp, linalg::FillOp>(op))
     return success();
 
   auto genericOp = dyn_cast<linalg::GenericOp>(op);
   if (!genericOp || !::isRowMajorMatmul(genericOp))
     return failure();
 
   // TODO(ntv): non-identity layout.
   auto isStaticMemRefWithIdentityLayout = [](Value v) {

mlir/lib/Dialect/SCF/SCF.cpp

 //===----------------------------------------------------------------------===//
 // YieldOp
 //===----------------------------------------------------------------------===//
 static LogicalResult verify(YieldOp op) {
   auto parentOp = op.getParentOp();
   auto results = parentOp->getResults();
   auto operands = op.getOperands();
 
-  if (isa<IfOp>(parentOp) || isa<ForOp>(parentOp)) {
+  if (isa<IfOp, ForOp>(parentOp)) {
     if (parentOp->getNumResults() != op.getNumOperands())
       return op.emitOpError() << "parent of yield must have same number of "
                                  "results as the yield operands";
     for (auto e : llvm::zip(results, operands)) {
       if (std::get<0>(e).getType() != std::get<1>(e).getType())
         return op.emitOpError()
                << "types mismatch between yield op and its parent";
     }

mlir/lib/Dialect/SPIRV/SPIRVDialect.cpp

 //===----------------------------------------------------------------------===//
 // InlinerInterface
 //===----------------------------------------------------------------------===//
 
 /// Returns true if the given region contains spv.Return or spv.ReturnValue ops.
 static inline bool containsReturn(Region &region) {
   return llvm::any_of(region, [](Block &block) {
     Operation *terminator = block.getTerminator();
-    return isa<spirv::ReturnOp>(terminator) ||
-           isa<spirv::ReturnValueOp>(terminator);
+    return isa<spirv::ReturnOp, spirv::ReturnValueOp>(terminator);
   });
 }
 
 namespace {
 /// This class defines the interface for inlining within the SPIR-V dialect.
 struct SPIRVInlinerInterface : public DialectInlinerInterface {
   using DialectInlinerInterface::DialectInlinerInterface;
 
   /// Returns true if the given region 'src' can be inlined into the region
   /// 'dest' that is attached to an operation registered to the current dialect.
   bool isLegalToInline(Region *dest, Region *src,
                        BlockAndValueMapping &) const final {
     // Return true here when inlining into spv.func, spv.selection, and
     // spv.loop operations.
     auto *op = dest->getParentOp();
-    return isa<spirv::FuncOp>(op) || isa<spirv::SelectionOp>(op) ||
-           isa<spirv::LoopOp>(op);
+    return isa<spirv::FuncOp, spirv::SelectionOp, spirv::LoopOp>(op);
   }
 
   /// Returns true if the given operation 'op', that is registered to this
   /// dialect, can be inlined into the region 'dest' that is attached to an
   /// operation registered to the current dialect.
   bool isLegalToInline(Operation *op, Region *dest,
                        BlockAndValueMapping &) const final {
     // TODO(antiagainst): Enable inlining structured control flows with return.
-    if ((isa<spirv::SelectionOp>(op) || isa<spirv::LoopOp>(op)) &&
+    if ((isa<spirv::SelectionOp, spirv::LoopOp>(op)) &&
         containsReturn(op->getRegion(0)))
       return false;
     // TODO(antiagainst): we need to filter OpKill here to avoid inlining it to
     // a loop continue construct:
     // https://github.com/KhronosGroup/SPIRV-Headers/issues/86
     // However OpKill is fragment shader specific and we don't support it yet.
     return true;
   }

mlir/lib/Interfaces/SideEffectInterfaces.cpp

 /// Include the definitions of the side effect interfaces.
 #include "mlir/Interfaces/SideEffectInterfaces.cpp.inc"
 
 //===----------------------------------------------------------------------===//
 // MemoryEffects
 //===----------------------------------------------------------------------===//
 
 bool MemoryEffects::Effect::classof(const SideEffects::Effect *effect) {
-  return isa<Allocate>(effect) || isa<Free>(effect) || isa<Read>(effect) ||
-         isa<Write>(effect);
+  return isa<Allocate, Free, Read, Write>(effect);
 }
 
 //===----------------------------------------------------------------------===//
 // SideEffect Utilities
 //===----------------------------------------------------------------------===//
 
 bool mlir::isOpTriviallyDead(Operation *op) {
   return op->use_empty() && wouldOpBeTriviallyDead(op);

mlir/lib/Pass/IRPrinting.cpp

private:
   /// being operated on in a pass. This field is only used when the
   /// configuration asked for change detection.
   DenseMap<Pass *, OperationFingerPrint> beforePassFingerPrints;
 };
 } // end anonymous namespace
 
 /// Returns true if the given pass is hidden from IR printing.
 static bool isHiddenPass(Pass *pass) {
-  return isa<OpToOpPassAdaptor>(pass) || isa<VerifierPass>(pass);
+  return isa<OpToOpPassAdaptor, VerifierPass>(pass);
 }
 
 static void printIR(Operation *op, bool printModuleScope, raw_ostream &out,
                     OpPrintingFlags flags) {
   // Check to see if we are printing the top-level module.
   auto module = dyn_cast<ModuleOp>(op);
   if (module && !op->getBlock())
     return module.print(out << "\n", flags);

mlir/lib/TableGen/Dialect.cpp

std::string tblgen::Dialect::getCppClassName() const {
   std::string cppName = def->getName().str();
   llvm::erase_if(cppName, [](char c) { return c == '_'; });
   return cppName;
 }
 
 static StringRef getAsStringOrEmpty(const llvm::Record &record,
                                     StringRef fieldName) {
   if (auto valueInit = record.getValueInit(fieldName)) {
-    if (llvm::isa<llvm::CodeInit>(valueInit) ||
-        llvm::isa<llvm::StringInit>(valueInit))
+    if (llvm::isa<llvm::CodeInit, llvm::StringInit>(valueInit))
       return record.getValueAsString(fieldName);
   }
   return "";
 }
 
 StringRef tblgen::Dialect::getSummary() const {
   return getAsStringOrEmpty(*def, "summary");
 }

mlir/lib/TableGen/Operator.cpp

 }
 
 StringRef tblgen::Operator::getSummary() const {
   return def.getValueAsString("summary");
 }
 
 bool tblgen::Operator::hasAssemblyFormat() const {
   auto *valueInit = def.getValueInit("assemblyFormat");
-  return isa<llvm::CodeInit>(valueInit) || isa<llvm::StringInit>(valueInit);
+  return isa<llvm::CodeInit, llvm::StringInit>(valueInit);
 }
 
 StringRef tblgen::Operator::getAssemblyFormat() const {
   return TypeSwitch<llvm::Init *, StringRef>(def.getValueInit("assemblyFormat"))
       .Case<llvm::StringInit, llvm::CodeInit>(
           [&](auto *init) { return init->getValue(); });
 }
 

mlir/lib/TableGen/Pattern.cpp

bool tblgen::DagLeaf::isConstantAttr() const {
   return isSubClassOf("ConstantAttr");
 }
 
 bool tblgen::DagLeaf::isEnumAttrCase() const {
   return isSubClassOf("EnumAttrCaseInfo");
 }
 
 bool tblgen::DagLeaf::isStringAttr() const {
-  return isa<llvm::StringInit>(def) || isa<llvm::CodeInit>(def);
+  return isa<llvm::StringInit, llvm::CodeInit>(def);
 }
 
 tblgen::Constraint tblgen::DagLeaf::getAsConstraint() const {
   assert((isOperandMatcher() || isAttrMatcher()) &&
          "the DAG leaf must be operand or attribute");
   return Constraint(cast<llvm::DefInit>(def)->getDef());
 }
 

mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp

private:
   /// The current module being created.
   ModuleOp module;
   /// The entry block of the current function being processed.
   Block *currentEntryBlock;
 
   /// Globals are inserted before the first function, if any.
   Block::iterator getGlobalInsertPt() {
     auto i = module.getBody()->begin();
-    while (!isa<LLVMFuncOp>(i) && !isa<ModuleTerminatorOp>(i))
+    while (!isa<LLVMFuncOp, ModuleTerminatorOp>(i))
       ++i;
     return i;
   }
 
   /// Functions are always inserted before the module terminator.
   Block::iterator getFuncInsertPt() {
     return std::prev(module.getBody()->end());
   }

mlir/lib/Target/LLVMIR/ModuleTranslation.cpp

if (auto *arrayTy = dyn_cast<llvm::ArrayType>(llvmType)) {
       auto *vectorTy = cast<llvm::VectorType>(llvmType);
       elementType = vectorTy->getElementType();
       numElements = vectorTy->getNumElements();
     }
     // Splat value is a scalar. Extract it only if the element type is not
     // another sequence type. The recursion terminates because each step removes
     // one outer sequential type.
     bool elementTypeSequential =
-        isa<llvm::ArrayType>(elementType) || isa<llvm::VectorType>(elementType);
+        isa<llvm::ArrayType, llvm::VectorType>(elementType);
     llvm::Constant *child = getLLVMConstant(
         elementType,
         elementTypeSequential ? splatAttr : splatAttr.getSplatValue(), loc);
     if (!child)
       return nullptr;
     if (llvmType->isVectorTy())
       return llvm::ConstantVector::getSplat(
           llvm::ElementCount(numElements, /*Scalable=*/false), child);

mlir/lib/Transforms/LoopFusion.cpp

 mlir::createLoopFusionPass(unsigned fastMemorySpace,
                            uint64_t localBufSizeThreshold, bool maximalFusion) {
   return std::make_unique<LoopFusion>(fastMemorySpace, localBufSizeThreshold,
                                       maximalFusion);
 }
 
 // TODO(b/117228571) Replace when this is modeled through side-effects/op traits
 static bool isMemRefDereferencingOp(Operation &op) {
-  if (isa<AffineReadOpInterface>(op) || isa<AffineWriteOpInterface>(op) ||
-      isa<AffineDmaStartOp>(op) || isa<AffineDmaWaitOp>(op))
-    return true;
-  return false;
+  return isa<AffineReadOpInterface, AffineWriteOpInterface, AffineDmaStartOp,
+             AffineDmaWaitOp>(op);
 }
 
 namespace {
 
 // LoopNestStateCollector walks loop nests and collects load and store
 // operations, and whether or not an IfInst was encountered in the loop nest.
 struct LoopNestStateCollector {
   SmallVector<AffineForOp, 4> forOps;

mlir/lib/Transforms/MemRefDataFlowOpt.cpp

void MemRefDataFlowOpt::runOnFunction() {
   for (auto memref : memrefsToErase) {
     // If the memref hasn't been alloc'ed in this function, skip.
     Operation *defOp = memref.getDefiningOp();
     if (!defOp || !isa<AllocOp>(defOp))
       // TODO(mlir-team): if the memref was returned by a 'call' operation, we
       // could still erase it if the call had no side-effects.
       continue;
     if (llvm::any_of(memref.getUsers(), [&](Operation *ownerOp) {
-          return (!isa<AffineStoreOp>(ownerOp) && !isa<DeallocOp>(ownerOp));
+          return !isa<AffineStoreOp, DeallocOp>(ownerOp);
         }))
       continue;
 
     // Erase all stores, the dealloc, and the alloc on the memref.
     for (auto *user : llvm::make_early_inc_range(memref.getUsers()))
       user->erase();
     defOp->erase();
   }
 }

mlir/lib/Transforms/PipelineDataTransfer.cpp

 std::unique_ptr<OperationPass<FuncOp>> mlir::createPipelineDataTransferPass() {
   return std::make_unique<PipelineDataTransfer>();
 }
 
 // Returns the position of the tag memref operand given a DMA operation.
 // Temporary utility: will be replaced when DmaStart/DmaFinish abstract op's are
 // added.  TODO(b/117228571)
 static unsigned getTagMemRefPos(Operation &dmaOp) {
-  assert(isa<AffineDmaStartOp>(dmaOp) || isa<AffineDmaWaitOp>(dmaOp));
+  assert((isa<AffineDmaStartOp, AffineDmaWaitOp>(dmaOp)));
   if (auto dmaStartOp = dyn_cast<AffineDmaStartOp>(dmaOp)) {
     return dmaStartOp.getTagMemRefOperandIndex();
   }
   // First operand for a dma finish operation.
   return 0;
 }
 
 /// Doubles the buffer of the supplied memref on the specified 'affine.for'

mlir/lib/Transforms/Utils/LoopFusionUtils.cpp

static Operation *getLastDependentOpInRange(Operation *opA, Operation *opB) {
   // *) 'opX' and 'opB' access the same memref and at least one of the accesses
   //    is a store.
   // *) 'opX' produces an SSA Value which is used by 'opB'.
   Operation *lastDepOp = nullptr;
   for (Block::reverse_iterator it = std::next(Block::reverse_iterator(opB));
        it != Block::reverse_iterator(opA); ++it) {
     Operation *opX = &(*it);
     opX->walk([&](Operation *op) {
-      if (isa<AffineReadOpInterface>(op) || isa<AffineWriteOpInterface>(op)) {
+      if (isa<AffineReadOpInterface, AffineWriteOpInterface>(op)) {
         if (isDependentLoadOrStoreOp(op, values)) {
           lastDepOp = opX;
           return WalkResult::interrupt();
         }
         return WalkResult::advance();
       }
       for (auto value : op->getResults()) {
         for (auto user : value.getUsers()) {

 
 // Gathers all load and store ops in loop nest rooted at 'forOp' into
 // 'loadAndStoreOps'.
 static bool
 gatherLoadsAndStores(AffineForOp forOp,
                      SmallVectorImpl<Operation *> &loadAndStoreOps) {
   bool hasIfOp = false;
   forOp.walk([&](Operation *op) {
-    if (isa<AffineReadOpInterface>(op) || isa<AffineWriteOpInterface>(op))
+    if (isa<AffineReadOpInterface, AffineWriteOpInterface>(op))
       loadAndStoreOps.push_back(op);
     else if (isa<AffineIfOp>(op))
       hasIfOp = true;
   });
   return !hasIfOp;
 }
 
 // TODO(andydavis) Prevent fusion of loop nests with side-effecting operations.

mlir/lib/Transforms/Utils/Utils.cpp

 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/TypeSwitch.h"
 using namespace mlir;
 
 /// Return true if this operation dereferences one or more memref's.
 // Temporary utility: will be replaced when this is modeled through
 // side-effects/op traits. TODO(b/117228571)
 static bool isMemRefDereferencingOp(Operation &op) {
-  if (isa<AffineReadOpInterface>(op) || isa<AffineWriteOpInterface>(op) ||
-      isa<AffineDmaStartOp>(op) || isa<AffineDmaWaitOp>(op))
-    return true;
-  return false;
+  return isa<AffineReadOpInterface, AffineWriteOpInterface, AffineDmaStartOp,
+             AffineDmaWaitOp>(op);
 }
 
 /// Return the AffineMapAttr associated with memory 'op' on 'memref'.
 static NamedAttribute getAffineMapAttrForMemRef(Operation *op, Value memref) {
   return TypeSwitch<Operation *, NamedAttribute>(op)
       .Case<AffineDmaStartOp, AffineReadOpInterface, AffinePrefetchOp,
             AffineWriteOpInterface, AffineDmaWaitOp>(
           [=](auto op) { return op.getAffineMapAttrForMemRef(memref); });

mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp

static std::string replaceAllSubstrs(std::string str, const std::string &match,
   return str;
 }
 
 // Returns whether the record has a value of the given name that can be returned
 // via getValueAsString.
 static inline bool hasStringAttribute(const Record &record,
                                       StringRef fieldName) {
   auto valueInit = record.getValueInit(fieldName);
-  return isa<CodeInit>(valueInit) || isa<StringInit>(valueInit);
+  return isa<CodeInit, StringInit>(valueInit);
 }
 
 static std::string getArgumentName(const Operator &op, int index) {
   const auto &operand = op.getOperand(index);
   if (!operand.name.empty())
     return std::string(operand.name);
   else
     return std::string(formatv("{0}_{1}", generatedArgName, index));