[PowerPC] Only make copies of registers on stack in variadic function when va_start is called

[lkail]

Summary

On PPC64, for a variadic function, if va_start is not called, it won't access any variadic argument on stack, thus we can save stores of registers used to pass arguments.

[steven.zhang]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

4295

Please add some necessary comments here to prove that, we don't need these stores if there is no va_start.

[lkail]

Address @steven.zhang 's comment.

[steven.zhang]

The change makes sense to me. Please hold on for several days in case others have comments.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

SDValue PPCTargetLowering::LowerFormalArguments_64SVR4(
   // taking the difference between two stack areas will result in an aligned
   // stack.
   MinReservedArea =
       EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
   FuncInfo->setMinReservedArea(MinReservedArea);
 
   // If the function takes variable number of arguments, make a frame index for
   // the start of the first vararg value... for expansion of llvm.va_start.
-  if (isVarArg) {
+  if (isVarArg && MFI.hasVAStart()) {
     int Depth = ArgOffset;
 
     FuncInfo->setVarArgsFrameIndex(
       MFI.CreateFixedObject(PtrByteSize, Depth, true));
     SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
 
     // If this function is vararg, store any remaining integer argument regs
     // to their spots on the stack so that they may be loaded by dereferencing
     // the result of va_next.
     for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
          GPR_idx < Num_GPR_Regs; ++GPR_idx) {
       unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
       SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
       SDValue Store =
           DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
       MemOps.push_back(Store);
-      // Increment the address by four for the next argument to store
+      // Increment the address by PtrByteSize for the next argument to store.
       SDValue PtrOff = DAG.getConstant(PtrByteSize, dl, PtrVT);
       FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
     }
   }
 
   if (!MemOps.empty())
     Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
 

llvm/test/CodeGen/PowerPC/legalize-vaarg.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ;RUN: llc < %s --mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec | FileCheck %s -check-prefix=BE
 ;RUN: llc < %s --mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec | FileCheck %s -check-prefix=LE
 
 define <8 x i32> @test_large_vec_vaarg(i32 %n, ...) {
 ; BE-LABEL: test_large_vec_vaarg:
 ; BE:       # %bb.0:
 ; BE-NEXT:    ld 3, -8(1)
-; BE-NEXT:    std 4, 56(1)
-; BE-NEXT:    std 5, 64(1)
-; BE-NEXT:    std 6, 72(1)
-; BE-NEXT:    std 7, 80(1)
-; BE-NEXT:    std 8, 88(1)
-; BE-NEXT:    std 9, 96(1)
-; BE-NEXT:    std 10, 104(1)
 ; BE-NEXT:    addi 3, 3, 15
 ; BE-NEXT:    rldicr 3, 3, 0, 59
 ; BE-NEXT:    addi 4, 3, 16
 ; BE-NEXT:    addi 5, 3, 31
 ; BE-NEXT:    std 4, -8(1)
 ; BE-NEXT:    rldicr 4, 5, 0, 59
 ; BE-NEXT:    lvx 2, 0, 3
 ; BE-NEXT:    addi 3, 4, 16
 ; BE-NEXT:    std 3, -8(1)
 ; BE-NEXT:    lvx 3, 0, 4
 ; BE-NEXT:    blr
 ;
 ; LE-LABEL: test_large_vec_vaarg:
 ; LE:       # %bb.0:
 ; LE-NEXT:    ld 3, -8(1)
-; LE-NEXT:    std 4, 40(1)
-; LE-NEXT:    std 5, 48(1)
-; LE-NEXT:    std 6, 56(1)
-; LE-NEXT:    std 7, 64(1)
 ; LE-NEXT:    addi 3, 3, 15
 ; LE-NEXT:    rldicr 3, 3, 0, 59
-; LE-NEXT:    std 8, 72(1)
-; LE-NEXT:    std 9, 80(1)
-; LE-NEXT:    std 10, 88(1)
 ; LE-NEXT:    addi 4, 3, 31
 ; LE-NEXT:    addi 5, 3, 16
 ; LE-NEXT:    rldicr 4, 4, 0, 59
 ; LE-NEXT:    std 5, -8(1)
 ; LE-NEXT:    addi 5, 4, 16
 ; LE-NEXT:    lvx 2, 0, 3
 ; LE-NEXT:    std 5, -8(1)
 ; LE-NEXT:    lvx 3, 0, 4
 ; LE-NEXT:    blr
   %args = alloca i8*, align 4
   %x = va_arg i8** %args, <8 x i32>
   ret <8 x i32> %x
 }

llvm/test/CodeGen/PowerPC/ppc64-varargs.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs -mtriple=powerpc64 \
 ; RUN:   < %s | FileCheck --check-prefix=BE %s
 ; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs -mtriple=powerpc64le \
 ; RUN:   < %s | FileCheck --check-prefix=LE %s
 
 define i32 @f(...) nounwind {
 ; BE-LABEL: f:
 ; BE:       # %bb.0: # %entry
-; BE-NEXT:    mr r11, r3
 ; BE-NEXT:    li r3, 0
-; BE-NEXT:    std r11, 48(r1)
-; BE-NEXT:    std r4, 56(r1)
-; BE-NEXT:    std r5, 64(r1)
-; BE-NEXT:    std r6, 72(r1)
-; BE-NEXT:    std r7, 80(r1)
-; BE-NEXT:    std r8, 88(r1)
-; BE-NEXT:    std r9, 96(r1)
-; BE-NEXT:    std r10, 104(r1)
 ; BE-NEXT:    blr
 ;
 ; LE-LABEL: f:
 ; LE:       # %bb.0: # %entry
-; LE-NEXT:    std r3, 32(r1)
 ; LE-NEXT:    li r3, 0
-; LE-NEXT:    std r4, 40(r1)
-; LE-NEXT:    std r5, 48(r1)
-; LE-NEXT:    std r6, 56(r1)
-; LE-NEXT:    std r7, 64(r1)
-; LE-NEXT:    std r8, 72(r1)
-; LE-NEXT:    std r9, 80(r1)
-; LE-NEXT:    std r10, 88(r1)
 ; LE-NEXT:    blr
 entry:
   ret i32 0
 }
 
 define i32 @f1(...) nounwind {
 ; BE-LABEL: f1:
 ; BE:       # %bb.0: # %entry