[PowerPC][PCRelative] Thread Local Storage Support for Initial Exec

[kamaub]

Summary

This patch is the initial support for the Intial Exec Thread Local
Local Storage model to produce code sequence and relocations correct
to the ABI for the model when using PC relative memory operations.

[stefanp]

Overall this seems fine. I have a number of comments but they are mostly minor.

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp

333

nit:
isPCRel -> IsPCRel

llvm/lib/Target/PowerPC/PPC.h

114

Why 32 and not 16?

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

3037

nit:
isPCRel -> IsPCRel

3041

The only difference between the two global addresses is the flags that are added in the PCRel case.
It may be clearer to write it as: (ignore my spacing)

    SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
	​                                     isPCRel ? (PPCII::MO_PCREL_FLAG | PPCII::MO_TPREL_FLAG)  : 0)

3045

Same thing here:

SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
    isPCRel ? PPCII::MO_TLS | PPCII::MO_PCREL_FLAG : PPCII::MO_TLS)

llvm/test/CodeGen/PowerPC/pcrel-tls-inital-exec.ll

6

nit:
Should probably use pwr10 instead of future in both places.

[NeHuang]

Overall looks good to me.
Would be better to add tests for assembly reader check in llvm/test/MC/PowerPC

llvm/lib/Target/PowerPC/PPC.h

114

16 is used for MO_TLSGD_FLAG = 16 in https://reviews.llvm.org/D82315
We originally planned to set 32 here for the convenience of code merging.

[kamaub]

Addressing review comments.

[kamaub]

• Rebasing patch to be dependant on D82315 - TLS Support for General Dynamic.
• Adding Combination flag MO_GOT_TPREL_PCREL_FLAG to more explicitly define the king that will output @got@tprel@pcrel relocation.
• Adding assembly reader test cases by request of reviewer for more robust testing.
• Minor format changes.

[stefanp]

I think this patch is getting close. A couple more comments from me.

llvm/lib/Target/PowerPC/PPCMCInstLower.cpp

90

I would move the setting of VK_PPC_TLS_PCREL into the switch above.
The PPCII::MO_TLS is not really a flag and with the current code we set RefKind = MCSymbolRefExpr::VK_PPC_TLS and then we set it to MCSymbolRefExpr::VK_PPC_TLS_PCREL afterward.

llvm/test/CodeGen/PowerPC/pcrel-tls-initial-exec.ll

6 ↗

(On Diff #273768)

nit:
Use mcpu=pwr10

[kamaub]

• rearranging conditional logic for emitting MCSymbolRefExpr::VK_PPC_TLS_PCREL so that it is less redundant and reads better.
• replacing future with pwr10 in test cases and adding better comments.

[NeHuang]

Overall looks fine to me, but of course please wait to hear from Stefan and Nemanja.
Some nits added.

llvm/lib/Target/PowerPC/PPC.h

113

nit: use MO_GOT_FLAG | MO_TPREL_FLAG | MO_PCREL_FLAG to be consistent with order in relocation name and the flag name. You can also update it for MO_GOT_TLSGD_PCREL_FLAG

llvm/test/CodeGen/PowerPC/pcrel-tls-initial-exec.ll

13 ↗

(On Diff #276031)

nit: change to InitialExecAddressLoad to better describe the case

23 ↗

(On Diff #276031)

Please add a comment here for the one-byte displacement. Same for line 39.

29 ↗

(On Diff #276031)

nit: change to InitialExecValueLoad

llvm/test/MC/PowerPC/pcrel-tls-initial-exec-address-load-reloc.s

7 ↗

(On Diff #276031)

R_PPC64_TLS (with one-byte displacement)

15 ↗

(On Diff #276031)

• You can only keep necessary assembly in the test and remove the comments.
• Rename the function.

InitialExecAddressLoad:
  pld 3, x@got@tprel@pcrel(0), 1
  add 3, 3, x@tls@pcrel
  blr

llvm/test/MC/PowerPC/pcrel-tls-initial-exec-value-load-reloc.s

7 ↗

(On Diff #276031)

ditto

21 ↗

(On Diff #276031)

ditto

[kamaub]

Rebasing and addressing review comments:

• rebased on the updated version of D82315
• updated test cases according to reviews
• updated llvm-readobj run lines in test cases to reflect interface change

[kamaub]

Rebasing and updating patch to use TLS enablement option.

[stefanp]

Couple of nits.
LGTM

llvm/test/MC/PowerPC/pcrel-tls-initial-exec-address-load-reloc.s

18 ↗

(On Diff #283895)

nit:
You can delete the comment (# @InitialExec) here and just leave the label.

llvm/test/MC/PowerPC/pcrel-tls-initial-exec-value-load-reloc.s

18 ↗

(On Diff #283895)

nit:
You can delete the comment and just leave the label.

llvm/include/llvm/BinaryFormat/ELFRelocs/PowerPC64.def

 #undef R_PPC64_ADDR16_HIGHA
 #undef R_PPC64_TPREL16_HIGH
 #undef R_PPC64_TPREL16_HIGHA
 #undef R_PPC64_DTPREL16_HIGH
 #undef R_PPC64_DTPREL16_HIGHA
 #undef R_PPC64_REL24_NOTOC
 #undef R_PPC64_PCREL34
 #undef R_PPC64_GOT_PCREL34
+#undef R_PPC64_GOT_TPREL_PCREL64
 #undef R_PPC64_IRELATIVE
 #undef R_PPC64_REL16
 #undef R_PPC64_REL16_LO
 #undef R_PPC64_REL16_HI
 #undef R_PPC64_REL16_HA
 
 ELF_RELOC(R_PPC64_NONE,                 0)
 ELF_RELOC(R_PPC64_ADDR32,               1)

 ELF_RELOC(R_PPC64_ADDR16_HIGHA,         111)
 ELF_RELOC(R_PPC64_TPREL16_HIGH,         112)
 ELF_RELOC(R_PPC64_TPREL16_HIGHA,        113)
 ELF_RELOC(R_PPC64_DTPREL16_HIGH,        114)
 ELF_RELOC(R_PPC64_DTPREL16_HIGHA,       115)
 ELF_RELOC(R_PPC64_REL24_NOTOC,          116)
 ELF_RELOC(R_PPC64_PCREL34,              132)
 ELF_RELOC(R_PPC64_GOT_PCREL34,          133)
+ELF_RELOC(R_PPC64_GOT_TPREL_PCREL34,    150)
 ELF_RELOC(R_PPC64_IRELATIVE,            248)
 ELF_RELOC(R_PPC64_REL16,                249)
 ELF_RELOC(R_PPC64_REL16_LO,             250)
 ELF_RELOC(R_PPC64_REL16_HI,             251)
 ELF_RELOC(R_PPC64_REL16_HA,             252)

llvm/include/llvm/MC/MCExpr.h

enum VariantKind : uint16_t {
     VK_PPC_GOT_TLSGD_HI,    // symbol@got@tlsgd@h
     VK_PPC_GOT_TLSGD_HA,    // symbol@got@tlsgd@ha
     VK_PPC_TLSGD,           // symbol@tlsgd
     VK_PPC_GOT_TLSLD,       // symbol@got@tlsld
     VK_PPC_GOT_TLSLD_LO,    // symbol@got@tlsld@l
     VK_PPC_GOT_TLSLD_HI,    // symbol@got@tlsld@h
     VK_PPC_GOT_TLSLD_HA,    // symbol@got@tlsld@ha
     VK_PPC_GOT_PCREL,       // symbol@got@pcrel
+    VK_PPC_GOT_TPREL_PCREL, // symbol@got@tprel@pcrel
+    VK_PPC_TLS_PCREL,       // symbol@tls@pcrel
     VK_PPC_TLSLD,           // symbol@tlsld
     VK_PPC_LOCAL,           // symbol@local
     VK_PPC_NOTOC,           // symbol@notoc
 
     VK_COFF_IMGREL32, // symbol@imgrel (image-relative)
 
     VK_Hexagon_LO16,
     VK_Hexagon_HI16,

llvm/lib/MC/MCExpr.cpp

StringRef MCSymbolRefExpr::getVariantKindName(VariantKind Kind) {
   case VK_PPC_GOT_TLSGD_HA: return "got@tlsgd@ha";
   case VK_PPC_TLSGD: return "tlsgd";
   case VK_PPC_GOT_TLSLD: return "got@tlsld";
   case VK_PPC_GOT_TLSLD_LO: return "got@tlsld@l";
   case VK_PPC_GOT_TLSLD_HI: return "got@tlsld@h";
   case VK_PPC_GOT_TLSLD_HA: return "got@tlsld@ha";
   case VK_PPC_GOT_PCREL:
     return "got@pcrel";
+  case VK_PPC_GOT_TPREL_PCREL:
+    return "got@tprel@pcrel";
+  case VK_PPC_TLS_PCREL:
+    return "tls@pcrel";
   case VK_PPC_TLSLD: return "tlsld";
   case VK_PPC_LOCAL: return "local";
   case VK_PPC_NOTOC: return "notoc";
   case VK_COFF_IMGREL32: return "IMGREL";
   case VK_Hexagon_LO16: return "LO16";
   case VK_Hexagon_HI16: return "HI16";
   case VK_Hexagon_GPREL: return "GPREL";
   case VK_Hexagon_GD_GOT: return "GDGOT";
StringRef MCSymbolRefExpr::getVariantKindName(VariantKind Kind) {
   case VK_AMDGPU_ABS32_HI: return "abs32@hi";
   }
   llvm_unreachable("Invalid variant kind");
 }
 
 MCSymbolRefExpr::VariantKind
 MCSymbolRefExpr::getVariantKindForName(StringRef Name) {
   return StringSwitch<VariantKind>(Name.lower())
       .Case("dtprel", VK_DTPREL)
       .Case("dtpoff", VK_DTPOFF)
       .Case("got", VK_GOT)
       .Case("gotoff", VK_GOTOFF)
       .Case("gotrel", VK_GOTREL)
       .Case("pcrel", VK_PCREL)
       .Case("gotpcrel", VK_GOTPCREL)
       .Case("gottpoff", VK_GOTTPOFF)
       .Case("indntpoff", VK_INDNTPOFF)
       .Case("ntpoff", VK_NTPOFF)
       .Case("gotntpoff", VK_GOTNTPOFF)
       .Case("plt", VK_PLT)
       .Case("tlscall", VK_TLSCALL)
       .Case("tlsdesc", VK_TLSDESC)
       .Case("tlsgd", VK_TLSGD)
       .Case("tlsld", VK_TLSLD)
       .Case("tlsldm", VK_TLSLDM)
       .Case("tpoff", VK_TPOFF)
       .Case("tprel", VK_TPREL)
       .Case("tlvp", VK_TLVP)
       .Case("tlvppage", VK_TLVPPAGE)
       .Case("tlvppageoff", VK_TLVPPAGEOFF)
       .Case("page", VK_PAGE)
       .Case("pageoff", VK_PAGEOFF)
       .Case("gotpage", VK_GOTPAGE)
       .Case("gotpageoff", VK_GOTPAGEOFF)
       .Case("imgrel", VK_COFF_IMGREL32)
       .Case("secrel32", VK_SECREL)
       .Case("size", VK_SIZE)
       .Case("abs8", VK_X86_ABS8)
       .Case("l", VK_PPC_LO)
       .Case("h", VK_PPC_HI)
       .Case("ha", VK_PPC_HA)
       .Case("high", VK_PPC_HIGH)
       .Case("higha", VK_PPC_HIGHA)
       .Case("higher", VK_PPC_HIGHER)
       .Case("highera", VK_PPC_HIGHERA)
       .Case("highest", VK_PPC_HIGHEST)
       .Case("highesta", VK_PPC_HIGHESTA)
       .Case("got@l", VK_PPC_GOT_LO)
       .Case("got@h", VK_PPC_GOT_HI)
       .Case("got@ha", VK_PPC_GOT_HA)
       .Case("local", VK_PPC_LOCAL)
       .Case("tocbase", VK_PPC_TOCBASE)
       .Case("toc", VK_PPC_TOC)
       .Case("toc@l", VK_PPC_TOC_LO)
       .Case("toc@h", VK_PPC_TOC_HI)
       .Case("toc@ha", VK_PPC_TOC_HA)
       .Case("u", VK_PPC_U)
       .Case("l", VK_PPC_L)
       .Case("tls", VK_PPC_TLS)
       .Case("dtpmod", VK_PPC_DTPMOD)
       .Case("tprel@l", VK_PPC_TPREL_LO)
       .Case("tprel@h", VK_PPC_TPREL_HI)
       .Case("tprel@ha", VK_PPC_TPREL_HA)
       .Case("tprel@high", VK_PPC_TPREL_HIGH)
       .Case("tprel@higha", VK_PPC_TPREL_HIGHA)
       .Case("tprel@higher", VK_PPC_TPREL_HIGHER)
       .Case("tprel@highera", VK_PPC_TPREL_HIGHERA)
       .Case("tprel@highest", VK_PPC_TPREL_HIGHEST)
       .Case("tprel@highesta", VK_PPC_TPREL_HIGHESTA)
       .Case("dtprel@l", VK_PPC_DTPREL_LO)
       .Case("dtprel@h", VK_PPC_DTPREL_HI)
       .Case("dtprel@ha", VK_PPC_DTPREL_HA)
       .Case("dtprel@high", VK_PPC_DTPREL_HIGH)
       .Case("dtprel@higha", VK_PPC_DTPREL_HIGHA)
       .Case("dtprel@higher", VK_PPC_DTPREL_HIGHER)
       .Case("dtprel@highera", VK_PPC_DTPREL_HIGHERA)
       .Case("dtprel@highest", VK_PPC_DTPREL_HIGHEST)
       .Case("dtprel@highesta", VK_PPC_DTPREL_HIGHESTA)
       .Case("got@tprel", VK_PPC_GOT_TPREL)
       .Case("got@tprel@l", VK_PPC_GOT_TPREL_LO)
       .Case("got@tprel@h", VK_PPC_GOT_TPREL_HI)
       .Case("got@tprel@ha", VK_PPC_GOT_TPREL_HA)
       .Case("got@dtprel", VK_PPC_GOT_DTPREL)
       .Case("got@dtprel@l", VK_PPC_GOT_DTPREL_LO)
       .Case("got@dtprel@h", VK_PPC_GOT_DTPREL_HI)
       .Case("got@dtprel@ha", VK_PPC_GOT_DTPREL_HA)
       .Case("got@tlsgd", VK_PPC_GOT_TLSGD)
       .Case("got@tlsgd@l", VK_PPC_GOT_TLSGD_LO)
       .Case("got@tlsgd@h", VK_PPC_GOT_TLSGD_HI)
       .Case("got@tlsgd@ha", VK_PPC_GOT_TLSGD_HA)
       .Case("got@tlsld", VK_PPC_GOT_TLSLD)
       .Case("got@tlsld@l", VK_PPC_GOT_TLSLD_LO)
       .Case("got@tlsld@h", VK_PPC_GOT_TLSLD_HI)
       .Case("got@tlsld@ha", VK_PPC_GOT_TLSLD_HA)
       .Case("got@pcrel", VK_PPC_GOT_PCREL)
+      .Case("got@tprel@pcrel", VK_PPC_GOT_TPREL_PCREL)
+      .Case("tls@pcrel", VK_PPC_TLS_PCREL)
       .Case("notoc", VK_PPC_NOTOC)
       .Case("gdgot", VK_Hexagon_GD_GOT)
       .Case("gdplt", VK_Hexagon_GD_PLT)
       .Case("iegot", VK_Hexagon_IE_GOT)
       .Case("ie", VK_Hexagon_IE)
       .Case("ldgot", VK_Hexagon_LD_GOT)
       .Case("ldplt", VK_Hexagon_LD_PLT)
       .Case("none", VK_ARM_NONE)
       .Case("got_prel", VK_ARM_GOT_PREL)
       .Case("target1", VK_ARM_TARGET1)
       .Case("target2", VK_ARM_TARGET2)
       .Case("prel31", VK_ARM_PREL31)
       .Case("sbrel", VK_ARM_SBREL)
       .Case("tlsldo", VK_ARM_TLSLDO)
       .Case("lo8", VK_AVR_LO8)
       .Case("hi8", VK_AVR_HI8)
       .Case("hlo8", VK_AVR_HLO8)
       .Case("typeindex", VK_WASM_TYPEINDEX)
       .Case("tbrel", VK_WASM_TBREL)
       .Case("mbrel", VK_WASM_MBREL)
       .Case("gotpcrel32@lo", VK_AMDGPU_GOTPCREL32_LO)
       .Case("gotpcrel32@hi", VK_AMDGPU_GOTPCREL32_HI)
       .Case("rel32@lo", VK_AMDGPU_REL32_LO)
       .Case("rel32@hi", VK_AMDGPU_REL32_HI)
       .Case("rel64", VK_AMDGPU_REL64)
       .Case("abs32@lo", VK_AMDGPU_ABS32_LO)
       .Case("abs32@hi", VK_AMDGPU_ABS32_HI)
       .Default(VK_Invalid);
 }
 
 void MCSymbolRefExpr::printVariantKind(raw_ostream &OS) const {
   if (useParensForSymbolVariant())
     OS << '(' << MCSymbolRefExpr::getVariantKindName(getKind()) << ')';
   else
     OS << '@' << MCSymbolRefExpr::getVariantKindName(getKind());
 }

llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp

public:
   }
 
   static std::unique_ptr<PPCOperand>
   CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
       return CreateImm(CE->getValue(), S, E, IsPPC64);
 
     if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
-      if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
+      if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS ||
+          SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS_PCREL)
         return CreateTLSReg(SRE, S, E, IsPPC64);
 
     if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) {
       int64_t Res;
       if (TE->evaluateAsConstant(Res))
         return CreateContextImm(Res, S, E, IsPPC64);
     }
 

llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp

case PPC::fixup_ppc_pcrel34:
       default:
         llvm_unreachable("Unsupported Modifier for fixup_ppc_pcrel34");
       case MCSymbolRefExpr::VK_PCREL:
         Type = ELF::R_PPC64_PCREL34;
         break;
       case MCSymbolRefExpr::VK_PPC_GOT_PCREL:
         Type = ELF::R_PPC64_GOT_PCREL34;
         break;
+      case MCSymbolRefExpr::VK_PPC_GOT_TPREL_PCREL:
+        Type = ELF::R_PPC64_GOT_TPREL_PCREL34;
+        break;
       }
       break;
     case FK_Data_4:
     case FK_PCRel_4:
       Type = ELF::R_PPC_REL32;
       break;
     case FK_Data_8:
     case FK_PCRel_8:
case PPC::fixup_ppc_nofixup:
           Type = ELF::R_PPC_TLSLD;
         break;
       case MCSymbolRefExpr::VK_PPC_TLS:
         if (is64Bit())
           Type = ELF::R_PPC64_TLS;
         else
           Type = ELF::R_PPC_TLS;
         break;
+      case MCSymbolRefExpr::VK_PPC_TLS_PCREL:
+        Type = ELF::R_PPC64_TLS;
+        break;
       }
       break;
     case FK_Data_8:
       switch (Modifier) {
       default: llvm_unreachable("Unsupported Modifier");
       case MCSymbolRefExpr::VK_PPC_TOCBASE:
         Type = ELF::R_PPC64_TOC;
         break;

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp

PPCMCCodeEmitter::getMemRI34PCRelEncoding(const MCInst &MI, unsigned OpNo,
   default:
     llvm_unreachable("Unsupported MCExpr for getMemRI34PCRelEncoding.");
   case MCExpr::SymbolRef: {
     // Relocation alone.
     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(Expr);
     (void)SRE;
     // Currently these are the only valid PCRelative Relocations.
     assert((SRE->getKind() == MCSymbolRefExpr::VK_PCREL ||
-            SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_PCREL) &&
-           "VariantKind must be VK_PCREL or VK_PPC_GOT_PCREL");
+            SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_PCREL ||
+            SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_TPREL_PCREL) &&
+           "VariantKind must be VK_PCREL or VK_PPC_GOT_PCREL or "
+           "VK_PPC_GOT_TPREL_PCREL");
     // Generate the fixup for the relocation.
     Fixups.push_back(
         MCFixup::create(0, Expr,
                         static_cast<MCFixupKind>(PPC::fixup_ppc_pcrel34)));
     // There is no offset to return so just return 0.
     return 0;
   }
   case MCExpr::Binary: {

 unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
                                        SmallVectorImpl<MCFixup> &Fixups,
                                        const MCSubtargetInfo &STI) const {
   const MCOperand &MO = MI.getOperand(OpNo);
   if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI);
 
   // Add a fixup for the TLS register, which simply provides a relocation
   // hint to the linker that this statement is part of a relocation sequence.
-  // Return the thread-pointer register's encoding.
-  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
+  // Return the thread-pointer register's encoding. Add a one byte displacement
+  // if using PC relative memops.
+  const MCExpr *Expr = MO.getExpr();
+  const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(Expr);
+  bool isPCRel = SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS_PCREL;
+  Fixups.push_back(MCFixup::create(isPCRel ? 1 : 0, Expr,
                                    (MCFixupKind)PPC::fixup_ppc_nofixup));
   const Triple &TT = STI.getTargetTriple();
   bool isPPC64 = TT.isPPC64();
   return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2);
 }
 
 unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
                                        SmallVectorImpl<MCFixup> &Fixups,
                                        const MCSubtargetInfo &STI) const {

llvm/lib/Target/PowerPC/PPC.h

enum TOF {
     /// the current instruction address(pc), e.g., var@pcrel. Fixup is VK_PCREL.
     MO_PCREL_FLAG = 4,
 
     /// MO_GOT_FLAG - If this bit is set the symbol reference is to be computed
     /// via the GOT. For example when combined with the MO_PCREL_FLAG it should
     /// produce the relocation @got@pcrel. Fixup is VK_PPC_GOT_PCREL.
     MO_GOT_FLAG = 8,
 
+    /// MO_TLSGD_FLAG - If this bit is set the symbol reference is relative to
+    /// TLS Initial Exec model. When it is combined with MO_PCREL_FLAG it
+    /// should produce the relocation @got@tprel@pcrel.
+    /// Fix up is VK_PPC_GOT_TPREL_PCREL
+    MO_TPREL_FLAG = 32,
+
     /// The next are not flags but distinct values.
     MO_ACCESS_MASK = 0xf00,
 
     /// MO_LO, MO_HA - lo16(symbol) and ha16(symbol)
     MO_LO = 1 << 8,
     MO_HA = 2 << 8,
 
     MO_TPREL_LO = 4 << 8,

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

if (Model == TLSModel::LocalExec) {
     SDValue TLSReg = is64bit ? DAG.getRegister(PPC::X13, MVT::i64)
                              : DAG.getRegister(PPC::R2, MVT::i32);
 
     SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
     return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
   }
 
   if (Model == TLSModel::InitialExec) {
-    SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
-    SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
-                                                PPCII::MO_TLS);
+    bool isPCRel = Subtarget.isUsingPCRelativeCalls();
+    SDValue TGA = isPCRel ? DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
+                                                       PPCII::MO_PCREL_FLAG |
+                                                           PPCII::MO_TPREL_FLAG)
+                          : DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
+    SDValue TGATLS =
+        isPCRel ? DAG.getTargetGlobalAddress(
+                      GV, dl, PtrVT, 0, PPCII::MO_TLS | PPCII::MO_PCREL_FLAG)
+                : DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TLS);
+    SDValue TPOffset;
+    if (isPCRel) {
+      SDValue MatPCRel = DAG.getNode(PPCISD::MAT_PCREL_ADDR, dl, PtrVT, TGA);
+      TPOffset = DAG.getLoad(MVT::i64, dl, DAG.getEntryNode(), MatPCRel,
+                             MachinePointerInfo());
+    } else {
       SDValue GOTPtr;
       if (is64bit) {
         setUsesTOCBasePtr(DAG);
         SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
-      GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
-                           PtrVT, GOTReg, TGA);
+        GOTPtr =
+            DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl, PtrVT, GOTReg, TGA);
       } else {
         if (!TM.isPositionIndependent())
           GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
         else if (picLevel == PICLevel::SmallPIC)
           GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
         else
           GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
       }
-    SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
-                                   PtrVT, TGA, GOTPtr);
+      TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl, PtrVT, TGA, GOTPtr);
+    }
     return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
   }
 
   if (Model == TLSModel::GeneralDynamic) {
     SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
     SDValue GOTPtr;
     if (is64bit) {
       setUsesTOCBasePtr(DAG);
       SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
       GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
                                    GOTReg, TGA);
     } else {

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

 
 ArrayRef<std::pair<unsigned, const char *>>
 PPCInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
   using namespace PPCII;
   static const std::pair<unsigned, const char *> TargetFlags[] = {
       {MO_PLT, "ppc-plt"},
       {MO_PIC_FLAG, "ppc-pic"},
       {MO_PCREL_FLAG, "ppc-pcrel"},
-      {MO_GOT_FLAG, "ppc-got"}};
+      {MO_GOT_FLAG, "ppc-got"},
+      {MO_TPREL_FLAG, "ppc-tprel"}};
   return makeArrayRef(TargetFlags);
 }
 
 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
 // The VSX versions have the advantage of a full 64-register target whereas
 // the FP ones have the advantage of lower latency and higher throughput. So
 // what we are after is using the faster instructions in low register pressure
 // situations and using the larger register file in high register pressure

llvm/lib/Target/PowerPC/PPCMCInstLower.cpp

static MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol,
   }
 
   if (MO.getTargetFlags() == PPCII::MO_PLT)
     RefKind = MCSymbolRefExpr::VK_PLT;
   else if (MO.getTargetFlags() == PPCII::MO_PCREL_FLAG)
     RefKind = MCSymbolRefExpr::VK_PCREL;
   else if (MO.getTargetFlags() == (PPCII::MO_PCREL_FLAG | PPCII::MO_GOT_FLAG))
     RefKind = MCSymbolRefExpr::VK_PPC_GOT_PCREL;
+  else if (MO.getTargetFlags() == (PPCII::MO_PCREL_FLAG | PPCII::MO_TPREL_FLAG))
+    RefKind = MCSymbolRefExpr::VK_PPC_GOT_TPREL_PCREL;
+  else if (MO.getTargetFlags() == (PPCII::MO_TLS | PPCII::MO_PCREL_FLAG))
+    RefKind = MCSymbolRefExpr::VK_PPC_TLS_PCREL;
 
   const MachineInstr *MI = MO.getParent();
   const MachineFunction *MF = MI->getMF();
   const Module *M = MF->getFunction().getParent();
   const PPCSubtarget *Subtarget = &(MF->getSubtarget<PPCSubtarget>());
   const TargetMachine &TM = Printer.TM;
 
   unsigned MIOpcode = MI->getOpcode();

llvm/test/CodeGen/PowerPC/pcrel-tls-inital-exec.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=future -ppc-asm-full-reg-names < %s | \
+; RUN:   FileCheck %s --check-prefix=CHECK-S
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=future -ppc-asm-full-reg-names --filetype=obj < %s | \
+; RUN:   llvm-objdump --mcpu=future -dr - | FileCheck %s --check-prefix=CHECK-O
+
+@x = external thread_local global i32, align 4
+
+define i32* @InitialExec() {
+; CHECK-S-LABEL: InitialExec:
+; CHECK-S:       # %bb.0: # %entry
+; CHECK-S-NEXT:    pld r3, x@got@tprel@pcrel(0), 1
+; CHECK-S-NEXT:    add r3, r3, x@tls@pcrel
+; CHECK-S-NEXT:    blr
+; CHECK-O-LABEL: <InitialExec>:
+; CHECK-O:         00 00 10 04 00 00 60 e4        pld 3, 0(0), 1
+; CHECK-O-NEXT:    0000000000000000:  R_PPC64_GOT_TPREL_PCREL34 x
+; CHECK-O-NEXT:    14 6a 63 7c                    add 3, 3, 13
+; CHECK-O-NEXT:    0000000000000009:  R_PPC64_TLS x
+; CHECK-O-NEXT:    20 00 80 4e                    blr
+entry:
+  ret i32* @x
+}
+
+define i32 @InitialExecLoad() {
+; CHECK-S-LABEL: InitialExecLoad:
+; CHECK-S:       # %bb.0: # %entry
+; CHECK-S-NEXT:    pld r3, x@got@tprel@pcrel(0), 1
+; CHECK-S-NEXT:    lwzx r3, r3, x@tls@pcrel
+; CHECK-S-NEXT:    blr
+; CHECK-O-LABEL: <InitialExecLoad>:
+; CHECK-O:         00 00 10 04 00 00 60 e4        pld 3, 0(0), 1
+; CHECK-O-NEXT:    0000000000000020:  R_PPC64_GOT_TPREL_PCREL34 x
+; CHECK-O-NEXT:    2e 68 63 7c                    lwzx 3, 3, 13
+; CHECK-O-NEXT:    0000000000000029:  R_PPC64_TLS x
+; CHECK-O-NEXT:    20 00 80 4e                    blr
+entry:
+  %0 = load i32, i32* @x, align 4
+  ret i32 %0
+}