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BypassSlowDivision: Fix dropping debug info
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Authored by arsenm on Jun 11 2020, 1:05 PM.

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Reviewers

echristo
jlebar
aprantl
scott.linder
ramana-nvr
vsk

Summary

I don't know anything about debug info, but this seems like more work
should be necessary. This constructs a new IRBuilder and reconstructs
the original divides rather than moving the original.

One problem this has is if a div/rem pair are handled, both end up
with the same debugloc. I'm not sure how to fix this, since this uses
a cache when it sees the same input operands again, which will have
the first instance's location attached.

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arsenm created this revision.Jun 11 2020, 1:05 PM

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dblaikie added a subscriber: dblaikie.Jun 11 2020, 1:18 PM

Re: "This constructs a new IRBuilder and reconstructs the original divides rather than moving the original", you're not changing the algorithm here, just the way locations are assigned, right? Not sure I understand what's meant by 'reconstructs the original divides'.

llvm/lib/Transforms/Utils/BypassSlowDivision.cpp
441	Is it simpler to just pass in the builder (which has the location set already)?
llvm/test/Transforms/CodeGenPrepare/AMDGPU/bypass-slow-div-debug-info.ll
29	I think this is good? At least, it seems better than having the source location of the srem (!10) appear in the fast block.

In D81685#2088957, @vsk wrote:

Re: "This constructs a new IRBuilder and reconstructs the original divides rather than moving the original", you're not changing the algorithm here, just the way locations are assigned, right? Not sure I understand what's meant by 'reconstructs the original divides'.

I mean mechanically it produces a new IR instruction and deletes the old instruction, rather than move the old instruction to the new block

llvm/lib/Transforms/Utils/BypassSlowDivision.cpp
441	I did that originally, but it didn't work in all of the cases (which required getting the DebugLoc from FastDivInsertionTask). Since I had to track it separately anyway, it seemed cleaner to always get it from there
llvm/test/Transforms/CodeGenPrepare/AMDGPU/bypass-slow-div-debug-info.ll
29	I would hope the rem would get the location of the original rem, but I guess this is better than nothing (especially for architectures where these will end up merging into SDIVREM/UDIVREM later anyway)

aprantl added inline comments.Jun 12 2020, 10:39 AM

llvm/test/Transforms/CodeGenPrepare/AMDGPU/bypass-slow-div-debug-info.ll
32	Can you replace !6 with ![[DBG:[0-9]+]] and the CHECK that DBG is the expected location? The numbering isn't really guaranteed.

vsk added inline comments.Jun 12 2020, 10:52 AM

llvm/test/Transforms/CodeGenPrepare/AMDGPU/bypass-slow-div-debug-info.ll
29	One issue with using the location of the original rem is that single-stepping would look like 'line 3 -> line 4 -> line 3'. It's unfortunate to lose the unique breakpoint location for the rem, but if there were a second rem that used the cached value, this would happen anyway.

arsenm marked an inline comment as done.Jun 12 2020, 10:54 AM

arsenm added inline comments.

llvm/test/Transforms/CodeGenPrepare/AMDGPU/bypass-slow-div-debug-info.ll
32	That would mean switching to handwritten checks rather than update_test_checks

arsenm marked an inline comment as done.Jun 15 2020, 11:35 AM

arsenm added inline comments.

llvm/test/Transforms/CodeGenPrepare/AMDGPU/bypass-slow-div-debug-info.ll
32	I think it would be more painful to have manually written checks to avoid hardcoding the number than to just regenerate the test if these numbers were to ever change.

This looks good to me. I think using update_test_checks here is fine, but could you leave this up for another day or so to give Adrian a chance to review?

This revision is now accepted and ready to land.Jun 15 2020, 2:01 PM

b13f6b0fe0263ea53f628652d31ec0983ca6b751

Revision Contents

Path

Size

llvm/

lib/

Transforms/

Utils/

BypassSlowDivision.cpp

9 lines

test/

Transforms/

CodeGenPrepare/

AMDGPU/

bypass-slow-div-debug-info.ll

76 lines

Diff 270212

llvm/lib/Transforms/Utils/BypassSlowDivision.cpp

Show First 20 Lines • Show All 257 Lines • ▼ Show 20 Lines

/// Add new basic block for slow div and rem operations and put it before		/// Add new basic block for slow div and rem operations and put it before
/// SuccessorBB.		/// SuccessorBB.
QuotRemWithBB FastDivInsertionTask::createSlowBB(BasicBlock *SuccessorBB) {		QuotRemWithBB FastDivInsertionTask::createSlowBB(BasicBlock *SuccessorBB) {
QuotRemWithBB DivRemPair;		QuotRemWithBB DivRemPair;
DivRemPair.BB = BasicBlock::Create(MainBB->getParent()->getContext(), "",		DivRemPair.BB = BasicBlock::Create(MainBB->getParent()->getContext(), "",
MainBB->getParent(), SuccessorBB);		MainBB->getParent(), SuccessorBB);
IRBuilder<> Builder(DivRemPair.BB, DivRemPair.BB->begin());		IRBuilder<> Builder(DivRemPair.BB, DivRemPair.BB->begin());
		Builder.SetCurrentDebugLocation(SlowDivOrRem->getDebugLoc());

Value *Dividend = SlowDivOrRem->getOperand(0);		Value *Dividend = SlowDivOrRem->getOperand(0);
Value *Divisor = SlowDivOrRem->getOperand(1);		Value *Divisor = SlowDivOrRem->getOperand(1);

if (isSignedOp()) {		if (isSignedOp()) {
DivRemPair.Quotient = Builder.CreateSDiv(Dividend, Divisor);		DivRemPair.Quotient = Builder.CreateSDiv(Dividend, Divisor);
DivRemPair.Remainder = Builder.CreateSRem(Dividend, Divisor);		DivRemPair.Remainder = Builder.CreateSRem(Dividend, Divisor);
} else {		} else {
DivRemPair.Quotient = Builder.CreateUDiv(Dividend, Divisor);		DivRemPair.Quotient = Builder.CreateUDiv(Dividend, Divisor);
DivRemPair.Remainder = Builder.CreateURem(Dividend, Divisor);		DivRemPair.Remainder = Builder.CreateURem(Dividend, Divisor);
}		}

Builder.CreateBr(SuccessorBB);		Builder.CreateBr(SuccessorBB);
return DivRemPair;		return DivRemPair;
}		}

/// Add new basic block for fast div and rem operations and put it before		/// Add new basic block for fast div and rem operations and put it before
/// SuccessorBB.		/// SuccessorBB.
QuotRemWithBB FastDivInsertionTask::createFastBB(BasicBlock *SuccessorBB) {		QuotRemWithBB FastDivInsertionTask::createFastBB(BasicBlock *SuccessorBB) {
QuotRemWithBB DivRemPair;		QuotRemWithBB DivRemPair;
DivRemPair.BB = BasicBlock::Create(MainBB->getParent()->getContext(), "",		DivRemPair.BB = BasicBlock::Create(MainBB->getParent()->getContext(), "",
MainBB->getParent(), SuccessorBB);		MainBB->getParent(), SuccessorBB);
IRBuilder<> Builder(DivRemPair.BB, DivRemPair.BB->begin());		IRBuilder<> Builder(DivRemPair.BB, DivRemPair.BB->begin());
		Builder.SetCurrentDebugLocation(SlowDivOrRem->getDebugLoc());

Value *Dividend = SlowDivOrRem->getOperand(0);		Value *Dividend = SlowDivOrRem->getOperand(0);
Value *Divisor = SlowDivOrRem->getOperand(1);		Value *Divisor = SlowDivOrRem->getOperand(1);
Value *ShortDivisorV =		Value *ShortDivisorV =
Builder.CreateCast(Instruction::Trunc, Divisor, BypassType);		Builder.CreateCast(Instruction::Trunc, Divisor, BypassType);
Value *ShortDividendV =		Value *ShortDividendV =
Builder.CreateCast(Instruction::Trunc, Dividend, BypassType);		Builder.CreateCast(Instruction::Trunc, Dividend, BypassType);

Show All 9 Lines	QuotRemWithBB FastDivInsertionTask::createFastBB(BasicBlock *SuccessorBB) {
return DivRemPair;		return DivRemPair;
}		}

/// Creates Phi nodes for result of Div and Rem.		/// Creates Phi nodes for result of Div and Rem.
QuotRemPair FastDivInsertionTask::createDivRemPhiNodes(QuotRemWithBB &LHS,		QuotRemPair FastDivInsertionTask::createDivRemPhiNodes(QuotRemWithBB &LHS,
QuotRemWithBB &RHS,		QuotRemWithBB &RHS,
BasicBlock *PhiBB) {		BasicBlock *PhiBB) {
IRBuilder<> Builder(PhiBB, PhiBB->begin());		IRBuilder<> Builder(PhiBB, PhiBB->begin());
		Builder.SetCurrentDebugLocation(SlowDivOrRem->getDebugLoc());
PHINode *QuoPhi = Builder.CreatePHI(getSlowType(), 2);		PHINode *QuoPhi = Builder.CreatePHI(getSlowType(), 2);
QuoPhi->addIncoming(LHS.Quotient, LHS.BB);		QuoPhi->addIncoming(LHS.Quotient, LHS.BB);
QuoPhi->addIncoming(RHS.Quotient, RHS.BB);		QuoPhi->addIncoming(RHS.Quotient, RHS.BB);
PHINode *RemPhi = Builder.CreatePHI(getSlowType(), 2);		PHINode *RemPhi = Builder.CreatePHI(getSlowType(), 2);
RemPhi->addIncoming(LHS.Remainder, LHS.BB);		RemPhi->addIncoming(LHS.Remainder, LHS.BB);
RemPhi->addIncoming(RHS.Remainder, RHS.BB);		RemPhi->addIncoming(RHS.Remainder, RHS.BB);
return QuotRemPair(QuoPhi, RemPhi);		return QuotRemPair(QuoPhi, RemPhi);
}		}

/// Creates a runtime check to test whether both the divisor and dividend fit		/// Creates a runtime check to test whether both the divisor and dividend fit
/// into BypassType. The check is inserted at the end of MainBB. True return		/// into BypassType. The check is inserted at the end of MainBB. True return
/// value means that the operands fit. Either of the operands may be NULL if it		/// value means that the operands fit. Either of the operands may be NULL if it
/// doesn't need a runtime check.		/// doesn't need a runtime check.
Value FastDivInsertionTask::insertOperandRuntimeCheck(Value Op1, Value *Op2) {		Value FastDivInsertionTask::insertOperandRuntimeCheck(Value Op1, Value *Op2) {
assert((Op1 \|\| Op2) && "Nothing to check");		assert((Op1 \|\| Op2) && "Nothing to check");
IRBuilder<> Builder(MainBB, MainBB->end());		IRBuilder<> Builder(MainBB, MainBB->end());
		Builder.SetCurrentDebugLocation(SlowDivOrRem->getDebugLoc());

Value *OrV;		Value *OrV;
if (Op1 && Op2)		if (Op1 && Op2)
OrV = Builder.CreateOr(Op1, Op2);		OrV = Builder.CreateOr(Op1, Op2);
else		else
OrV = Op1 ? Op1 : Op2;		OrV = Op1 ? Op1 : Op2;

// BitMask is inverted to check if the operands are		// BitMask is inverted to check if the operands are
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines	Optional<QuotRemPair> FastDivInsertionTask::insertFastDivAndRem() {
// bitcast instructions. As a result, some constants may look like an		// bitcast instructions. As a result, some constants may look like an
// instruction at first, and an additional check is necessary to find out if		// instruction at first, and an additional check is necessary to find out if
// an operand is actually a constant.		// an operand is actually a constant.
if (auto *BCI = dyn_cast<BitCastInst>(Divisor))		if (auto *BCI = dyn_cast<BitCastInst>(Divisor))
if (BCI->getParent() == SlowDivOrRem->getParent() &&		if (BCI->getParent() == SlowDivOrRem->getParent() &&
isa<ConstantInt>(BCI->getOperand(0)))		isa<ConstantInt>(BCI->getOperand(0)))
return None;		return None;

		IRBuilder<> Builder(MainBB, MainBB->end());
		Builder.SetCurrentDebugLocation(SlowDivOrRem->getDebugLoc());

if (DividendShort && !isSignedOp()) {		if (DividendShort && !isSignedOp()) {
// If the division is unsigned and Dividend is known to be short, then		// If the division is unsigned and Dividend is known to be short, then
// either		// either
// 1) Divisor is less or equal to Dividend, and the result can be computed		// 1) Divisor is less or equal to Dividend, and the result can be computed
// with a short division.		// with a short division.
// 2) Divisor is greater than Dividend. In this case, no division is needed		// 2) Divisor is greater than Dividend. In this case, no division is needed
// at all: The quotient is 0 and the remainder is equal to Dividend.		// at all: The quotient is 0 and the remainder is equal to Dividend.
//		//
// So instead of checking at runtime whether Divisor fits into BypassType,		// So instead of checking at runtime whether Divisor fits into BypassType,
// we emit a runtime check to differentiate between these two cases. This		// we emit a runtime check to differentiate between these two cases. This
// lets us entirely avoid a long div.		// lets us entirely avoid a long div.

// Split the basic block before the div/rem.		// Split the basic block before the div/rem.
BasicBlock *SuccessorBB = MainBB->splitBasicBlock(SlowDivOrRem);		BasicBlock *SuccessorBB = MainBB->splitBasicBlock(SlowDivOrRem);
// Remove the unconditional branch from MainBB to SuccessorBB.		// Remove the unconditional branch from MainBB to SuccessorBB.
MainBB->getInstList().back().eraseFromParent();		MainBB->getInstList().back().eraseFromParent();
QuotRemWithBB Long;		QuotRemWithBB Long;
Long.BB = MainBB;		Long.BB = MainBB;
Long.Quotient = ConstantInt::get(getSlowType(), 0);		Long.Quotient = ConstantInt::get(getSlowType(), 0);
Long.Remainder = Dividend;		Long.Remainder = Dividend;
QuotRemWithBB Fast = createFastBB(SuccessorBB);		QuotRemWithBB Fast = createFastBB(SuccessorBB);
QuotRemPair Result = createDivRemPhiNodes(Fast, Long, SuccessorBB);		QuotRemPair Result = createDivRemPhiNodes(Fast, Long, SuccessorBB);
IRBuilder<> Builder(MainBB, MainBB->end());
Value *CmpV = Builder.CreateICmpUGE(Dividend, Divisor);		Value *CmpV = Builder.CreateICmpUGE(Dividend, Divisor);
Builder.CreateCondBr(CmpV, Fast.BB, SuccessorBB);		Builder.CreateCondBr(CmpV, Fast.BB, SuccessorBB);
return Result;		return Result;
} else {		} else {
// General case. Create both slow and fast div/rem pairs and choose one of		// General case. Create both slow and fast div/rem pairs and choose one of
// them at runtime.		// them at runtime.

// Split the basic block before the div/rem.		// Split the basic block before the div/rem.
BasicBlock *SuccessorBB = MainBB->splitBasicBlock(SlowDivOrRem);		BasicBlock *SuccessorBB = MainBB->splitBasicBlock(SlowDivOrRem);
// Remove the unconditional branch from MainBB to SuccessorBB.		// Remove the unconditional branch from MainBB to SuccessorBB.
MainBB->getInstList().back().eraseFromParent();		MainBB->getInstList().back().eraseFromParent();
QuotRemWithBB Fast = createFastBB(SuccessorBB);		QuotRemWithBB Fast = createFastBB(SuccessorBB);
QuotRemWithBB Slow = createSlowBB(SuccessorBB);		QuotRemWithBB Slow = createSlowBB(SuccessorBB);
QuotRemPair Result = createDivRemPhiNodes(Fast, Slow, SuccessorBB);		QuotRemPair Result = createDivRemPhiNodes(Fast, Slow, SuccessorBB);
Value *CmpV = insertOperandRuntimeCheck(DividendShort ? nullptr : Dividend,		Value *CmpV = insertOperandRuntimeCheck(DividendShort ? nullptr : Dividend,
		vskUnsubmitted Not Done Reply Inline Actions Is it simpler to just pass in the builder (which has the location set already)? vsk: Is it simpler to just pass in the builder (which has the location set already)?
		arsenmAuthorUnsubmitted Done Reply Inline Actions I did that originally, but it didn't work in all of the cases (which required getting the DebugLoc from FastDivInsertionTask). Since I had to track it separately anyway, it seemed cleaner to always get it from there arsenm: I did that originally, but it didn't work in all of the cases (which required getting the…
DivisorShort ? nullptr : Divisor);		DivisorShort ? nullptr : Divisor);
IRBuilder<> Builder(MainBB, MainBB->end());
Builder.CreateCondBr(CmpV, Fast.BB, Slow.BB);		Builder.CreateCondBr(CmpV, Fast.BB, Slow.BB);
return Result;		return Result;
}		}
}		}

/// This optimization identifies DIV/REM instructions in a BB that can be		/// This optimization identifies DIV/REM instructions in a BB that can be
/// profitably bypassed and carried out with a shorter, faster divide.		/// profitably bypassed and carried out with a shorter, faster divide.
bool llvm::bypassSlowDivision(BasicBlock *BB,		bool llvm::bypassSlowDivision(BasicBlock *BB,
Show All 32 Lines

llvm/test/Transforms/CodeGenPrepare/AMDGPU/bypass-slow-div-debug-info.ll

This file was added.

				; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
				; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -codegenprepare %s \| FileCheck %s
				; Make sure BypassSlowdivision doesn't ddrop debug info

				define i64 @sdiv64(i64 %a, i64 %b) {
				; CHECK-LABEL: @sdiv64(
				; CHECK-NEXT: [[TMP1:%.]] = or i64 [[A:%.]], [[B:%.*]], !dbg !6
				; CHECK-NEXT: [[TMP2:%.*]] = and i64 [[TMP1]], -4294967296, !dbg !6
				; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[TMP2]], 0, !dbg !6
				; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.]], label [[TMP9:%.]], !dbg !6
				; CHECK: 4:
				; CHECK-NEXT: [[TMP5:%.*]] = trunc i64 [[B]] to i32, !dbg !6
				; CHECK-NEXT: [[TMP6:%.*]] = trunc i64 [[A]] to i32, !dbg !6
				; CHECK-NEXT: [[TMP7:%.*]] = udiv i32 [[TMP6]], [[TMP5]], !dbg !6
				; CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64, !dbg !6
				; CHECK-NEXT: br label [[TMP11:%.*]], !dbg !6
				; CHECK: 9:
				; CHECK-NEXT: [[TMP10:%.*]] = sdiv i64 [[A]], [[B]], !dbg !6
				; CHECK-NEXT: br label [[TMP11]], !dbg !6
				; CHECK: 11:
				; CHECK-NEXT: [[TMP12:%.*]] = phi i64 [ [[TMP8]], [[TMP4]] ], [ [[TMP10]], [[TMP9]] ], !dbg !6
				; CHECK-NEXT: ret i64 [[TMP12]]
				;
				%d = sdiv i64 %a, %b, !dbg !6
				ret i64 %d
				}

				; FIXME: The debugloc for the rem parts end up with the dbg of the
				; division.
				vskUnsubmitted Not Done Reply Inline Actions I think this is good? At least, it seems better than having the source location of the srem (!10) appear in the fast block. vsk: I think this is good? At least, it seems better than having the source location of the srem (!
				arsenmAuthorUnsubmitted Done Reply Inline Actions I would hope the rem would get the location of the original rem, but I guess this is better than nothing (especially for architectures where these will end up merging into SDIVREM/UDIVREM later anyway) arsenm: I would hope the rem would get the location of the original rem, but I guess this is better…
				vskUnsubmitted Not Done Reply Inline Actions One issue with using the location of the original rem is that single-stepping would look like 'line 3 -> line 4 -> line 3'. It's unfortunate to lose the unique breakpoint location for the rem, but if there were a second rem that used the cached value, this would happen anyway. vsk: One issue with using the location of the original rem is that single-stepping would look like…
				define <2 x i64> @sdivrem64(i64 %a, i64 %b) {
				; CHECK-LABEL: @sdivrem64(
				; CHECK-NEXT: [[TMP1:%.]] = or i64 [[A:%.]], [[B:%.*]], !dbg !6
				aprantlUnsubmitted Not Done Reply Inline Actions Can you replace !6 with ![[DBG:[0-9]+]] and the CHECK that DBG is the expected location? The numbering isn't really guaranteed. aprantl: Can you replace !6 with ![[DBG:[0-9]+]] and the CHECK that DBG is the expected location? The…
				arsenmAuthorUnsubmitted Done Reply Inline Actions That would mean switching to handwritten checks rather than update_test_checks arsenm: That would mean switching to handwritten checks rather than update_test_checks
				arsenmAuthorUnsubmitted Done Reply Inline Actions I think it would be more painful to have manually written checks to avoid hardcoding the number than to just regenerate the test if these numbers were to ever change. arsenm: I think it would be more painful to have manually written checks to avoid hardcoding the number…
				; CHECK-NEXT: [[TMP2:%.*]] = and i64 [[TMP1]], -4294967296, !dbg !6
				; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[TMP2]], 0, !dbg !6
				; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.]], label [[TMP11:%.]], !dbg !6
				; CHECK: 4:
				; CHECK-NEXT: [[TMP5:%.*]] = trunc i64 [[B]] to i32, !dbg !6
				; CHECK-NEXT: [[TMP6:%.*]] = trunc i64 [[A]] to i32, !dbg !6
				; CHECK-NEXT: [[TMP7:%.*]] = udiv i32 [[TMP6]], [[TMP5]], !dbg !6
				; CHECK-NEXT: [[TMP8:%.*]] = urem i32 [[TMP6]], [[TMP5]], !dbg !6
				; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP7]] to i64, !dbg !6
				; CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[TMP8]] to i64, !dbg !6
				; CHECK-NEXT: br label [[TMP14:%.*]], !dbg !6
				; CHECK: 11:
				; CHECK-NEXT: [[TMP12:%.*]] = sdiv i64 [[A]], [[B]], !dbg !6
				; CHECK-NEXT: [[TMP13:%.*]] = srem i64 [[A]], [[B]], !dbg !6
				; CHECK-NEXT: br label [[TMP14]], !dbg !6
				; CHECK: 14:
				; CHECK-NEXT: [[TMP15:%.*]] = phi i64 [ [[TMP9]], [[TMP4]] ], [ [[TMP12]], [[TMP11]] ], !dbg !6
				; CHECK-NEXT: [[TMP16:%.*]] = phi i64 [ [[TMP10]], [[TMP4]] ], [ [[TMP13]], [[TMP11]] ], !dbg !6
				; CHECK-NEXT: [[INS0:%.*]] = insertelement <2 x i64> undef, i64 [[TMP15]], i32 0
				; CHECK-NEXT: [[INS1:%.*]] = insertelement <2 x i64> [[INS0]], i64 [[TMP16]], i32 1
				; CHECK-NEXT: ret <2 x i64> [[INS1]]
				;
				%d = sdiv i64 %a, %b, !dbg !6
				%r = srem i64 %a, %b, !dbg !10
				%ins0 = insertelement <2 x i64> undef, i64 %d, i32 0
				%ins1 = insertelement <2 x i64> %ins0, i64 %r, i32 1
				ret <2 x i64> %ins1
				}

				!llvm.dbg.cu = !{!0}
				!llvm.module.flags = !{!3, !4}
				!llvm.ident = !{!5}

				!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.5 ", isOptimized: false, runtimeVersion: 0, emissionKind: NoDebug, enums: !2, retainedTypes: !2, globals: !2, imports: !2)
				!1 = !DIFile(filename: "basic.c", directory: ".")
				!2 = !{}
				!3 = !{i32 2, !"Dwarf Version", i32 4}
				!4 = !{i32 1, !"Debug Info Version", i32 3}
				!5 = !{!"clang version 3.5 "}
				!6 = !DILocation(line: 3, scope: !7)
				!7 = distinct !DILexicalBlock(scope: !8, file: !1, line: 3)
				!8 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 1, type: !9, scopeLine: 1, virtualIndex: 6, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !2)
				!9 = !DISubroutineType(types: !2)
				!10 = !DILocation(line: 4, scope: !7)