This is an archive of the discontinued LLVM Phabricator instance.

[AArch64][SVE] Add legalization support for i32/i64 vector srem/urem
ClosedPublic

Authored by efriedma on Jun 9 2020, 3:09 PM.

Details

Summary

Implement them on top of sdiv/udiv, similar to what we do for integer types.

Potential future work: implementing i8/i16 srem/urem, optimizations for constant divisors, optimizing the mul+sub to mls.

Diff Detail

Event Timeline

efriedma created this revision.Jun 9 2020, 3:09 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 9 2020, 3:10 PM

Please can you regenerate/commit llvm-ir-to-intrinsic.ll against trunk first to reduce the diffs?

efriedma updated this revision to Diff 270204.Jun 11 2020, 12:15 PM

Committed test update separately

sdesmalen accepted this revision.Jun 16 2020, 1:55 PM

Nice improvement, LGTM!

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
1360

nit: missing whitespace above this line.

llvm/lib/Target/ARM/ARMISelLowering.cpp
213

If you're adding these for ARM Neon and MVE, they should probably have tests similar to the one for SVE?

This revision is now accepted and ready to land.Jun 16 2020, 1:55 PM
efriedma marked 3 inline comments as done.Jun 16 2020, 3:10 PM
efriedma added inline comments.
llvm/lib/Target/ARM/ARMISelLowering.cpp
213

NEON and MVE don't have a vector divide instruction. All this change does is make sure expandREM properly fails (so we continue calling UnrollVectorOp).

We have test coverage for this unrolling already.

RKSimon added inline comments.Jun 17 2020, 7:33 AM
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
7828

assert((Node->getOpcode() == ISD::SREM || Node->getOpcode() == ISD::UREM) && "");

This revision was automatically updated to reflect the committed changes.
efriedma marked an inline comment as done.