[MSP430] Enable some basic support for debug information

[atrosinenko]

Summary

This commit technically permits LLVM to emit the debug information for ELF files for MSP430 architecture. Aside from this, it only defines the register numbers as defined by part 10.1 of MSP430 EABI specification (assuming the 1-byte subregisters share the register numbers with corresponding full-size registers).

This commit was basically tested by me with TI-provided GCC 8.3.1 toolchain by compiling an example program with clang (please note manual linking may be required due to upstream clang not yet handling the -msim option necessary to run binaries on the GDB-provided simulator) and then running it and single-stepping with msp430-elf-gdb like this:

$sysroot/bin/msp430-elf-gdb ./test -ex "target sim" -ex "load ./test"
(gdb) ... traditional GDB commands follow ...

While this implementation is most probably far from completeness and is considered experimental, it can already help with debugging MSP430 programs as well as finding issues in LLVM debug info support for MSP430 itself.

One of the use cases includes trying to find a point where UBSan check in a trap-on-error mode was triggered.

The expected debug information format is described in the MSP430 Embedded Application Binary Interface specification, part 10.

[aprantl]

Can this be tested by checking assembler output?

[atrosinenko]

Implemented a test. Please note it depends on D82055: [DebugInfo] Explicitly permit addr_size = 0x02 when parsing DWARF data.

[aprantl]

llvm/test/DebugInfo/MSP430/dwarf-basics.ll

114 ↗

(On Diff #271487)

please remove all non-essential attributes (everything in quotes is a good start). They make tests difficult to maintain.

[atrosinenko]

Thanks! I have dropped the entire #0 and #1 attribute lists - that did not change the output. All the debug information nodes, on the other hand, were left intact (just in case) apart from omitting some parts of the producer string.

The patch was re-uploaded as two commits (that information was accidentally lost during previous update via web interface).

[atrosinenko]

Meanwhile, is it acceptable that byte-sized and word-sized registers share the same DWARF register numbers such as r12 (16 bit) and r12b (8 bit) in this example?

[aprantl]

Meanwhile, is it acceptable that byte-sized and word-sized registers share the same DWARF register numbers such as r12 (16 bit) and r12b (8 bit) in this example?

These kinds of decisions are supposed to be specified by the ABI document for the platform (not in the DWARF standard), so you'd have to direct this question to whatever consortium defines the ABI for MSP430.

[atrosinenko]

In D81488#2104502, @aprantl wrote:

Meanwhile, is it acceptable that byte-sized and word-sized registers share the same DWARF register numbers such as r12 (16 bit) and r12b (8 bit) in this example?

These kinds of decisions are supposed to be specified by the ABI document for the platform (not in the DWARF standard), so you'd have to direct this question to whatever consortium defines the ABI for MSP430.

Thank you for the explanation! The MSP430 EABI document released in 2013, part "10.1 DWARF Register Names", mentions R0-R15 register numbers only. Recent msp430-gcc v8.3.1 does recognize

cpp
char g(void) {
  register char y asm("r6");
  return y;
}

but does not recognize asm("r6b"). So, maybe R*B are more of LLVM internal abstractions.

[atrosinenko]

Unit test failure here is expected because D82055: [DebugInfo] Explicitly permit addr_size = 0x02 when parsing DWARF data have to be landed before.

[asl]

LGTM, thanks!

llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp

MSP430MCAsmInfo::MSP430MCAsmInfo(const Triple &TT,
                                  const MCTargetOptions &Options) {
   CodePointerSize = CalleeSaveStackSlotSize = 2;
 
   CommentString = ";";
   SeparatorString = "{";
 
   AlignmentIsInBytes = false;
   UsesELFSectionDirectiveForBSS = true;
+
+  SupportsDebugInformation = true;
 }

llvm/lib/Target/MSP430/MSP430RegisterInfo.td

 //  Declarations that describe the MSP430 register file
 //===----------------------------------------------------------------------===//
 
 class MSP430Reg<bits<4> num, string n, list<string> alt = []> : Register<n> {
   field bits<4> Num = num;
   let Namespace = "MSP430";
   let HWEncoding{3-0} = num;
   let AltNames = alt;
+  let DwarfNumbers = [num];
 }
 
 class MSP430RegWithSubregs<bits<4> num, string n, list<Register> subregs,
                            list<string> alt = []> 
   : RegisterWithSubRegs<n, subregs> {
   field bits<4> Num = num;
   let Namespace = "MSP430";
   let HWEncoding{3-0} = num;
   let AltNames = alt;
+  let DwarfNumbers = [num];
 }
 
 //===----------------------------------------------------------------------===//
 //  Registers
 //===----------------------------------------------------------------------===//
 
 def PCB  : MSP430Reg<0,  "r0", ["pc"]>;
 def SPB  : MSP430Reg<1,  "r1", ["sp"]>;