[AMDGPU] Allow PAL to put RO global in .text or .rodata

[tpr]

Summary

In LLPC (PAL OS type), I would like to be able to choose whether an RO
constant goes in .text with a relative fixup to reference it (for full
pipeline compilation) or in .rodata with a reloc to reference it (shader
compilation).

This commit allows that. LLPC will override the global's section name
with ".text" to get the global into .text.

Change-Id: I14c9525225572a16f0c01d394565e6ebfa39456d

[tpr]

V2: Fixed tests.

[tpr]

Ping.

[s-perron]

This looks reasonable to me, but I am not an owner of this code.

llvm/lib/Target/AMDGPU/AMDGPUTargetObjectFile.cpp

 }
 
 MCSection *AMDGPUTargetObjectFile::getExplicitSectionGlobal(
     const GlobalObject *GO, SectionKind SK, const TargetMachine &TM) const {
   // Set metadata access for the explicit section
   StringRef SectionName = GO->getSection();
   if (SectionName.startswith(".AMDGPU.comment."))
     SK = SectionKind::getMetadata();
+  else if (SectionName.startswith(".text"))
+    SK = SectionKind::getText();
 
   return TargetLoweringObjectFileELF::getExplicitSectionGlobal(GO, SK, TM);
 }

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

unsigned SITargetLowering::isCFIntrinsic(const SDNode *Intr) const {
   // directly as branch conditions.
   return 0;
 }
 
 bool SITargetLowering::shouldEmitFixup(const GlobalValue *GV) const {
   const Triple &TT = getTargetMachine().getTargetTriple();
   return (GV->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS ||
           GV->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT) &&
-         AMDGPU::shouldEmitConstantsToTextSection(TT);
+         (AMDGPU::shouldEmitConstantsToTextSection(TT) ||
+          GV->getSection().startswith(".text"));
 }
 
 bool SITargetLowering::shouldEmitGOTReloc(const GlobalValue *GV) const {
   // FIXME: Either avoid relying on address space here or change the default
   // address space for functions to avoid the explicit check.
   return (GV->getValueType()->isFunctionTy() ||
           !isNonGlobalAddrSpace(GV->getAddressSpace())) &&
          !shouldEmitFixup(GV) &&

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

 
 bool isReadOnlySegment(const GlobalValue *GV) {
   unsigned AS = GV->getAddressSpace();
   return AS == AMDGPUAS::CONSTANT_ADDRESS ||
          AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT;
 }
 
 bool shouldEmitConstantsToTextSection(const Triple &TT) {
-  return TT.getOS() == Triple::AMDPAL || TT.getArch() == Triple::r600;
+  return TT.getArch() == Triple::r600;
 }
 
 int getIntegerAttribute(const Function &F, StringRef Name, int Default) {
   Attribute A = F.getFnAttribute(Name);
   int Result = Default;
 
   if (A.isStringAttribute()) {
     StringRef Str = A.getValueAsString();

llvm/test/CodeGen/AMDGPU/elf.rodata.ll

+; RUN: llc < %s -march=amdgcn -mcpu=fiji -filetype=obj | llvm-readobj --symbols -S --sd - | FileCheck %s
+
+; CHECK: Section {
+; CHECK: Name: .text
+; CHECK: Type: SHT_PROGBITS (0x1)
+; CHECK: Flags [ (0x6)
+; CHECK: Size: 16
+; CHECK: SectionData (
+; CHECK: 0000: 414D4431 414D4431 414D4431 414D4431  |AMD1AMD1AMD1AMD1|
+; CHECK: )
+; CHECK: }
+
+; CHECK: Section {
+; CHECK: Name: .rodata
+; CHECK: Type: SHT_PROGBITS (0x1)
+; CHECK: Flags [ (0x2)
+; CHECK: Size: 16
+; CHECK: SectionData (
+; CHECK: 0000: 414D4432 414D4432 414D4432 414D4432  |AMD2AMD2AMD2AMD2|
+; CHECK: )
+; CHECK: }
+
+
+@rodata_info_var_1 = internal global [4 x i32][i32 826559809, i32 826559809, i32 826559809, i32 826559809], section ".text"
+@rodata_info_var_2 = constant [4 x i32][i32 843337025, i32 843337025, i32 843337025, i32 843337025]