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[X86] WIP Codegen support for AVX5124FMAPS/AVX5124VNNI instructions.
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Authored by craig.topper on May 18 2020, 12:11 AM.

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Reviewers: None

Summary

These instructions have weird register allocation constraints
that requires 4 consecutive registers. LLVM has support for
this using REG_SEQUENCE.

These instructions are also weird in that they do a 128 bit load
conditional on whether any bit of the mask is non-zero. This
differs from normal masked loads. They also have no register form.
We need to use target specific memory ISD opcodes to make sure
memory operands are propagated correctly to the machine instruction.

I've had part of this patch lying around for a couple years. I
tried to clean it up some this weekend. Still need to add tests
and finish the patterns for the scalar instructions. Not completely
sure I'm happy with the intrinsic format for those yet.

Some of the test changes are just from introducing the quad register
classes. This seems to break something in the critical anti dep
breaker if I remember from when I investigated this a year or two
ago.

Diff Detail

Repository: rG LLVM Github Monorepo

Event Timeline

craig.topper created this revision.May 18 2020, 12:11 AM

Herald added a project: Restricted Project. · View Herald TranscriptMay 18 2020, 12:11 AM

Herald added subscribers: jdoerfert, hiraditya. · View Herald Transcript

Harbormaster failed remote builds in B57026: Diff 264548!May 18 2020, 2:06 AM

Change scalar intrinsic to using v4f32. Still not sure about this.

Add some test cases to show that things work. Still need AVX5124VNNI

Harbormaster failed remote builds in B57166: Diff 264801!May 19 2020, 12:30 AM

Really include the test file

Harbormaster failed remote builds in B57287: Diff 265068!May 19 2020, 5:06 PM

Revision Contents

Path

Size

llvm/

include/

llvm/

IR/

Intrinsics.td

1 line

IntrinsicsX86.td

48 lines

Support/

X86DisassemblerDecoderCommon.h

3 lines

lib/

Target/

X86/

AsmParser/

X86Operand.h

85 lines

Disassembler/

X86Disassembler.cpp

4 lines

X86DisassemblerDecoder.h

22 lines

MCTargetDesc/

X86InstPrinterCommon.h

1 line

X86InstPrinterCommon.cpp

75 lines

6 lines

8 lines

40 lines

164 lines

X86InstrFragmentsSIMD.td

27 lines

X86InstrInfo.td

15 lines

X86RegisterInfo.td

32 lines

X86Subtarget.h

8 lines

test/

CodeGen/

X86/

avx5124fmaps-intrinsics.ll

158 lines

2 lines

88 lines

12 lines

16 lines

54 lines

utils/

TableGen/

X86RecognizableInstr.cpp

4 lines

Diff 265068

llvm/include/llvm/IR/Intrinsics.td

	Show First 20 Lines • Show All 224 Lines • ▼ Show 20 Lines
	def llvm_empty_ty : LLVMType<OtherVT>; // { }			def llvm_empty_ty : LLVMType<OtherVT>; // { }
	def llvm_descriptor_ty : LLVMPointerType<llvm_empty_ty>; // { }*			def llvm_descriptor_ty : LLVMPointerType<llvm_empty_ty>; // { }*
	def llvm_metadata_ty : LLVMType<MetadataVT>; // !{...}			def llvm_metadata_ty : LLVMType<MetadataVT>; // !{...}
	def llvm_token_ty : LLVMType<token>; // token			def llvm_token_ty : LLVMType<token>; // token

	def llvm_x86mmx_ty : LLVMType<x86mmx>;			def llvm_x86mmx_ty : LLVMType<x86mmx>;
	def llvm_ptrx86mmx_ty : LLVMPointerType<llvm_x86mmx_ty>; // <1 x i64>*			def llvm_ptrx86mmx_ty : LLVMPointerType<llvm_x86mmx_ty>; // <1 x i64>*

				def llvm_v1i1_ty : LLVMType<v1i1>; // 1 x i1
	def llvm_v2i1_ty : LLVMType<v2i1>; // 2 x i1			def llvm_v2i1_ty : LLVMType<v2i1>; // 2 x i1
	def llvm_v4i1_ty : LLVMType<v4i1>; // 4 x i1			def llvm_v4i1_ty : LLVMType<v4i1>; // 4 x i1
	def llvm_v8i1_ty : LLVMType<v8i1>; // 8 x i1			def llvm_v8i1_ty : LLVMType<v8i1>; // 8 x i1
	def llvm_v16i1_ty : LLVMType<v16i1>; // 16 x i1			def llvm_v16i1_ty : LLVMType<v16i1>; // 16 x i1
	def llvm_v32i1_ty : LLVMType<v32i1>; // 32 x i1			def llvm_v32i1_ty : LLVMType<v32i1>; // 32 x i1
	def llvm_v64i1_ty : LLVMType<v64i1>; // 64 x i1			def llvm_v64i1_ty : LLVMType<v64i1>; // 64 x i1
	def llvm_v128i1_ty : LLVMType<v128i1>; // 128 x i1			def llvm_v128i1_ty : LLVMType<v128i1>; // 128 x i1
	def llvm_v512i1_ty : LLVMType<v512i1>; // 512 x i1			def llvm_v512i1_ty : LLVMType<v512i1>; // 512 x i1
	▲ Show 20 Lines • Show All 1,240 Lines • Show Last 20 Lines

llvm/include/llvm/IR/IntrinsicsX86.td

Show First 20 Lines • Show All 1,855 Lines • ▼ Show 20 Lines	def int_x86_avx512_vpmadd52h_uq_512 :
Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty, llvm_v8i64_ty,		Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty, llvm_v8i64_ty,
llvm_v8i64_ty], [IntrNoMem]>;		llvm_v8i64_ty], [IntrNoMem]>;
def int_x86_avx512_vpmadd52l_uq_512 :		def int_x86_avx512_vpmadd52l_uq_512 :
GCCBuiltin<"__builtin_ia32_vpmadd52luq512">,		GCCBuiltin<"__builtin_ia32_vpmadd52luq512">,
Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty, llvm_v8i64_ty,		Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty, llvm_v8i64_ty,
llvm_v8i64_ty], [IntrNoMem]>;		llvm_v8i64_ty], [IntrNoMem]>;
}		}

		// AVX5124FMAPS
		let TargetPrefix = "x86" in {
		def int_x86_avx512_mask_v4fmadd_ps_512 :
		Intrinsic<[llvm_v16f32_ty],
		[llvm_v16f32_ty, llvm_v16f32_ty, llvm_v16f32_ty,
		llvm_v16f32_ty, llvm_v16f32_ty, llvm_ptr_ty,
		llvm_v16i1_ty],
		[IntrReadMem, IntrArgMemOnly]>;

		def int_x86_avx512_mask_v4fnmadd_ps_512 :
		Intrinsic<[llvm_v16f32_ty],
		[llvm_v16f32_ty, llvm_v16f32_ty, llvm_v16f32_ty,
		llvm_v16f32_ty, llvm_v16f32_ty, llvm_ptr_ty,
		llvm_v16i1_ty],
		[IntrReadMem, IntrArgMemOnly]>;

		def int_x86_avx512_mask_v4fmadd_ss :
		Intrinsic<[llvm_v4f32_ty],
		[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty,
		llvm_v4f32_ty, llvm_v4f32_ty, llvm_ptr_ty,
		llvm_v1i1_ty],
		[IntrReadMem, IntrArgMemOnly]>;

		def int_x86_avx512_mask_v4fnmadd_ss :
		Intrinsic<[llvm_v4f32_ty],
		[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty,
		llvm_v4f32_ty, llvm_v4f32_ty, llvm_ptr_ty,
		llvm_v1i1_ty],
		[IntrReadMem, IntrArgMemOnly]>;
		}

// VNNI		// VNNI
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".		let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx512_vpdpbusd_128 :		def int_x86_avx512_vpdpbusd_128 :
GCCBuiltin<"__builtin_ia32_vpdpbusd128">,		GCCBuiltin<"__builtin_ia32_vpdpbusd128">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty,		Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty,
llvm_v4i32_ty], [IntrNoMem]>;		llvm_v4i32_ty], [IntrNoMem]>;
def int_x86_avx512_vpdpbusd_256 :		def int_x86_avx512_vpdpbusd_256 :
GCCBuiltin<"__builtin_ia32_vpdpbusd256">,		GCCBuiltin<"__builtin_ia32_vpdpbusd256">,
Show All 39 Lines	def int_x86_avx512_vpdpwssds_256 :
Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_v8i32_ty,		Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_v8i32_ty,
llvm_v8i32_ty], [IntrNoMem]>;		llvm_v8i32_ty], [IntrNoMem]>;
def int_x86_avx512_vpdpwssds_512 :		def int_x86_avx512_vpdpwssds_512 :
GCCBuiltin<"__builtin_ia32_vpdpwssds512">,		GCCBuiltin<"__builtin_ia32_vpdpwssds512">,
Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty, llvm_v16i32_ty,		Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty, llvm_v16i32_ty,
llvm_v16i32_ty], [IntrNoMem]>;		llvm_v16i32_ty], [IntrNoMem]>;
}		}

		// AVX5124VNNIW
		let TargetPrefix = "x86" in {
		def int_x86_avx512_mask_vp4dpwssd_512 :
		Intrinsic<[llvm_v16i32_ty],
		[llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty,
		llvm_v16i32_ty, llvm_v16i32_ty, llvm_ptr_ty,
		llvm_v16i1_ty],
		[IntrReadMem, IntrArgMemOnly]>;

		def int_x86_avx512_mask_vp4dpwssds_512 :
		Intrinsic<[llvm_v16i32_ty],
		[llvm_v16i32_ty, llvm_v16i32_ty, llvm_v16i32_ty,
		llvm_v16i32_ty, llvm_v16i32_ty, llvm_ptr_ty,
		llvm_v16i1_ty],
		[IntrReadMem, IntrArgMemOnly]>;
		}

//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//
// XOP		// XOP

let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".		let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_xop_vpermil2pd : GCCBuiltin<"__builtin_ia32_vpermil2pd">,		def int_x86_xop_vpermil2pd : GCCBuiltin<"__builtin_ia32_vpermil2pd">,
Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty,		Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty,
llvm_v2i64_ty, llvm_i8_ty],		llvm_v2i64_ty, llvm_i8_ty],
[IntrNoMem, ImmArg<3>]>;		[IntrNoMem, ImmArg<3>]>;
▲ Show 20 Lines • Show All 3,024 Lines • Show Last 20 Lines

llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h

	//===-- X86DisassemblerDecoderCommon.h - Disassembler decoder ---- C++ --===//			//===-- X86DisassemblerDecoderCommon.h - Disassembler decoder ---- C++ --===//
				Lint: Lint Inline Actions clang-format not found in user's PATH; not linting file. Lint: Lint: clang-format not found in user's PATH; not linting file.
	//			//
	// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.			// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
	// See https://llvm.org/LICENSE.txt for license information.			// See https://llvm.org/LICENSE.txt for license information.
	// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception			// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
	//			//
	//===----------------------------------------------------------------------===//			//===----------------------------------------------------------------------===//
	//			//
	▲ Show 20 Lines • Show All 388 Lines • ▼ Show 20 Lines
	enum OperandEncoding {			enum OperandEncoding {
	ENCODINGS			ENCODINGS
	ENCODING_max			ENCODING_max
	};			};
	#undef ENUM_ENTRY			#undef ENUM_ENTRY

	// Semantic interpretations of instruction operands.			// Semantic interpretations of instruction operands.
	#define TYPES \			#define TYPES \
	ENUM_ENTRY(TYPE_NONE, "") \			ENUM_ENTRY(TYPE_NONE, "") \
				Lint: Pre-merge checks Inline Actions clang-format: please reformat the code - ENUM_ENTRY(TYPE_NONE, "") \ - ENUM_ENTRY(TYPE_REL, "immediate address") \ - ENUM_ENTRY(TYPE_R8, "1-byte register operand") \ - ENUM_ENTRY(TYPE_R16, "2-byte") \ - ENUM_ENTRY(TYPE_R32, "4-byte") \ - ENUM_ENTRY(TYPE_R64, "8-byte") \ - ENUM_ENTRY(TYPE_IMM, "immediate operand") \ - ENUM_ENTRY(TYPE_UIMM8, "1-byte unsigned immediate operand") \ - ENUM_ENTRY(TYPE_M, "Memory operand") \ - ENUM_ENTRY(TYPE_MVSIBX, "Memory operand using XMM index") \ 40 diff lines are omitted. See full diff. Lint: Pre-merge checks: clang-format: please reformat the code ``` - ENUM_ENTRY(TYPE_NONE, "")…
	ENUM_ENTRY(TYPE_REL, "immediate address") \			ENUM_ENTRY(TYPE_REL, "immediate address") \
	ENUM_ENTRY(TYPE_R8, "1-byte register operand") \			ENUM_ENTRY(TYPE_R8, "1-byte register operand") \
	ENUM_ENTRY(TYPE_R16, "2-byte") \			ENUM_ENTRY(TYPE_R16, "2-byte") \
	ENUM_ENTRY(TYPE_R32, "4-byte") \			ENUM_ENTRY(TYPE_R32, "4-byte") \
	ENUM_ENTRY(TYPE_R64, "8-byte") \			ENUM_ENTRY(TYPE_R64, "8-byte") \
	ENUM_ENTRY(TYPE_IMM, "immediate operand") \			ENUM_ENTRY(TYPE_IMM, "immediate operand") \
	ENUM_ENTRY(TYPE_UIMM8, "1-byte unsigned immediate operand") \			ENUM_ENTRY(TYPE_UIMM8, "1-byte unsigned immediate operand") \
	ENUM_ENTRY(TYPE_M, "Memory operand") \			ENUM_ENTRY(TYPE_M, "Memory operand") \
	ENUM_ENTRY(TYPE_MVSIBX, "Memory operand using XMM index") \			ENUM_ENTRY(TYPE_MVSIBX, "Memory operand using XMM index") \
	ENUM_ENTRY(TYPE_MVSIBY, "Memory operand using YMM index") \			ENUM_ENTRY(TYPE_MVSIBY, "Memory operand using YMM index") \
	ENUM_ENTRY(TYPE_MVSIBZ, "Memory operand using ZMM index") \			ENUM_ENTRY(TYPE_MVSIBZ, "Memory operand using ZMM index") \
	ENUM_ENTRY(TYPE_SRCIDX, "memory at source index") \			ENUM_ENTRY(TYPE_SRCIDX, "memory at source index") \
	ENUM_ENTRY(TYPE_DSTIDX, "memory at destination index") \			ENUM_ENTRY(TYPE_DSTIDX, "memory at destination index") \
	ENUM_ENTRY(TYPE_MOFFS, "memory offset (relative to segment base)") \			ENUM_ENTRY(TYPE_MOFFS, "memory offset (relative to segment base)") \
	ENUM_ENTRY(TYPE_ST, "Position on the floating-point stack") \			ENUM_ENTRY(TYPE_ST, "Position on the floating-point stack") \
	ENUM_ENTRY(TYPE_MM64, "8-byte MMX register") \			ENUM_ENTRY(TYPE_MM64, "8-byte MMX register") \
	ENUM_ENTRY(TYPE_XMM, "16-byte") \			ENUM_ENTRY(TYPE_XMM, "16-byte") \
	ENUM_ENTRY(TYPE_YMM, "32-byte") \			ENUM_ENTRY(TYPE_YMM, "32-byte") \
	ENUM_ENTRY(TYPE_ZMM, "64-byte") \			ENUM_ENTRY(TYPE_ZMM, "64-byte") \
				ENUM_ENTRY(TYPE_XMM_QUAD, "16-byte quad") \
				ENUM_ENTRY(TYPE_YMM_QUAD, "32-byte quad") \
				ENUM_ENTRY(TYPE_ZMM_QUAD, "64-byte quad") \
	ENUM_ENTRY(TYPE_VK, "mask register") \			ENUM_ENTRY(TYPE_VK, "mask register") \
	ENUM_ENTRY(TYPE_VK_PAIR, "mask register pair") \			ENUM_ENTRY(TYPE_VK_PAIR, "mask register pair") \
	ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand") \			ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand") \
	ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \			ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \
				Lint: Pre-merge checks Inline Actions clang-format: please reformat the code - ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \ + ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \ Lint: Pre-merge checks: clang-format: please reformat the code ``` - ENUM_ENTRY(TYPE_DEBUGREG, "Debug register…
	ENUM_ENTRY(TYPE_CONTROLREG, "Control register operand") \			ENUM_ENTRY(TYPE_CONTROLREG, "Control register operand") \
	ENUM_ENTRY(TYPE_BNDR, "MPX bounds register") \			ENUM_ENTRY(TYPE_BNDR, "MPX bounds register") \
				Lint: Pre-merge checks Inline Actions clang-format: please reformat the code - ENUM_ENTRY(TYPE_BNDR, "MPX bounds register") \ + ENUM_ENTRY(TYPE_BNDR, "MPX bounds register") \ Lint: Pre-merge checks: clang-format: please reformat the code ``` - ENUM_ENTRY(TYPE_BNDR, "MPX bounds…
	\			\
	ENUM_ENTRY(TYPE_Rv, "Register operand of operand size") \			ENUM_ENTRY(TYPE_Rv, "Register operand of operand size") \
				Lint: Pre-merge checks Inline Actions clang-format: please reformat the code - ENUM_ENTRY(TYPE_Rv, "Register operand of operand size") \ - ENUM_ENTRY(TYPE_RELv, "Immediate address of operand size") \ - ENUM_ENTRY(TYPE_DUP0, "Duplicate of operand 0") \ - ENUM_ENTRY(TYPE_DUP1, "operand 1") \ - ENUM_ENTRY(TYPE_DUP2, "operand 2") \ - ENUM_ENTRY(TYPE_DUP3, "operand 3") \ - ENUM_ENTRY(TYPE_DUP4, "operand 4") \ + ENUM_ENTRY(TYPE_Rv, "Register operand of operand size") \ + ENUM_ENTRY(TYPE_RELv, "Immediate address of operand size") \ + ENUM_ENTRY(TYPE_DUP0, "Duplicate of operand 0") \ 4 diff lines are omitted. See full diff. Lint: Pre-merge checks: clang-format: please reformat the code ``` - ENUM_ENTRY(TYPE_Rv, "Register operand of…
	ENUM_ENTRY(TYPE_RELv, "Immediate address of operand size") \			ENUM_ENTRY(TYPE_RELv, "Immediate address of operand size") \
	ENUM_ENTRY(TYPE_DUP0, "Duplicate of operand 0") \			ENUM_ENTRY(TYPE_DUP0, "Duplicate of operand 0") \
	ENUM_ENTRY(TYPE_DUP1, "operand 1") \			ENUM_ENTRY(TYPE_DUP1, "operand 1") \
	ENUM_ENTRY(TYPE_DUP2, "operand 2") \			ENUM_ENTRY(TYPE_DUP2, "operand 2") \
	ENUM_ENTRY(TYPE_DUP3, "operand 3") \			ENUM_ENTRY(TYPE_DUP3, "operand 3") \
	ENUM_ENTRY(TYPE_DUP4, "operand 4") \			ENUM_ENTRY(TYPE_DUP4, "operand 4") \

	#define ENUM_ENTRY(n, d) n,			#define ENUM_ENTRY(n, d) n,
	Show All 27 Lines

llvm/lib/Target/X86/AsmParser/X86Operand.h

//===- X86Operand.h - Parsed X86 machine instruction ------------- C++ --===//		//===- X86Operand.h - Parsed X86 machine instruction ------------- C++ --===//
		Lint: Lint Inline Actions clang-format not found in user's PATH; not linting file. Lint: Lint: clang-format not found in user's PATH; not linting file.
//		//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.		// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.		// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception		// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//		//
//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//

▲ Show 20 Lines • Show All 467 Lines • ▼ Show 20 Lines	return Kind == Register &&
X86MCRegisterClasses[X86::VK8RegClassID].contains(getReg());		X86MCRegisterClasses[X86::VK8RegClassID].contains(getReg());
}		}

bool isVK16Pair() const {		bool isVK16Pair() const {
return Kind == Register &&		return Kind == Register &&
X86MCRegisterClasses[X86::VK16RegClassID].contains(getReg());		X86MCRegisterClasses[X86::VK16RegClassID].contains(getReg());
}		}

		bool isVR128XQuad() const {
		return Kind == Register &&
		X86MCRegisterClasses[X86::VR128XRegClassID].contains(getReg());
		Lint: Pre-merge checks Inline Actions clang-format: please reformat the code - X86MCRegisterClasses[X86::VR128XRegClassID].contains(getReg()); + X86MCRegisterClasses[X86::VR128XRegClassID].contains(getReg()); Lint: Pre-merge checks: clang-format: please reformat the code ``` - X86MCRegisterClasses[X86::VR128XRegClassID].
		}

		bool isVR512Quad() const {
		return Kind == Register &&
		X86MCRegisterClasses[X86::VR512RegClassID].contains(getReg());
		Lint: Pre-merge checks Inline Actions clang-format: please reformat the code - X86MCRegisterClasses[X86::VR512RegClassID].contains(getReg()); + X86MCRegisterClasses[X86::VR512RegClassID].contains(getReg()); Lint: Pre-merge checks: clang-format: please reformat the code ``` - X86MCRegisterClasses[X86::VR512RegClassID].
		}

void addExpr(MCInst &Inst, const MCExpr *Expr) const {		void addExpr(MCInst &Inst, const MCExpr *Expr) const {
// Add as immediates when possible.		// Add as immediates when possible.
if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))		if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
Inst.addOperand(MCOperand::createImm(CE->getValue()));		Inst.addOperand(MCOperand::createImm(CE->getValue()));
else		else
Inst.addOperand(MCOperand::createExpr(Expr));		Inst.addOperand(MCOperand::createExpr(Expr));
}		}

Show All 39 Lines	void addMaskPairOperands(MCInst &Inst, unsigned N) const {
case X86::K6:		case X86::K6:
case X86::K7:		case X86::K7:
Reg = X86::K6_K7;		Reg = X86::K6_K7;
break;		break;
}		}
Inst.addOperand(MCOperand::createReg(Reg));		Inst.addOperand(MCOperand::createReg(Reg));
}		}

		void addQuadRegOperands(MCInst &Inst, unsigned N) const {
		assert(N == 1 && "Invalid number of operands!");
		unsigned Reg = getReg();
		switch (Reg) {
		default: llvm_unreachable("Unexpected register!");
		Lint: Pre-merge checks Inline Actions clang-format: please reformat the code - default: llvm_unreachable("Unexpected register!"); - case X86::XMM1: case X86::XMM2: case X86::XMM3: - case X86::XMM5: case X86::XMM6: case X86::XMM7: - case X86::XMM9: case X86::XMM10: case X86::XMM11: - case X86::XMM13: case X86::XMM14: case X86::XMM15: - case X86::XMM17: case X86::XMM18: case X86::XMM19: - case X86::XMM21: case X86::XMM22: case X86::XMM23: - case X86::XMM25: case X86::XMM26: case X86::XMM27: - case X86::XMM29: case X86::XMM30: case X86::XMM31: - case X86::ZMM1: case X86::ZMM2: case X86::ZMM3: 57 diff lines are omitted. See full diff. Lint: Pre-merge checks: clang-format: please reformat the code ``` - default: llvm_unreachable("Unexpected register!
		case X86::XMM1: case X86::XMM2: case X86::XMM3:
		case X86::XMM5: case X86::XMM6: case X86::XMM7:
		case X86::XMM9: case X86::XMM10: case X86::XMM11:
		case X86::XMM13: case X86::XMM14: case X86::XMM15:
		case X86::XMM17: case X86::XMM18: case X86::XMM19:
		case X86::XMM21: case X86::XMM22: case X86::XMM23:
		case X86::XMM25: case X86::XMM26: case X86::XMM27:
		case X86::XMM29: case X86::XMM30: case X86::XMM31:
		case X86::ZMM1: case X86::ZMM2: case X86::ZMM3:
		case X86::ZMM5: case X86::ZMM6: case X86::ZMM7:
		case X86::ZMM9: case X86::ZMM10: case X86::ZMM11:
		case X86::ZMM13: case X86::ZMM14: case X86::ZMM15:
		case X86::ZMM17: case X86::ZMM18: case X86::ZMM19:
		case X86::ZMM21: case X86::ZMM22: case X86::ZMM23:
		case X86::ZMM25: case X86::ZMM26: case X86::ZMM27:
		case X86::ZMM29: case X86::ZMM30: case X86::ZMM31:
		// Leave the unaligned register alone so we can generate their encoding.
		break;
		case X86::XMM0:
		Reg = X86::XMM0_XMM1_XMM2_XMM3;
		break;
		case X86::XMM4:
		Reg = X86::XMM4_XMM5_XMM6_XMM7;
		break;
		case X86::XMM8:
		Reg = X86::XMM8_XMM9_XMM10_XMM11;
		break;
		case X86::XMM12:
		Reg = X86::XMM12_XMM13_XMM14_XMM15;
		break;
		case X86::XMM16:
		Reg = X86::XMM16_XMM17_XMM18_XMM19;
		break;
		case X86::XMM20:
		Reg = X86::XMM20_XMM21_XMM22_XMM23;
		break;
		case X86::XMM24:
		Reg = X86::XMM24_XMM25_XMM26_XMM27;
		break;
		case X86::XMM28:
		Reg = X86::XMM28_XMM29_XMM30_XMM31;
		break;
		case X86::ZMM0:
		Reg = X86::ZMM0_ZMM1_ZMM2_ZMM3;
		break;
		case X86::ZMM4:
		Reg = X86::ZMM4_ZMM5_ZMM6_ZMM7;
		break;
		case X86::ZMM8:
		Reg = X86::ZMM8_ZMM9_ZMM10_ZMM11;
		break;
		case X86::ZMM12:
		Reg = X86::ZMM12_ZMM13_ZMM14_ZMM15;
		break;
		case X86::ZMM16:
		Reg = X86::ZMM16_ZMM17_ZMM18_ZMM19;
		break;
		case X86::ZMM20:
		Reg = X86::ZMM20_ZMM21_ZMM22_ZMM23;
		break;
		case X86::ZMM24:
		Reg = X86::ZMM24_ZMM25_ZMM26_ZMM27;
		break;
		case X86::ZMM28:
		Reg = X86::ZMM28_ZMM29_ZMM30_ZMM31;
		break;
		}
		Inst.addOperand(MCOperand::createReg(Reg));
		}

void addMemOperands(MCInst &Inst, unsigned N) const {		void addMemOperands(MCInst &Inst, unsigned N) const {
assert((N == 5) && "Invalid number of operands!");		assert((N == 5) && "Invalid number of operands!");
Inst.addOperand(MCOperand::createReg(getMemBaseReg()));		Inst.addOperand(MCOperand::createReg(getMemBaseReg()));
Inst.addOperand(MCOperand::createImm(getMemScale()));		Inst.addOperand(MCOperand::createImm(getMemScale()));
Inst.addOperand(MCOperand::createReg(getMemIndexReg()));		Inst.addOperand(MCOperand::createReg(getMemIndexReg()));
addExpr(Inst, getMemDisp());		addExpr(Inst, getMemDisp());
Inst.addOperand(MCOperand::createReg(getMemSegReg()));		Inst.addOperand(MCOperand::createReg(getMemSegReg()));
}		}
▲ Show 20 Lines • Show All 130 Lines • Show Last 20 Lines

llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp

//===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===//		//===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===//
		Lint: Lint Inline Actions clang-format not found in user's PATH; not linting file. Lint: Lint: clang-format not found in user's PATH; not linting file.
//		//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.		// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.		// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception		// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//		//
//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//
//		//
▲ Show 20 Lines • Show All 762 Lines • ▼ Show 20 Lines	case TYPE_R64: \
*valid = 0; \		*valid = 0; \
return prefix##_RAX + index; \		return prefix##_RAX + index; \
case TYPE_ZMM: \		case TYPE_ZMM: \
return prefix##_ZMM0 + index; \		return prefix##_ZMM0 + index; \
case TYPE_YMM: \		case TYPE_YMM: \
return prefix##_YMM0 + index; \		return prefix##_YMM0 + index; \
case TYPE_XMM: \		case TYPE_XMM: \
return prefix##_XMM0 + index; \		return prefix##_XMM0 + index; \
		case TYPE_ZMM_QUAD: \
		return prefix##_ZMM0_ZMM1_ZMM2_ZMM3 + (index / 4); \
		case TYPE_XMM_QUAD: \
		return prefix##_XMM0_XMM1_XMM2_XMM3 + (index / 4); \
case TYPE_VK: \		case TYPE_VK: \
index &= 0xf; \		index &= 0xf; \
if (index > 7) \		if (index > 7) \
*valid = 0; \		*valid = 0; \
return prefix##_K0 + index; \		return prefix##_K0 + index; \
case TYPE_VK_PAIR: \		case TYPE_VK_PAIR: \
if (index > 7) \		if (index > 7) \
*valid = 0; \		*valid = 0; \
▲ Show 20 Lines • Show All 1,555 Lines • Show Last 20 Lines

llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h

//===-- X86DisassemblerDecoderInternal.h - Disassembler decoder -- C++ --===//		//===-- X86DisassemblerDecoderInternal.h - Disassembler decoder -- C++ --===//
		Lint: Lint Inline Actions clang-format not found in user's PATH; not linting file. Lint: Lint: clang-format not found in user's PATH; not linting file.
//		//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.		// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.		// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception		// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//		//
//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//
//		//
▲ Show 20 Lines • Show All 300 Lines • ▼ Show 20 Lines	#define REGS_ZMM \
ENTRY(ZMM25) \		ENTRY(ZMM25) \
ENTRY(ZMM26) \		ENTRY(ZMM26) \
ENTRY(ZMM27) \		ENTRY(ZMM27) \
ENTRY(ZMM28) \		ENTRY(ZMM28) \
ENTRY(ZMM29) \		ENTRY(ZMM29) \
ENTRY(ZMM30) \		ENTRY(ZMM30) \
ENTRY(ZMM31)		ENTRY(ZMM31)

		#define REGS_XMM_QUADS \
		Lint: Pre-merge checks Inline Actions clang-format: please reformat the code -#define REGS_XMM_QUADS \ - ENTRY(XMM0_XMM1_XMM2_XMM3) \ - ENTRY(XMM4_XMM5_XMM6_XMM7) \ - ENTRY(XMM8_XMM9_XMM10_XMM11) \ - ENTRY(XMM12_XMM13_XMM14_XMM15) \ - ENTRY(XMM16_XMM17_XMM18_XMM19) \ - ENTRY(XMM20_XMM21_XMM22_XMM23) \ - ENTRY(XMM24_XMM25_XMM26_XMM27) \ +#define REGS_XMM_QUADS \ + ENTRY(XMM0_XMM1_XMM2_XMM3) \ 6 diff lines are omitted. See full diff. Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define REGS_XMM_QUADS \ - ENTRY…
		ENTRY(XMM0_XMM1_XMM2_XMM3) \
		ENTRY(XMM4_XMM5_XMM6_XMM7) \
		ENTRY(XMM8_XMM9_XMM10_XMM11) \
		ENTRY(XMM12_XMM13_XMM14_XMM15) \
		ENTRY(XMM16_XMM17_XMM18_XMM19) \
		ENTRY(XMM20_XMM21_XMM22_XMM23) \
		ENTRY(XMM24_XMM25_XMM26_XMM27) \
		ENTRY(XMM28_XMM29_XMM30_XMM31)

		#define REGS_ZMM_QUADS \
		Lint: Pre-merge checks Inline Actions clang-format: please reformat the code -#define REGS_ZMM_QUADS \ - ENTRY(ZMM0_ZMM1_ZMM2_ZMM3) \ - ENTRY(ZMM4_ZMM5_ZMM6_ZMM7) \ - ENTRY(ZMM8_ZMM9_ZMM10_ZMM11) \ - ENTRY(ZMM12_ZMM13_ZMM14_ZMM15) \ - ENTRY(ZMM16_ZMM17_ZMM18_ZMM19) \ - ENTRY(ZMM20_ZMM21_ZMM22_ZMM23) \ - ENTRY(ZMM24_ZMM25_ZMM26_ZMM27) \ +#define REGS_ZMM_QUADS \ + ENTRY(ZMM0_ZMM1_ZMM2_ZMM3) \ 6 diff lines are omitted. See full diff. Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define REGS_ZMM_QUADS \ - ENTRY…
		ENTRY(ZMM0_ZMM1_ZMM2_ZMM3) \
		ENTRY(ZMM4_ZMM5_ZMM6_ZMM7) \
		ENTRY(ZMM8_ZMM9_ZMM10_ZMM11) \
		ENTRY(ZMM12_ZMM13_ZMM14_ZMM15) \
		ENTRY(ZMM16_ZMM17_ZMM18_ZMM19) \
		ENTRY(ZMM20_ZMM21_ZMM22_ZMM23) \
		ENTRY(ZMM24_ZMM25_ZMM26_ZMM27) \
		ENTRY(ZMM28_ZMM29_ZMM30_ZMM31)

#define REGS_MASKS \		#define REGS_MASKS \
ENTRY(K0) \		ENTRY(K0) \
ENTRY(K1) \		ENTRY(K1) \
ENTRY(K2) \		ENTRY(K2) \
ENTRY(K3) \		ENTRY(K3) \
ENTRY(K4) \		ENTRY(K4) \
ENTRY(K5) \		ENTRY(K5) \
ENTRY(K6) \		ENTRY(K6) \
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines	#define ALL_EA_BASES \
EA_BASES_16BIT \		EA_BASES_16BIT \
EA_BASES_32BIT \		EA_BASES_32BIT \
EA_BASES_64BIT		EA_BASES_64BIT

#define ALL_SIB_BASES \		#define ALL_SIB_BASES \
REGS_32BIT \		REGS_32BIT \
REGS_64BIT		REGS_64BIT

#define ALL_REGS \		#define ALL_REGS \
		Lint: Pre-merge checks Inline Actions clang-format: please reformat the code -#define ALL_REGS \ - REGS_8BIT \ - REGS_16BIT \ - REGS_32BIT \ - REGS_64BIT \ - REGS_MMX \ - REGS_XMM \ - REGS_YMM \ - REGS_ZMM \ - REGS_XMM_QUADS \ 24 diff lines are omitted. See full diff. Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define ALL_REGS \ - REGS_8BIT \…
REGS_8BIT \		REGS_8BIT \
REGS_16BIT \		REGS_16BIT \
REGS_32BIT \		REGS_32BIT \
REGS_64BIT \		REGS_64BIT \
REGS_MMX \		REGS_MMX \
REGS_XMM \		REGS_XMM \
REGS_YMM \		REGS_YMM \
REGS_ZMM \		REGS_ZMM \
		REGS_XMM_QUADS \
		REGS_ZMM_QUADS \
REGS_MASKS \		REGS_MASKS \
REGS_MASK_PAIRS \		REGS_MASK_PAIRS \
REGS_SEGMENT \		REGS_SEGMENT \
REGS_DEBUG \		REGS_DEBUG \
REGS_CONTROL \		REGS_CONTROL \
REGS_BOUND \		REGS_BOUND \
ENTRY(RIP)		ENTRY(RIP)

▲ Show 20 Lines • Show All 227 Lines • Show Last 20 Lines

llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.h

//===-- X86InstPrinterCommon.cpp - X86 assembly instruction printing ------===//		//===-- X86InstPrinterCommon.cpp - X86 assembly instruction printing ------===//
		Lint: Lint Inline Actions clang-format not found in user's PATH; not linting file. Lint: Lint: clang-format not found in user's PATH; not linting file.
//		//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.		// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.		// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception		// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//		//
//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//
//		//
Show All 22 Lines	public:
void printRoundingControl(const MCInst *MI, unsigned Op, raw_ostream &O);		void printRoundingControl(const MCInst *MI, unsigned Op, raw_ostream &O);
void printPCRelImm(const MCInst *MI, uint64_t Address, unsigned OpNo,		void printPCRelImm(const MCInst *MI, uint64_t Address, unsigned OpNo,
raw_ostream &O);		raw_ostream &O);

protected:		protected:
void printInstFlags(const MCInst *MI, raw_ostream &O);		void printInstFlags(const MCInst *MI, raw_ostream &O);
void printOptionalSegReg(const MCInst *MI, unsigned OpNo, raw_ostream &O);		void printOptionalSegReg(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printVKPair(const MCInst *MI, unsigned OpNo, raw_ostream &OS);		void printVKPair(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
		void printQuadReg(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
};		};

} // end namespace llvm		} // end namespace llvm

#endif // LLVM_LIB_TARGET_X86_MCTARGETDESC_X86ATTINSTPRINTER_H		#endif // LLVM_LIB_TARGET_X86_MCTARGETDESC_X86ATTINSTPRINTER_H

llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp

//===--- X86InstPrinterCommon.cpp - X86 assembly instruction printing -----===//		//===--- X86InstPrinterCommon.cpp - X86 assembly instruction printing -----===//
		Lint: Lint Inline Actions clang-format not found in user's PATH; not linting file. Lint: Lint: clang-format not found in user's PATH; not linting file.
//		//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.		// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.		// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception		// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//		//
//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//
//		//
▲ Show 20 Lines • Show All 354 Lines • ▼ Show 20 Lines	case X86::K4_K5:
printRegName(OS, X86::K4);		printRegName(OS, X86::K4);
return;		return;
case X86::K6_K7:		case X86::K6_K7:
printRegName(OS, X86::K6);		printRegName(OS, X86::K6);
return;		return;
}		}
llvm_unreachable("Unknown mask pair register name");		llvm_unreachable("Unknown mask pair register name");
}		}

		void X86InstPrinterCommon::printQuadReg(const MCInst *MI, unsigned OpNo,
		raw_ostream &OS) {
		unsigned Reg = MI->getOperand(OpNo).getReg();
		switch (Reg) {
		case X86::XMM1: case X86::XMM2: case X86::XMM3:
		Lint: Pre-merge checks Inline Actions clang-format: please reformat the code - case X86::XMM1: case X86::XMM2: case X86::XMM3: - case X86::XMM5: case X86::XMM6: case X86::XMM7: - case X86::XMM9: case X86::XMM10: case X86::XMM11: - case X86::XMM13: case X86::XMM14: case X86::XMM15: - case X86::XMM17: case X86::XMM18: case X86::XMM19: - case X86::XMM21: case X86::XMM22: case X86::XMM23: - case X86::XMM25: case X86::XMM26: case X86::XMM27: - case X86::XMM29: case X86::XMM30: case X86::XMM31: - case X86::ZMM1: case X86::ZMM2: case X86::ZMM3: - case X86::ZMM5: case X86::ZMM6: case X86::ZMM7: 54 diff lines are omitted. See full diff. Lint: Pre-merge checks: clang-format: please reformat the code ``` - case X86::XMM1: case X86::XMM2: case X86::XMM3…
		case X86::XMM5: case X86::XMM6: case X86::XMM7:
		case X86::XMM9: case X86::XMM10: case X86::XMM11:
		case X86::XMM13: case X86::XMM14: case X86::XMM15:
		case X86::XMM17: case X86::XMM18: case X86::XMM19:
		case X86::XMM21: case X86::XMM22: case X86::XMM23:
		case X86::XMM25: case X86::XMM26: case X86::XMM27:
		case X86::XMM29: case X86::XMM30: case X86::XMM31:
		case X86::ZMM1: case X86::ZMM2: case X86::ZMM3:
		case X86::ZMM5: case X86::ZMM6: case X86::ZMM7:
		case X86::ZMM9: case X86::ZMM10: case X86::ZMM11:
		case X86::ZMM13: case X86::ZMM14: case X86::ZMM15:
		case X86::ZMM17: case X86::ZMM18: case X86::ZMM19:
		case X86::ZMM21: case X86::ZMM22: case X86::ZMM23:
		case X86::ZMM25: case X86::ZMM26: case X86::ZMM27:
		case X86::ZMM29: case X86::ZMM30: case X86::ZMM31:
		// We can get unaligned values from the parser, just print them.
		printRegName(OS, Reg);
		return;
		case X86::XMM0_XMM1_XMM2_XMM3:
		printRegName(OS, X86::XMM0);
		return;
		case X86::XMM4_XMM5_XMM6_XMM7:
		printRegName(OS, X86::XMM4);
		return;
		case X86::XMM8_XMM9_XMM10_XMM11:
		printRegName(OS, X86::XMM8);
		return;
		case X86::XMM12_XMM13_XMM14_XMM15:
		printRegName(OS, X86::XMM12);
		return;
		case X86::XMM16_XMM17_XMM18_XMM19:
		printRegName(OS, X86::XMM16);
		return;
		case X86::XMM20_XMM21_XMM22_XMM23:
		printRegName(OS, X86::XMM20);
		return;
		case X86::XMM24_XMM25_XMM26_XMM27:
		printRegName(OS, X86::XMM24);
		return;
		case X86::XMM28_XMM29_XMM30_XMM31:
		printRegName(OS, X86::XMM28);
		return;
		case X86::ZMM0_ZMM1_ZMM2_ZMM3:
		printRegName(OS, X86::ZMM0);
		return;
		case X86::ZMM4_ZMM5_ZMM6_ZMM7:
		printRegName(OS, X86::ZMM4);
		return;
		case X86::ZMM8_ZMM9_ZMM10_ZMM11:
		printRegName(OS, X86::ZMM8);
		return;
		case X86::ZMM12_ZMM13_ZMM14_ZMM15:
		printRegName(OS, X86::ZMM12);
		return;
		case X86::ZMM16_ZMM17_ZMM18_ZMM19:
		printRegName(OS, X86::ZMM16);
		return;
		case X86::ZMM20_ZMM21_ZMM22_ZMM23:
		printRegName(OS, X86::ZMM20);
		return;
		case X86::ZMM24_ZMM25_ZMM26_ZMM27:
		printRegName(OS, X86::ZMM24);
		return;
		case X86::ZMM28_ZMM29_ZMM30_ZMM31:
		printRegName(OS, X86::ZMM28);
		return;
		}
		llvm_unreachable("Unknown quad reg register name");
		}

llvm/lib/Target/X86/X86.td

Show First 20 Lines • Show All 127 Lines • ▼ Show 20 Lines	def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",
"Support 16-bit floating point conversion instructions",		"Support 16-bit floating point conversion instructions",
[FeatureAVX]>;		[FeatureAVX]>;
def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",		def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
"Enable AVX-512 instructions",		"Enable AVX-512 instructions",
[FeatureAVX2, FeatureFMA, FeatureF16C]>;		[FeatureAVX2, FeatureFMA, FeatureF16C]>;
def FeatureERI : SubtargetFeature<"avx512er", "HasERI", "true",		def FeatureERI : SubtargetFeature<"avx512er", "HasERI", "true",
"Enable AVX-512 Exponential and Reciprocal Instructions",		"Enable AVX-512 Exponential and Reciprocal Instructions",
[FeatureAVX512]>;		[FeatureAVX512]>;
		def FeatureAVX5124FMAPS : SubtargetFeature<"avx5124fmaps", "HasAVX5124FMAPS", "true",
		"Enable AVX-512 4FMAPS Instructions",
		[FeatureAVX512]>;
		def FeatureAVX5124VNNI : SubtargetFeature<"avx5124vnni", "HasAVX5124FMAPS", "true",
		"Enable AVX-512 4VNNI Instructions",
		[FeatureAVX512]>;
def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true",		def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true",
"Enable AVX-512 Conflict Detection Instructions",		"Enable AVX-512 Conflict Detection Instructions",
[FeatureAVX512]>;		[FeatureAVX512]>;
def FeatureVPOPCNTDQ : SubtargetFeature<"avx512vpopcntdq", "HasVPOPCNTDQ",		def FeatureVPOPCNTDQ : SubtargetFeature<"avx512vpopcntdq", "HasVPOPCNTDQ",
"true", "Enable AVX-512 Population Count Instructions",		"true", "Enable AVX-512 Population Count Instructions",
[FeatureAVX512]>;		[FeatureAVX512]>;
def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true",		def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true",
"Enable AVX-512 PreFetch Instructions",		"Enable AVX-512 PreFetch Instructions",
▲ Show 20 Lines • Show All 1,197 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86ISelLowering.h

//===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------- C++ --===//		//===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------- C++ --===//
		Lint: Lint Inline Actions clang-format not found in user's PATH; not linting file. Lint: Lint: clang-format not found in user's PATH; not linting file.
//		//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.		// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.		// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception		// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//		//
//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//
//		//
▲ Show 20 Lines • Show All 807 Lines • ▼ Show 20 Lines	enum NodeType : unsigned {
// Vector truncating masked store with unsigned/signed saturation		// Vector truncating masked store with unsigned/signed saturation
VMTRUNCSTOREUS,		VMTRUNCSTOREUS,
VMTRUNCSTORES,		VMTRUNCSTORES,

// X86 specific gather and scatter		// X86 specific gather and scatter
MGATHER,		MGATHER,
MSCATTER,		MSCATTER,

		// AVX5124FMAPS
		V4FMADD,
		V4FNMADD,

		// AVX5124VNNI
		VP4DPWSSD,
		VP4DPWSSDS,

// WARNING: Do not add anything in the end unless you want the node to		// WARNING: Do not add anything in the end unless you want the node to
// have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all		// have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all
// opcodes will be thought as target memory ops!		// opcodes will be thought as target memory ops!
};		};
} // end namespace X86ISD		} // end namespace X86ISD

/// Define some predicates that are used for node matching.		/// Define some predicates that are used for node matching.
namespace X86 {		namespace X86 {
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llvm/lib/Target/X86/X86ISelLowering.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//		//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
		Lint: Lint Inline Actions clang-format not found in user's PATH; not linting file. Lint: Lint: clang-format not found in user's PATH; not linting file.
//		//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.		// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.		// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception		// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//		//
//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//
//		//
▲ Show 20 Lines • Show All 4,978 Lines • ▼ Show 20 Lines	static bool hasFPCMov(unsigned X86CC) {
}		}
}		}


bool X86TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,		bool X86TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
const CallInst &I,		const CallInst &I,
MachineFunction &MF,		MachineFunction &MF,
unsigned Intrinsic) const {		unsigned Intrinsic) const {
		switch (Intrinsic) {
		case Intrinsic::x86_avx512_mask_vp4dpwssd_512:
		case Intrinsic::x86_avx512_mask_vp4dpwssds_512:
		case Intrinsic::x86_avx512_mask_v4fmadd_ps_512:
		case Intrinsic::x86_avx512_mask_v4fnmadd_ps_512:
		case Intrinsic::x86_avx512_mask_v4fmadd_ss:
		case Intrinsic::x86_avx512_mask_v4fnmadd_ss:
		switch (Intrinsic) {
		default: llvm_unreachable("Unexpected intrinsic");
		case Intrinsic::x86_avx512_mask_vp4dpwssd_512:
		Info.opc = X86ISD::VP4DPWSSD;
		Lint: Pre-merge checks Inline Actions clang-format: please reformat the code - default: llvm_unreachable("Unexpected intrinsic"); + default: + llvm_unreachable("Unexpected intrinsic"); Lint: Pre-merge checks: clang-format: please reformat the code ``` - default: llvm_unreachable("Unexpected…
		Info.memVT = MVT::v4i32;
		break;
		case Intrinsic::x86_avx512_mask_vp4dpwssds_512:
		Info.opc = X86ISD::VP4DPWSSDS;
		Info.memVT = MVT::v4i32;
		break;
		case Intrinsic::x86_avx512_mask_v4fmadd_ps_512:
		case Intrinsic::x86_avx512_mask_v4fmadd_ss:
		Info.opc = X86ISD::V4FMADD;
		Info.memVT = MVT::v4f32;
		break;
		case Intrinsic::x86_avx512_mask_v4fnmadd_ps_512:
		case Intrinsic::x86_avx512_mask_v4fnmadd_ss:
		Info.opc = X86ISD::V4FNMADD;
		Info.memVT = MVT::v4f32;
		break;
		}

		Info.ptrVal = I.getArgOperand(5);
		Info.offset = 0;
		Info.size = Info.memVT.getStoreSize();
		Info.align = Align(1);
		Info.flags = MachineMemOperand::MOLoad;
		return true;
		}

const IntrinsicData* IntrData = getIntrinsicWithChain(Intrinsic);		const IntrinsicData* IntrData = getIntrinsicWithChain(Intrinsic);
if (!IntrData)		if (!IntrData)
return false;		return false;

Info.flags = MachineMemOperand::MONone;		Info.flags = MachineMemOperand::MONone;
Info.offset = 0;		Info.offset = 0;

▲ Show 20 Lines • Show All 25,415 Lines • ▼ Show 20 Lines	#define NODE_NAME_CASE(NODE) case X86ISD::NODE: return "X86ISD::" #NODE;
NODE_NAME_CASE(DPBF16PS)		NODE_NAME_CASE(DPBF16PS)
NODE_NAME_CASE(LWPINS)		NODE_NAME_CASE(LWPINS)
NODE_NAME_CASE(MGATHER)		NODE_NAME_CASE(MGATHER)
NODE_NAME_CASE(MSCATTER)		NODE_NAME_CASE(MSCATTER)
NODE_NAME_CASE(VPDPBUSD)		NODE_NAME_CASE(VPDPBUSD)
NODE_NAME_CASE(VPDPBUSDS)		NODE_NAME_CASE(VPDPBUSDS)
NODE_NAME_CASE(VPDPWSSD)		NODE_NAME_CASE(VPDPWSSD)
NODE_NAME_CASE(VPDPWSSDS)		NODE_NAME_CASE(VPDPWSSDS)
		NODE_NAME_CASE(VP4DPWSSD)
		NODE_NAME_CASE(VP4DPWSSDS)
		NODE_NAME_CASE(V4FMADD)
		NODE_NAME_CASE(V4FNMADD)
NODE_NAME_CASE(VPSHUFBITQMB)		NODE_NAME_CASE(VPSHUFBITQMB)
NODE_NAME_CASE(GF2P8MULB)		NODE_NAME_CASE(GF2P8MULB)
NODE_NAME_CASE(GF2P8AFFINEQB)		NODE_NAME_CASE(GF2P8AFFINEQB)
NODE_NAME_CASE(GF2P8AFFINEINVQB)		NODE_NAME_CASE(GF2P8AFFINEINVQB)
NODE_NAME_CASE(NT_CALL)		NODE_NAME_CASE(NT_CALL)
NODE_NAME_CASE(NT_BRIND)		NODE_NAME_CASE(NT_BRIND)
NODE_NAME_CASE(UMWAIT)		NODE_NAME_CASE(UMWAIT)
NODE_NAME_CASE(TPAUSE)		NODE_NAME_CASE(TPAUSE)
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llvm/lib/Target/X86/X86InstrAVX512.td

This file is larger than 256 KB, so syntax highlighting is disabled by default.

Show First 20 Lines • Show All 12,124 Lines • ▼ Show 20 Lines	defm VGF2P8AFFINEQB : GF2P8AFFINE_avx512_common<0xCE, "vgf2p8affineqb",
X86GF2P8affineqb, SchedWriteVecIMul>,		X86GF2P8affineqb, SchedWriteVecIMul>,
EVEX_4V, EVEX_CD8<8, CD8VF>, VEX_W, AVX512AIi8Base;		EVEX_4V, EVEX_CD8<8, CD8VF>, VEX_W, AVX512AIi8Base;


//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//
// AVX5124FMAPS		// AVX5124FMAPS
//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//

		multiclass avx512_quad_pseudo<string InstrStr, SDNode OpNode,
		X86VectorVTInfo _, RegisterClass QuadRC,
		SubRegIndex subreg0, SubRegIndex subreg1,
		SubRegIndex subreg2, SubRegIndex subreg3> {
		def : Pat<(_.VT (OpNode _.RC:$src1, _.RC:$src2a, _.RC:$src2b, _.RC:$src2c,
		_.RC:$src2d, addr:$src3, (_.KVT immAllOnesV))),
		(!cast<Instruction>(InstrStr#"rm")
		_.RC:$src1, (REG_SEQUENCE QuadRC, _.RC:$src2a, subreg0,
		_.RC:$src2b, subreg1,
		_.RC:$src2c, subreg2,
		_.RC:$src2d, subreg3),
		addr:$src3)>;

		def : Pat<(_.VT (OpNode _.RC:$src1, _.RC:$src2a, _.RC:$src2b, _.RC:$src2c,
		_.RC:$src2d, addr:$src3, _.KRCWM:$mask)),
		(!cast<Instruction>(InstrStr#"rmkz")
		_.RC:$src1, _.KRCWM:$mask,
		(REG_SEQUENCE QuadRC, _.RC:$src2a, subreg0,
		_.RC:$src2b, subreg1,
		_.RC:$src2c, subreg2,
		_.RC:$src2d, subreg3),
		addr:$src3)>;

		def : Pat<(_.VT (vselect _.KRCWM:$mask, (OpNode _.RC:$src1, _.RC:$src2a,
		_.RC:$src2b, _.RC:$src2c,
		_.RC:$src2d, addr:$src3,
		_.KRCWM:$mask),
		_.RC:$src1)),
		(!cast<Instruction>(InstrStr#"rmk")
		_.RC:$src1, _.KRCWM:$mask,
		(REG_SEQUENCE QuadRC, _.RC:$src2a, subreg0,
		_.RC:$src2b, subreg1,
		_.RC:$src2c, subreg2,
		_.RC:$src2d, subreg3),
		addr:$src3)>;

		def : Pat<(_.VT (vselect _.KRCWM:$mask, (OpNode _.RC:$src1, _.RC:$src2a,
		_.RC:$src2b, _.RC:$src2c,
		_.RC:$src2d, addr:$src3,
		_.KRCWM:$mask),
		_.ImmAllZerosV)),
		(!cast<Instruction>(InstrStr#"rmkz")
		_.RC:$src1, _.KRCWM:$mask,
		(REG_SEQUENCE QuadRC, _.RC:$src2a, subreg0,
		_.RC:$src2b, subreg1,
		_.RC:$src2c, subreg2,
		_.RC:$src2d, subreg3),
		addr:$src3)>;
		}

		multiclass avx512_quad_pseudo_scalar<string InstrStr, SDNode OpNode,
		X86VectorVTInfo _, RegisterClass QuadRC,
		SubRegIndex subreg0, SubRegIndex subreg1,
		SubRegIndex subreg2, SubRegIndex subreg3> {
		def : Pat<(_.VT (OpNode _.RC:$src1, _.RC:$src2a, _.RC:$src2b, _.RC:$src2c,
		_.RC:$src2d, addr:$src3, (_.KVT immAllOnesV))),
		(!cast<Instruction>(InstrStr#"rm")
		_.RC:$src1, (REG_SEQUENCE QuadRC, _.RC:$src2a, subreg0,
		_.RC:$src2b, subreg1,
		_.RC:$src2c, subreg2,
		_.RC:$src2d, subreg3),
		addr:$src3)>;
		def : Pat<(_.VT (OpNode _.RC:$src1, _.RC:$src2a, _.RC:$src2b, _.RC:$src2c,
		_.RC:$src2d, addr:$src3, _.KRCWM:$mask)),
		(!cast<Instruction>(InstrStr#"rmkz")
		_.RC:$src1, _.KRCWM:$mask,
		(REG_SEQUENCE QuadRC, _.RC:$src2a, subreg0,
		_.RC:$src2b, subreg1,
		_.RC:$src2c, subreg2,
		_.RC:$src2d, subreg3),
		addr:$src3)>;
		}

let hasSideEffects = 0, mayLoad = 1, ExeDomain = SSEPackedSingle,		let hasSideEffects = 0, mayLoad = 1, ExeDomain = SSEPackedSingle,
Constraints = "$src1 = $dst", Uses = [MXCSR], mayRaiseFPException = 1 in {		Constraints = "$src1 = $dst", Uses = [MXCSR], mayRaiseFPException = 1 in {
		let hasExtraSrcRegAllocReq = 1 in {
defm V4FMADDPSrm : AVX512_maskable_3src_in_asm<0x9A, MRMSrcMem, v16f32_info,		defm V4FMADDPSrm : AVX512_maskable_3src_in_asm<0x9A, MRMSrcMem, v16f32_info,
(outs VR512:$dst), (ins VR512:$src2, f128mem:$src3),		(outs VR512:$dst), (ins VR512Quad:$src2, f128mem:$src3),
"v4fmaddps", "$src3, $src2", "$src2, $src3",		"v4fmaddps", "$src3, $src2", "$src2, $src3",
[]>, EVEX_V512, EVEX_4V, T8XD, EVEX_CD8<32, CD8VQ>,		[]>, EVEX_V512, EVEX_4V, T8XD, EVEX_CD8<32, CD8VQ>;
Sched<[SchedWriteFMA.ZMM.Folded]>;

defm V4FNMADDPSrm : AVX512_maskable_3src_in_asm<0xAA, MRMSrcMem, v16f32_info,		defm V4FNMADDPSrm : AVX512_maskable_3src_in_asm<0xAA, MRMSrcMem, v16f32_info,
(outs VR512:$dst), (ins VR512:$src2, f128mem:$src3),		(outs VR512:$dst), (ins VR512Quad:$src2, f128mem:$src3),
"v4fnmaddps", "$src3, $src2", "$src2, $src3",		"v4fnmaddps", "$src3, $src2", "$src2, $src3",
[]>, EVEX_V512, EVEX_4V, T8XD, EVEX_CD8<32, CD8VQ>,		[]>, EVEX_V512, EVEX_4V, T8XD, EVEX_CD8<32, CD8VQ>;
Sched<[SchedWriteFMA.ZMM.Folded]>;

defm V4FMADDSSrm : AVX512_maskable_3src_in_asm<0x9B, MRMSrcMem, f32x_info,		defm V4FMADDSSrm : AVX512_maskable_3src_in_asm<0x9B, MRMSrcMem, f32x_info,
(outs VR128X:$dst), (ins VR128X:$src2, f128mem:$src3),		(outs VR128X:$dst), (ins VR128XQuad:$src2, f128mem:$src3),
"v4fmaddss", "$src3, $src2", "$src2, $src3",		"v4fmaddss", "$src3, $src2", "$src2, $src3",
[]>, VEX_LIG, EVEX_4V, T8XD, EVEX_CD8<32, CD8VF>,		[]>, EVEX_V128, EVEX_4V, T8XD, EVEX_CD8<32, CD8VF>;
Sched<[SchedWriteFMA.Scl.Folded]>;

defm V4FNMADDSSrm : AVX512_maskable_3src_in_asm<0xAB, MRMSrcMem, f32x_info,		defm V4FNMADDSSrm : AVX512_maskable_3src_in_asm<0xAB, MRMSrcMem, f32x_info,
(outs VR128X:$dst), (ins VR128X:$src2, f128mem:$src3),		(outs VR128X:$dst), (ins VR128XQuad:$src2, f128mem:$src3),
"v4fnmaddss", "$src3, $src2", "$src2, $src3",		"v4fnmaddss", "$src3, $src2", "$src2, $src3",
[]>, VEX_LIG, EVEX_4V, T8XD, EVEX_CD8<32, CD8VF>,		[]>, EVEX_V128, EVEX_4V, T8XD, EVEX_CD8<32, CD8VF>;
Sched<[SchedWriteFMA.Scl.Folded]>;		}
		}

		let Predicates = [HasAVX5124FMAPS] in {
		defm : avx512_quad_pseudo<"V4FMADDPS", X86v4fmadd, v16f32_info, VR512QUAD,
		zsub_0, zsub_1, zsub_2, zsub_3>;
		defm : avx512_quad_pseudo<"V4FNMADDPS", X86v4fnmadd, v16f32_info, VR512QUAD,
		zsub_0, zsub_1, zsub_2, zsub_3>;

		defm : avx512_quad_pseudo_scalar<"V4FMADDSS", X86v4fmadd, f32x_info, VR128XQUAD,
		xsub_0, xsub_1, xsub_2, xsub_3>;
		defm : avx512_quad_pseudo_scalar<"V4FNMADDSS", X86v4fnmadd, f32x_info, VR128XQUAD,
		xsub_0, xsub_1, xsub_2, xsub_3>;
}		}

//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//
// AVX5124VNNIW		// AVX5124VNNIW
//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//

let hasSideEffects = 0, mayLoad = 1, ExeDomain = SSEPackedInt,		let hasSideEffects = 0, mayLoad = 1, ExeDomain = SSEPackedInt,
Constraints = "$src1 = $dst" in {		Constraints = "$src1 = $dst" in {
		let hasExtraSrcRegAllocReq = 1 in {
defm VP4DPWSSDrm : AVX512_maskable_3src_in_asm<0x52, MRMSrcMem, v16i32_info,		defm VP4DPWSSDrm : AVX512_maskable_3src_in_asm<0x52, MRMSrcMem, v16i32_info,
(outs VR512:$dst), (ins VR512:$src2, f128mem:$src3),		(outs VR512:$dst), (ins VR512Quad:$src2, i128mem:$src3),
"vp4dpwssd", "$src3, $src2", "$src2, $src3",		"vp4dpwssd", "$src3, $src2", "$src2, $src3",
[]>, EVEX_V512, EVEX_4V, T8XD, EVEX_CD8<32, CD8VQ>,		[]>, EVEX_V512, EVEX_4V, T8XD, EVEX_CD8<32, CD8VQ>;
Sched<[SchedWriteFMA.ZMM.Folded]>;

defm VP4DPWSSDSrm : AVX512_maskable_3src_in_asm<0x53, MRMSrcMem, v16i32_info,		defm VP4DPWSSDSrm : AVX512_maskable_3src_in_asm<0x53, MRMSrcMem, v16i32_info,
(outs VR512:$dst), (ins VR512:$src2, f128mem:$src3),		(outs VR512:$dst), (ins VR512Quad:$src2, i128mem:$src3),
"vp4dpwssds", "$src3, $src2", "$src2, $src3",		"vp4dpwssds", "$src3, $src2", "$src2, $src3",
[]>, EVEX_V512, EVEX_4V, T8XD, EVEX_CD8<32, CD8VQ>,		[]>, EVEX_V512, EVEX_4V, T8XD, EVEX_CD8<32, CD8VQ>;
Sched<[SchedWriteFMA.ZMM.Folded]>;		}
		}

		let Predicates = [HasAVX5124VNNI] in {
		defm : avx512_quad_pseudo<"VP4DPWSSD", X86vp4dpwssd, v16i32_info, VR512QUAD,
		zsub_0, zsub_1, zsub_2, zsub_3>;
		defm : avx512_quad_pseudo<"VP4DPWSSDS", X86vp4dpwssds, v16i32_info, VR512QUAD,
		zsub_0, zsub_1, zsub_2, zsub_3>;
}		}

		//===----------------------------------------------------------------------===//
		// VP2INTERSECT
		//===----------------------------------------------------------------------===//

let hasSideEffects = 0 in {		let hasSideEffects = 0 in {
let mayStore = 1, SchedRW = [WriteFStoreX] in		let mayStore = 1, SchedRW = [WriteFStoreX] in
def MASKPAIR16STORE : PseudoI<(outs), (ins anymem:$dst, VK16PAIR:$src), []>;		def MASKPAIR16STORE : PseudoI<(outs), (ins anymem:$dst, VK16PAIR:$src), []>;
let mayLoad = 1, SchedRW = [WriteFLoadX] in		let mayLoad = 1, SchedRW = [WriteFLoadX] in
def MASKPAIR16LOAD : PseudoI<(outs VK16PAIR:$dst), (ins anymem:$src), []>;		def MASKPAIR16LOAD : PseudoI<(outs VK16PAIR:$dst), (ins anymem:$src), []>;
}		}

//===----------------------------------------------------------------------===//
// VP2INTERSECT
//===----------------------------------------------------------------------===//

multiclass avx512_vp2intersect_modes<X86FoldableSchedWrite sched, X86VectorVTInfo _> {		multiclass avx512_vp2intersect_modes<X86FoldableSchedWrite sched, X86VectorVTInfo _> {
def rr : I<0x68, MRMSrcReg,		def rr : I<0x68, MRMSrcReg,
(outs _.KRPC:$dst),		(outs _.KRPC:$dst),
(ins _.RC:$src1, _.RC:$src2),		(ins _.RC:$src1, _.RC:$src2),
!strconcat("vp2intersect", _.Suffix,		!strconcat("vp2intersect", _.Suffix,
"\t{$src2, $src1, $dst\|$dst, $src1, $src2}"),		"\t{$src2, $src1, $dst\|$dst, $src1, $src2}"),
[(set _.KRPC:$dst, (X86vp2intersect		[(set _.KRPC:$dst, (X86vp2intersect
_.RC:$src1, (_.VT _.RC:$src2)))]>,		_.RC:$src1, (_.VT _.RC:$src2)))]>,
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llvm/lib/Target/X86/X86InstrFragmentsSIMD.td

	Show First 20 Lines • Show All 573 Lines • ▼ Show 20 Lines
	// VNNI			// VNNI
	def SDTVnni : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,			def SDTVnni : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
	SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;			SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
	def X86Vpdpbusd : SDNode<"X86ISD::VPDPBUSD", SDTVnni>;			def X86Vpdpbusd : SDNode<"X86ISD::VPDPBUSD", SDTVnni>;
	def X86Vpdpbusds : SDNode<"X86ISD::VPDPBUSDS", SDTVnni>;			def X86Vpdpbusds : SDNode<"X86ISD::VPDPBUSDS", SDTVnni>;
	def X86Vpdpwssd : SDNode<"X86ISD::VPDPWSSD", SDTVnni>;			def X86Vpdpwssd : SDNode<"X86ISD::VPDPWSSD", SDTVnni>;
	def X86Vpdpwssds : SDNode<"X86ISD::VPDPWSSDS", SDTVnni>;			def X86Vpdpwssds : SDNode<"X86ISD::VPDPWSSDS", SDTVnni>;

				// AVX5124VNNI
				def SDTVnni4 : SDTypeProfile<1, 7, [SDTCisVT<0, v16i32>,
				SDTCisVT<1, v16i32>,
				SDTCisVT<2, v16i32>,
				SDTCisVT<3, v16i32>,
				SDTCisVT<4, v16i32>,
				SDTCisVT<5, v16i32>,
				SDTCisPtrTy<6>,
				SDTCisVT<7, v16i1>]>;
				def X86vp4dpwssd : SDNode<"X86ISD::VP4DPWSSD", SDTVnni4,
				[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
				def X86vp4dpwssds : SDNode<"X86ISD::VP4DPWSSDS", SDTVnni4,
				[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;

				// AVX5124FMAPS
				def SDTv4fmadd : SDTypeProfile<1, 7, [SDTCisSameAs<0, 1>,
				SDTCisSameAs<0, 2>,
				SDTCisSameAs<0, 3>,
				SDTCisSameAs<0, 4>,
				SDTCisSameAs<0, 5>,
				SDTCisPtrTy<6>,
				SDTCVecEltisVT<7, i1>]>;
				def X86v4fmadd : SDNode<"X86ISD::V4FMADD", SDTv4fmadd,
				[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
				def X86v4fnmadd : SDNode<"X86ISD::V4FNMADD", SDTv4fmadd,
				[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;

	def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", SDTFPUnaryOp>;			def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", SDTFPUnaryOp>;
	def X86rsqrt28SAE: SDNode<"X86ISD::RSQRT28_SAE", SDTFPUnaryOp>;			def X86rsqrt28SAE: SDNode<"X86ISD::RSQRT28_SAE", SDTFPUnaryOp>;
	def X86rcp28 : SDNode<"X86ISD::RCP28", SDTFPUnaryOp>;			def X86rcp28 : SDNode<"X86ISD::RCP28", SDTFPUnaryOp>;
	def X86rcp28SAE : SDNode<"X86ISD::RCP28_SAE", SDTFPUnaryOp>;			def X86rcp28SAE : SDNode<"X86ISD::RCP28_SAE", SDTFPUnaryOp>;
	def X86exp2 : SDNode<"X86ISD::EXP2", SDTFPUnaryOp>;			def X86exp2 : SDNode<"X86ISD::EXP2", SDTFPUnaryOp>;
	def X86exp2SAE : SDNode<"X86ISD::EXP2_SAE", SDTFPUnaryOp>;			def X86exp2SAE : SDNode<"X86ISD::EXP2_SAE", SDTFPUnaryOp>;

	def X86rsqrt14s : SDNode<"X86ISD::RSQRT14S", SDTFPBinOp>;			def X86rsqrt14s : SDNode<"X86ISD::RSQRT14S", SDTFPBinOp>;
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llvm/lib/Target/X86/X86InstrInfo.td

	Show First 20 Lines • Show All 801 Lines • ▼ Show 20 Lines
	def VK8Pair : RegisterOperand<VK8PAIR, "printVKPair"> {			def VK8Pair : RegisterOperand<VK8PAIR, "printVKPair"> {
	let ParserMatchClass = VK8PairAsmOperand;			let ParserMatchClass = VK8PairAsmOperand;
	}			}

	def VK16Pair : RegisterOperand<VK16PAIR, "printVKPair"> {			def VK16Pair : RegisterOperand<VK16PAIR, "printVKPair"> {
	let ParserMatchClass = VK16PairAsmOperand;			let ParserMatchClass = VK16PairAsmOperand;
	}			}

				let RenderMethod = "addQuadRegOperands" in {
				def VR128XQuadAsmOperand : AsmOperandClass { let Name = "VR128XQuad"; }
				def VR512QuadAsmOperand : AsmOperandClass { let Name = "VR512Quad"; }
				}

				def VR128XQuad : RegisterOperand<VR128XQUAD, "printQuadReg"> {
				let ParserMatchClass = VR128XQuadAsmOperand;
				}

				def VR512Quad : RegisterOperand<VR512QUAD, "printQuadReg"> {
				let ParserMatchClass = VR512QuadAsmOperand;
				}

	//===----------------------------------------------------------------------===//			//===----------------------------------------------------------------------===//
	// X86 Complex Pattern Definitions.			// X86 Complex Pattern Definitions.
	//			//

	// Define X86-specific addressing mode.			// Define X86-specific addressing mode.
	def addr : ComplexPattern<iPTR, 5, "selectAddr", [], [SDNPWantParent]>;			def addr : ComplexPattern<iPTR, 5, "selectAddr", [], [SDNPWantParent]>;
	def lea32addr : ComplexPattern<i32, 5, "selectLEAAddr",			def lea32addr : ComplexPattern<i32, 5, "selectLEAAddr",
	[add, sub, mul, X86mul_imm, shl, or, frameindex],			[add, sub, mul, X86mul_imm, shl, or, frameindex],
	▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
	def HasAVX512 : Predicate<"Subtarget->hasAVX512()">;			def HasAVX512 : Predicate<"Subtarget->hasAVX512()">;
	def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">;			def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">;
	def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">;			def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">;
	def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">;			def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">;
	def HasCDI : Predicate<"Subtarget->hasCDI()">;			def HasCDI : Predicate<"Subtarget->hasCDI()">;
	def HasVPOPCNTDQ : Predicate<"Subtarget->hasVPOPCNTDQ()">;			def HasVPOPCNTDQ : Predicate<"Subtarget->hasVPOPCNTDQ()">;
	def HasPFI : Predicate<"Subtarget->hasPFI()">;			def HasPFI : Predicate<"Subtarget->hasPFI()">;
	def HasERI : Predicate<"Subtarget->hasERI()">;			def HasERI : Predicate<"Subtarget->hasERI()">;
				def HasAVX5124FMAPS : Predicate<"Subtarget->hasAVX5124FMAPS()">;
				def HasAVX5124VNNI : Predicate<"Subtarget->hasAVX5124VNNI()">;
	def HasDQI : Predicate<"Subtarget->hasDQI()">;			def HasDQI : Predicate<"Subtarget->hasDQI()">;
	def NoDQI : Predicate<"!Subtarget->hasDQI()">;			def NoDQI : Predicate<"!Subtarget->hasDQI()">;
	def HasBWI : Predicate<"Subtarget->hasBWI()">;			def HasBWI : Predicate<"Subtarget->hasBWI()">;
	def NoBWI : Predicate<"!Subtarget->hasBWI()">;			def NoBWI : Predicate<"!Subtarget->hasBWI()">;
	def HasVLX : Predicate<"Subtarget->hasVLX()">;			def HasVLX : Predicate<"Subtarget->hasVLX()">;
	def NoVLX : Predicate<"!Subtarget->hasVLX()">;			def NoVLX : Predicate<"!Subtarget->hasVLX()">;
	def NoVLX_Or_NoBWI : Predicate<"!Subtarget->hasVLX() \|\| !Subtarget->hasBWI()">;			def NoVLX_Or_NoBWI : Predicate<"!Subtarget->hasVLX() \|\| !Subtarget->hasBWI()">;
	def NoVLX_Or_NoDQI : Predicate<"!Subtarget->hasVLX() \|\| !Subtarget->hasDQI()">;			def NoVLX_Or_NoDQI : Predicate<"!Subtarget->hasVLX() \|\| !Subtarget->hasDQI()">;
	▲ Show 20 Lines • Show All 2,724 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86RegisterInfo.td

Show All 24 Lines	let Namespace = "X86" in {
def sub_8bit_hi_phony : SubRegIndex<8, 8>;		def sub_8bit_hi_phony : SubRegIndex<8, 8>;
def sub_16bit : SubRegIndex<16>;		def sub_16bit : SubRegIndex<16>;
def sub_16bit_hi : SubRegIndex<16, 16>;		def sub_16bit_hi : SubRegIndex<16, 16>;
def sub_32bit : SubRegIndex<32>;		def sub_32bit : SubRegIndex<32>;
def sub_xmm : SubRegIndex<128>;		def sub_xmm : SubRegIndex<128>;
def sub_ymm : SubRegIndex<256>;		def sub_ymm : SubRegIndex<256>;
def sub_mask_0 : SubRegIndex<-1>;		def sub_mask_0 : SubRegIndex<-1>;
def sub_mask_1 : SubRegIndex<-1, -1>;		def sub_mask_1 : SubRegIndex<-1, -1>;
		def xsub_0 : SubRegIndex<128>;
		def xsub_1 : SubRegIndex<128>;
		def xsub_2 : SubRegIndex<128>;
		def xsub_3 : SubRegIndex<128>;
		def ysub_0 : SubRegIndex<256>;
		def ysub_1 : SubRegIndex<256>;
		def ysub_2 : SubRegIndex<256>;
		def ysub_3 : SubRegIndex<256>;
		def zsub_0 : SubRegIndex<512>;
		def zsub_1 : SubRegIndex<512>;
		def zsub_2 : SubRegIndex<512>;
		def zsub_3 : SubRegIndex<512>;
}		}

//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//
// Register definitions...		// Register definitions...
//		//

// In the register alias definitions below, we define which registers alias		// In the register alias definitions below, we define which registers alias
// which others. We only specify which registers the small registers alias,		// which others. We only specify which registers the small registers alias,
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def FR64X : RegisterClass<"X86", [f64], 64, (add FR32X)>;		def FR64X : RegisterClass<"X86", [f64], 64, (add FR32X)>;

// Extended VR128 and VR256 for AVX-512 instructions		// Extended VR128 and VR256 for AVX-512 instructions
def VR128X : RegisterClass<"X86", [v4f32, v2f64, v16i8, v8i16, v4i32, v2i64, f128],		def VR128X : RegisterClass<"X86", [v4f32, v2f64, v16i8, v8i16, v4i32, v2i64, f128],
128, (add FR32X)>;		128, (add FR32X)>;
def VR256X : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64],		def VR256X : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64],
256, (sequence "YMM%u", 0, 31)>;		256, (sequence "YMM%u", 0, 31)>;

		def VR128XQUADS : RegisterTuples<[xsub_0, xsub_1, xsub_2, xsub_3],
		[(decimate VR128X, 4),
		(decimate (shl VR128X, 1), 4),
		(decimate (shl VR128X, 2), 4),
		(decimate (shl VR128X, 3), 4)]>;

		def VR128XQUAD : RegisterClass<"X86", [untyped], 32, (add VR128XQUADS)> {
		let Size = 128;
		}

		def VR512QUADS : RegisterTuples<[zsub_0, zsub_1, zsub_2, zsub_3],
		[(decimate VR512, 4),
		(decimate (shl VR512, 1), 4),
		(decimate (shl VR512, 2), 4),
		(decimate (shl VR512, 3), 4)]>;

		def VR512QUAD : RegisterClass<"X86", [untyped], 512, (add VR512QUADS)> {
		let Size = 2048;
		}

// Mask registers		// Mask registers
def VK1 : RegisterClass<"X86", [v1i1], 16, (sequence "K%u", 0, 7)> {let Size = 16;}		def VK1 : RegisterClass<"X86", [v1i1], 16, (sequence "K%u", 0, 7)> {let Size = 16;}
def VK2 : RegisterClass<"X86", [v2i1], 16, (add VK1)> {let Size = 16;}		def VK2 : RegisterClass<"X86", [v2i1], 16, (add VK1)> {let Size = 16;}
def VK4 : RegisterClass<"X86", [v4i1], 16, (add VK2)> {let Size = 16;}		def VK4 : RegisterClass<"X86", [v4i1], 16, (add VK2)> {let Size = 16;}
def VK8 : RegisterClass<"X86", [v8i1], 16, (add VK4)> {let Size = 16;}		def VK8 : RegisterClass<"X86", [v8i1], 16, (add VK4)> {let Size = 16;}
def VK16 : RegisterClass<"X86", [v16i1], 16, (add VK8)> {let Size = 16;}		def VK16 : RegisterClass<"X86", [v16i1], 16, (add VK8)> {let Size = 16;}
def VK32 : RegisterClass<"X86", [v32i1], 32, (add VK16)> {let Size = 32;}		def VK32 : RegisterClass<"X86", [v32i1], 32, (add VK16)> {let Size = 32;}
def VK64 : RegisterClass<"X86", [v64i1], 64, (add VK32)> {let Size = 64;}		def VK64 : RegisterClass<"X86", [v64i1], 64, (add VK32)> {let Size = 64;}
Show All 21 Lines

llvm/lib/Target/X86/X86Subtarget.h

//===-- X86Subtarget.h - Define Subtarget for the X86 ----------- C++ ---===//		//===-- X86Subtarget.h - Define Subtarget for the X86 ----------- C++ ---===//
		Lint: Lint Inline Actions clang-format not found in user's PATH; not linting file. Lint: Lint: clang-format not found in user's PATH; not linting file.
//		//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.		// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.		// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception		// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//		//
//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//
//		//
▲ Show 20 Lines • Show All 319 Lines • ▼ Show 20 Lines	protected:
bool SlowIncDec = false;		bool SlowIncDec = false;

/// Processor has AVX-512 PreFetch Instructions		/// Processor has AVX-512 PreFetch Instructions
bool HasPFI = false;		bool HasPFI = false;

/// Processor has AVX-512 Exponential and Reciprocal Instructions		/// Processor has AVX-512 Exponential and Reciprocal Instructions
bool HasERI = false;		bool HasERI = false;

		/// Processor has AVX-512 4FMAPS Instructions
		bool HasAVX5124FMAPS = false;

		/// Processor has AVX-512 4VNNI Instructions
		bool HasAVX5124VNNI = false;

/// Processor has AVX-512 Conflict Detection Instructions		/// Processor has AVX-512 Conflict Detection Instructions
bool HasCDI = false;		bool HasCDI = false;

/// Processor has AVX-512 population count Instructions		/// Processor has AVX-512 population count Instructions
bool HasVPOPCNTDQ = false;		bool HasVPOPCNTDQ = false;

/// Processor has AVX-512 Doubleword and Quadword instructions		/// Processor has AVX-512 Doubleword and Quadword instructions
bool HasDQI = false;		bool HasDQI = false;
▲ Show 20 Lines • Show All 354 Lines • ▼ Show 20 Lines	public:
bool LEAusesAG() const { return LEAUsesAG; }		bool LEAusesAG() const { return LEAUsesAG; }
bool slowLEA() const { return SlowLEA; }		bool slowLEA() const { return SlowLEA; }
bool slow3OpsLEA() const { return Slow3OpsLEA; }		bool slow3OpsLEA() const { return Slow3OpsLEA; }
bool slowIncDec() const { return SlowIncDec; }		bool slowIncDec() const { return SlowIncDec; }
bool hasCDI() const { return HasCDI; }		bool hasCDI() const { return HasCDI; }
bool hasVPOPCNTDQ() const { return HasVPOPCNTDQ; }		bool hasVPOPCNTDQ() const { return HasVPOPCNTDQ; }
bool hasPFI() const { return HasPFI; }		bool hasPFI() const { return HasPFI; }
bool hasERI() const { return HasERI; }		bool hasERI() const { return HasERI; }
		bool hasAVX5124FMAPS() const { return HasAVX5124FMAPS; }
		bool hasAVX5124VNNI() const { return HasAVX5124VNNI; }
bool hasDQI() const { return HasDQI; }		bool hasDQI() const { return HasDQI; }
bool hasBWI() const { return HasBWI; }		bool hasBWI() const { return HasBWI; }
bool hasVLX() const { return HasVLX; }		bool hasVLX() const { return HasVLX; }
bool hasPKU() const { return HasPKU; }		bool hasPKU() const { return HasPKU; }
bool hasVNNI() const { return HasVNNI; }		bool hasVNNI() const { return HasVNNI; }
bool hasBF16() const { return HasBF16; }		bool hasBF16() const { return HasBF16; }
bool hasVP2INTERSECT() const { return HasVP2INTERSECT; }		bool hasVP2INTERSECT() const { return HasVP2INTERSECT; }
bool hasBITALG() const { return HasBITALG; }		bool hasBITALG() const { return HasBITALG; }
▲ Show 20 Lines • Show All 201 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/avx5124fmaps-intrinsics.ll

This file was added.

				; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
				; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx5124fmaps \| FileCheck %s

				declare <16 x float> @llvm.x86.avx512.mask.v4fmadd.ps.512(<16 x float>, <16 x float>, <16 x float>, <16 x float>, <16 x float> %a4, i8*, <16 x i1>)
				declare <16 x float> @llvm.x86.avx512.mask.v4fnmadd.ps.512(<16 x float>, <16 x float>, <16 x float>, <16 x float>, <16 x float> %a4, i8*, <16 x i1>)
				declare <4 x float> @llvm.x86.avx512.mask.v4fmadd.ss(<4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float> %a4, i8*, <1 x i1>)
				declare <4 x float> @llvm.x86.avx512.mask.v4fnmadd.ss(<4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float> %a4, i8*, <1 x i1>)

				define <16 x float> @fmaddps(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, <16 x float> %a3, <16 x float> %a4, i8* %ptr) {
				; CHECK-LABEL: fmaddps:
				; CHECK: # %bb.0:
				; CHECK-NEXT: vmovaps %zmm4, %zmm7
				; CHECK-NEXT: vmovaps %zmm3, %zmm6
				; CHECK-NEXT: vmovaps %zmm2, %zmm5
				; CHECK-NEXT: vmovaps %zmm1, %zmm4
				; CHECK-NEXT: v4fmaddps (%rdi), %zmm4, %zmm0
				; CHECK-NEXT: retq
				%a = call <16 x float> @llvm.x86.avx512.mask.v4fmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, <16 x float> %a3, <16 x float> %a4, i8* %ptr, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)
				ret <16 x float> %a
				}

				define <16 x float> @fmaddps_mask_no_passthru(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, <16 x float> %a3, <16 x float> %a4, i8* %ptr, <16 x i32> %mask) {
				; CHECK-LABEL: fmaddps_mask_no_passthru:
				; CHECK: # %bb.0:
				; CHECK-NEXT: vmovaps %zmm4, %zmm11
				; CHECK-NEXT: vptestnmd %zmm5, %zmm5, %k1
				; CHECK-NEXT: vmovaps %zmm3, %zmm10
				; CHECK-NEXT: vmovaps %zmm2, %zmm9
				; CHECK-NEXT: vmovaps %zmm1, %zmm8
				; CHECK-NEXT: v4fmaddps (%rdi), %zmm8, %zmm0 {%k1} {z}
				; CHECK-NEXT: retq
				%m = icmp eq <16 x i32> %mask, zeroinitializer
				%a = call <16 x float> @llvm.x86.avx512.mask.v4fmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, <16 x float> %a3, <16 x float> %a4, i8* %ptr, <16 x i1> %m)
				ret <16 x float> %a
				}

				define <16 x float> @fmaddps_mask(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, <16 x float> %a3, <16 x float> %a4, i8* %ptr, <16 x i32> %mask) {
				; CHECK-LABEL: fmaddps_mask:
				; CHECK: # %bb.0:
				; CHECK-NEXT: vmovaps %zmm4, %zmm11
				; CHECK-NEXT: vptestnmd %zmm5, %zmm5, %k1
				; CHECK-NEXT: vmovaps %zmm3, %zmm10
				; CHECK-NEXT: vmovaps %zmm2, %zmm9
				; CHECK-NEXT: vmovaps %zmm1, %zmm8
				; CHECK-NEXT: v4fmaddps (%rdi), %zmm8, %zmm0 {%k1}
				; CHECK-NEXT: retq
				%m = icmp eq <16 x i32> %mask, zeroinitializer
				%a = call <16 x float> @llvm.x86.avx512.mask.v4fmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, <16 x float> %a3, <16 x float> %a4, i8* %ptr, <16 x i1> %m)
				%b = select <16 x i1> %m, <16 x float> %a, <16 x float> %a0
				ret <16 x float> %b
				}

				define <16 x float> @fmaddps_maskz(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, <16 x float> %a3, <16 x float> %a4, i8* %ptr, <16 x i32> %mask) {
				; CHECK-LABEL: fmaddps_maskz:
				; CHECK: # %bb.0:
				; CHECK-NEXT: vmovaps %zmm4, %zmm11
				; CHECK-NEXT: vptestnmd %zmm5, %zmm5, %k1
				; CHECK-NEXT: vmovaps %zmm3, %zmm10
				; CHECK-NEXT: vmovaps %zmm2, %zmm9
				; CHECK-NEXT: vmovaps %zmm1, %zmm8
				; CHECK-NEXT: v4fmaddps (%rdi), %zmm8, %zmm0 {%k1} {z}
				; CHECK-NEXT: retq
				%m = icmp eq <16 x i32> %mask, zeroinitializer
				%a = call <16 x float> @llvm.x86.avx512.mask.v4fmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, <16 x float> %a3, <16 x float> %a4, i8* %ptr, <16 x i1> %m)
				%b = select <16 x i1> %m, <16 x float> %a, <16 x float> zeroinitializer
				ret <16 x float> %b
				}

				define <16 x float> @fnmaddps(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, <16 x float> %a3, <16 x float> %a4, i8* %ptr) {
				; CHECK-LABEL: fnmaddps:
				; CHECK: # %bb.0:
				; CHECK-NEXT: vmovaps %zmm4, %zmm7
				; CHECK-NEXT: vmovaps %zmm3, %zmm6
				; CHECK-NEXT: vmovaps %zmm2, %zmm5
				; CHECK-NEXT: vmovaps %zmm1, %zmm4
				; CHECK-NEXT: v4fnmaddps (%rdi), %zmm4, %zmm0
				; CHECK-NEXT: retq
				%a = call <16 x float> @llvm.x86.avx512.mask.v4fnmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, <16 x float> %a3, <16 x float> %a4, i8* %ptr, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)
				ret <16 x float> %a
				}

				define <16 x float> @fnmaddps_mask_no_passthru(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, <16 x float> %a3, <16 x float> %a4, i8* %ptr, <16 x i32> %mask) {
				; CHECK-LABEL: fnmaddps_mask_no_passthru:
				; CHECK: # %bb.0:
				; CHECK-NEXT: vmovaps %zmm4, %zmm11
				; CHECK-NEXT: vptestnmd %zmm5, %zmm5, %k1
				; CHECK-NEXT: vmovaps %zmm3, %zmm10
				; CHECK-NEXT: vmovaps %zmm2, %zmm9
				; CHECK-NEXT: vmovaps %zmm1, %zmm8
				; CHECK-NEXT: v4fnmaddps (%rdi), %zmm8, %zmm0 {%k1} {z}
				; CHECK-NEXT: retq
				%m = icmp eq <16 x i32> %mask, zeroinitializer
				%a = call <16 x float> @llvm.x86.avx512.mask.v4fnmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, <16 x float> %a3, <16 x float> %a4, i8* %ptr, <16 x i1> %m)
				ret <16 x float> %a
				}

				define <16 x float> @fnmaddps_mask(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, <16 x float> %a3, <16 x float> %a4, i8* %ptr, <16 x i32> %mask) {
				; CHECK-LABEL: fnmaddps_mask:
				; CHECK: # %bb.0:
				; CHECK-NEXT: vmovaps %zmm4, %zmm11
				; CHECK-NEXT: vptestnmd %zmm5, %zmm5, %k1
				; CHECK-NEXT: vmovaps %zmm3, %zmm10
				; CHECK-NEXT: vmovaps %zmm2, %zmm9
				; CHECK-NEXT: vmovaps %zmm1, %zmm8
				; CHECK-NEXT: v4fnmaddps (%rdi), %zmm8, %zmm0 {%k1}
				; CHECK-NEXT: retq
				%m = icmp eq <16 x i32> %mask, zeroinitializer
				%a = call <16 x float> @llvm.x86.avx512.mask.v4fnmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, <16 x float> %a3, <16 x float> %a4, i8* %ptr, <16 x i1> %m)
				%b = select <16 x i1> %m, <16 x float> %a, <16 x float> %a0
				ret <16 x float> %b
				}

				define <16 x float> @fnmaddps_maskz(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, <16 x float> %a3, <16 x float> %a4, i8* %ptr, <16 x i32> %mask) {
				; CHECK-LABEL: fnmaddps_maskz:
				; CHECK: # %bb.0:
				; CHECK-NEXT: vmovaps %zmm4, %zmm11
				; CHECK-NEXT: vptestnmd %zmm5, %zmm5, %k1
				; CHECK-NEXT: vmovaps %zmm3, %zmm10
				; CHECK-NEXT: vmovaps %zmm2, %zmm9
				; CHECK-NEXT: vmovaps %zmm1, %zmm8
				; CHECK-NEXT: v4fnmaddps (%rdi), %zmm8, %zmm0 {%k1} {z}
				; CHECK-NEXT: retq
				%m = icmp eq <16 x i32> %mask, zeroinitializer
				%a = call <16 x float> @llvm.x86.avx512.mask.v4fnmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, <16 x float> %a3, <16 x float> %a4, i8* %ptr, <16 x i1> %m)
				%b = select <16 x i1> %m, <16 x float> %a, <16 x float> zeroinitializer
				ret <16 x float> %b
				}

				define <4 x float> @fmaddss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, <4 x float> %a3, <4 x float> %a4, i8* %ptr) {
				; CHECK-LABEL: fmaddss:
				; CHECK: # %bb.0:
				; CHECK-NEXT: vmovaps %xmm4, %xmm7
				; CHECK-NEXT: vmovaps %xmm3, %xmm6
				; CHECK-NEXT: vmovaps %xmm2, %xmm5
				; CHECK-NEXT: vmovaps %xmm1, %xmm4
				; CHECK-NEXT: v4fmaddss (%rdi), %xmm4, %xmm0
				; CHECK-NEXT: retq
				%a = call <4 x float> @llvm.x86.avx512.mask.v4fmadd.ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, <4 x float> %a3, <4 x float> %a4, i8* %ptr, <1 x i1> <i1 true>)
				ret <4 x float> %a
				}

				define <4 x float> @fmaddss_mask_no_passthru(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, <4 x float> %a3, <4 x float> %a4, i8* %ptr, <4 x i32> %mask) {
				; CHECK-LABEL: fmaddss_mask_no_passthru:
				; CHECK: # %bb.0:
				; CHECK-NEXT: # kill: def $xmm5 killed $xmm5 def $zmm5
				; CHECK-NEXT: vmovaps %xmm4, %xmm11
				; CHECK-NEXT: vptestnmd %zmm5, %zmm5, %k1
				; CHECK-NEXT: vmovaps %xmm3, %xmm10
				; CHECK-NEXT: vmovaps %xmm2, %xmm9
				; CHECK-NEXT: vmovaps %xmm1, %xmm8
				; CHECK-NEXT: v4fmaddss (%rdi), %xmm8, %xmm0 {%k1} {z}
				; CHECK-NEXT: vzeroupper
				; CHECK-NEXT: retq
				%m = icmp eq <4 x i32> %mask, zeroinitializer
				%m1 = shufflevector <4 x i1> %m, <4 x i1> undef, <1 x i32> <i32 0>
				%a = call <4 x float> @llvm.x86.avx512.mask.v4fmadd.ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, <4 x float> %a3, <4 x float> %a4, i8* %ptr, <1 x i1> %m1)
				ret <4 x float> %a
				}

llvm/test/CodeGen/X86/dynamic-regmask.ll

	; RUN: llc -mtriple=x86_64-pc-win32 -stop-after machine-sink %s -o %t.mir			; RUN: llc -mtriple=x86_64-pc-win32 -stop-after machine-sink %s -o %t.mir
	; RUN: FileCheck %s < %t.mir			; RUN: FileCheck %s < %t.mir
	; RUN: llc %t.mir -mtriple=x86_64-pc-win32 -run-pass machine-sink			; RUN: llc %t.mir -mtriple=x86_64-pc-win32 -run-pass machine-sink
	; Check that callee saved registers are printed in a format that can then be parsed.			; Check that callee saved registers are printed in a format that can then be parsed.

	declare x86_regcallcc i32 @callee(i32 %a0, i32 %b0, i32 %c0, i32 %d0, i32 %e0)			declare x86_regcallcc i32 @callee(i32 %a0, i32 %b0, i32 %c0, i32 %d0, i32 %e0)

	define i32 @caller(i32 %a0) nounwind {			define i32 @caller(i32 %a0) nounwind {
	%b1 = call x86_regcallcc i32 @callee(i32 %a0, i32 %a0, i32 %a0, i32 %a0, i32 %a0)			%b1 = call x86_regcallcc i32 @callee(i32 %a0, i32 %a0, i32 %a0, i32 %a0, i32 %a0)
	%b2 = add i32 %b1, %a0			%b2 = add i32 %b1, %a0
	ret i32 %b2			ret i32 %b2
	}			}
	; CHECK: name: caller			; CHECK: name: caller
	; CHECK: CALL64pcrel32 @callee, CustomRegMask($bh,$bl,$bp,$bph,$bpl,$bx,$ebp,$ebx,$esp,$hbp,$hbx,$hsp,$rbp,$rbx,$rsp,$sp,$sph,$spl,$r10,$r11,$r12,$r13,$r14,$r15,$xmm8,$xmm9,$xmm10,$xmm11,$xmm12,$xmm13,$xmm14,$xmm15,$r10b,$r11b,$r12b,$r13b,$r14b,$r15b,$r10bh,$r11bh,$r12bh,$r13bh,$r14bh,$r15bh,$r10d,$r11d,$r12d,$r13d,$r14d,$r15d,$r10w,$r11w,$r12w,$r13w,$r14w,$r15w,$r10wh,$r11wh,$r12wh,$r13wh,$r14wh,$r15wh), implicit $rsp, implicit $ssp, implicit $eax, implicit $ecx, implicit $edx, implicit $edi, implicit $esi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax			; CHECK: CALL64pcrel32 @callee, CustomRegMask($bh,$bl,$bp,$bph,$bpl,$bx,$ebp,$ebx,$esp,$hbp,$hbx,$hsp,$rbp,$rbx,$rsp,$sp,$sph,$spl,$r10,$r11,$r12,$r13,$r14,$r15,$xmm8,$xmm9,$xmm10,$xmm11,$xmm12,$xmm13,$xmm14,$xmm15,$r10b,$r11b,$r12b,$r13b,$r14b,$r15b,$r10bh,$r11bh,$r12bh,$r13bh,$r14bh,$r15bh,$r10d,$r11d,$r12d,$r13d,$r14d,$r15d,$r10w,$r11w,$r12w,$r13w,$r14w,$r15w,$r10wh,$r11wh,$r12wh,$r13wh,$r14wh,$r15wh,$xmm8_xmm9_xmm10_xmm11,$xmm12_xmm13_xmm14_xmm15), implicit $rsp, implicit $ssp, implicit $eax, implicit $ecx, implicit $edx, implicit $edi, implicit $esi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
	; CHECK: RET 0, $eax			; CHECK: RET 0, $eax

	define x86_regcallcc {i32, i32, i32} @test_callee(i32 %a0, i32 %b0, i32 %c0, i32 %d0, i32 %e0) nounwind {			define x86_regcallcc {i32, i32, i32} @test_callee(i32 %a0, i32 %b0, i32 %c0, i32 %d0, i32 %e0) nounwind {
	%b1 = mul i32 7, %e0			%b1 = mul i32 7, %e0
	%b2 = udiv i32 5, %e0			%b2 = udiv i32 5, %e0
	%b3 = mul i32 7, %d0			%b3 = mul i32 7, %d0
	%b4 = insertvalue {i32, i32, i32} undef, i32 %b1, 0			%b4 = insertvalue {i32, i32, i32} undef, i32 %b1, 0
	%b5 = insertvalue {i32, i32, i32} %b4, i32 %b2, 1			%b5 = insertvalue {i32, i32, i32} %b4, i32 %b2, 1
	%b6 = insertvalue {i32, i32, i32} %b5, i32 %b3, 2			%b6 = insertvalue {i32, i32, i32} %b5, i32 %b3, 2
	ret {i32, i32, i32} %b6			ret {i32, i32, i32} %b6
	}			}
	; CHECK: name: test_callee			; CHECK: name: test_callee
	; CHECK: calleeSavedRegisters: [ '$rbx', '$rbp', '$rsp', '$r10', '$r11', '$r12',			; CHECK: calleeSavedRegisters: [ '$rbx', '$rbp', '$rsp', '$r10', '$r11', '$r12',
	; CHECK: '$r13', '$r14', '$r15', '$xmm8', '$xmm9', '$xmm10',			; CHECK: '$r13', '$r14', '$r15', '$xmm8', '$xmm9', '$xmm10',
	; CHECK: '$xmm11', '$xmm12', '$xmm13', '$xmm14', '$xmm15' ]			; CHECK: '$xmm11', '$xmm12', '$xmm13', '$xmm14', '$xmm15' ]
	; CHECK: RET 0, $eax, $ecx, $edx			; CHECK: RET 0, $eax, $ecx, $edx

llvm/test/CodeGen/X86/fma.ll

	Show First 20 Lines • Show All 350 Lines • ▼ Show 20 Lines
	; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm1, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x4c,0x24,0x04,0x02]			; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm1, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x4c,0x24,0x04,0x02]
	; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm0, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x04,0x24,0x02]			; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm0, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x04,0x24,0x02]
	; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]			; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
	; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4			; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
	; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill			; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0x7c,0x24,0x60]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0x7c,0x24,0x60]
	; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload			; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x40]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x40]
	; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 ## 16-byte Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x54,0x24,0x30]
	; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload			; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x4c,0x24,0x20]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x4c,0x24,0x20]
	; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x01]			; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x01]
	; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm2, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x54,0x24,0x04,0x01]			; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
				; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x30]
	; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x01]			; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x01]
				; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x04,0x01]
	; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]			; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
	; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4			; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
	; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill			; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0x7c,0x24,0x54]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0x7c,0x24,0x54]
	; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload			; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x40]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x40]
	; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x08]			; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x08]
	; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload			; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x30]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x30]
	; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x04]			; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x04]
	; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload			; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x20]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x20]
	; FMACALL32_BDVER2-NEXT: vmovss %xmm0, (%esp) ## encoding: [0xc5,0xfa,0x11,0x04,0x24]			; FMACALL32_BDVER2-NEXT: vmovss %xmm0, (%esp) ## encoding: [0xc5,0xfa,0x11,0x04,0x24]
	; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]			; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
	; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4			; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
	; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload			; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x40]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x40]
	; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 ## 16-byte Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x54,0x24,0x30]
	; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload			; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x4c,0x24,0x20]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x4c,0x24,0x20]
	; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x03]			; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x03]
	; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm2, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x54,0x24,0x04,0x03]			; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
				; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x30]
	; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x03]			; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x03]
				; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x04,0x03]
	; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x1c]			; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x1c]
	; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload			; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0x6c,0x24,0x54]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0x6c,0x24,0x54]
	; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x18]			; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x18]
	; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload			; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0x6c,0x24,0x60]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0x6c,0x24,0x60]
	; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x14]			; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x14]
	; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]			; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
	▲ Show 20 Lines • Show All 213 Lines • ▼ Show 20 Lines
	; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x02]			; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x02]
	; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]			; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
	; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]			; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
	; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4			; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
	; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill			; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0xb4,0x00,0x00,0x00]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0xb4,0x00,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload			; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x60]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x60]
	; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 ## 16-byte Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x54,0x24,0x50]
	; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload			; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x4c,0x24,0x40]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x4c,0x24,0x40]
	; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x01]			; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x01]
	; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm2, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x54,0x24,0x04,0x01]			; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
				; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x50]
	; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x01]			; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x01]
				; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x04,0x01]
	; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]			; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
	; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4			; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
	; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill			; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0xa8,0x00,0x00,0x00]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0xa8,0x00,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload			; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x60]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x60]
	; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x08]			; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x08]
	; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload			; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
	▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
	; FMACALL32_BDVER2-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload			; FMACALL32_BDVER2-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x10,0x84,0x24,0xc0,0x00,0x00,0x00]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x10,0x84,0x24,0xc0,0x00,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: vmovss %xmm0, (%esp) ## encoding: [0xc5,0xfa,0x11,0x04,0x24]			; FMACALL32_BDVER2-NEXT: vmovss %xmm0, (%esp) ## encoding: [0xc5,0xfa,0x11,0x04,0x24]
	; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]			; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
	; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]			; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
	; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4			; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
	; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload			; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x60]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x60]
	; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 ## 16-byte Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x54,0x24,0x50]
	; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload			; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x4c,0x24,0x40]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x4c,0x24,0x40]
	; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x03]			; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x03]
	; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm2, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x54,0x24,0x04,0x03]			; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
				; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x50]
	; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x03]			; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x03]
				; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x04,0x03]
	; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x3c]			; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x3c]
	; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload			; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0x6c,0x24,0x78]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0x6c,0x24,0x78]
	; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x38]			; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x38]
	; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload			; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0x84,0x00,0x00,0x00]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0x84,0x00,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x34]			; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x34]
	; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload			; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload
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	;			;
	; FMACALL32_BDVER2-LABEL: test_v16f32:			; FMACALL32_BDVER2-LABEL: test_v16f32:
	; FMACALL32_BDVER2: ## %bb.0: ## %entry			; FMACALL32_BDVER2: ## %bb.0: ## %entry
	; FMACALL32_BDVER2-NEXT: pushl %ebp ## encoding: [0x55]			; FMACALL32_BDVER2-NEXT: pushl %ebp ## encoding: [0x55]
	; FMACALL32_BDVER2-NEXT: movl %esp, %ebp ## encoding: [0x89,0xe5]			; FMACALL32_BDVER2-NEXT: movl %esp, %ebp ## encoding: [0x89,0xe5]
	; FMACALL32_BDVER2-NEXT: andl $-32, %esp ## encoding: [0x83,0xe4,0xe0]			; FMACALL32_BDVER2-NEXT: andl $-32, %esp ## encoding: [0x83,0xe4,0xe0]
	; FMACALL32_BDVER2-NEXT: subl $448, %esp ## encoding: [0x81,0xec,0xc0,0x01,0x00,0x00]			; FMACALL32_BDVER2-NEXT: subl $448, %esp ## encoding: [0x81,0xec,0xc0,0x01,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: ## imm = 0x1C0			; FMACALL32_BDVER2-NEXT: ## imm = 0x1C0
	; FMACALL32_BDVER2-NEXT: vmovaps 56(%ebp), %xmm4 ## encoding: [0xc5,0xf8,0x28,0x65,0x38]			; FMACALL32_BDVER2-NEXT: vmovaps %ymm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 32-byte Spill
	; FMACALL32_BDVER2-NEXT: vmovaps %ymm2, {{[-0-9]+}}(%e{{[sb]}}p) ## 32-byte Spill			; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x29,0x84,0x24,0x80,0x01,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x29,0x94,0x24,0x60,0x01,0x00,0x00]			; FMACALL32_BDVER2-NEXT: vmovaps 56(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x38]
	; FMACALL32_BDVER2-NEXT: vextractf128 $1, %ymm3, %xmm2 ## encoding: [0xc4,0xe3,0x7d,0x19,0xda,0x01]
	; FMACALL32_BDVER2-NEXT: vmovaps %ymm1, {{[-0-9]+}}(%e{{[sb]}}p) ## 32-byte Spill			; FMACALL32_BDVER2-NEXT: vmovaps %ymm1, {{[-0-9]+}}(%e{{[sb]}}p) ## 32-byte Spill
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x29,0x8c,0x24,0x80,0x00,0x00,0x00]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x29,0x8c,0x24,0x80,0x00,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: vextractf128 $1, %ymm1, %xmm1 ## encoding: [0xc4,0xe3,0x7d,0x19,0xc9,0x01]			; FMACALL32_BDVER2-NEXT: vextractf128 $1, %ymm1, %xmm1 ## encoding: [0xc4,0xe3,0x7d,0x19,0xc9,0x01]
	; FMACALL32_BDVER2-NEXT: vmovaps %ymm3, {{[-0-9]+}}(%e{{[sb]}}p) ## 32-byte Spill			; FMACALL32_BDVER2-NEXT: vmovaps %ymm3, {{[-0-9]+}}(%e{{[sb]}}p) ## 32-byte Spill
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x29,0x5c,0x24,0x60]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x29,0x5c,0x24,0x60]
	; FMACALL32_BDVER2-NEXT: vmovaps %ymm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 32-byte Spill			; FMACALL32_BDVER2-NEXT: vmovaps %ymm2, {{[-0-9]+}}(%e{{[sb]}}p) ## 32-byte Spill
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x29,0x84,0x24,0x80,0x01,0x00,0x00]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x29,0x94,0x24,0x60,0x01,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: vmovaps %xmm2, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x29,0x94,0x24,0xc0,0x00,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm2, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x54,0x24,0x04,0x02]
	; FMACALL32_BDVER2-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill			; FMACALL32_BDVER2-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x29,0x8c,0x24,0xb0,0x00,0x00,0x00]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x29,0x8c,0x24,0xb0,0x00,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x02]			; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x02]
	; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm4, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x64,0x24,0x08,0x02]			; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x02]
				; FMACALL32_BDVER2-NEXT: vextractf128 $1, %ymm3, %xmm0 ## encoding: [0xc4,0xe3,0x7d,0x19,0xd8,0x01]
				; FMACALL32_BDVER2-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
				; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x29,0x84,0x24,0xc0,0x00,0x00,0x00]
				; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x04,0x02]
	; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]			; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
	; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]			; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
	; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4			; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
				; FMACALL32_BDVER2-NEXT: vmovaps 56(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x38]
	; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill			; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0x54,0x01,0x00,0x00]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0x54,0x01,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: vmovaps 56(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x38]
	; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 ## 16-byte Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x94,0x24,0xc0,0x00,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload			; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x8c,0x24,0xb0,0x00,0x00,0x00]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x8c,0x24,0xb0,0x00,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x01]			; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x01]
	; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm2, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x54,0x24,0x04,0x01]			; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
				; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x84,0x24,0xc0,0x00,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x01]			; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x01]
				; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x04,0x01]
	; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]			; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
	; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4			; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
	; FMACALL32_BDVER2-NEXT: vmovaps 56(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x38]			; FMACALL32_BDVER2-NEXT: vmovaps 56(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x38]
	; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill			; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0x48,0x01,0x00,0x00]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0x48,0x01,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x08]			; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x08]
	; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload			; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x84,0x24,0xc0,0x00,0x00,0x00]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x84,0x24,0xc0,0x00,0x00,0x00]
	▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x84,0x24,0x80,0x01,0x00,0x00]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x84,0x24,0x80,0x01,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: vextractf128 $1, %ymm0, %xmm0 ## encoding: [0xc4,0xe3,0x7d,0x19,0xc0,0x01]			; FMACALL32_BDVER2-NEXT: vextractf128 $1, %ymm0, %xmm0 ## encoding: [0xc4,0xe3,0x7d,0x19,0xc0,0x01]
	; FMACALL32_BDVER2-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill			; FMACALL32_BDVER2-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x29,0x44,0x24,0x60]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x29,0x44,0x24,0x60]
	; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x04,0x24,0x03]			; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x04,0x24,0x03]
	; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]			; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
	; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]			; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
	; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4			; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
				; FMACALL32_BDVER2-NEXT: vmovaps 24(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x18]
	; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill			; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0x00,0x01,0x00,0x00]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0x00,0x01,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: vmovaps 24(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x18]
	; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 ## 16-byte Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x94,0x24,0x80,0x00,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload			; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x4c,0x24,0x60]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x4c,0x24,0x60]
	; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x02]			; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x02]
	; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm2, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x54,0x24,0x04,0x02]			; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
				; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x84,0x24,0x80,0x00,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x02]			; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x02]
				; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x04,0x02]
	; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]			; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
	; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4			; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
				; FMACALL32_BDVER2-NEXT: vmovaps 24(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x18]
	; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill			; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0xf4,0x00,0x00,0x00]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0xf4,0x00,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: vmovaps 24(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x18]
	; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 ## 16-byte Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x94,0x24,0x80,0x00,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload			; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x4c,0x24,0x60]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x4c,0x24,0x60]
	; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x01]			; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x01]
	; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm2, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x54,0x24,0x04,0x01]			; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
				; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x84,0x24,0x80,0x00,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x01]			; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x01]
				; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x04,0x01]
	; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]			; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
	; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4			; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
	; FMACALL32_BDVER2-NEXT: vmovaps 24(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x18]			; FMACALL32_BDVER2-NEXT: vmovaps 24(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x18]
	; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill			; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0xe8,0x00,0x00,0x00]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0xe8,0x00,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x08]			; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x08]
	; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload			; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x84,0x24,0x80,0x00,0x00,0x00]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x84,0x24,0x80,0x00,0x00,0x00]
	▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
	; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x04]			; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x04]
	; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload			; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x84,0x24,0x80,0x01,0x00,0x00]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x84,0x24,0x80,0x01,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: vmovss %xmm0, (%esp) ## encoding: [0xc5,0xfa,0x11,0x04,0x24]			; FMACALL32_BDVER2-NEXT: vmovss %xmm0, (%esp) ## encoding: [0xc5,0xfa,0x11,0x04,0x24]
	; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]			; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
	; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]			; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
	; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4			; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
	; FMACALL32_BDVER2-NEXT: vmovaps 56(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x38]			; FMACALL32_BDVER2-NEXT: vmovaps 56(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x38]
	; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 ## 16-byte Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x94,0x24,0xc0,0x00,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload			; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x8c,0x24,0xb0,0x00,0x00,0x00]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x8c,0x24,0xb0,0x00,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x03]			; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x03]
	; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm2, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x54,0x24,0x04,0x03]			; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
				; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x84,0x24,0xc0,0x00,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x03]			; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x03]
				; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x04,0x03]
	; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x3c]			; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x3c]
	; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload			; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0xd0,0x00,0x00,0x00]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0xd0,0x00,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x38]			; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x38]
	; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload			; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0xdc,0x00,0x00,0x00]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0xdc,0x00,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x34]			; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x34]
	; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload			; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload
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	; AVX512VL-NEXT: retq ## encoding: [0xc3]			; AVX512VL-NEXT: retq ## encoding: [0xc3]
	;			;
	; FMACALL32_BDVER2-LABEL: test_v4f64:			; FMACALL32_BDVER2-LABEL: test_v4f64:
	; FMACALL32_BDVER2: ## %bb.0: ## %entry			; FMACALL32_BDVER2: ## %bb.0: ## %entry
	; FMACALL32_BDVER2-NEXT: subl $252, %esp ## encoding: [0x81,0xec,0xfc,0x00,0x00,0x00]			; FMACALL32_BDVER2-NEXT: subl $252, %esp ## encoding: [0x81,0xec,0xfc,0x00,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: vextractf128 $1, %ymm2, %xmm3 ## encoding: [0xc4,0xe3,0x7d,0x19,0xd3,0x01]			; FMACALL32_BDVER2-NEXT: vextractf128 $1, %ymm2, %xmm3 ## encoding: [0xc4,0xe3,0x7d,0x19,0xd3,0x01]
	; FMACALL32_BDVER2-NEXT: vmovups %ymm2, {{[-0-9]+}}(%e{{[sb]}}p) ## 32-byte Spill			; FMACALL32_BDVER2-NEXT: vmovups %ymm2, {{[-0-9]+}}(%e{{[sb]}}p) ## 32-byte Spill
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x11,0x94,0x24,0xc0,0x00,0x00,0x00]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x11,0x94,0x24,0xc0,0x00,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: vmovups %ymm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 32-byte Spill
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x11,0x84,0x24,0x80,0x00,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: vextractf128 $1, %ymm1, %xmm2 ## encoding: [0xc4,0xe3,0x7d,0x19,0xca,0x01]			; FMACALL32_BDVER2-NEXT: vextractf128 $1, %ymm1, %xmm2 ## encoding: [0xc4,0xe3,0x7d,0x19,0xca,0x01]
	; FMACALL32_BDVER2-NEXT: vextractf128 $1, %ymm0, %xmm0 ## encoding: [0xc4,0xe3,0x7d,0x19,0xc0,0x01]
	; FMACALL32_BDVER2-NEXT: vmovups %ymm1, {{[-0-9]+}}(%e{{[sb]}}p) ## 32-byte Spill			; FMACALL32_BDVER2-NEXT: vmovups %ymm1, {{[-0-9]+}}(%e{{[sb]}}p) ## 32-byte Spill
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x11,0x8c,0x24,0xa0,0x00,0x00,0x00]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x11,0x8c,0x24,0xa0,0x00,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill			; FMACALL32_BDVER2-NEXT: vextractf128 $1, %ymm0, %xmm1 ## encoding: [0xc4,0xe3,0x7d,0x19,0xc1,0x01]
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x29,0x44,0x24,0x60]			; FMACALL32_BDVER2-NEXT: vmovups %ymm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 32-byte Spill
	; FMACALL32_BDVER2-NEXT: vmovlhps %xmm2, %xmm0, %xmm0 ## encoding: [0xc5,0xf8,0x16,0xc2]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x11,0x84,0x24,0x80,0x00,0x00,0x00]
	; FMACALL32_BDVER2-NEXT: ## xmm0 = xmm0[0],xmm2[0]			; FMACALL32_BDVER2-NEXT: vmovlhps %xmm2, %xmm1, %xmm0 ## encoding: [0xc5,0xf0,0x16,0xc2]
				; FMACALL32_BDVER2-NEXT: ## xmm0 = xmm1[0],xmm2[0]
	; FMACALL32_BDVER2-NEXT: vmovaps %xmm3, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill			; FMACALL32_BDVER2-NEXT: vmovaps %xmm3, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x29,0x5c,0x24,0x70]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x29,0x5c,0x24,0x70]
	; FMACALL32_BDVER2-NEXT: vmovlps %xmm3, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xf8,0x13,0x5c,0x24,0x10]			; FMACALL32_BDVER2-NEXT: vmovlps %xmm3, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xf8,0x13,0x5c,0x24,0x10]
	; FMACALL32_BDVER2-NEXT: vmovaps %xmm2, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill			; FMACALL32_BDVER2-NEXT: vmovaps %xmm2, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x29,0x54,0x24,0x50]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x29,0x54,0x24,0x50]
				; FMACALL32_BDVER2-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
				; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x29,0x4c,0x24,0x60]
	; FMACALL32_BDVER2-NEXT: vmovups %xmm0, (%esp) ## encoding: [0xc5,0xf8,0x11,0x04,0x24]			; FMACALL32_BDVER2-NEXT: vmovups %xmm0, (%esp) ## encoding: [0xc5,0xf8,0x11,0x04,0x24]
	; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]			; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
	; FMACALL32_BDVER2-NEXT: calll _fma ## encoding: [0xe8,A,A,A,A]			; FMACALL32_BDVER2-NEXT: calll _fma ## encoding: [0xe8,A,A,A,A]
	; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fma-4, kind: FK_PCRel_4			; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fma-4, kind: FK_PCRel_4
	; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill			; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0x7c,0x24,0x44]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0x7c,0x24,0x44]
	; FMACALL32_BDVER2-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload			; FMACALL32_BDVER2-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
	; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x10,0x84,0x24,0xc0,0x00,0x00,0x00]			; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x10,0x84,0x24,0xc0,0x00,0x00,0x00]
	▲ Show 20 Lines • Show All 419 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/pr44140.ll

	Show All 16 Lines
	; CHECK-NEXT: .cfi_def_cfa_offset 592			; CHECK-NEXT: .cfi_def_cfa_offset 592
	; CHECK-NEXT: vmovaps {{.*#+}} xmm6 = [1010101010101010101,2020202020202020202]			; CHECK-NEXT: vmovaps {{.*#+}} xmm6 = [1010101010101010101,2020202020202020202]
	; CHECK-NEXT: xorl %esi, %esi			; CHECK-NEXT: xorl %esi, %esi
	; CHECK-NEXT: .p2align 4, 0x90			; CHECK-NEXT: .p2align 4, 0x90
	; CHECK-NEXT: .LBB1_1: # %fake-loop			; CHECK-NEXT: .LBB1_1: # %fake-loop
	; CHECK-NEXT: # =>This Inner Loop Header: Depth=1			; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
	; CHECK-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm0			; CHECK-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm0
	; CHECK-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm1			; CHECK-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm1
	; CHECK-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm7
	; CHECK-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm2			; CHECK-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm2
	; CHECK-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm3			; CHECK-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm3
	; CHECK-NEXT: vmovups %ymm0, {{[0-9]+}}(%rsp)			; CHECK-NEXT: vmovups %ymm0, {{[0-9]+}}(%rsp)
	; CHECK-NEXT: vmovups %ymm1, {{[0-9]+}}(%rsp)			; CHECK-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm0
	; CHECK-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm1
	; CHECK-NEXT: vmovups %ymm3, {{[0-9]+}}(%rsp)			; CHECK-NEXT: vmovups %ymm3, {{[0-9]+}}(%rsp)
	; CHECK-NEXT: vmovups %ymm2, {{[0-9]+}}(%rsp)			; CHECK-NEXT: vmovups %ymm2, {{[0-9]+}}(%rsp)
	; CHECK-NEXT: vmovups %ymm7, {{[0-9]+}}(%rsp)			; CHECK-NEXT: vmovups %ymm1, {{[0-9]+}}(%rsp)
	; CHECK-NEXT: vmovups %ymm3, {{[0-9]+}}(%rsp)			; CHECK-NEXT: vmovups %ymm3, {{[0-9]+}}(%rsp)
	; CHECK-NEXT: vmovups %ymm2, {{[0-9]+}}(%rsp)			; CHECK-NEXT: vmovups %ymm2, {{[0-9]+}}(%rsp)
	; CHECK-NEXT: vmovups %ymm7, {{[0-9]+}}(%rsp)
	; CHECK-NEXT: vmovups %ymm1, {{[0-9]+}}(%rsp)
	; CHECK-NEXT: vmovups %ymm1, {{[0-9]+}}(%rsp)			; CHECK-NEXT: vmovups %ymm1, {{[0-9]+}}(%rsp)
				; CHECK-NEXT: vmovups %ymm0, {{[0-9]+}}(%rsp)
				; CHECK-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm0
				; CHECK-NEXT: vmovups %ymm0, {{[0-9]+}}(%rsp)
				; CHECK-NEXT: vmovups %ymm0, {{[0-9]+}}(%rsp)
	; CHECK-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm5			; CHECK-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm5
	; CHECK-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm4			; CHECK-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm4
	; CHECK-NEXT: vmovups %ymm5, {{[0-9]+}}(%rsp)			; CHECK-NEXT: vmovups %ymm5, {{[0-9]+}}(%rsp)
	; CHECK-NEXT: vmovups %ymm4, {{[0-9]+}}(%rsp)			; CHECK-NEXT: vmovups %ymm4, {{[0-9]+}}(%rsp)
	; CHECK-NEXT: vzeroupper			; CHECK-NEXT: vzeroupper
	; CHECK-NEXT: callq opaque			; CHECK-NEXT: callq opaque
	; CHECK-NEXT: vmovaps %xmm6, {{[0-9]+}}(%rsp)			; CHECK-NEXT: vmovaps %xmm6, {{[0-9]+}}(%rsp)
	; CHECK-NEXT: testb %sil, %sil			; CHECK-NEXT: testb %sil, %sil
	▲ Show 20 Lines • Show All 51 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/recip-fastmath.ll

	Show First 20 Lines • Show All 1,113 Lines • ▼ Show 20 Lines
	; FMA-RECIP-NEXT: vfmsub213ps {{.#+}} ymm1 = (ymm2 ymm1) - ymm3			; FMA-RECIP-NEXT: vfmsub213ps {{.#+}} ymm1 = (ymm2 ymm1) - ymm3
	; FMA-RECIP-NEXT: vfnmadd132ps {{.#+}} ymm1 = -(ymm1 ymm2) + ymm2			; FMA-RECIP-NEXT: vfnmadd132ps {{.#+}} ymm1 = -(ymm1 ymm2) + ymm2
	; FMA-RECIP-NEXT: retq			; FMA-RECIP-NEXT: retq
	;			;
	; BDVER2-LABEL: v16f32_one_step:			; BDVER2-LABEL: v16f32_one_step:
	; BDVER2: # %bb.0:			; BDVER2: # %bb.0:
	; BDVER2-NEXT: vrcpps %ymm0, %ymm2			; BDVER2-NEXT: vrcpps %ymm0, %ymm2
	; BDVER2-NEXT: vmovaps {{.*#+}} ymm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]			; BDVER2-NEXT: vmovaps {{.*#+}} ymm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
	; BDVER2-NEXT: vrcpps %ymm1, %ymm4
	; BDVER2-NEXT: vfmsubps {{.#+}} ymm0 = (ymm0 ymm2) - ymm3			; BDVER2-NEXT: vfmsubps {{.#+}} ymm0 = (ymm0 ymm2) - ymm3
	; BDVER2-NEXT: vfmsubps {{.#+}} ymm1 = (ymm1 ymm4) - ymm3
	; BDVER2-NEXT: vfnmaddps {{.#+}} ymm0 = -(ymm2 ymm0) + ymm2			; BDVER2-NEXT: vfnmaddps {{.#+}} ymm0 = -(ymm2 ymm0) + ymm2
	; BDVER2-NEXT: vfnmaddps {{.#+}} ymm1 = -(ymm4 ymm1) + ymm4			; BDVER2-NEXT: vrcpps %ymm1, %ymm2
				; BDVER2-NEXT: vfmsubps {{.#+}} ymm1 = (ymm1 ymm2) - ymm3
				; BDVER2-NEXT: vfnmaddps {{.#+}} ymm1 = -(ymm2 ymm1) + ymm2
	; BDVER2-NEXT: retq			; BDVER2-NEXT: retq
	;			;
	; BTVER2-LABEL: v16f32_one_step:			; BTVER2-LABEL: v16f32_one_step:
	; BTVER2: # %bb.0:			; BTVER2: # %bb.0:
	; BTVER2-NEXT: vmovaps {{.*#+}} ymm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]			; BTVER2-NEXT: vmovaps {{.*#+}} ymm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
	; BTVER2-NEXT: vrcpps %ymm0, %ymm2			; BTVER2-NEXT: vrcpps %ymm0, %ymm2
	; BTVER2-NEXT: vrcpps %ymm1, %ymm4
	; BTVER2-NEXT: vmulps %ymm2, %ymm0, %ymm0			; BTVER2-NEXT: vmulps %ymm2, %ymm0, %ymm0
	; BTVER2-NEXT: vmulps %ymm4, %ymm1, %ymm1
	; BTVER2-NEXT: vsubps %ymm0, %ymm3, %ymm0			; BTVER2-NEXT: vsubps %ymm0, %ymm3, %ymm0
	; BTVER2-NEXT: vsubps %ymm1, %ymm3, %ymm1
	; BTVER2-NEXT: vmulps %ymm0, %ymm2, %ymm0			; BTVER2-NEXT: vmulps %ymm0, %ymm2, %ymm0
	; BTVER2-NEXT: vmulps %ymm1, %ymm4, %ymm1
	; BTVER2-NEXT: vaddps %ymm0, %ymm2, %ymm0			; BTVER2-NEXT: vaddps %ymm0, %ymm2, %ymm0
	; BTVER2-NEXT: vaddps %ymm1, %ymm4, %ymm1			; BTVER2-NEXT: vrcpps %ymm1, %ymm2
				; BTVER2-NEXT: vmulps %ymm2, %ymm1, %ymm1
				; BTVER2-NEXT: vsubps %ymm1, %ymm3, %ymm1
				; BTVER2-NEXT: vmulps %ymm1, %ymm2, %ymm1
				; BTVER2-NEXT: vaddps %ymm1, %ymm2, %ymm1
	; BTVER2-NEXT: retq			; BTVER2-NEXT: retq
	;			;
	; SANDY-LABEL: v16f32_one_step:			; SANDY-LABEL: v16f32_one_step:
	; SANDY: # %bb.0:			; SANDY: # %bb.0:
	; SANDY-NEXT: vrcpps %ymm0, %ymm2			; SANDY-NEXT: vrcpps %ymm0, %ymm2
	; SANDY-NEXT: vmulps %ymm2, %ymm0, %ymm0			; SANDY-NEXT: vmulps %ymm2, %ymm0, %ymm0
	; SANDY-NEXT: vmovaps {{.*#+}} ymm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]			; SANDY-NEXT: vmovaps {{.*#+}} ymm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
	; SANDY-NEXT: vsubps %ymm0, %ymm3, %ymm0			; SANDY-NEXT: vsubps %ymm0, %ymm3, %ymm0
	▲ Show 20 Lines • Show All 261 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/recip-fastmath2.ll

	Show First 20 Lines • Show All 273 Lines • ▼ Show 20 Lines
	; FMA-RECIP-NEXT: vfmsub213ss {{.#+}} xmm0 = (xmm3 xmm0) - xmm1			; FMA-RECIP-NEXT: vfmsub213ss {{.#+}} xmm0 = (xmm3 xmm0) - xmm1
	; FMA-RECIP-NEXT: vfnmadd213ss {{.#+}} xmm0 = -(xmm2 xmm0) + xmm3			; FMA-RECIP-NEXT: vfnmadd213ss {{.#+}} xmm0 = -(xmm2 xmm0) + xmm3
	; FMA-RECIP-NEXT: retq			; FMA-RECIP-NEXT: retq
	;			;
	; BDVER2-LABEL: f32_two_step_2:			; BDVER2-LABEL: f32_two_step_2:
	; BDVER2: # %bb.0:			; BDVER2: # %bb.0:
	; BDVER2-NEXT: vrcpss %xmm0, %xmm0, %xmm1			; BDVER2-NEXT: vrcpss %xmm0, %xmm0, %xmm1
	; BDVER2-NEXT: vfmsubss {{.#+}} xmm2 = (xmm0 xmm1) - mem			; BDVER2-NEXT: vfmsubss {{.#+}} xmm2 = (xmm0 xmm1) - mem
	; BDVER2-NEXT: vmovss {{.*#+}} xmm4 = mem[0],zero,zero,zero
	; BDVER2-NEXT: vfnmaddss {{.#+}} xmm1 = -(xmm1 xmm2) + xmm1			; BDVER2-NEXT: vfnmaddss {{.#+}} xmm1 = -(xmm1 xmm2) + xmm1
	; BDVER2-NEXT: vmulss %xmm4, %xmm1, %xmm3			; BDVER2-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
	; BDVER2-NEXT: vfmsubss {{.#+}} xmm0 = (xmm0 xmm3) - xmm4			; BDVER2-NEXT: vmulss %xmm2, %xmm1, %xmm3
				; BDVER2-NEXT: vfmsubss {{.#+}} xmm0 = (xmm0 xmm3) - xmm2
	; BDVER2-NEXT: vfnmaddss {{.#+}} xmm0 = -(xmm1 xmm0) + xmm3			; BDVER2-NEXT: vfnmaddss {{.#+}} xmm0 = -(xmm1 xmm0) + xmm3
	; BDVER2-NEXT: retq			; BDVER2-NEXT: retq
	;			;
	; BTVER2-LABEL: f32_two_step_2:			; BTVER2-LABEL: f32_two_step_2:
	; BTVER2: # %bb.0:			; BTVER2: # %bb.0:
	; BTVER2-NEXT: vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero			; BTVER2-NEXT: vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero
	; BTVER2-NEXT: vrcpss %xmm0, %xmm0, %xmm1			; BTVER2-NEXT: vrcpss %xmm0, %xmm0, %xmm1
	; BTVER2-NEXT: vmovss {{.*#+}} xmm4 = mem[0],zero,zero,zero
	; BTVER2-NEXT: vmulss %xmm1, %xmm0, %xmm2			; BTVER2-NEXT: vmulss %xmm1, %xmm0, %xmm2
	; BTVER2-NEXT: vsubss %xmm2, %xmm3, %xmm2			; BTVER2-NEXT: vsubss %xmm2, %xmm3, %xmm2
	; BTVER2-NEXT: vmulss %xmm2, %xmm1, %xmm2			; BTVER2-NEXT: vmulss %xmm2, %xmm1, %xmm2
	; BTVER2-NEXT: vaddss %xmm2, %xmm1, %xmm1			; BTVER2-NEXT: vaddss %xmm2, %xmm1, %xmm1
	; BTVER2-NEXT: vmulss %xmm4, %xmm1, %xmm3			; BTVER2-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
				; BTVER2-NEXT: vmulss %xmm2, %xmm1, %xmm3
	; BTVER2-NEXT: vmulss %xmm3, %xmm0, %xmm0			; BTVER2-NEXT: vmulss %xmm3, %xmm0, %xmm0
	; BTVER2-NEXT: vsubss %xmm0, %xmm4, %xmm0			; BTVER2-NEXT: vsubss %xmm0, %xmm2, %xmm0
	; BTVER2-NEXT: vmulss %xmm0, %xmm1, %xmm0			; BTVER2-NEXT: vmulss %xmm0, %xmm1, %xmm0
	; BTVER2-NEXT: vaddss %xmm0, %xmm3, %xmm0			; BTVER2-NEXT: vaddss %xmm0, %xmm3, %xmm0
	; BTVER2-NEXT: retq			; BTVER2-NEXT: retq
	;			;
	; SANDY-LABEL: f32_two_step_2:			; SANDY-LABEL: f32_two_step_2:
	; SANDY: # %bb.0:			; SANDY: # %bb.0:
	; SANDY-NEXT: vrcpss %xmm0, %xmm0, %xmm1			; SANDY-NEXT: vrcpss %xmm0, %xmm0, %xmm1
	; SANDY-NEXT: vmulss %xmm1, %xmm0, %xmm2			; SANDY-NEXT: vmulss %xmm1, %xmm0, %xmm2
	▲ Show 20 Lines • Show All 309 Lines • ▼ Show 20 Lines
	; FMA-RECIP-NEXT: vfmsub213ps {{.#+}} xmm0 = (xmm3 xmm0) - xmm1			; FMA-RECIP-NEXT: vfmsub213ps {{.#+}} xmm0 = (xmm3 xmm0) - xmm1
	; FMA-RECIP-NEXT: vfnmadd213ps {{.#+}} xmm0 = -(xmm2 xmm0) + xmm3			; FMA-RECIP-NEXT: vfnmadd213ps {{.#+}} xmm0 = -(xmm2 xmm0) + xmm3
	; FMA-RECIP-NEXT: retq			; FMA-RECIP-NEXT: retq
	;			;
	; BDVER2-LABEL: v4f32_two_step2:			; BDVER2-LABEL: v4f32_two_step2:
	; BDVER2: # %bb.0:			; BDVER2: # %bb.0:
	; BDVER2-NEXT: vrcpps %xmm0, %xmm1			; BDVER2-NEXT: vrcpps %xmm0, %xmm1
	; BDVER2-NEXT: vfmsubps {{.#+}} xmm2 = (xmm0 xmm1) - mem			; BDVER2-NEXT: vfmsubps {{.#+}} xmm2 = (xmm0 xmm1) - mem
	; BDVER2-NEXT: vmovaps {{.*#+}} xmm4 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0]
	; BDVER2-NEXT: vfnmaddps {{.#+}} xmm1 = -(xmm1 xmm2) + xmm1			; BDVER2-NEXT: vfnmaddps {{.#+}} xmm1 = -(xmm1 xmm2) + xmm1
	; BDVER2-NEXT: vmulps %xmm4, %xmm1, %xmm3			; BDVER2-NEXT: vmovaps {{.*#+}} xmm2 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0]
	; BDVER2-NEXT: vfmsubps {{.#+}} xmm0 = (xmm0 xmm3) - xmm4			; BDVER2-NEXT: vmulps %xmm2, %xmm1, %xmm3
				; BDVER2-NEXT: vfmsubps {{.#+}} xmm0 = (xmm0 xmm3) - xmm2
	; BDVER2-NEXT: vfnmaddps {{.#+}} xmm0 = -(xmm1 xmm0) + xmm3			; BDVER2-NEXT: vfnmaddps {{.#+}} xmm0 = -(xmm1 xmm0) + xmm3
	; BDVER2-NEXT: retq			; BDVER2-NEXT: retq
	;			;
	; BTVER2-LABEL: v4f32_two_step2:			; BTVER2-LABEL: v4f32_two_step2:
	; BTVER2: # %bb.0:			; BTVER2: # %bb.0:
	; BTVER2-NEXT: vmovaps {{.*#+}} xmm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0]			; BTVER2-NEXT: vmovaps {{.*#+}} xmm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0]
	; BTVER2-NEXT: vrcpps %xmm0, %xmm1			; BTVER2-NEXT: vrcpps %xmm0, %xmm1
	; BTVER2-NEXT: vmovaps {{.*#+}} xmm4 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0]
	; BTVER2-NEXT: vmulps %xmm1, %xmm0, %xmm2			; BTVER2-NEXT: vmulps %xmm1, %xmm0, %xmm2
	; BTVER2-NEXT: vsubps %xmm2, %xmm3, %xmm2			; BTVER2-NEXT: vsubps %xmm2, %xmm3, %xmm2
	; BTVER2-NEXT: vmulps %xmm2, %xmm1, %xmm2			; BTVER2-NEXT: vmulps %xmm2, %xmm1, %xmm2
	; BTVER2-NEXT: vaddps %xmm2, %xmm1, %xmm1			; BTVER2-NEXT: vaddps %xmm2, %xmm1, %xmm1
	; BTVER2-NEXT: vmulps %xmm4, %xmm1, %xmm3			; BTVER2-NEXT: vmovaps {{.*#+}} xmm2 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0]
				; BTVER2-NEXT: vmulps %xmm2, %xmm1, %xmm3
	; BTVER2-NEXT: vmulps %xmm3, %xmm0, %xmm0			; BTVER2-NEXT: vmulps %xmm3, %xmm0, %xmm0
	; BTVER2-NEXT: vsubps %xmm0, %xmm4, %xmm0			; BTVER2-NEXT: vsubps %xmm0, %xmm2, %xmm0
	; BTVER2-NEXT: vmulps %xmm0, %xmm1, %xmm0			; BTVER2-NEXT: vmulps %xmm0, %xmm1, %xmm0
	; BTVER2-NEXT: vaddps %xmm0, %xmm3, %xmm0			; BTVER2-NEXT: vaddps %xmm0, %xmm3, %xmm0
	; BTVER2-NEXT: retq			; BTVER2-NEXT: retq
	;			;
	; SANDY-LABEL: v4f32_two_step2:			; SANDY-LABEL: v4f32_two_step2:
	; SANDY: # %bb.0:			; SANDY: # %bb.0:
	; SANDY-NEXT: vrcpps %xmm0, %xmm1			; SANDY-NEXT: vrcpps %xmm0, %xmm1
	; SANDY-NEXT: vmulps %xmm1, %xmm0, %xmm2			; SANDY-NEXT: vmulps %xmm1, %xmm0, %xmm2
	▲ Show 20 Lines • Show All 342 Lines • ▼ Show 20 Lines
	; FMA-RECIP-NEXT: vfmsub213ps {{.#+}} ymm0 = (ymm3 ymm0) - ymm1			; FMA-RECIP-NEXT: vfmsub213ps {{.#+}} ymm0 = (ymm3 ymm0) - ymm1
	; FMA-RECIP-NEXT: vfnmadd213ps {{.#+}} ymm0 = -(ymm2 ymm0) + ymm3			; FMA-RECIP-NEXT: vfnmadd213ps {{.#+}} ymm0 = -(ymm2 ymm0) + ymm3
	; FMA-RECIP-NEXT: retq			; FMA-RECIP-NEXT: retq
	;			;
	; BDVER2-LABEL: v8f32_two_step2:			; BDVER2-LABEL: v8f32_two_step2:
	; BDVER2: # %bb.0:			; BDVER2: # %bb.0:
	; BDVER2-NEXT: vrcpps %ymm0, %ymm1			; BDVER2-NEXT: vrcpps %ymm0, %ymm1
	; BDVER2-NEXT: vfmsubps {{.#+}} ymm2 = (ymm0 ymm1) - mem			; BDVER2-NEXT: vfmsubps {{.#+}} ymm2 = (ymm0 ymm1) - mem
	; BDVER2-NEXT: vmovaps {{.*#+}} ymm4 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0,5.0E+0,6.0E+0,7.0E+0,8.0E+0]
	; BDVER2-NEXT: vfnmaddps {{.#+}} ymm1 = -(ymm1 ymm2) + ymm1			; BDVER2-NEXT: vfnmaddps {{.#+}} ymm1 = -(ymm1 ymm2) + ymm1
	; BDVER2-NEXT: vmulps %ymm4, %ymm1, %ymm3			; BDVER2-NEXT: vmovaps {{.*#+}} ymm2 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0,5.0E+0,6.0E+0,7.0E+0,8.0E+0]
	; BDVER2-NEXT: vfmsubps {{.#+}} ymm0 = (ymm0 ymm3) - ymm4			; BDVER2-NEXT: vmulps %ymm2, %ymm1, %ymm3
				; BDVER2-NEXT: vfmsubps {{.#+}} ymm0 = (ymm0 ymm3) - ymm2
	; BDVER2-NEXT: vfnmaddps {{.#+}} ymm0 = -(ymm1 ymm0) + ymm3			; BDVER2-NEXT: vfnmaddps {{.#+}} ymm0 = -(ymm1 ymm0) + ymm3
	; BDVER2-NEXT: retq			; BDVER2-NEXT: retq
	;			;
	; BTVER2-LABEL: v8f32_two_step2:			; BTVER2-LABEL: v8f32_two_step2:
	; BTVER2: # %bb.0:			; BTVER2: # %bb.0:
	; BTVER2-NEXT: vmovaps {{.*#+}} ymm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]			; BTVER2-NEXT: vmovaps {{.*#+}} ymm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
	; BTVER2-NEXT: vrcpps %ymm0, %ymm1			; BTVER2-NEXT: vrcpps %ymm0, %ymm1
	; BTVER2-NEXT: vmovaps {{.*#+}} ymm4 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0,5.0E+0,6.0E+0,7.0E+0,8.0E+0]
	; BTVER2-NEXT: vmulps %ymm1, %ymm0, %ymm2			; BTVER2-NEXT: vmulps %ymm1, %ymm0, %ymm2
	; BTVER2-NEXT: vsubps %ymm2, %ymm3, %ymm2			; BTVER2-NEXT: vsubps %ymm2, %ymm3, %ymm2
	; BTVER2-NEXT: vmulps %ymm2, %ymm1, %ymm2			; BTVER2-NEXT: vmulps %ymm2, %ymm1, %ymm2
	; BTVER2-NEXT: vaddps %ymm2, %ymm1, %ymm1			; BTVER2-NEXT: vaddps %ymm2, %ymm1, %ymm1
	; BTVER2-NEXT: vmulps %ymm4, %ymm1, %ymm3			; BTVER2-NEXT: vmovaps {{.*#+}} ymm2 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0,5.0E+0,6.0E+0,7.0E+0,8.0E+0]
				; BTVER2-NEXT: vmulps %ymm2, %ymm1, %ymm3
	; BTVER2-NEXT: vmulps %ymm3, %ymm0, %ymm0			; BTVER2-NEXT: vmulps %ymm3, %ymm0, %ymm0
	; BTVER2-NEXT: vsubps %ymm0, %ymm4, %ymm0			; BTVER2-NEXT: vsubps %ymm0, %ymm2, %ymm0
	; BTVER2-NEXT: vmulps %ymm0, %ymm1, %ymm0			; BTVER2-NEXT: vmulps %ymm0, %ymm1, %ymm0
	; BTVER2-NEXT: vaddps %ymm0, %ymm3, %ymm0			; BTVER2-NEXT: vaddps %ymm0, %ymm3, %ymm0
	; BTVER2-NEXT: retq			; BTVER2-NEXT: retq
	;			;
	; SANDY-LABEL: v8f32_two_step2:			; SANDY-LABEL: v8f32_two_step2:
	; SANDY: # %bb.0:			; SANDY: # %bb.0:
	; SANDY-NEXT: vrcpps %ymm0, %ymm1			; SANDY-NEXT: vrcpps %ymm0, %ymm1
	; SANDY-NEXT: vmulps %ymm1, %ymm0, %ymm2			; SANDY-NEXT: vmulps %ymm1, %ymm0, %ymm2
	▲ Show 20 Lines • Show All 157 Lines • ▼ Show 20 Lines
	; FMA-RECIP-NEXT: vfmsub213ps {{.#+}} ymm1 = (ymm4 ymm1) - ymm3			; FMA-RECIP-NEXT: vfmsub213ps {{.#+}} ymm1 = (ymm4 ymm1) - ymm3
	; FMA-RECIP-NEXT: vfnmadd213ps {{.#+}} ymm1 = -(ymm2 ymm1) + ymm4			; FMA-RECIP-NEXT: vfnmadd213ps {{.#+}} ymm1 = -(ymm2 ymm1) + ymm4
	; FMA-RECIP-NEXT: retq			; FMA-RECIP-NEXT: retq
	;			;
	; BDVER2-LABEL: v16f32_one_step2:			; BDVER2-LABEL: v16f32_one_step2:
	; BDVER2: # %bb.0:			; BDVER2: # %bb.0:
	; BDVER2-NEXT: vrcpps %ymm0, %ymm2			; BDVER2-NEXT: vrcpps %ymm0, %ymm2
	; BDVER2-NEXT: vmovaps {{.*#+}} ymm3 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0,5.0E+0,6.0E+0,7.0E+0,8.0E+0]			; BDVER2-NEXT: vmovaps {{.*#+}} ymm3 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0,5.0E+0,6.0E+0,7.0E+0,8.0E+0]
	; BDVER2-NEXT: vrcpps %ymm1, %ymm5
	; BDVER2-NEXT: vmulps %ymm3, %ymm2, %ymm4			; BDVER2-NEXT: vmulps %ymm3, %ymm2, %ymm4
	; BDVER2-NEXT: vfmsubps {{.#+}} ymm0 = (ymm0 ymm4) - ymm3			; BDVER2-NEXT: vfmsubps {{.#+}} ymm0 = (ymm0 ymm4) - ymm3
	; BDVER2-NEXT: vmovaps {{.*#+}} ymm3 = [9.0E+0,1.0E+1,1.1E+1,1.2E+1,1.3E+1,1.4E+1,1.5E+1,1.6E+1]			; BDVER2-NEXT: vmovaps {{.*#+}} ymm3 = [9.0E+0,1.0E+1,1.1E+1,1.2E+1,1.3E+1,1.4E+1,1.5E+1,1.6E+1]
	; BDVER2-NEXT: vfnmaddps {{.#+}} ymm0 = -(ymm2 ymm0) + ymm4			; BDVER2-NEXT: vfnmaddps {{.#+}} ymm0 = -(ymm2 ymm0) + ymm4
	; BDVER2-NEXT: vmulps %ymm3, %ymm5, %ymm4			; BDVER2-NEXT: vrcpps %ymm1, %ymm2
				; BDVER2-NEXT: vmulps %ymm3, %ymm2, %ymm4
	; BDVER2-NEXT: vfmsubps {{.#+}} ymm1 = (ymm1 ymm4) - ymm3			; BDVER2-NEXT: vfmsubps {{.#+}} ymm1 = (ymm1 ymm4) - ymm3
	; BDVER2-NEXT: vfnmaddps {{.#+}} ymm1 = -(ymm5 ymm1) + ymm4			; BDVER2-NEXT: vfnmaddps {{.#+}} ymm1 = -(ymm2 ymm1) + ymm4
	; BDVER2-NEXT: retq			; BDVER2-NEXT: retq
	;			;
	; BTVER2-LABEL: v16f32_one_step2:			; BTVER2-LABEL: v16f32_one_step2:
	; BTVER2: # %bb.0:			; BTVER2: # %bb.0:
	; BTVER2-NEXT: vmovaps {{.*#+}} ymm3 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0,5.0E+0,6.0E+0,7.0E+0,8.0E+0]			; BTVER2-NEXT: vmovaps {{.*#+}} ymm3 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0,5.0E+0,6.0E+0,7.0E+0,8.0E+0]
	; BTVER2-NEXT: vrcpps %ymm0, %ymm2			; BTVER2-NEXT: vrcpps %ymm0, %ymm2
	; BTVER2-NEXT: vmulps %ymm3, %ymm2, %ymm4			; BTVER2-NEXT: vmulps %ymm3, %ymm2, %ymm4
	; BTVER2-NEXT: vmulps %ymm4, %ymm0, %ymm0			; BTVER2-NEXT: vmulps %ymm4, %ymm0, %ymm0
	▲ Show 20 Lines • Show All 364 Lines • ▼ Show 20 Lines
	; BDVER2-NEXT: vmovaps {{.*#+}} ymm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]			; BDVER2-NEXT: vmovaps {{.*#+}} ymm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
	; BDVER2-NEXT: vfmsubps {{.#+}} ymm4 = (ymm0 ymm2) - ymm3			; BDVER2-NEXT: vfmsubps {{.#+}} ymm4 = (ymm0 ymm2) - ymm3
	; BDVER2-NEXT: vfnmaddps {{.#+}} ymm2 = -(ymm2 ymm4) + ymm2			; BDVER2-NEXT: vfnmaddps {{.#+}} ymm2 = -(ymm2 ymm4) + ymm2
	; BDVER2-NEXT: vmovaps {{.*#+}} ymm4 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0,5.0E+0,6.0E+0,7.0E+0,8.0E+0]			; BDVER2-NEXT: vmovaps {{.*#+}} ymm4 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0,5.0E+0,6.0E+0,7.0E+0,8.0E+0]
	; BDVER2-NEXT: vmulps %ymm4, %ymm2, %ymm5			; BDVER2-NEXT: vmulps %ymm4, %ymm2, %ymm5
	; BDVER2-NEXT: vfmsubps {{.#+}} ymm0 = (ymm0 ymm5) - ymm4			; BDVER2-NEXT: vfmsubps {{.#+}} ymm0 = (ymm0 ymm5) - ymm4
	; BDVER2-NEXT: vfnmaddps {{.#+}} ymm0 = -(ymm2 ymm0) + ymm5			; BDVER2-NEXT: vfnmaddps {{.#+}} ymm0 = -(ymm2 ymm0) + ymm5
	; BDVER2-NEXT: vrcpps %ymm1, %ymm2			; BDVER2-NEXT: vrcpps %ymm1, %ymm2
	; BDVER2-NEXT: vmovaps {{.*#+}} ymm5 = [9.0E+0,1.0E+1,1.1E+1,1.2E+1,1.3E+1,1.4E+1,1.5E+1,1.6E+1]
	; BDVER2-NEXT: vfmsubps {{.#+}} ymm3 = (ymm1 ymm2) - ymm3			; BDVER2-NEXT: vfmsubps {{.#+}} ymm3 = (ymm1 ymm2) - ymm3
	; BDVER2-NEXT: vfnmaddps {{.#+}} ymm2 = -(ymm2 ymm3) + ymm2			; BDVER2-NEXT: vfnmaddps {{.#+}} ymm2 = -(ymm2 ymm3) + ymm2
	; BDVER2-NEXT: vmulps %ymm5, %ymm2, %ymm4			; BDVER2-NEXT: vmovaps {{.*#+}} ymm3 = [9.0E+0,1.0E+1,1.1E+1,1.2E+1,1.3E+1,1.4E+1,1.5E+1,1.6E+1]
	; BDVER2-NEXT: vfmsubps {{.#+}} ymm1 = (ymm1 ymm4) - ymm5			; BDVER2-NEXT: vmulps %ymm3, %ymm2, %ymm4
				; BDVER2-NEXT: vfmsubps {{.#+}} ymm1 = (ymm1 ymm4) - ymm3
	; BDVER2-NEXT: vfnmaddps {{.#+}} ymm1 = -(ymm2 ymm1) + ymm4			; BDVER2-NEXT: vfnmaddps {{.#+}} ymm1 = -(ymm2 ymm1) + ymm4
	; BDVER2-NEXT: retq			; BDVER2-NEXT: retq
	;			;
	; BTVER2-LABEL: v16f32_two_step2:			; BTVER2-LABEL: v16f32_two_step2:
	; BTVER2: # %bb.0:			; BTVER2: # %bb.0:
	; BTVER2-NEXT: vmovaps {{.*#+}} ymm4 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]			; BTVER2-NEXT: vmovaps {{.*#+}} ymm4 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
	; BTVER2-NEXT: vrcpps %ymm0, %ymm2			; BTVER2-NEXT: vrcpps %ymm0, %ymm2
	; BTVER2-NEXT: vmulps %ymm2, %ymm0, %ymm3			; BTVER2-NEXT: vmulps %ymm2, %ymm0, %ymm3
	; BTVER2-NEXT: vsubps %ymm3, %ymm4, %ymm3			; BTVER2-NEXT: vsubps %ymm3, %ymm4, %ymm3
	; BTVER2-NEXT: vmulps %ymm3, %ymm2, %ymm3			; BTVER2-NEXT: vmulps %ymm3, %ymm2, %ymm3
	; BTVER2-NEXT: vaddps %ymm3, %ymm2, %ymm2			; BTVER2-NEXT: vaddps %ymm3, %ymm2, %ymm2
	; BTVER2-NEXT: vmovaps {{.*#+}} ymm3 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0,5.0E+0,6.0E+0,7.0E+0,8.0E+0]			; BTVER2-NEXT: vmovaps {{.*#+}} ymm3 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0,5.0E+0,6.0E+0,7.0E+0,8.0E+0]
	; BTVER2-NEXT: vmulps %ymm3, %ymm2, %ymm5			; BTVER2-NEXT: vmulps %ymm3, %ymm2, %ymm5
	; BTVER2-NEXT: vmulps %ymm5, %ymm0, %ymm0			; BTVER2-NEXT: vmulps %ymm5, %ymm0, %ymm0
	; BTVER2-NEXT: vsubps %ymm0, %ymm3, %ymm0			; BTVER2-NEXT: vsubps %ymm0, %ymm3, %ymm0
	; BTVER2-NEXT: vmulps %ymm0, %ymm2, %ymm0			; BTVER2-NEXT: vmulps %ymm0, %ymm2, %ymm0
	; BTVER2-NEXT: vrcpps %ymm1, %ymm2			; BTVER2-NEXT: vrcpps %ymm1, %ymm2
	; BTVER2-NEXT: vmulps %ymm2, %ymm1, %ymm3			; BTVER2-NEXT: vmulps %ymm2, %ymm1, %ymm3
	; BTVER2-NEXT: vaddps %ymm0, %ymm5, %ymm0			; BTVER2-NEXT: vaddps %ymm0, %ymm5, %ymm0
	; BTVER2-NEXT: vmovaps {{.*#+}} ymm5 = [9.0E+0,1.0E+1,1.1E+1,1.2E+1,1.3E+1,1.4E+1,1.5E+1,1.6E+1]
	; BTVER2-NEXT: vsubps %ymm3, %ymm4, %ymm3			; BTVER2-NEXT: vsubps %ymm3, %ymm4, %ymm3
	; BTVER2-NEXT: vmulps %ymm3, %ymm2, %ymm3			; BTVER2-NEXT: vmulps %ymm3, %ymm2, %ymm3
	; BTVER2-NEXT: vaddps %ymm3, %ymm2, %ymm2			; BTVER2-NEXT: vaddps %ymm3, %ymm2, %ymm2
	; BTVER2-NEXT: vmulps %ymm5, %ymm2, %ymm4			; BTVER2-NEXT: vmovaps {{.*#+}} ymm3 = [9.0E+0,1.0E+1,1.1E+1,1.2E+1,1.3E+1,1.4E+1,1.5E+1,1.6E+1]
				; BTVER2-NEXT: vmulps %ymm3, %ymm2, %ymm4
	; BTVER2-NEXT: vmulps %ymm4, %ymm1, %ymm1			; BTVER2-NEXT: vmulps %ymm4, %ymm1, %ymm1
	; BTVER2-NEXT: vsubps %ymm1, %ymm5, %ymm1			; BTVER2-NEXT: vsubps %ymm1, %ymm3, %ymm1
	; BTVER2-NEXT: vmulps %ymm1, %ymm2, %ymm1			; BTVER2-NEXT: vmulps %ymm1, %ymm2, %ymm1
	; BTVER2-NEXT: vaddps %ymm1, %ymm4, %ymm1			; BTVER2-NEXT: vaddps %ymm1, %ymm4, %ymm1
	; BTVER2-NEXT: retq			; BTVER2-NEXT: retq
	;			;
	; SANDY-LABEL: v16f32_two_step2:			; SANDY-LABEL: v16f32_two_step2:
	; SANDY: # %bb.0:			; SANDY: # %bb.0:
	; SANDY-NEXT: vrcpps %ymm0, %ymm2			; SANDY-NEXT: vrcpps %ymm0, %ymm2
	; SANDY-NEXT: vmulps %ymm2, %ymm0, %ymm3			; SANDY-NEXT: vmulps %ymm2, %ymm0, %ymm3
	▲ Show 20 Lines • Show All 227 Lines • Show Last 20 Lines

llvm/utils/TableGen/X86RecognizableInstr.cpp

//===- X86RecognizableInstr.cpp - Disassembler instruction spec --- C++ --===//		//===- X86RecognizableInstr.cpp - Disassembler instruction spec --- C++ --===//
		Lint: Lint Inline Actions clang-format not found in user's PATH; not linting file. Lint: Lint: clang-format not found in user's PATH; not linting file.
//		//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.		// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.		// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception		// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//		//
//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//
//		//
▲ Show 20 Lines • Show All 908 Lines • ▼ Show 20 Lines	OperandType RecognizableInstr::typeFromString(const std::string &s,
TYPE("offset32_64", TYPE_MOFFS)		TYPE("offset32_64", TYPE_MOFFS)
TYPE("offset64_8", TYPE_MOFFS)		TYPE("offset64_8", TYPE_MOFFS)
TYPE("offset64_16", TYPE_MOFFS)		TYPE("offset64_16", TYPE_MOFFS)
TYPE("offset64_32", TYPE_MOFFS)		TYPE("offset64_32", TYPE_MOFFS)
TYPE("offset64_64", TYPE_MOFFS)		TYPE("offset64_64", TYPE_MOFFS)
TYPE("VR256", TYPE_YMM)		TYPE("VR256", TYPE_YMM)
TYPE("VR256X", TYPE_YMM)		TYPE("VR256X", TYPE_YMM)
TYPE("VR512", TYPE_ZMM)		TYPE("VR512", TYPE_ZMM)
		TYPE("VR128XQuad", TYPE_XMM_QUAD)
		Lint: Pre-merge checks Inline Actions clang-format: please reformat the code - TYPE("VR128XQuad", TYPE_XMM_QUAD) - TYPE("VR512Quad", TYPE_ZMM_QUAD) + TYPE("VR128XQuad", TYPE_XMM_QUAD) + TYPE("VR512Quad", TYPE_ZMM_QUAD) Lint: Pre-merge checks: clang-format: please reformat the code ``` - TYPE("VR128XQuad", TYPE_XMM_QUAD)…
		TYPE("VR512Quad", TYPE_ZMM_QUAD)
TYPE("VK1", TYPE_VK)		TYPE("VK1", TYPE_VK)
TYPE("VK1WM", TYPE_VK)		TYPE("VK1WM", TYPE_VK)
TYPE("VK2", TYPE_VK)		TYPE("VK2", TYPE_VK)
TYPE("VK2WM", TYPE_VK)		TYPE("VK2WM", TYPE_VK)
TYPE("VK4", TYPE_VK)		TYPE("VK4", TYPE_VK)
TYPE("VK4WM", TYPE_VK)		TYPE("VK4WM", TYPE_VK)
TYPE("VK8", TYPE_VK)		TYPE("VK8", TYPE_VK)
TYPE("VK8WM", TYPE_VK)		TYPE("VK8WM", TYPE_VK)
▲ Show 20 Lines • Show All 159 Lines • ▼ Show 20 Lines	RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s,
ENCODING("FR64", ENCODING_VVVV)		ENCODING("FR64", ENCODING_VVVV)
ENCODING("VR128", ENCODING_VVVV)		ENCODING("VR128", ENCODING_VVVV)
ENCODING("VR256", ENCODING_VVVV)		ENCODING("VR256", ENCODING_VVVV)
ENCODING("FR32X", ENCODING_VVVV)		ENCODING("FR32X", ENCODING_VVVV)
ENCODING("FR64X", ENCODING_VVVV)		ENCODING("FR64X", ENCODING_VVVV)
ENCODING("VR128X", ENCODING_VVVV)		ENCODING("VR128X", ENCODING_VVVV)
ENCODING("VR256X", ENCODING_VVVV)		ENCODING("VR256X", ENCODING_VVVV)
ENCODING("VR512", ENCODING_VVVV)		ENCODING("VR512", ENCODING_VVVV)
		ENCODING("VR128XQuad", ENCODING_VVVV)
		Lint: Pre-merge checks Inline Actions clang-format: please reformat the code - ENCODING("VR128XQuad", ENCODING_VVVV) - ENCODING("VR512Quad", ENCODING_VVVV) + ENCODING("VR128XQuad", ENCODING_VVVV) + ENCODING("VR512Quad", ENCODING_VVVV) Lint: Pre-merge checks: clang-format: please reformat the code ``` - ENCODING("VR128XQuad", ENCODING_VVVV)…
		ENCODING("VR512Quad", ENCODING_VVVV)
ENCODING("VK1", ENCODING_VVVV)		ENCODING("VK1", ENCODING_VVVV)
ENCODING("VK2", ENCODING_VVVV)		ENCODING("VK2", ENCODING_VVVV)
ENCODING("VK4", ENCODING_VVVV)		ENCODING("VK4", ENCODING_VVVV)
ENCODING("VK8", ENCODING_VVVV)		ENCODING("VK8", ENCODING_VVVV)
ENCODING("VK16", ENCODING_VVVV)		ENCODING("VK16", ENCODING_VVVV)
ENCODING("VK32", ENCODING_VVVV)		ENCODING("VK32", ENCODING_VVVV)
ENCODING("VK64", ENCODING_VVVV)		ENCODING("VK64", ENCODING_VVVV)
ENCODING("VK1PAIR", ENCODING_VVVV)		ENCODING("VK1PAIR", ENCODING_VVVV)
▲ Show 20 Lines • Show All 122 Lines • Show Last 20 Lines