[SelectionDAGBuilder] Stop setting alignment to one for hidden sret values

[arichardson]

Summary

We allocated a suitably aligned frame index so we know that all the values
have ABI alignment.
For MIPS this avoids using pair of lwl + lwr instructions instead of a
single lw. I found this when compiling CHERI pure capability code where
we can't use the lwl/lwr unaligned loads/stores and and were to falling
back to a byte load + shift + or sequence.

This should save a few instructions for MIPS and possibly other backends
that don't have fast unaligned loads/stores.
It also improves code generation for CodeGen/X86/pr34653.ll since it can
now use aligned loads.

Depends on D78998.

[efriedma]

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

1836

The alignment of the stack slot is computed using Align Alignment = DL.getPrefTypeAlign(CLI.RetTy);, Is there some reason to do something different here?

9287

You don't need to use min() here. The "alignment" argument of getLoad is actually the alignment of the object referred to by the MachinePointerInfo, excluding the offset.

[arichardson]

• address review feedback. Also appears to improve codegen in one wasm test

[efriedma]

LGTM with one minor comment.

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

1849

commonAlignment(BaseAlign, Offsets[i])

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

if (!FuncInfo.CanLowerReturn) {
 
     SmallVector<EVT, 4> ValueVTs, MemVTs;
     SmallVector<uint64_t, 4> Offsets;
     ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &MemVTs,
                     &Offsets);
     unsigned NumValues = ValueVTs.size();
 
     SmallVector<SDValue, 4> Chains(NumValues);
+    Align BaseAlign = DL.getPrefTypeAlign(I.getOperand(0)->getType());
     for (unsigned i = 0; i != NumValues; ++i) {
       // An aggregate return value cannot wrap around the address space, so
       // offsets to its parts don't wrap either.
       SDValue Ptr = DAG.getObjectPtrOffset(getCurSDLoc(), RetPtr, Offsets[i]);
 
       SDValue Val = RetOp.getValue(RetOp.getResNo() + i);
       if (MemVTs[i] != ValueVTs[i])
         Val = DAG.getPtrExtOrTrunc(Val, getCurSDLoc(), MemVTs[i]);
-      Chains[i] = DAG.getStore(Chain, getCurSDLoc(), Val,
+      Chains[i] = DAG.getStore(
+          Chain, getCurSDLoc(), Val,
           // FIXME: better loc info would be nice.
-          Ptr, MachinePointerInfo::getUnknownStack(DAG.getMachineFunction()));
+          Ptr, MachinePointerInfo::getUnknownStack(DAG.getMachineFunction()),
+          commonAlignment(BaseAlign, Offsets[i]));
     }
 
     Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
                         MVT::Other, Chains);
   } else if (I.getNumOperands() != 0) {
     SmallVector<EVT, 4> ValueVTs;
     ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
     unsigned NumValues = ValueVTs.size();
if (!CanLowerReturn) {
     ReturnValues.resize(NumValues);
     SmallVector<SDValue, 4> Chains(NumValues);
 
     // An aggregate return value cannot wrap around the address space, so
     // offsets to its parts don't wrap either.
     SDNodeFlags Flags;
     Flags.setNoUnsignedWrap(true);
 
+    MachineFunction &MF = CLI.DAG.getMachineFunction();
+    Align HiddenSRetAlign = MF.getFrameInfo().getObjectAlign(DemoteStackIdx);
     for (unsigned i = 0; i < NumValues; ++i) {
       SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
                                     CLI.DAG.getConstant(Offsets[i], CLI.DL,
                                                         PtrVT), Flags);
       SDValue L = CLI.DAG.getLoad(
           RetTys[i], CLI.DL, CLI.Chain, Add,
           MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(),
                                             DemoteStackIdx, Offsets[i]),
-          /* Alignment = */ 1);
+          HiddenSRetAlign);
       ReturnValues[i] = L;
       Chains[i] = L.getValue(1);
     }
 
     CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
   } else {
     // Collect the legal value parts into potentially illegal values
     // that correspond to the original function's return values.

llvm/test/CodeGen/Mips/implicit-sret.ll

 define internal void @test() unnamed_addr nounwind {
 ; CHECK-LABEL: test:
 ; CHECK:       # %bb.0: # %start
 ; CHECK-NEXT:    daddiu $sp, $sp, -48
 ; CHECK-NEXT:    sd $ra, 40($sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    daddiu $4, $sp, 8
 ; CHECK-NEXT:    jal implicit_sret_decl
 ; CHECK-NEXT:    nop
-; CHECK-NEXT:    # implicit-def: $at_64
-; CHECK-NEXT:    ldl $1, 24($sp)
-; CHECK-NEXT:    ldr $1, 31($sp)
+; CHECK-NEXT:    ld $6, 24($sp)
+; CHECK-NEXT:    ld $5, 16($sp)
+; CHECK-NEXT:    ld $7, 32($sp)
+; CHECK-NEXT:    lw $1, 8($sp)
 ; CHECK-NEXT:    # implicit-def: $v0_64
-; CHECK-NEXT:    ldl $2, 16($sp)
-; CHECK-NEXT:    ldr $2, 23($sp)
-; CHECK-NEXT:    # implicit-def: $v1_64
-; CHECK-NEXT:    ldl $3, 32($sp)
-; CHECK-NEXT:    ldr $3, 39($sp)
-; CHECK-NEXT:    # implicit-def: $a1
-; CHECK-NEXT:    lwl $5, 8($sp)
-; CHECK-NEXT:    lwr $5, 11($sp)
-; CHECK-NEXT:    # implicit-def: $a0_64
-; CHECK-NEXT:    move $4, $5
-; CHECK-NEXT:    move $5, $2
-; CHECK-NEXT:    move $6, $1
-; CHECK-NEXT:    move $7, $3
+; CHECK-NEXT:    move $2, $1
+; CHECK-NEXT:    move $4, $2
 ; CHECK-NEXT:    jal use_sret
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    ld $ra, 40($sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    daddiu $sp, $sp, 48
 ; CHECK-NEXT:    jr $ra
 ; CHECK-NEXT:    nop
 start:
   %0 = call { i32, i128, i64 } @implicit_sret_decl()

 define internal void @test2() unnamed_addr nounwind {
 ; CHECK-LABEL: test2:
 ; CHECK:       # %bb.0: # %start
 ; CHECK-NEXT:    daddiu $sp, $sp, -32
 ; CHECK-NEXT:    sd $ra, 24($sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    daddiu $4, $sp, 0
 ; CHECK-NEXT:    jal implicit_sret_decl2
 ; CHECK-NEXT:    nop
-; CHECK-NEXT:    # implicit-def: $at
-; CHECK-NEXT:    lwl $1, 20($sp)
-; CHECK-NEXT:    lwr $1, 23($sp)
-; CHECK-NEXT:    # implicit-def: $v0
-; CHECK-NEXT:    lwl $2, 12($sp)
-; CHECK-NEXT:    lwr $2, 15($sp)
-; CHECK-NEXT:    # implicit-def: $v1
-; CHECK-NEXT:    lwl $3, 4($sp)
-; CHECK-NEXT:    lwr $3, 7($sp)
+; CHECK-NEXT:    lw $1, 20($sp)
+; CHECK-NEXT:    lw $2, 12($sp)
+; CHECK-NEXT:    lw $3, 4($sp)
 ; CHECK-NEXT:    # implicit-def: $a0_64
 ; CHECK-NEXT:    move $4, $3
 ; CHECK-NEXT:    # implicit-def: $a1_64
 ; CHECK-NEXT:    move $5, $2
 ; CHECK-NEXT:    # implicit-def: $a2_64
 ; CHECK-NEXT:    move $6, $1
 ; CHECK-NEXT:    jal use_sret2
 ; CHECK-NEXT:    nop

llvm/test/CodeGen/WebAssembly/offset.ll

define void @aggregate_load_store({i32,i32,i32,i32}* %p, {i32,i32,i32,i32}* %q) {
   ret void
 }
 
 ; Fold the offsets when lowering aggregate return values. The stores get
 ; merged into i64 stores.
 
 ; CHECK-LABEL: aggregate_return:
 ; CHECK: i64.const   $push[[L0:[0-9]+]]=, 0{{$}}
-; CHECK: i64.store   8($0):p2align=2, $pop[[L0]]{{$}}
+; CHECK: i64.store   8($0), $pop[[L0]]{{$}}
 ; CHECK: i64.const   $push[[L1:[0-9]+]]=, 0{{$}}
-; CHECK: i64.store   0($0):p2align=2, $pop[[L1]]{{$}}
+; CHECK: i64.store   0($0), $pop[[L1]]{{$}}
 define {i32,i32,i32,i32} @aggregate_return() {
   ret {i32,i32,i32,i32} zeroinitializer
 }
 
 ; Fold the offsets when lowering aggregate return values. The stores are not
 ; merged.
 
 ; CHECK-LABEL: aggregate_return_without_merge:

llvm/test/CodeGen/X86/pr34653.ll

 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    .cfi_offset %rbp, -16
 ; CHECK-NEXT:    movq %rsp, %rbp
 ; CHECK-NEXT:    .cfi_def_cfa_register %rbp
 ; CHECK-NEXT:    andq $-512, %rsp # imm = 0xFE00
 ; CHECK-NEXT:    subq $1536, %rsp # imm = 0x600
 ; CHECK-NEXT:    leaq {{[0-9]+}}(%rsp), %rdi
 ; CHECK-NEXT:    callq test
-; CHECK-NEXT:    vmovupd {{[0-9]+}}(%rsp), %xmm0
-; CHECK-NEXT:    vmovupd {{[0-9]+}}(%rsp), %xmm1
-; CHECK-NEXT:    vmovupd {{[0-9]+}}(%rsp), %xmm2
-; CHECK-NEXT:    vmovupd {{[0-9]+}}(%rsp), %xmm3
-; CHECK-NEXT:    vmovupd {{[0-9]+}}(%rsp), %xmm4
-; CHECK-NEXT:    vmovupd {{[0-9]+}}(%rsp), %xmm5
-; CHECK-NEXT:    vmovupd {{[0-9]+}}(%rsp), %xmm6
-; CHECK-NEXT:    vmovupd {{[0-9]+}}(%rsp), %xmm7
-; CHECK-NEXT:    vmovupd {{[0-9]+}}(%rsp), %xmm8
-; CHECK-NEXT:    vmovupd {{[0-9]+}}(%rsp), %xmm9
-; CHECK-NEXT:    vmovupd {{[0-9]+}}(%rsp), %xmm10
-; CHECK-NEXT:    vmovupd {{[0-9]+}}(%rsp), %xmm11
-; CHECK-NEXT:    vmovupd {{[0-9]+}}(%rsp), %xmm12
-; CHECK-NEXT:    vmovupd {{[0-9]+}}(%rsp), %xmm13
-; CHECK-NEXT:    vmovupd {{[0-9]+}}(%rsp), %xmm14
-; CHECK-NEXT:    vmovupd {{[0-9]+}}(%rsp), %xmm15
-; CHECK-NEXT:    vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT:    vmovupd {{[0-9]+}}(%rsp), %xmm0
-; CHECK-NEXT:    vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT:    vmovupd {{[0-9]+}}(%rsp), %xmm0
-; CHECK-NEXT:    vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT:    vmovupd {{[0-9]+}}(%rsp), %xmm0
+; CHECK-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-NEXT:    vmovsd {{.*#+}} xmm1 = mem[0],zero
+; CHECK-NEXT:    vmovsd {{.*#+}} xmm2 = mem[0],zero
+; CHECK-NEXT:    vmovsd {{.*#+}} xmm3 = mem[0],zero
+; CHECK-NEXT:    vmovsd {{.*#+}} xmm4 = mem[0],zero
+; CHECK-NEXT:    vmovsd {{.*#+}} xmm5 = mem[0],zero
+; CHECK-NEXT:    vmovsd {{.*#+}} xmm6 = mem[0],zero
+; CHECK-NEXT:    vmovsd {{.*#+}} xmm7 = mem[0],zero
+; CHECK-NEXT:    vmovsd {{.*#+}} xmm8 = mem[0],zero
+; CHECK-NEXT:    vmovsd {{.*#+}} xmm9 = mem[0],zero
+; CHECK-NEXT:    vmovsd {{.*#+}} xmm10 = mem[0],zero
+; CHECK-NEXT:    vmovsd {{.*#+}} xmm11 = mem[0],zero
+; CHECK-NEXT:    vmovsd {{.*#+}} xmm12 = mem[0],zero
+; CHECK-NEXT:    vmovsd {{.*#+}} xmm13 = mem[0],zero
+; CHECK-NEXT:    vmovsd {{.*#+}} xmm14 = mem[0],zero
+; CHECK-NEXT:    vmovsd {{.*#+}} xmm15 = mem[0],zero
 ; CHECK-NEXT:    vmovsd {{.*#+}} xmm16 = mem[0],zero
 ; CHECK-NEXT:    vmovsd {{.*#+}} xmm17 = mem[0],zero
 ; CHECK-NEXT:    vmovsd {{.*#+}} xmm18 = mem[0],zero
 ; CHECK-NEXT:    vmovsd {{.*#+}} xmm19 = mem[0],zero
 ; CHECK-NEXT:    vmovsd {{.*#+}} xmm20 = mem[0],zero
 ; CHECK-NEXT:    vmovsd {{.*#+}} xmm21 = mem[0],zero
 ; CHECK-NEXT:    vmovsd {{.*#+}} xmm22 = mem[0],zero
 ; CHECK-NEXT:    vmovsd {{.*#+}} xmm23 = mem[0],zero
 ; CHECK-NEXT:    vmovsd {{.*#+}} xmm24 = mem[0],zero
 ; CHECK-NEXT:    vmovsd {{.*#+}} xmm25 = mem[0],zero
 ; CHECK-NEXT:    vmovsd {{.*#+}} xmm26 = mem[0],zero
 ; CHECK-NEXT:    vmovsd {{.*#+}} xmm27 = mem[0],zero
 ; CHECK-NEXT:    vmovsd {{.*#+}} xmm28 = mem[0],zero
 ; CHECK-NEXT:    vmovsd {{.*#+}} xmm29 = mem[0],zero
 ; CHECK-NEXT:    vmovsd {{.*#+}} xmm30 = mem[0],zero
 ; CHECK-NEXT:    vmovsd {{.*#+}} xmm31 = mem[0],zero
 ; CHECK-NEXT:    vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; CHECK-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; CHECK-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; CHECK-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT:    vmovsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
-; CHECK-NEXT:    # xmm0 = mem[0],zero
-; CHECK-NEXT:    vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT:    vmovsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
-; CHECK-NEXT:    # xmm0 = mem[0],zero
+; CHECK-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT:    vmovsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
-; CHECK-NEXT:    # xmm0 = mem[0],zero
+; CHECK-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT:    vmovsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
-; CHECK-NEXT:    # xmm0 = mem[0],zero
+; CHECK-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    movq %rbp, %rsp
 ; CHECK-NEXT:    popq %rbp
 ; CHECK-NEXT:    .cfi_def_cfa %rsp, 8
 ; CHECK-NEXT:    retq
 entry:
   %v = call fastcc <38 x double> @test()
   %v.0 = extractelement <38 x double> %v, i32 0
   ret void
 }