AArch64: materialize large stack offset into xzr correctly.

[t.p.northover]

Summary

When a stack offset was too big to materialize in a single instruction, we were trying to do it in stages:

adds xD, sp, #imm
adds xD, xD, #imm

Unfortunately, if xD is xzr then the second instruction (adds xzr, xzr, #imm) doesn't exist and wouldn't do what was needed if it did. Instead we can use a temporary register for all but the last addition.

[ostannard]

llvm/test/CodeGen/AArch64/large-stack-cmp.ll

5

If two adds are being emitted we should test for both of them, and it would be good to test the immediate values too.

[ostannard]

Actually, if the destination is XZR, the adds won't have any effect, so surely we don't need to emit any instructions? Could we just early-return without emitting anything if DestReg == XZR?

[t.p.northover]

Actually, if the destination is XZR, the adds won't have any effect, so surely we don't need to emit any instructions? Could we just early-return without emitting anything if DestReg == XZR?

The operation is actually a comparison so the nzcv produced is live. And since the code is needed anyway I'd be inclined to let generic DCE handle the non-flag-setting variant.

llvm/test/CodeGen/AArch64/large-stack-cmp.ll

5

cmn is the canonical alias for adds when the destination is xzr, so we already are.

[t.p.northover]

Ping.

[t.p.northover]

Ping.

[ostannard]

LGTM

[t.p.northover]

Thanks. Pushed as dace8224f38a.

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

   //  assert(Offset < (1 << 24) && "unimplemented reg plus immediate");
 
   const unsigned MaxEncodableValue = MaxEncoding << ShiftSize;
+  Register TmpReg = DestReg;
+  if (TmpReg == AArch64::XZR)
+    TmpReg = MBB.getParent()->getRegInfo().createVirtualRegister(
+        &AArch64::GPR64RegClass);
   do {
     uint64_t ThisVal = std::min<uint64_t>(Offset, MaxEncodableValue);
     unsigned LocalShiftSize = 0;

     }
     assert((ThisVal >> ShiftSize) <= MaxEncoding &&
            "Encoding cannot handle value that big");
-    auto MBI = BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
+
+    Offset -= ThisVal << LocalShiftSize;
+    if (Offset == 0)
+      TmpReg = DestReg;
+    auto MBI = BuildMI(MBB, MBBI, DL, TII->get(Opc), TmpReg)
                    .addReg(SrcReg)
                    .addImm(Sign * (int)ThisVal);
     if (ShiftSize)

           BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_AddFP))
               .addImm(Imm)
               .setMIFlag(Flag);
-        assert((Offset - Imm) == 0 && "Expected remaining offset to be zero to "
-                                      "emit a single SEH directive");
+        assert(Offset == 0 && "Expected remaining offset to be zero to "
       } else if (DestReg == AArch64::SP) {
         if (HasWinCFI)
           *HasWinCFI = true;

         *HasWinCFI = true;
     }
 
-    SrcReg = DestReg;
-    Offset -= ThisVal << LocalShiftSize;
+    SrcReg = TmpReg;
   } while (Offset);
 }
 

llvm/test/CodeGen/AArch64/large-stack-cmp.ll

+; RUN: llc -mtriple=arm64-apple-ios %s -o - | FileCheck %s
+
+define void @foo() {
+; CHECK-LABEL: foo:
+; CHECK: adds [[TMP:x[0-9]+]], sp,
+; CHECK: cmn [[TMP]],
+
+%var = alloca i32, i32 12
+  %var2 = alloca i32, i32 1030
+  %tst = icmp eq i32* %var, null
+  br i1 %tst, label %true, label %false
+
+true:
+  call void @bar()
+  ret void
+
+false:
+  call void @baz()
+  ret void
+}
+
+declare void @bar()
+declare void @baz()