[llvm] [X86] Fixed type bug in vselect for AVX masked load

[aartbik]

Summary

Bugzilla issue 45563
https://bugs.llvm.org/show_bug.cgi?id=45563

[mehdi_amini]

Nice find! LGTM, but it'd be better to wait for @craig.topper approval as well.

[craig.topper]

LGTM

[RKSimon]

llvm/test/CodeGen/X86/avx-bug-45563.ll

1 ↗

(On Diff #258877)

@aartbik Very minor but please can you rename this file pr45563.ll ?

[aartbik]

renamed regression test

llvm/test/CodeGen/X86/avx-bug-45563.ll

1 ↗

(On Diff #258877)

Renamed.

[nemanjai]

llvm/test/CodeGen/X86/pr45563.ll

1

This test case is causing failures on non-X86 built bots. The target triple is missing which means that the default triple will be used - which will be different on every target.
Example of a failure:
http://lab.llvm.org:8011/builders/clang-ppc64le-linux-multistage/builds/12152/steps/ninja%20check%201/logs/FAIL%3A%20LLVM%3A%3Apr45563.ll

llvm/lib/Target/X86/X86ISelLowering.cpp

if (PassThru.isUndef() || ISD::isBuildVectorAllZeros(PassThru.getNode()))
       return Op;
 
     SDValue NewLoad = DAG.getMaskedLoad(
         VT, dl, N->getChain(), N->getBasePtr(), N->getOffset(), Mask,
         getZeroVector(VT, Subtarget, DAG, dl), N->getMemoryVT(),
         N->getMemOperand(), N->getAddressingMode(), N->getExtensionType(),
         N->isExpandingLoad());
     // Emit a blend.
-    SDValue Select = DAG.getNode(ISD::VSELECT, dl, MaskVT, Mask, NewLoad,
-                                 PassThru);
+    SDValue Select = DAG.getNode(ISD::VSELECT, dl, VT, Mask, NewLoad, PassThru);
     return DAG.getMergeValues({ Select, NewLoad.getValue(1) }, dl);
   }
 
   assert((!N->isExpandingLoad() || Subtarget.hasAVX512()) &&
          "Expanding masked load is supported on AVX-512 target only!");
 
   assert((!N->isExpandingLoad() || ScalarVT.getSizeInBits() >= 32) &&
          "Expanding masked load is supported for 32 and 64-bit types only!");
static SDValue LowerMLOAD(SDValue Op, const X86Subtarget &Subtarget,
   MVT WideMaskVT = MVT::getVectorVT(MVT::i1, NumEltsInWideVec);
 
   Mask = ExtendToType(Mask, WideMaskVT, DAG, true);
   SDValue NewLoad = DAG.getMaskedLoad(
       WideDataVT, dl, N->getChain(), N->getBasePtr(), N->getOffset(), Mask,
       PassThru, N->getMemoryVT(), N->getMemOperand(), N->getAddressingMode(),
       N->getExtensionType(), N->isExpandingLoad());
 
-  SDValue Exract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
-                               NewLoad.getValue(0),
-                               DAG.getIntPtrConstant(0, dl));
-  SDValue RetOps[] = {Exract, NewLoad.getValue(1)};
+  SDValue Extract =
+      DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, NewLoad.getValue(0),
+  SDValue RetOps[] = {Extract, NewLoad.getValue(1)};
   return DAG.getMergeValues(RetOps, dl);
 }
 
 static SDValue LowerMSTORE(SDValue Op, const X86Subtarget &Subtarget,
                            SelectionDAG &DAG) {
   MaskedStoreSDNode *N = cast<MaskedStoreSDNode>(Op.getNode());
   SDValue DataToStore = N->getValue();
   MVT VT = DataToStore.getSimpleValueType();

llvm/test/CodeGen/X86/pr45563.ll

+; RUN: llc < %s -debug-only=isel -O3 -mattr=avx  2>&1 | FileCheck %s
+
+; Bug 45563:
+; The LowerMLOAD() method AVX masked load branch should
+; use the operand vector type rather than the mask type.
+; Given, for example:
+;   v4f64,ch = masked_load ..
+; The select should be:
+;   v4f64 = vselect ..
+; instead of:
+;   v4i64 = vselect ..
+
+define <16 x double> @bug45563(<16 x double>* %addr, <16 x double> %dst, <16 x i64> %e, <16 x i64> %f) {
+; CHECK-LABEL: bug45563:
+; CHECK:       v4f64 = vselect
+  %mask = icmp slt <16 x i64> %e, %f
+  %res = call <16 x double> @llvm.masked.load.v16f64.p0v16f64(<16 x double>* %addr, i32 4, <16 x i1>%mask, <16 x double> %dst)
+  ret <16 x double> %res
+}
+
+declare <16 x double> @llvm.masked.load.v16f64.p0v16f64(<16 x double>* %addr, i32 %align, <16 x i1> %mask, <16 x double> %dst)