[SDAG] simplify FP binops to undef

[spatel]

Summary

As discussed in the commit thread for rGa253a2a and D73978, we can do more undef folding for FP ops. The nnan and ninf fast-math-flags specify that if an operand is the disallowed value, the result is poison, so we can produce an undef result.

But this doesn't work as expected (the undef operand cases remain) because of a Flags propagation problem in SelectionDAGBuilder.

I've added DAGCombiner calls to enable these for the other cases because we've shown in other patches that (because of the limited way that SDAG iterates), it is possible to miss simplifications like this if they are done only at node creation time.

[aqjune]

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

7307

Nit: I think it is opposite; poison -> undef is allowed, but undef -> poison is not allowed. LangRef says a poison value may be relaxed into an undef value, which takes an arbitrary bit-pattern.

[lebedev.ri]

LGTM, thank you.
If we don't do this in middle-end, we should.

I'm guessing this is already done for FNEG?
What about FCMP/PHI/SELECT?

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

7307

I think i agree here.

[spatel]

Patch updated:
Improved code comment.

[spatel]

In D75576#1904936, @lebedev.ri wrote:

LGTM, thank you.
If we don't do this in middle-end, we should.

Yes, that would be a follow-on. There's less risk/reward in making the change here vs. IR, so I started here to be safer.

I'm guessing this is already done for FNEG?
What about FCMP/PHI/SELECT?

FNEG - no. Similarly, we don't do much/anything with opcodes that exist in SDAG but not IR.
FCMP is still in flux. We allow FMF on those currently, but I've been trying to transition away from that. So PHI/SELECT are relatively new to allow FMF in IR, and that has not been extended to SDAG yet.
In summary, we're a long way from complete in either layer.

llvm/include/llvm/CodeGen/SelectionDAG.h

#endif
   /// Try to simplify a select/vselect into 1 of its operands or a constant.
   SDValue simplifySelect(SDValue Cond, SDValue TVal, SDValue FVal);
 
   /// Try to simplify a shift into 1 of its operands or a constant.
   SDValue simplifyShift(SDValue X, SDValue Y);
 
   /// Try to simplify a floating-point binary operation into 1 of its operands
   /// or a constant.
-  SDValue simplifyFPBinop(unsigned Opcode, SDValue X, SDValue Y);
+  SDValue simplifyFPBinop(unsigned Opcode, SDValue X, SDValue Y,
+                          SDNodeFlags Flags);
 
   /// VAArg produces a result and token chain, and takes a pointer
   /// and a source value as input.
   SDValue getVAArg(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr,
                    SDValue SV, unsigned Align);
 
   /// Gets a node for an atomic cmpxchg op. There are two
   /// valid Opcodes. ISD::ATOMIC_CMO_SWAP produces the value loaded and a

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

SDValue DAGCombiner::visitFADD(SDNode *N) {
   SDValue N1 = N->getOperand(1);
   bool N0CFP = isConstantFPBuildVectorOrConstantFP(N0);
   bool N1CFP = isConstantFPBuildVectorOrConstantFP(N1);
   EVT VT = N->getValueType(0);
   SDLoc DL(N);
   const TargetOptions &Options = DAG.getTarget().Options;
   const SDNodeFlags Flags = N->getFlags();
 
+  if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags))
+    return R;
+
   // fold vector ops
   if (VT.isVector())
     if (SDValue FoldedVOp = SimplifyVBinOp(N))
       return FoldedVOp;
 
   // fold (fadd c1, c2) -> c1 + c2
   if (N0CFP && N1CFP)
     return DAG.getNode(ISD::FADD, DL, VT, N0, N1, Flags);
SDValue DAGCombiner::visitFSUB(SDNode *N) {
   SDValue N1 = N->getOperand(1);
   ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0, true);
   ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1, true);
   EVT VT = N->getValueType(0);
   SDLoc DL(N);
   const TargetOptions &Options = DAG.getTarget().Options;
   const SDNodeFlags Flags = N->getFlags();
 
+  if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags))
+    return R;
+
   // fold vector ops
   if (VT.isVector())
     if (SDValue FoldedVOp = SimplifyVBinOp(N))
       return FoldedVOp;
 
   // fold (fsub c1, c2) -> c1-c2
   if (N0CFP && N1CFP)
     return DAG.getNode(ISD::FSUB, DL, VT, N0, N1, Flags);
SDValue DAGCombiner::visitFMUL(SDNode *N) {
   SDValue N1 = N->getOperand(1);
   ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0, true);
   ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1, true);
   EVT VT = N->getValueType(0);
   SDLoc DL(N);
   const TargetOptions &Options = DAG.getTarget().Options;
   const SDNodeFlags Flags = N->getFlags();
 
+  if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags))
+    return R;
+
   // fold vector ops
   if (VT.isVector()) {
     // This just handles C1 * C2 for vectors. Other vector folds are below.
     if (SDValue FoldedVOp = SimplifyVBinOp(N))
       return FoldedVOp;
   }
 
   // fold (fmul c1, c2) -> c1*c2
SDValue DAGCombiner::visitFDIV(SDNode *N) {
   SDValue N1 = N->getOperand(1);
   ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
   ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
   EVT VT = N->getValueType(0);
   SDLoc DL(N);
   const TargetOptions &Options = DAG.getTarget().Options;
   SDNodeFlags Flags = N->getFlags();
 
+  if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags))
+    return R;
+
   // fold vector ops
   if (VT.isVector())
     if (SDValue FoldedVOp = SimplifyVBinOp(N))
       return FoldedVOp;
 
   // fold (fdiv c1, c2) -> c1/c2
   if (N0CFP && N1CFP)
     return DAG.getNode(ISD::FDIV, SDLoc(N), VT, N0, N1, Flags);

 }
 
 SDValue DAGCombiner::visitFREM(SDNode *N) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
   ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
   ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
   EVT VT = N->getValueType(0);
+  SDNodeFlags Flags = N->getFlags();
+
+  if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags))
+    return R;
 
   // fold (frem c1, c2) -> fmod(c1,c2)
   if (N0CFP && N1CFP)
     return DAG.getNode(ISD::FREM, SDLoc(N), VT, N0, N1, N->getFlags());
 
   if (SDValue NewSel = foldBinOpIntoSelect(N))
     return NewSel;
 

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
   case ISD::FADD:
   case ISD::FSUB:
   case ISD::FMUL:
   case ISD::FDIV:
   case ISD::FREM:
     assert(VT.isFloatingPoint() && "This operator only applies to FP types!");
     assert(N1.getValueType() == N2.getValueType() &&
            N1.getValueType() == VT && "Binary operator types must match!");
-    if (SDValue V = simplifyFPBinop(Opcode, N1, N2))
+    if (SDValue V = simplifyFPBinop(Opcode, N1, N2, Flags))
       return V;
     break;
   case ISD::FCOPYSIGN:   // N1 and result must match.  N1/N2 need not match.
     assert(N1.getValueType() == VT &&
            N1.getValueType().isFloatingPoint() &&
            N2.getValueType().isFloatingPoint() &&
            "Invalid FCOPYSIGN!");
     break;
auto isShiftTooBig = [X](ConstantSDNode *Val) {
     return !Val || Val->getAPIntValue().uge(X.getScalarValueSizeInBits());
   };
   if (ISD::matchUnaryPredicate(Y, isShiftTooBig, true))
     return getUNDEF(X.getValueType());
 
   return SDValue();
 }
 
-// TODO: Use fast-math-flags to enable more simplifications.
-SDValue SelectionDAG::simplifyFPBinop(unsigned Opcode, SDValue X, SDValue Y) {
+SDValue SelectionDAG::simplifyFPBinop(unsigned Opcode, SDValue X, SDValue Y,
+                                      SDNodeFlags Flags) {
+  // If this operation has 'nnan' or 'ninf' and at least 1 disallowed operand
+  // (an undef operand can be chosen to be Nan/Inf), then the result of this
+  // operation is poison. That result can be relaxed to undef.
+  ConstantFPSDNode *XC = isConstOrConstSplatFP(X, /* AllowUndefs */ true);
   ConstantFPSDNode *YC = isConstOrConstSplatFP(Y, /* AllowUndefs */ true);
+  bool HasNan = (XC && XC->getValueAPF().isNaN()) ||
+                (YC && YC->getValueAPF().isNaN());
+  bool HasInf = (XC && XC->getValueAPF().isInfinity()) ||
+                (YC && YC->getValueAPF().isInfinity());
+
+  if (Flags.hasNoNaNs() && (HasNan || X.isUndef() || Y.isUndef()))
+    return getUNDEF(X.getValueType());
+
+  if (Flags.hasNoInfs() && (HasInf || X.isUndef() || Y.isUndef()))
+    return getUNDEF(X.getValueType());
+
   if (!YC)
     return SDValue();
 
   // X + -0.0 --> X
   if (Opcode == ISD::FADD)
     if (YC->getValueAPF().isNegZero())
       return X;
 

llvm/test/CodeGen/AArch64/fp-const-fold.ll

 ; CHECK-NEXT:    ret
   %r =  call double @llvm.fma.f64(double 0x7ff0000000000000, double 0.0, double 42.0)
   ret double %r
 }
 
 define double @fdiv_nnan_nan_op0(double %x) {
 ; CHECK-LABEL: fdiv_nnan_nan_op0:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #-2251799813685248
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fdiv d0, d1, d0
 ; CHECK-NEXT:    ret
   %r = fdiv nnan double 0xfff8000000000000, %x
   ret double %r
 }
 
 define double @fmul_nnan_nan_op1(double %x) {
 ; CHECK-LABEL: fmul_nnan_nan_op1:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #9221120237041090560
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fmul d0, d0, d1
 ; CHECK-NEXT:    ret
   %r = fmul nnan double %x, 0x7ff8000000000000
   ret double %r
 }
 
+; Negative test - nan is ok.
+; TODO: Should simplify to nan.
+
 define double @fdiv_ninf_nan_op0(double %x) {
 ; CHECK-LABEL: fdiv_ninf_nan_op0:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #-2251799813685248
 ; CHECK-NEXT:    fmov d1, x8
 ; CHECK-NEXT:    fdiv d0, d1, d0
 ; CHECK-NEXT:    ret
   %r = fdiv ninf double 0xfff8000000000000, %x
   ret double %r
 }
 
+; Negative test - nan is ok.
+; TODO: Should simplify to nan.
+
 define double @fadd_ninf_nan_op1(double %x) {
 ; CHECK-LABEL: fadd_ninf_nan_op1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #9221120237041090560
 ; CHECK-NEXT:    fmov d1, x8
 ; CHECK-NEXT:    fadd d0, d0, d1
 ; CHECK-NEXT:    ret
   %r = fadd ninf double %x, 0x7ff8000000000000
   ret double %r
 }
 
 define double @fdiv_ninf_inf_op0(double %x) {
 ; CHECK-LABEL: fdiv_ninf_inf_op0:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #9218868437227405312
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fdiv d0, d1, d0
 ; CHECK-NEXT:    ret
   %r = fdiv ninf double 0x7ff0000000000000, %x
   ret double %r
 }
 
 define double @fadd_ninf_inf_op1(double %x) {
 ; CHECK-LABEL: fadd_ninf_inf_op1:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #-4503599627370496
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fadd d0, d0, d1
 ; CHECK-NEXT:    ret
   %r = fadd ninf double %x, 0xfff0000000000000
   ret double %r
 }
 
+; Negative test - inf is ok.
+; TODO: Should simplify to inf.
+
 define double @fsub_nnan_inf_op0(double %x) {
 ; CHECK-LABEL: fsub_nnan_inf_op0:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #9218868437227405312
 ; CHECK-NEXT:    fmov d1, x8
 ; CHECK-NEXT:    fsub d0, d1, d0
 ; CHECK-NEXT:    ret
   %r = fsub nnan double 0x7ff0000000000000, %x
   ret double %r
 }
 
+; Negative test - inf is ok.
+; TODO: Should simplify to -inf.
+
 define double @fmul_nnan_inf_op1(double %x) {
 ; CHECK-LABEL: fmul_nnan_inf_op1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #-4503599627370496
 ; CHECK-NEXT:    fmov d1, x8
 ; CHECK-NEXT:    fmul d0, d0, d1
 ; CHECK-NEXT:    ret
   %r = fmul nnan double %x, 0xfff0000000000000
   ret double %r
 }
 
+; TODO: Should simplify to undef
+
 define double @fdiv_nnan_undef_op0(double %x) {
 ; CHECK-LABEL: fdiv_nnan_undef_op0:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #9221120237041090560
 ; CHECK-NEXT:    fmov d0, x8
 ; CHECK-NEXT:    ret
   %r = fdiv nnan double undef, %x
   ret double %r
 }
 
+; TODO: Should simplify to undef
+
 define double @fdiv_nnan_undef_op1(double %x) {
 ; CHECK-LABEL: fdiv_nnan_undef_op1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #9221120237041090560
 ; CHECK-NEXT:    fmov d0, x8
 ; CHECK-NEXT:    ret
   %r = fdiv nnan double %x, undef
   ret double %r
 }
 
+; TODO: Should simplify to undef
+
 define double @fdiv_ninf_undef_op0(double %x) {
 ; CHECK-LABEL: fdiv_ninf_undef_op0:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #9221120237041090560
 ; CHECK-NEXT:    fmov d0, x8
 ; CHECK-NEXT:    ret
   %r = fdiv ninf double undef, %x
   ret double %r
 }
 
+; TODO: Should simplify to undef
+
 define double @fdiv_ninf_undef_op1(double %x) {
 ; CHECK-LABEL: fdiv_ninf_undef_op1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #9221120237041090560
 ; CHECK-NEXT:    fmov d0, x8
 ; CHECK-NEXT:    ret
   %r = fdiv ninf double %x, undef
   ret double %r
 }
 
 declare double @llvm.fma.f64(double, double, double)