This patch reuses the existing MatchRotate ROTL/ROTR rotation pattern code to also recognize the more general FSHL/FSHR funnel shift patterns when we have constant shift amounts.
Details
Diff Detail
- Repository
- rG LLVM Github Monorepo
Event Timeline
llvm/test/CodeGen/X86/avg.ll | ||
---|---|---|
2564–2592 | All this doesn't look like an improvement, | |
llvm/test/CodeGen/X86/bitreverse.ll | ||
1114 ↗ | (On Diff #246436) | Technically this implies more registers are being used here, |
llvm/test/CodeGen/X86/known-bits.ll | ||
123 | Demandedbits failure? (no longer narrowed into 32-bit) |
The Hexagon changes LGTM.
llvm/lib/Target/Hexagon/HexagonPatterns.td | ||
---|---|---|
1098 ↗ | (On Diff #246436) | You are correct. This should be A2_combine_lh. |
llvm/lib/Target/Hexagon/HexagonPatterns.td | ||
---|---|---|
1098 ↗ | (On Diff #246436) | Cheers, I'll create a test and commit the fix shortly. |
llvm/test/CodeGen/X86/known-bits.ll | ||
---|---|---|
123 | I'm still looking at the best way to handle overflow ops with SimplifyDemandedBits/ShrinkDemandedOp |
LGTM - see inline for a nit.
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | ||
---|---|---|
6418–6419 | Nit: the code structure of these checks seems odd to me. if (IsRotate && (HasROTL || HasROTR)) Res = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, LHSShiftArg, HasROTL ? LHSShiftAmt : RHSShiftAmt); else Res = DAG.getNode(HasFSHL ? ISD::FSHL : ISD::FSHR, DL, VT, LHSShiftArg, RHSShiftArg, HasFSHL ? LHSShiftAmt : RHSShiftAmt); |
/// ... where C1+C2 == bitwidth(x)