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Differential D75030

[AMDGPU] Use conservative defaults for XNACK/SRAM ECC
AbandonedPublic

Authored by kerbowa on Feb 23 2020, 11:03 PM.

Details

Reviewers
rampitec
arsenm
t-tye
kzhuravl
nhaehnle
scott.linder
Summary

RFC. WIP. Use conservatively correct settings for XNACK and SRAM ECC for all
subtargets which may support either feature. The conservative settings
in this case are XNACK on and SRAM ECC on.

Although some additional updates must be completed outside of the
backend to facilitate this change, I'm posting this review now for
visibility.

Diff Detail

Event Timeline

kerbowa created this revision.Feb 23 2020, 11:03 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 23 2020, 11:03 PM
Herald added subscribers: llvm-commits, asbirlea, jfb and 8 others. · View Herald Transcript
Harbormaster completed remote builds in B47111: Diff 246143.Feb 23 2020, 11:12 PM
asbirlea removed a subscriber: asbirlea.Feb 24 2020, 7:29 AM
rampitec added a comment.Feb 24 2020, 9:59 AM

Maybe extract AMDGPU.td changes into a separate patch for the time being? These seem safe.

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
155

That's a right thing to do, but I suppose needs some testing and fixing at least known apps doing so before we can submit.

kerbowa edited the summary of this revision. (Show Details)Feb 28 2020, 7:16 AM
scott.linder added a reviewer: scott.linder.Feb 28 2020, 7:19 AM
scott.linder added a subscriber: scott.linder.
scott.linder added inline comments.
llvm/lib/Target/AMDGPU/AMDGPU.td
753

Could you also include an update to processors table in llvm/docs/AMDGPUUsage.rst for all the changing defaults? It is currently wrong anyway because we forbid XNACK on some targets, but if we are fixing things it would be good to fix it as well.

arsenm added inline comments.Apr 2 2020, 9:11 AM
llvm/lib/Target/AMDGPU/AMDGPU.td
781

This feature should really be removed from all subtargets, but that's a separate change

kerbowa abandoned this revision.Oct 19 2020, 9:36 AM
Herald added a subscriber: wenlei. · View Herald TranscriptOct 19 2020, 9:36 AM

Large Diff

This large diff affects 176 files. Files without inline comments have been collapsed. Expand All Files

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Diff 246143

llvm/lib/Target/AMDGPU/AMDGPU.td

Show First 20 Lines • Show All 630 Lines • ▼ Show 20 Linesclass GCNSubtargetFeatureGeneration <string Value,
list<SubtargetFeature> Implies> : list<SubtargetFeature> Implies> :
SubtargetFeatureGeneration <Value, FeatureName, "GCNSubtarget", Implies>; SubtargetFeatureGeneration <Value, FeatureName, "GCNSubtarget", Implies>;
def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS", def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
"southern-islands", "southern-islands",
[FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128, [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
FeatureWavefrontSize64, FeatureWavefrontSize64,
FeatureLDSBankCount32, FeatureMovrel, FeatureTrigReducedRange, FeatureLDSBankCount32, FeatureMovrel, FeatureTrigReducedRange,
FeatureDoesNotSupportSRAMECC, FeatureDoesNotSupportXNACK] FeatureDoesNotSupportXNACK, FeatureDoesNotSupportSRAMECC]>;
>;
def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS", def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
"sea-islands", "sea-islands",
[FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128, [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureWavefrontSize64, FeatureFlatAddressSpace,
FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange, FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange,
FeatureGFX7GFX8GFX9Insts, FeatureDoesNotSupportSRAMECC] FeatureGFX7GFX8GFX9Insts, FeatureDoesNotSupportXNACK,
>; FeatureDoesNotSupportSRAMECC]>;
def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS", def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
"volcanic-islands", "volcanic-islands",
[FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128, [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureWavefrontSize64, FeatureFlatAddressSpace,
FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts, FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel, FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
FeatureScalarStores, FeatureInv2PiInlineImm, FeatureScalarStores, FeatureInv2PiInlineImm,
FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP, FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
FeatureIntClamp, FeatureTrigReducedRange, FeatureDoesNotSupportSRAMECC, FeatureIntClamp, FeatureTrigReducedRange, FeatureGFX8Insts,
FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts FeatureGFX7GFX8GFX9Insts, FeatureDoesNotSupportSRAMECC]>;
]
>;
def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9", def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
"gfx9", "gfx9",
[FeatureFP64, FeatureLocalMemorySize65536, [FeatureFP64, FeatureLocalMemorySize65536,
FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureWavefrontSize64, FeatureFlatAddressSpace,
FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts, FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm, FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode, FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
FeatureFastFMAF32, FeatureDPP, FeatureIntClamp, FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst, FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts, FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
FeatureAddNoCarryInsts, FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts, FeatureAddNoCarryInsts, FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts,
FeatureScalarFlatScratchInsts, FeatureScalarAtomics, FeatureR128A16 FeatureScalarFlatScratchInsts, FeatureScalarAtomics, FeatureR128A16]>;
]
>;
def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10", def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10",
"gfx10", "gfx10",
[FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128, [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
FeatureFlatAddressSpace, FeatureFlatAddressSpace,
FeatureCIInsts, Feature16BitInsts, FeatureCIInsts, Feature16BitInsts,
FeatureSMemRealTime, FeatureInv2PiInlineImm, FeatureSMemRealTime, FeatureInv2PiInlineImm,
FeatureApertureRegs, FeatureGFX9Insts, FeatureGFX10Insts, FeatureVOP3P, FeatureApertureRegs, FeatureGFX9Insts, FeatureGFX10Insts, FeatureVOP3P,
FeatureMovrel, FeatureFastFMAF32, FeatureDPP, FeatureIntClamp, FeatureMovrel, FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst, FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts, FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
FeatureAddNoCarryInsts, FeatureFmaMixInsts, FeatureGFX8Insts, FeatureAddNoCarryInsts, FeatureFmaMixInsts, FeatureGFX8Insts,
FeatureNoSdstCMPX, FeatureVscnt, FeatureRegisterBanking, FeatureNoSdstCMPX, FeatureVscnt, FeatureRegisterBanking,
FeatureVOP3Literal, FeatureDPP8, FeatureVOP3Literal, FeatureDPP8, FeatureNoDataDepHazard,
FeatureNoDataDepHazard, FeaturePkFmacF16Inst, FeatureDoesNotSupportSRAMECC, FeaturePkFmacF16Inst, FeatureGFX10A16, FeatureDoesNotSupportSRAMECC]>;
FeatureGFX10A16
]
>;
class FeatureSet<list<SubtargetFeature> Features_> { class FeatureSet<list<SubtargetFeature> Features_> {
list<SubtargetFeature> Features = Features_; list<SubtargetFeature> Features = Features_;
} }
def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands, def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands,
FeatureFastFMAF32, FeatureFastFMAF32,
HalfRate64Ops, HalfRate64Ops,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureDoesNotSupportXNACK,
FeatureCodeObjectV3]>; FeatureCodeObjectV3]>;
def FeatureISAVersion6_0_1 : FeatureSet< def FeatureISAVersion6_0_1 : FeatureSet<
[FeatureSouthernIslands, [FeatureSouthernIslands,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureDoesNotSupportXNACK,
FeatureCodeObjectV3]>; FeatureCodeObjectV3]>;
def FeatureISAVersion7_0_0 : FeatureSet< def FeatureISAVersion7_0_0 : FeatureSet<
[FeatureSeaIslands, [FeatureSeaIslands,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureDoesNotSupportXNACK,
FeatureCodeObjectV3]>; FeatureCodeObjectV3]>;
def FeatureISAVersion7_0_1 : FeatureSet< def FeatureISAVersion7_0_1 : FeatureSet<
[FeatureSeaIslands, [FeatureSeaIslands,
HalfRate64Ops, HalfRate64Ops,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureFastFMAF32, FeatureFastFMAF32,
FeatureDoesNotSupportXNACK,
FeatureCodeObjectV3]>; FeatureCodeObjectV3]>;
def FeatureISAVersion7_0_2 : FeatureSet< def FeatureISAVersion7_0_2 : FeatureSet<
[FeatureSeaIslands, [FeatureSeaIslands,
FeatureLDSBankCount16, FeatureLDSBankCount16,
FeatureFastFMAF32, FeatureFastFMAF32,
FeatureDoesNotSupportXNACK,
FeatureCodeObjectV3]>; FeatureCodeObjectV3]>;
def FeatureISAVersion7_0_3 : FeatureSet< def FeatureISAVersion7_0_3 : FeatureSet<
[FeatureSeaIslands, [FeatureSeaIslands,
FeatureLDSBankCount16, FeatureLDSBankCount16,
FeatureDoesNotSupportXNACK,
FeatureCodeObjectV3]>; FeatureCodeObjectV3]>;
def FeatureISAVersion7_0_4 : FeatureSet< def FeatureISAVersion7_0_4 : FeatureSet<
[FeatureSeaIslands, [FeatureSeaIslands,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureDoesNotSupportXNACK,
FeatureCodeObjectV3]>; FeatureCodeObjectV3]>;
def FeatureISAVersion8_0_1 : FeatureSet< def FeatureISAVersion8_0_1 : FeatureSet<
[FeatureVolcanicIslands, [FeatureVolcanicIslands,
FeatureFastFMAF32, FeatureFastFMAF32,
HalfRate64Ops, HalfRate64Ops,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureXNACK,
FeatureUnpackedD16VMem, FeatureUnpackedD16VMem,
FeatureCodeObjectV3]>; FeatureCodeObjectV3,
FeatureXNACK]>;
def FeatureISAVersion8_0_2 : FeatureSet< def FeatureISAVersion8_0_2 : FeatureSet<
[FeatureVolcanicIslands, [FeatureVolcanicIslands,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureSGPRInitBug, FeatureSGPRInitBug,
FeatureUnpackedD16VMem, FeatureUnpackedD16VMem,
FeatureDoesNotSupportXNACK, FeatureCodeObjectV3,
FeatureCodeObjectV3]>; FeatureXNACK]>;
def FeatureISAVersion8_0_3 : FeatureSet< def FeatureISAVersion8_0_3 : FeatureSet<
[FeatureVolcanicIslands, [FeatureVolcanicIslands,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureUnpackedD16VMem, FeatureUnpackedD16VMem,
FeatureDoesNotSupportXNACK, FeatureCodeObjectV3,
FeatureCodeObjectV3]>; FeatureXNACK]>;
scott.linderUnsubmitted
Not Done
ReplyInline Actions

Could you also include an update to processors table in llvm/docs/AMDGPUUsage.rst for all the changing defaults? It is currently wrong anyway because we forbid XNACK on some targets, but if we are fixing things it would be good to fix it as well.

scott.linder: Could you also include an update to processors table in llvm/docs/AMDGPUUsage.rst for all the…
def FeatureISAVersion8_1_0 : FeatureSet< def FeatureISAVersion8_1_0 : FeatureSet<
[FeatureVolcanicIslands, [FeatureVolcanicIslands,
FeatureLDSBankCount16, FeatureLDSBankCount16,
FeatureXNACK, FeatureCodeObjectV3,
FeatureCodeObjectV3]>; FeatureXNACK]>;
def FeatureISAVersion9_0_0 : FeatureSet< def FeatureISAVersion9_0_0 : FeatureSet<
[FeatureGFX9, [FeatureGFX9,
FeatureMadMixInsts, FeatureMadMixInsts,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureCodeObjectV3, FeatureCodeObjectV3,
FeatureDoesNotSupportXNACK, FeatureXNACK,
FeatureDoesNotSupportSRAMECC]>; FeatureDoesNotSupportSRAMECC]>;
def FeatureISAVersion9_0_2 : FeatureSet< def FeatureISAVersion9_0_2 : FeatureSet<
[FeatureGFX9, [FeatureGFX9,
FeatureMadMixInsts, FeatureMadMixInsts,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureCodeObjectV3,
FeatureXNACK, FeatureXNACK,
FeatureDoesNotSupportSRAMECC, FeatureDoesNotSupportSRAMECC]>;
FeatureCodeObjectV3]>;
def FeatureISAVersion9_0_4 : FeatureSet< def FeatureISAVersion9_0_4 : FeatureSet<
[FeatureGFX9, [FeatureGFX9,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureFmaMixInsts, FeatureFmaMixInsts,
FeatureDoesNotSupportXNACK, FeatureCodeObjectV3,
arsenmUnsubmitted
Not Done
ReplyInline Actions

This feature should really be removed from all subtargets, but that's a separate change

arsenm: This feature should really be removed from all subtargets, but that's a separate change
FeatureDoesNotSupportSRAMECC, FeatureXNACK,
FeatureCodeObjectV3]>; FeatureDoesNotSupportSRAMECC]>;
def FeatureISAVersion9_0_6 : FeatureSet< def FeatureISAVersion9_0_6 : FeatureSet<
[FeatureGFX9, [FeatureGFX9,
HalfRate64Ops, HalfRate64Ops,
FeatureFmaMixInsts, FeatureFmaMixInsts,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureDLInsts, FeatureDLInsts,
FeatureDot1Insts, FeatureDot1Insts,
FeatureDot2Insts, FeatureDot2Insts,
FeatureDoesNotSupportXNACK, FeatureCodeObjectV3,
FeatureCodeObjectV3]>; FeatureXNACK,
FeatureSRAMECC]>;
def FeatureISAVersion9_0_8 : FeatureSet< def FeatureISAVersion9_0_8 : FeatureSet<
[FeatureGFX9, [FeatureGFX9,
HalfRate64Ops, HalfRate64Ops,
FeatureFmaMixInsts, FeatureFmaMixInsts,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureDLInsts, FeatureDLInsts,
FeatureDot1Insts, FeatureDot1Insts,
FeatureDot2Insts, FeatureDot2Insts,
FeatureDot3Insts, FeatureDot3Insts,
FeatureDot4Insts, FeatureDot4Insts,
FeatureDot5Insts, FeatureDot5Insts,
FeatureDot6Insts, FeatureDot6Insts,
FeatureMAIInsts, FeatureMAIInsts,
FeaturePkFmacF16Inst, FeaturePkFmacF16Inst,
FeatureAtomicFaddInsts, FeatureAtomicFaddInsts,
FeatureSRAMECC, FeatureSRAMECC,
FeatureMFMAInlineLiteralBug, FeatureMFMAInlineLiteralBug,
FeatureCodeObjectV3]>; FeatureCodeObjectV3,
FeatureXNACK,
FeatureSRAMECC]>;
def FeatureISAVersion9_0_9 : FeatureSet< def FeatureISAVersion9_0_9 : FeatureSet<
[FeatureGFX9, [FeatureGFX9,
FeatureMadMixInsts, FeatureMadMixInsts,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureXNACK, FeatureCodeObjectV3,
FeatureCodeObjectV3]>; FeatureXNACK]>;
// TODO: Organize more features into groups. // TODO: Organize more features into groups.
def FeatureGroup { def FeatureGroup {
// Bugs present on gfx10.1. // Bugs present on gfx10.1.
list<SubtargetFeature> GFX10_1_Bugs = [ list<SubtargetFeature> GFX10_1_Bugs = [
FeatureVcmpxPermlaneHazard, FeatureVcmpxPermlaneHazard,
FeatureVMEMtoScalarWriteHazard, FeatureVMEMtoScalarWriteHazard,
FeatureSMEMtoVectorWriteHazard, FeatureSMEMtoVectorWriteHazard,
Show All 12 Lines !listconcat(FeatureGroup.GFX10_1_Bugs,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureDLInsts, FeatureDLInsts,
FeatureNSAEncoding, FeatureNSAEncoding,
FeatureWavefrontSize32, FeatureWavefrontSize32,
FeatureScalarStores, FeatureScalarStores,
FeatureScalarAtomics, FeatureScalarAtomics,
FeatureScalarFlatScratchInsts, FeatureScalarFlatScratchInsts,
FeatureLdsMisalignedBug, FeatureLdsMisalignedBug,
FeatureDoesNotSupportXNACK, FeatureCodeObjectV3,
FeatureCodeObjectV3])>; FeatureXNACK])>;
def FeatureISAVersion10_1_1 : FeatureSet< def FeatureISAVersion10_1_1 : FeatureSet<
!listconcat(FeatureGroup.GFX10_1_Bugs, !listconcat(FeatureGroup.GFX10_1_Bugs,
[FeatureGFX10, [FeatureGFX10,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureDLInsts, FeatureDLInsts,
FeatureDot1Insts, FeatureDot1Insts,
FeatureDot2Insts, FeatureDot2Insts,
FeatureDot5Insts, FeatureDot5Insts,
FeatureDot6Insts, FeatureDot6Insts,
FeatureNSAEncoding, FeatureNSAEncoding,
FeatureWavefrontSize32, FeatureWavefrontSize32,
FeatureScalarStores, FeatureScalarStores,
FeatureScalarAtomics, FeatureScalarAtomics,
FeatureScalarFlatScratchInsts, FeatureScalarFlatScratchInsts,
FeatureDoesNotSupportXNACK, FeatureCodeObjectV3,
FeatureCodeObjectV3])>; FeatureXNACK])>;
def FeatureISAVersion10_1_2 : FeatureSet< def FeatureISAVersion10_1_2 : FeatureSet<
!listconcat(FeatureGroup.GFX10_1_Bugs, !listconcat(FeatureGroup.GFX10_1_Bugs,
[FeatureGFX10, [FeatureGFX10,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureDLInsts, FeatureDLInsts,
FeatureDot1Insts, FeatureDot1Insts,
FeatureDot2Insts, FeatureDot2Insts,
FeatureDot5Insts, FeatureDot5Insts,
FeatureDot6Insts, FeatureDot6Insts,
FeatureNSAEncoding, FeatureNSAEncoding,
FeatureWavefrontSize32, FeatureWavefrontSize32,
FeatureScalarStores, FeatureScalarStores,
FeatureScalarAtomics, FeatureScalarAtomics,
FeatureScalarFlatScratchInsts, FeatureScalarFlatScratchInsts,
FeatureLdsMisalignedBug, FeatureLdsMisalignedBug,
FeatureDoesNotSupportXNACK, FeatureCodeObjectV3,
FeatureCodeObjectV3])>; FeatureXNACK])>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def AMDGPUInstrInfo : InstrInfo { def AMDGPUInstrInfo : InstrInfo {
let guessInstructionProperties = 1; let guessInstructionProperties = 1;
let noNamedPositionallyEncodedOperands = 1; let noNamedPositionallyEncodedOperands = 1;
} }
▲ Show 20 Lines • Show All 275 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp

Show First 20 Lines • Show All 144 Lines • ▼ Show 20 LinesGCNSubtarget::initializeSubtargetDependencies(const Triple &TT,
} }
// Don't crash on invalid devices. // Don't crash on invalid devices.
if (WavefrontSize == 0) if (WavefrontSize == 0)
WavefrontSize = 64; WavefrontSize = 64;
HasFminFmaxLegacy = getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS; HasFminFmaxLegacy = getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS;
// Disable XNACK on targets where it is not enabled by default unless it is if (DoesNotSupportXNACK && EnableXNACK) {
// explicitly requested. if (FS.contains("+xnack"))
if (!FS.contains("+xnack") && DoesNotSupportXNACK && EnableXNACK) { report_fatal_error("XNACK was requested for a processor that does not support it!");
rampitecUnsubmitted
Not Done
ReplyInline Actions

That's a right thing to do, but I suppose needs some testing and fixing at least known apps doing so before we can submit.

rampitec: That's a right thing to do, but I suppose needs some testing and fixing at least known apps…
ToggleFeature(AMDGPU::FeatureXNACK); ToggleFeature(AMDGPU::FeatureXNACK);
EnableXNACK = false; EnableXNACK = false;
} }
// ECC is on by default, but turn it off if the hardware doesn't support it // ECC is on by default, but turn it off if the hardware doesn't support it
// anyway. This matters for the gfx9 targets with d16 loads, but don't support // anyway. This matters for the gfx9 targets with d16 loads, but don't support
// ECC. // ECC.
if (DoesNotSupportSRAMECC && EnableSRAMECC) { if (DoesNotSupportSRAMECC && EnableSRAMECC) {
if (FS.contains("+sram-ecc"))
report_fatal_error("SRAM ECC was requested for a processor that does not support it!");
ToggleFeature(AMDGPU::FeatureSRAMECC); ToggleFeature(AMDGPU::FeatureSRAMECC);
EnableSRAMECC = false; EnableSRAMECC = false;
} }
return *this; return *this;
} }
AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT) : AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT) :
▲ Show 20 Lines • Show All 730 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.dec.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.gws.barrier.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.private.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.shared.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll

llvm/test/CodeGen/AMDGPU/add.i16.ll

llvm/test/CodeGen/AMDGPU/add.v2i16.ll

llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll

llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll

llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll

llvm/test/CodeGen/AMDGPU/amdhsa-trap-num-sgprs.ll

llvm/test/CodeGen/AMDGPU/and.ll

llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll

llvm/test/CodeGen/AMDGPU/atomicrmw-nand.ll

llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-v3.ll

llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size.ll

llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll

llvm/test/CodeGen/AMDGPU/attr-amdgpu-waves-per-eu.ll

llvm/test/CodeGen/AMDGPU/bitcast-vector-extract.ll

llvm/test/CodeGen/AMDGPU/bitreverse.ll

llvm/test/CodeGen/AMDGPU/break-smem-soft-clauses.mir

llvm/test/CodeGen/AMDGPU/break-vmem-soft-clauses.mir

llvm/test/CodeGen/AMDGPU/bswap.ll

llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll

llvm/test/CodeGen/AMDGPU/call-argument-types.ll

llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll

llvm/test/CodeGen/AMDGPU/call-waitcnt.ll

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