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[X86] Add DAG combines to form CVTPH2PS/CVTPS2PH from vXf16->vXf32/vXf64 fp_extends and vXf32->vXf16 fp_round.
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Authored by craig.topper on Feb 19 2020, 11:02 PM.

Details

Summary

Only handle power of 2 element count for simplicity. Not sure what to do with vXf64->vXf16 fp_round to avoid double rounding

Event Timeline

craig.topper created this revision.Feb 19 2020, 11:02 PM
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Add a DAG combine to call SimplifyDemandedVectorElts for v8i16->v4f32 case.

Add CVTPS2PH support as well

craig.topper retitled this revision from [X86] Add a DAG combine to form CVTPH2PS from vXf16->vXf32/vXf64 fp_extends. to [X86] Add DAG combines to form CVTPH2PS/CVTPS2PH from vXf16->vXf32/vXf64 fp_extends and vXf32->vXf16 fp_round..Feb 19 2020, 11:46 PM
craig.topper edited the summary of this revision. (Show Details)

Also remove vzext_movl from vcvtps2ph results if the upper bits have already been zeroed.

RKSimon accepted this revision.Feb 20 2020, 3:37 AM

LGTM, thanks for the doing this!

llvm/lib/Target/X86/X86ISelLowering.cpp
46766

Maybe comment what the 4 rc value is?

This revision is now accepted and ready to land.Feb 20 2020, 3:37 AM
This revision was automatically updated to reflect the committed changes.