[MIR][ARM] MachineOperand comments to print condition code names instead of constants

[SjoerdMeijer]

Summary

Some machine operands have their values encoded as immediates and are thus printed as immediates, for example:

dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg
t2Bcc %bb.4, 0, killed $cpsr

In this example, 14 is a condition code that means that the EOR instruction is not conditionally executed (it is "always executed"). The 0 on the next conditional branch instruction represents the equal condition code. The problem is that these constants make the MIR difficult to read (for a human), so here we propose to annotate MachineOperands with an annotation/comment:

dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 [always], $noreg
t2Bcc %bb.4, 0 [equal], killed $cpsr

As it is a comment, the MI lexer/parser completely ignores it. The benefit is that this keeps the change in the lexer extremely minimal and no target specific parsing needs to be done. The changes on the MIPrinter side are also minimal, as targets hooks are used to create the machine operand comments.

[efriedma]

I think something like this is nice to have: various instructions use immediates with weird encodings that make perfect sense in the code, but are sort of hard to read.

I don't really like the way this is implemented; it's adding a bunch of target-specific logic to target-independent code.

I wonder if, instead of replacing the immediate with a keyword, it would make sense to add some generic mechanism to print a comments after an operand, to sort of explain it. We could print the condition for a condition code, but we could also decode various other kinds of encoded immediates: for example, "26" is "lsl #3" in ADDrsi. Printing it as a comment would be simpler to implement because the parsing change would be much smaller: we continue just parsing an integer, and ignore the comment, instead of adding target-specific parsing rules.

[SjoerdMeijer]

In D74306#1867215, @efriedma wrote:

I think something like this is nice to have: various instructions use immediates with weird encodings that make perfect sense in the code, but are sort of hard to read.

Thanks for taking a look!

I don't really like the way this is implemented; it's adding a bunch of target-specific logic to target-independent code.

I could have tried harder to hide target specific logic in targets hooks in MIParse. In the MIRPrinter for example, I added a call to TII->getPredicateByName(). In the parser, for this WIP demo, I was lazy and just added getPredicateCondCode(), but could have done something similar. But I do fully agree of course that one way or another, that means more target specific parsing.

I wonder if, instead of replacing the immediate with a keyword, it would make sense to add some generic mechanism to print a comments after an operand, to sort of explain it. We could print the condition for a condition code, but we could also decode various other kinds of encoded immediates: for example, "26" is "lsl #3" in ADDrsi. Printing it as a comment would be simpler to implement because the parsing change would be much smaller: we continue just parsing an integer, and ignore the comment, instead of adding target-specific parsing rules.

Nice one, cheers, I do really like that idea! The only disadvantage I see is that one can argue that MIR output is possibly more verbose than needed, but all together this sounds like an excellent trade-off to me. I will give this a try and make a start with implementing this soon.

[SjoerdMeijer]

How about something like this?

[efriedma]

This is roughly what I was expecting; I think this is the right approach.

Maybe getImmOperandComment should be a target-specific method, instead of putting the predicate handling logic in target-independent code? We probably want some general-purpose hook for adding comments anyway.

[SjoerdMeijer]

Created createMIROperandComment() as general-purpose hook to create comments.

I've now updated all the tests, and so thought it was time to remove the WIP tag from the subject.

[ostannard]

llvm/include/llvm/CodeGen/TargetInstrInfo.h

1310

Is this still needed in the common TargetInstrInfo?

1313

Returning a const char * is going to make it hard for targets to dynamically construct comments, e.g. Eli's example of "26" -> "lsl #3" in ADDrsi. The MIR printer is only used for debugging, so using a std::string here should be fine.

llvm/lib/CodeGen/MIRParser/MILexer.cpp

107

Is this syntax used for comments anywhere else? It's not immediately obvious from reading the changed tests that this is a comment, could we use something more common like /* C-stlye */ comments?

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

500

I think it would be better to use the two-letter codes from the assembly syntax. They are more canonical, and easier to look up the exact meaning than these.

531

getPredicateByName can never return a null pointer.

[SjoerdMeijer]

Hi Oliver, thanks for looking too and the feedback!

Is this still needed in the common TargetInstrInfo?

Nope, good one, I have removed it. Now we only have createMIROperandComment() as a new target hook.

Returning a const char * is going to make it hard for targets

yep, done, that's a lot more convenient.

I think it would be better to use the two-letter codes from the assembly syntax. They are more canonical, and easier to look up the exact meaning than these.

Done, and related to this, I have completely removed getPredicateByName(), instead I can just call existing function ARMCondCodeToString().

Is this syntax used for comments anywhere else? It's not immediately obvious from reading the changed tests that this is a comment, could we use something more common like /* C-stlye */ comments?

I have no strong opinion on this. I chose [ and ] mainly for these 2 reasons:

• it's a character currently not used by the lexer,
• it is 1 character, which I found nice and concise and pleasant to read. I think I find it more pleasant to read than /* and */ in MIR code, but I appreciate this is very subjective, see next paragraph.

I have only added 1 changed test case, because the ~140 I had to change make things difficult to read here. I will make the final change changing all tests when we are happy about the exact syntax:

• I have adopted the 2-letter codes syntax. To make this readable, I have prefixed this with CC:: to indicate this is a condition code, so that for example you'll see [CC::al].
• As I said above, I have kept the [ and ] for now to open/close comments, but would be happy to change. If @efriedma has a preference, then I will take that into account, make the change, and then update all the tests.

About updating the tests, that's actually pretty straightforward because for about ~120 I can just use the script (just letting know that's how I changed them). For about 20 of them, that doesn't really work because of shared check-prefixes, so I need to change them "manually" with a little bit search/replace commands, but is not a big deal.

[SjoerdMeijer]

the same patch, but now with context.

[efriedma]

I can see two problems with [] comment delimiters:

1. ] is used somewhat frequently in target-specific assembly syntax, so it might end up overlapping with stuff some target wants to print. Maybe not that likely in practice.
2. It isn't obvious that the contents of the [] is a comment. Something like /**/ would give instant recognition to people even if they're not really familiar with MIR syntax.

Otherwise looks fine.

[SjoerdMeijer]

Thanks again for the suggestions/comments. The MachineOperand comments are now enclosed between /* and */, see the only test file that I have uploaded.

As a last step, I can now change all tests. I can upload them here, or commit directly when you're happy with this patch. The only reason I have not uploaded the ~140 changed tests, is because that makes this Phab diff a bit unwieldy.

[ostannard]

LGTM with one really minor nit.

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

501

Comments should end with full stops.

llvm/include/llvm/CodeGen/TargetInstrInfo.h

public:
   virtual void getNoop(MCInst &NopInst) const;
 
   /// Return true for post-incremented instructions.
   virtual bool isPostIncrement(const MachineInstr &MI) const { return false; }
 
   /// Returns true if the instruction is already predicated.
   virtual bool isPredicated(const MachineInstr &MI) const { return false; }
 
+  // Returns a MIRPrinter comment for this machine operand.
+  virtual std::string createMIROperandComment(const MachineInstr &MI,
+                                              const MachineOperand &Op,
+                                              unsigned OpIdx) const {
+    return std::string();
+  };
+
   /// Returns true if the instruction is a
   /// terminator instruction that has not been predicated.
   virtual bool isUnpredicatedTerminator(const MachineInstr &MI) const;
 
   /// Returns true if MI is an unconditional tail call.
   virtual bool isUnconditionalTailCall(const MachineInstr &MI) const {
     return false;
   }

llvm/lib/CodeGen/MIRParser/MILexer.cpp

 static Cursor skipComment(Cursor C) {
   if (C.peek() != ';')
     return C;
   while (!isNewlineChar(C.peek()) && !C.isEOF())
     C.advance();
   return C;
 }
 
+/// Machine operands can have comments, enclosed between '[' and ']'.
+/// This eats up all tokens, including the brackets.
+static Cursor skipMachineOperandComment(Cursor C) {
+  if (C.peek() != '[')
+    return C;
+
+  while (C.peek() != ']')
+    C.advance();
+
+  C.advance();
+  return C;
+}
+
 /// Return true if the given character satisfies the following regular
 /// expression: [-a-zA-Z$._0-9]
 static bool isIdentifierChar(char C) {
   return isalpha(C) || isdigit(C) || C == '_' || C == '-' || C == '.' ||
          C == '$';
 }
 
 /// Unescapes the given string value.

 StringRef llvm::lexMIToken(StringRef Source, MIToken &Token,
                            ErrorCallbackType ErrorCallback) {
   auto C = skipComment(skipWhitespace(Cursor(Source)));
   if (C.isEOF()) {
     Token.reset(MIToken::Eof, C.remaining());
     return C.remaining();
   }
 
+  C = skipMachineOperandComment(C);
+
   if (Cursor R = maybeLexMachineBasicBlock(C, Token, ErrorCallback))
     return R.remaining();
   if (Cursor R = maybeLexIdentifier(C, Token))
     return R.remaining();
   if (Cursor R = maybeLexJumpTableIndex(C, Token))
     return R.remaining();
   if (Cursor R = maybeLexStackObject(C, Token))
     return R.remaining();

llvm/lib/CodeGen/MIRPrinter.cpp

MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
       : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
         StackObjectOperandMapping(StackObjectOperandMapping) {}
 
   void print(const MachineBasicBlock &MBB);
 
   void print(const MachineInstr &MI);
   void printStackObjectReference(int FrameIndex);
   void print(const MachineInstr &MI, unsigned OpIdx,
-             const TargetRegisterInfo *TRI, bool ShouldPrintRegisterTies,
-             LLT TypeToPrint, bool PrintDef = true);
+             const TargetRegisterInfo *TRI, const TargetInstrInfo *TII,
+             bool ShouldPrintRegisterTies, LLT TypeToPrint,
+             bool PrintDef = true);
 };
 
 } // end namespace llvm
 
 namespace llvm {
 namespace yaml {
 
 /// This struct serializes the LLVM IR module.
void MIPrinter::print(const MachineInstr &MI) {
   SmallBitVector PrintedTypes(8);
   bool ShouldPrintRegisterTies = MI.hasComplexRegisterTies();
   unsigned I = 0, E = MI.getNumOperands();
   for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
          !MI.getOperand(I).isImplicit();
        ++I) {
     if (I)
       OS << ", ";
-    print(MI, I, TRI, ShouldPrintRegisterTies,
+    print(MI, I, TRI, TII, ShouldPrintRegisterTies,
           MI.getTypeToPrint(I, PrintedTypes, MRI),
           /*PrintDef=*/false);
   }
 
   if (I)
     OS << " = ";
   if (MI.getFlag(MachineInstr::FrameSetup))
     OS << "frame-setup ";
void MIPrinter::print(const MachineInstr &MI) {
   OS << TII->getName(MI.getOpcode());
   if (I < E)
     OS << ' ';
 
   bool NeedComma = false;
   for (; I < E; ++I) {
     if (NeedComma)
       OS << ", ";
-    print(MI, I, TRI, ShouldPrintRegisterTies,
+    print(MI, I, TRI, TII, ShouldPrintRegisterTies,
           MI.getTypeToPrint(I, PrintedTypes, MRI));
     NeedComma = true;
   }
 
   // Print any optional symbols attached to this instruction as-if they were
   // operands.
   if (MCSymbol *PreInstrSymbol = MI.getPreInstrSymbol()) {
     if (NeedComma)
void MIPrinter::printStackObjectReference(int FrameIndex) {
   auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
   assert(ObjectInfo != StackObjectOperandMapping.end() &&
          "Invalid frame index");
   const FrameIndexOperand &Operand = ObjectInfo->second;
   MachineOperand::printStackObjectReference(OS, Operand.ID, Operand.IsFixed,
                                             Operand.Name);
 }
 
+static std::string formatOperandComment(std::string Comment) {
+  if (Comment.empty())
+    return Comment;
+  return std::string(" [" + Comment + "]");
+}
+
 void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
                       const TargetRegisterInfo *TRI,
+                      const TargetInstrInfo *TII,
                       bool ShouldPrintRegisterTies, LLT TypeToPrint,
                       bool PrintDef) {
   const MachineOperand &Op = MI.getOperand(OpIdx);
+  std::string MOComment = TII->createMIROperandComment(MI, Op, OpIdx);
+
   switch (Op.getType()) {
   case MachineOperand::MO_Immediate:
     if (MI.isOperandSubregIdx(OpIdx)) {
       MachineOperand::printTargetFlags(OS, Op);
       MachineOperand::printSubRegIdx(OS, Op.getImm(), TRI);
       break;
     }
     LLVM_FALLTHROUGH;
void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
   case MachineOperand::MO_BlockAddress:
   case MachineOperand::MO_ShuffleMask: {
     unsigned TiedOperandIdx = 0;
     if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
       TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
     const TargetIntrinsicInfo *TII = MI.getMF()->getTarget().getIntrinsicInfo();
     Op.print(OS, MST, TypeToPrint, OpIdx, PrintDef, /*IsStandalone=*/false,
              ShouldPrintRegisterTies, TiedOperandIdx, TRI, TII);
+      OS << formatOperandComment(MOComment);
     break;
   }
   case MachineOperand::MO_FrameIndex:
     printStackObjectReference(Op.getIndex());
     break;
   case MachineOperand::MO_RegisterMask: {
     auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
     if (RegMaskInfo != RegisterMaskIds.end())

llvm/lib/Target/ARM/ARMBaseInstrInfo.h

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
                         int *BytesAdded = nullptr) const override;
 
   bool
   reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
 
   // Predication support.
   bool isPredicated(const MachineInstr &MI) const override;
 
+  // MIR printer helper function to annotate Operands with a comment.
+  std::string createMIROperandComment(const MachineInstr &MI,
+                                      const MachineOperand &Op,
+                                      unsigned OpIdx) const override;
+
   ARMCC::CondCodes getPredicate(const MachineInstr &MI) const {
     int PIdx = MI.findFirstPredOperandIdx();
     return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm()
                       : ARMCC::AL;
   }
 
   bool PredicateInstruction(MachineInstr &MI,
                             ArrayRef<MachineOperand> Pred) const override;

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

if (MI.isBundle()) {
     }
     return false;
   }
 
   int PIdx = MI.findFirstPredOperandIdx();
   return PIdx != -1 && MI.getOperand(PIdx).getImm() != ARMCC::AL;
 }
 
+std::string ARMBaseInstrInfo::createMIROperandComment(const MachineInstr &MI,
+                                                      const MachineOperand &Op,
+                                                      unsigned OpIdx) const {
+  // Only support immediates for now
+  if (Op.getType() != MachineOperand::MO_Immediate)
+    return std::string();
+
+  // And print its corresponding condition code if the immediate is a predicate
+  int FirstPredOp = MI.findFirstPredOperandIdx();
+  if (FirstPredOp != (int) OpIdx)
+    return std::string();
+
+  std::string CC = "CC::";
+  CC += ARMCondCodeToString((ARMCC::CondCodes)Op.getImm());
+  return CC;
+}
+
 bool ARMBaseInstrInfo::PredicateInstruction(
     MachineInstr &MI, ArrayRef<MachineOperand> Pred) const {
   unsigned Opc = MI.getOpcode();
   if (isUncondBranchOpcode(Opc)) {
     MI.setDesc(get(getMatchingCondBranchOpcode(Opc)));
     MachineInstrBuilder(*MI.getParent()->getParent(), MI)
       .addImm(Pred[0].getImm())
       .addReg(Pred[1].getReg());
     return true;
   }
 
   int PIdx = MI.findFirstPredOperandIdx();
   if (PIdx != -1) {
     MachineOperand &PMO = MI.getOperand(PIdx);
     PMO.setImm(Pred[0].getImm());
     MI.getOperand(PIdx+1).setReg(Pred[1].getReg());
     return true;
   }
   return false;
 }
 
 bool ARMBaseInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
                                          ArrayRef<MachineOperand> Pred2) const {
   if (Pred1.size() > 2 || Pred2.size() > 2)
     return false;

llvm/test/CodeGen/Thumb2/t2-teq-reduce.mir

 liveins:
   - { reg: '$r0', virtual-reg: '' }
   - { reg: '$r1', virtual-reg: '' }
 body:             |
   ; CHECK-LABEL: name: reg_reg_it_block
   ; CHECK: bb.0.entry:
   ; CHECK:   successors: %bb.2(0x80000000)
   ; CHECK:   liveins: $r0, $r1
-  ; CHECK:   t2B %bb.2, 14, $noreg
+  ; CHECK:   t2B %bb.2, 14 [CC::al], $noreg
   ; CHECK: bb.1.while.body.end:
   ; CHECK:   successors: %bb.2(0x80000000)
   ; CHECK:   liveins: $r0, $r1
-  ; CHECK:   renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.next.i.14)
-  ; CHECK:   tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr
+  ; CHECK:   renamable $r0 = tLDRi killed renamable $r0, 0, 14 [CC::al], $noreg :: (load 4 from %ir.next.i.14)
+  ; CHECK:   tCMPi8 renamable $r0, 0, 14 [CC::al], $noreg, implicit-def $cpsr
   ; CHECK:   BUNDLE implicit-def dead $itstate, implicit killed $cpsr, implicit $r0 {
   ; CHECK:     t2IT 0, 8, implicit-def $itstate
-  ; CHECK:     tBX_RET 0, killed $cpsr, implicit $r0, implicit internal killed $itstate
+  ; CHECK:     tBX_RET 0 [CC::eq], killed $cpsr, implicit $r0, implicit internal killed $itstate
   ; CHECK:   }
   ; CHECK: bb.2.while.begin:
   ; CHECK:   successors: %bb.4(0x04000000), %bb.3(0x7c000000)
   ; CHECK:   liveins: $r0, $r1
-  ; CHECK:   renamable $r2 = tLDRi renamable $r0, 1, 14, $noreg :: (load 4 from %ir.info.i)
-  ; CHECK:   renamable $r2 = tLDRHi killed renamable $r2, 0, 14, $noreg :: (load 2 from %ir.data16.i1)
-  ; CHECK:   dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg
-  ; CHECK:   t2Bcc %bb.4, 0, killed $cpsr
+  ; CHECK:   renamable $r2 = tLDRi renamable $r0, 1, 14 [CC::al], $noreg :: (load 4 from %ir.info.i)
+  ; CHECK:   renamable $r2 = tLDRHi killed renamable $r2, 0, 14 [CC::al], $noreg :: (load 2 from %ir.data16.i1)
+  ; CHECK:   dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 [CC::al], $noreg
+  ; CHECK:   t2Bcc %bb.4, 0 [CC::eq], killed $cpsr
   ; CHECK: bb.3.while.body.a:
   ; CHECK:   successors: %bb.4(0x4207fef8), %bb.1(0x3df80108)
   ; CHECK:   liveins: $r0, $r1
-  ; CHECK:   renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.next.i2)
-  ; CHECK:   tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr
+  ; CHECK:   renamable $r0 = tLDRi killed renamable $r0, 0, 14 [CC::al], $noreg :: (load 4 from %ir.next.i2)
+  ; CHECK:   tCMPi8 renamable $r0, 0, 14 [CC::al], $noreg, implicit-def $cpsr
   ; CHECK:   BUNDLE implicit-def dead $itstate, implicit-def dead $r2, implicit-def $cpsr, implicit $r0, implicit killed $cpsr, implicit $r1 {
   ; CHECK:     t2IT 1, 30, implicit-def $itstate
-  ; CHECK:     renamable $r2 = tLDRi renamable $r0, 1, 1, $cpsr, implicit internal $itstate :: (load 4 from %ir.info.i.1)
-  ; CHECK:     renamable $r2 = tLDRHi internal killed renamable $r2, 0, 1, $cpsr, implicit internal killed $r2, implicit internal $itstate :: (load 2 from %ir.data16.i.13)
-  ; CHECK:     t2TEQrr internal killed renamable $r2, renamable $r1, 1, killed $cpsr, implicit-def $cpsr, implicit internal killed $itstate
+  ; CHECK:     renamable $r2 = tLDRi renamable $r0, 1, 1 [CC::ne], $cpsr, implicit internal $itstate :: (load 4 from %ir.info.i.1)
+  ; CHECK:     renamable $r2 = tLDRHi internal killed renamable $r2, 0, 1 [CC::ne], $cpsr, implicit internal killed $r2, implicit internal $itstate :: (load 2 from %ir.data16.i.13)
+  ; CHECK:     t2TEQrr internal killed renamable $r2, renamable $r1, 1 [CC::ne], killed $cpsr, implicit-def $cpsr, implicit internal killed $itstate
   ; CHECK:   }
-  ; CHECK:   t2Bcc %bb.1, 1, killed $cpsr
+  ; CHECK:   t2Bcc %bb.1, 1 [CC::ne], killed $cpsr
   ; CHECK: bb.4.exit:
   ; CHECK:   liveins: $r0
-  ; CHECK:   tBX_RET 14, $noreg, implicit killed $r0
+  ; CHECK:   tBX_RET 14 [CC::al], $noreg, implicit killed $r0
   bb.0.entry:
     successors: %bb.1(0x80000000)
     liveins: $r0, $r1
 
     t2B %bb.1, 14, $noreg
 
   bb.3.while.body.end:
     successors: %bb.1(0x80000000)

 liveins:
   - { reg: '$r0', virtual-reg: '' }
   - { reg: '$r1', virtual-reg: '' }
 body:             |
   ; CHECK-LABEL: name: op_not_killed
   ; CHECK: bb.0.entry:
   ; CHECK:   successors: %bb.1(0x80000000)
   ; CHECK:   liveins: $r0, $r1
-  ; CHECK:   $r2 = tMOVr $r0, 14, $noreg
+  ; CHECK:   $r2 = tMOVr $r0, 14 [CC::al], $noreg
   ; CHECK: bb.1.while.begin:
   ; CHECK:   successors: %bb.5(0x04000000), %bb.2(0x7c000000)
   ; CHECK:   liveins: $r1, $r2
-  ; CHECK:   renamable $r0 = tLDRi renamable $r2, 1, 14, $noreg :: (load 4 from %ir.info.i)
-  ; CHECK:   renamable $r0 = tLDRHi killed renamable $r0, 0, 14, $noreg :: (load 2 from %ir.data16.i1)
-  ; CHECK:   t2TEQrr renamable $r0, renamable $r1, 14, $noreg, implicit-def $cpsr
-  ; CHECK:   t2Bcc %bb.5, 0, killed $cpsr
+  ; CHECK:   renamable $r0 = tLDRi renamable $r2, 1, 14 [CC::al], $noreg :: (load 4 from %ir.info.i)
+  ; CHECK:   renamable $r0 = tLDRHi killed renamable $r0, 0, 14 [CC::al], $noreg :: (load 2 from %ir.data16.i1)
+  ; CHECK:   t2TEQrr renamable $r0, renamable $r1, 14 [CC::al], $noreg, implicit-def $cpsr
+  ; CHECK:   t2Bcc %bb.5, 0 [CC::eq], killed $cpsr
   ; CHECK: bb.2.while.body.a:
   ; CHECK:   successors: %bb.5(0x04000000), %bb.3(0x7c000000)
   ; CHECK:   liveins: $r0, $r1, $r2
-  ; CHECK:   renamable $r2 = tLDRi killed renamable $r2, 0, 14, $noreg :: (load 4 from %ir.next.i2)
-  ; CHECK:   tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr
-  ; CHECK:   t2Bcc %bb.5, 0, killed $cpsr
+  ; CHECK:   renamable $r2 = tLDRi killed renamable $r2, 0, 14 [CC::al], $noreg :: (load 4 from %ir.next.i2)
+  ; CHECK:   tCMPi8 renamable $r2, 0, 14 [CC::al], $noreg, implicit-def $cpsr
+  ; CHECK:   t2Bcc %bb.5, 0 [CC::eq], killed $cpsr
   ; CHECK: bb.3.it.block:
   ; CHECK:   successors: %bb.5(0x04000000), %bb.4(0x7c000000)
   ; CHECK:   liveins: $r1, $r2
-  ; CHECK:   renamable $r0 = tLDRi renamable $r2, 1, 14, $noreg :: (load 4 from %ir.info.i.1)
-  ; CHECK:   renamable $r0 = tLDRHi killed renamable $r0, 0, 14, $noreg :: (load 2 from %ir.data16.i.13)
-  ; CHECK:   t2TEQrr renamable $r0, renamable $r1, 14, $noreg, implicit-def $cpsr
-  ; CHECK:   t2Bcc %bb.5, 0, killed $cpsr
+  ; CHECK:   renamable $r0 = tLDRi renamable $r2, 1, 14 [CC::al], $noreg :: (load 4 from %ir.info.i.1)
+  ; CHECK:   renamable $r0 = tLDRHi killed renamable $r0, 0, 14 [CC::al], $noreg :: (load 2 from %ir.data16.i.13)
+  ; CHECK:   t2TEQrr renamable $r0, renamable $r1, 14 [CC::al], $noreg, implicit-def $cpsr
+  ; CHECK:   t2Bcc %bb.5, 0 [CC::eq], killed $cpsr
   ; CHECK: bb.4.while.body.end:
   ; CHECK:   successors: %bb.5(0x04000000), %bb.1(0x7c000000)
   ; CHECK:   liveins: $r0, $r1, $r2
-  ; CHECK:   renamable $r2 = tLDRi killed renamable $r2, 0, 14, $noreg :: (load 4 from %ir.next.i.14)
-  ; CHECK:   tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr
-  ; CHECK:   t2Bcc %bb.1, 1, killed $cpsr
+  ; CHECK:   renamable $r2 = tLDRi killed renamable $r2, 0, 14 [CC::al], $noreg :: (load 4 from %ir.next.i.14)
+  ; CHECK:   tCMPi8 renamable $r2, 0, 14 [CC::al], $noreg, implicit-def $cpsr
+  ; CHECK:   t2Bcc %bb.1, 1 [CC::ne], killed $cpsr
   ; CHECK: bb.5.exit:
   ; CHECK:   liveins: $r0
-  ; CHECK:   tBX_RET 14, $noreg, implicit $r0
+  ; CHECK:   tBX_RET 14 [CC::al], $noreg, implicit $r0
   bb.0.entry:
     successors: %bb.1(0x80000000)
     liveins: $r0, $r1
 
     $r2 = tMOVr $r0, 14, $noreg
 
   bb.1.while.begin:
     successors: %bb.5(0x04000000), %bb.2(0x7c000000)