This is an archive of the discontinued LLVM Phabricator instance.

Differential D74306

[MIR][ARM] MachineOperand comments to print condition code names instead of constants
ClosedPublic

Authored by SjoerdMeijer on Feb 10 2020, 2:54 AM.

Details

Reviewers
ostannard
efriedma
samparker
dmgreen
Commits
rG7efabe5c7de4: [MIR][ARM] MachineOperand comments
Summary

Some machine operands have their values encoded as immediates and are thus printed as immediates, for example:

dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg
t2Bcc %bb.4, 0, killed $cpsr

In this example, 14 is a condition code that means that the EOR instruction is not conditionally executed (it is "always executed"). The 0 on the next conditional branch instruction represents the equal condition code. The problem is that these constants make the MIR difficult to read (for a human), so here we propose to annotate MachineOperands with an annotation/comment:

dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 [always], $noreg
t2Bcc %bb.4, 0 [equal], killed $cpsr

As it is a comment, the MI lexer/parser completely ignores it. The benefit is that this keeps the change in the lexer extremely minimal and no target specific parsing needs to be done. The changes on the MIPrinter side are also minimal, as targets hooks are used to create the machine operand comments.

Diff Detail

Event Timeline

SjoerdMeijer created this revision.Feb 10 2020, 2:54 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 10 2020, 2:54 AM
Herald added subscribers: hiraditya, kristof.beyls. · View Herald Transcript
efriedma added a comment.Feb 10 2020, 8:02 AM

I think something like this is nice to have: various instructions use immediates with weird encodings that make perfect sense in the code, but are sort of hard to read.

I don't really like the way this is implemented; it's adding a bunch of target-specific logic to target-independent code.

I wonder if, instead of replacing the immediate with a keyword, it would make sense to add some generic mechanism to print a comments after an operand, to sort of explain it. We could print the condition for a condition code, but we could also decode various other kinds of encoded immediates: for example, "26" is "lsl #3" in ADDrsi. Printing it as a comment would be simpler to implement because the parsing change would be much smaller: we continue just parsing an integer, and ignore the comment, instead of adding target-specific parsing rules.

SjoerdMeijer added a comment.Feb 10 2020, 8:39 AM
In D74306#1867215, @efriedma wrote:

I think something like this is nice to have: various instructions use immediates with weird encodings that make perfect sense in the code, but are sort of hard to read.

Thanks for taking a look!

I don't really like the way this is implemented; it's adding a bunch of target-specific logic to target-independent code.

I could have tried harder to hide target specific logic in targets hooks in MIParse. In the MIRPrinter for example, I added a call to TII->getPredicateByName(). In the parser, for this WIP demo, I was lazy and just added getPredicateCondCode(), but could have done something similar. But I do fully agree of course that one way or another, that means more target specific parsing.

I wonder if, instead of replacing the immediate with a keyword, it would make sense to add some generic mechanism to print a comments after an operand, to sort of explain it. We could print the condition for a condition code, but we could also decode various other kinds of encoded immediates: for example, "26" is "lsl #3" in ADDrsi. Printing it as a comment would be simpler to implement because the parsing change would be much smaller: we continue just parsing an integer, and ignore the comment, instead of adding target-specific parsing rules.

Nice one, cheers, I do really like that idea! The only disadvantage I see is that one can argue that MIR output is possibly more verbose than needed, but all together this sounds like an excellent trade-off to me. I will give this a try and make a start with implementing this soon.

SjoerdMeijer updated this revision to Diff 244237.Feb 12 2020, 11:42 AM

How about something like this?

efriedma added a comment.Feb 12 2020, 6:06 PM

This is roughly what I was expecting; I think this is the right approach.

Maybe getImmOperandComment should be a target-specific method, instead of putting the predicate handling logic in target-independent code? We probably want some general-purpose hook for adding comments anyway.

SjoerdMeijer updated this revision to Diff 244447.Feb 13 2020, 8:51 AM
SjoerdMeijer retitled this revision from [MIR][ARM] WIP: Print condition code names instead of magic constants to [MIR][ARM] MachineOperand comments to print condition code names instead of constants.
SjoerdMeijer edited the summary of this revision. (Show Details)

Created createMIROperandComment() as general-purpose hook to create comments.

I've now updated all the tests, and so thought it was time to remove the WIP tag from the subject.

Herald added subscribers: zzheng, qcolombet. · View Herald TranscriptFeb 13 2020, 8:51 AM
ostannard added inline comments.Feb 14 2020, 4:09 AM
llvm/include/llvm/CodeGen/TargetInstrInfo.h
1313

Is this still needed in the common TargetInstrInfo?

1316

Returning a const char * is going to make it hard for targets to dynamically construct comments, e.g. Eli's example of "26" -> "lsl #3" in ADDrsi. The MIR printer is only used for debugging, so using a std::string here should be fine.

llvm/lib/CodeGen/MIRParser/MILexer.cpp
107

Is this syntax used for comments anywhere else? It's not immediately obvious from reading the changed tests that this is a comment, could we use something more common like /* C-stlye */ comments?

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
500

I think it would be better to use the two-letter codes from the assembly syntax. They are more canonical, and easier to look up the exact meaning than these.

531

getPredicateByName can never return a null pointer.

SjoerdMeijer updated this revision to Diff 244639.Feb 14 2020, 6:21 AM

Hi Oliver, thanks for looking too and the feedback!

Is this still needed in the common TargetInstrInfo?

Nope, good one, I have removed it. Now we only have createMIROperandComment() as a new target hook.

Returning a const char * is going to make it hard for targets

yep, done, that's a lot more convenient.

I think it would be better to use the two-letter codes from the assembly syntax. They are more canonical, and easier to look up the exact meaning than these.

Done, and related to this, I have completely removed getPredicateByName(), instead I can just call existing function ARMCondCodeToString().

Is this syntax used for comments anywhere else? It's not immediately obvious from reading the changed tests that this is a comment, could we use something more common like /* C-stlye */ comments?

I have no strong opinion on this. I chose [ and ] mainly for these 2 reasons:

  • it's a character currently not used by the lexer,
  • it is 1 character, which I found nice and concise and pleasant to read. I think I find it more pleasant to read than /* and */ in MIR code, but I appreciate this is very subjective, see next paragraph.

I have only added 1 changed test case, because the ~140 I had to change make things difficult to read here. I will make the final change changing all tests when we are happy about the exact syntax:

  • I have adopted the 2-letter codes syntax. To make this readable, I have prefixed this with CC:: to indicate this is a condition code, so that for example you'll see [CC::al].
  • As I said above, I have kept the [ and ] for now to open/close comments, but would be happy to change. If @efriedma has a preference, then I will take that into account, make the change, and then update all the tests.

About updating the tests, that's actually pretty straightforward because for about ~120 I can just use the script (just letting know that's how I changed them). For about 20 of them, that doesn't really work because of shared check-prefixes, so I need to change them "manually" with a little bit search/replace commands, but is not a big deal.

SjoerdMeijer updated this revision to Diff 244643.Feb 14 2020, 6:24 AM

the same patch, but now with context.

efriedma added subscribers: MatzeB, arsenm.Feb 18 2020, 3:17 PM

I can see two problems with [] comment delimiters:

  1. ] is used somewhat frequently in target-specific assembly syntax, so it might end up overlapping with stuff some target wants to print. Maybe not that likely in practice.
  2. It isn't obvious that the contents of the [] is a comment. Something like /**/ would give instant recognition to people even if they're not really familiar with MIR syntax.

Otherwise looks fine.

SjoerdMeijer updated this revision to Diff 245595.Feb 20 2020, 12:37 AM

Thanks again for the suggestions/comments. The MachineOperand comments are now enclosed between /* and */, see the only test file that I have uploaded.

As a last step, I can now change all tests. I can upload them here, or commit directly when you're happy with this patch. The only reason I have not uploaded the ~140 changed tests, is because that makes this Phab diff a bit unwieldy.

ostannard accepted this revision.Feb 24 2020, 2:12 AM

LGTM with one really minor nit.

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
501

Comments should end with full stops.

This revision is now accepted and ready to land.Feb 24 2020, 2:12 AM
Closed by commit rG7efabe5c7de4: [MIR][ARM] MachineOperand comments (authored by SjoerdMeijer). · Explain WhyFeb 24 2020, 6:23 AM
This revision was automatically updated to reflect the committed changes.
SjoerdMeijer mentioned this in D96518: [MIRLangRef] Document MachineOperand comments.Feb 11 2021, 8:49 AM
SjoerdMeijer mentioned this in rGcc4dcd48b84e: [MIRLangRef] Document MachineOperand comments.Feb 12 2021, 2:16 AM

Revision Contents

PathSize
llvm/
include/
llvm/
CodeGen/
7 lines
lib/
CodeGen/
MIRParser/
16 lines
19 lines
Target/
ARM/
5 lines
18 lines
test/
CodeGen/
ARM/
34 lines
GlobalISel/
73 lines
484 lines
295 lines
545 lines
48 lines
72 lines
130 lines
4 lines
16 lines
32 lines
12 lines
30 lines
6 lines
28 lines
108 lines
27 lines
36 lines
17 lines
4 lines
121 lines
125 lines
26 lines
259 lines
28 lines
32 lines
12 lines
28 lines
81 lines
81 lines
35 lines
38 lines
22 lines
33 lines
94 lines
10 lines
29 lines
53 lines
29 lines
99 lines
42 lines
20 lines
36 lines
28 lines
17 lines
30 lines
43 lines
8 lines
7 lines
6 lines
15 lines
86 lines
2 lines
22 lines
39 lines
18 lines
9 lines
MIR/
ARM/
35 lines
18 lines
Thumb/
133 lines
191 lines
Thumb2/
LowOverheadLoops/
28 lines
14 lines
38 lines
12 lines
26 lines
12 lines
76 lines
29 lines
20 lines
20 lines
20 lines
30 lines
30 lines
30 lines
32 lines
32 lines
28 lines
16 lines
74 lines
26 lines
10 lines
162 lines
160 lines
158 lines
52 lines
130 lines
14 lines
20 lines
22 lines
26 lines
100 lines
183 lines
27 lines
34 lines
22 lines
106 lines
12 lines
80 lines
4 lines
26 lines
16 lines
22 lines
30 lines
146 lines
30 lines
32 lines
22 lines
30 lines
32 lines
20 lines
8 lines
8 lines
8 lines
36 lines
12 lines
16 lines
14 lines
56 lines
35 lines
34 lines
28 lines
108 lines
10 lines
15 lines
48 lines
20 lines
6 lines
6 lines
4 lines
4 lines
4 lines
4 lines
4 lines
4 lines
4 lines
12 lines
4 lines
12 lines
6 lines
15 lines
19 lines
62 lines
18 lines
DebugInfo/
MIR/
ARM/
2 lines

Diff 246195

llvm/include/llvm/CodeGen/TargetInstrInfo.h

Show First 20 Lines • Show All 1,303 Lines • ▼ Show 20 Linespublic:
virtual void getNoop(MCInst &NopInst) const; virtual void getNoop(MCInst &NopInst) const;
/// Return true for post-incremented instructions. /// Return true for post-incremented instructions.
virtual bool isPostIncrement(const MachineInstr &MI) const { return false; } virtual bool isPostIncrement(const MachineInstr &MI) const { return false; }
/// Returns true if the instruction is already predicated. /// Returns true if the instruction is already predicated.
virtual bool isPredicated(const MachineInstr &MI) const { return false; } virtual bool isPredicated(const MachineInstr &MI) const { return false; }
// Returns a MIRPrinter comment for this machine operand.
virtual std::string createMIROperandComment(const MachineInstr &MI,
ostannardUnsubmitted
Not Done
ReplyInline Actions

Is this still needed in the common TargetInstrInfo?

ostannard: Is this still needed in the common TargetInstrInfo?
const MachineOperand &Op,
unsigned OpIdx) const {
return std::string();
ostannardUnsubmitted
Not Done
ReplyInline Actions

Returning a const char * is going to make it hard for targets to dynamically construct comments, e.g. Eli's example of "26" -> "lsl #3" in ADDrsi. The MIR printer is only used for debugging, so using a std::string here should be fine.

ostannard: Returning a `const char *` is going to make it hard for targets to dynamically construct…
};
/// Returns true if the instruction is a /// Returns true if the instruction is a
/// terminator instruction that has not been predicated. /// terminator instruction that has not been predicated.
virtual bool isUnpredicatedTerminator(const MachineInstr &MI) const; virtual bool isUnpredicatedTerminator(const MachineInstr &MI) const;
/// Returns true if MI is an unconditional tail call. /// Returns true if MI is an unconditional tail call.
virtual bool isUnconditionalTailCall(const MachineInstr &MI) const { virtual bool isUnconditionalTailCall(const MachineInstr &MI) const {
return false; return false;
} }
▲ Show 20 Lines • Show All 552 Lines • Show Last 20 Lines

llvm/lib/CodeGen/MIRParser/MILexer.cpp

Show First 20 Lines • Show All 98 Lines • ▼ Show 20 Lines
static Cursor skipComment(Cursor C) { static Cursor skipComment(Cursor C) {
if (C.peek() != ';') if (C.peek() != ';')
return C; return C;
while (!isNewlineChar(C.peek()) && !C.isEOF()) while (!isNewlineChar(C.peek()) && !C.isEOF())
C.advance(); C.advance();
return C; return C;
} }
/// Machine operands can have comments, enclosed between /* and */.
ostannardUnsubmitted
Not Done
ReplyInline Actions

Is this syntax used for comments anywhere else? It's not immediately obvious from reading the changed tests that this is a comment, could we use something more common like /* C-stlye */ comments?

ostannard: Is this syntax used for comments anywhere else? It's not immediately obvious from reading the…
/// This eats up all tokens, including /* and */.
static Cursor skipMachineOperandComment(Cursor C) {
if (C.peek() != '/' || C.peek(1) != '*')
return C;
while (C.peek() != '*' || C.peek(1) != '/')
C.advance();
C.advance();
C.advance();
return C;
}
/// Return true if the given character satisfies the following regular /// Return true if the given character satisfies the following regular
/// expression: [-a-zA-Z$._0-9] /// expression: [-a-zA-Z$._0-9]
static bool isIdentifierChar(char C) { static bool isIdentifierChar(char C) {
return isalpha(C) || isdigit(C) || C == '_' || C == '-' || C == '.' || return isalpha(C) || isdigit(C) || C == '_' || C == '-' || C == '.' ||
C == '$'; C == '$';
} }
/// Unescapes the given string value. /// Unescapes the given string value.
▲ Show 20 Lines • Show All 571 Lines • ▼ Show 20 Lines
StringRef llvm::lexMIToken(StringRef Source, MIToken &Token, StringRef llvm::lexMIToken(StringRef Source, MIToken &Token,
ErrorCallbackType ErrorCallback) { ErrorCallbackType ErrorCallback) {
auto C = skipComment(skipWhitespace(Cursor(Source))); auto C = skipComment(skipWhitespace(Cursor(Source)));
if (C.isEOF()) { if (C.isEOF()) {
Token.reset(MIToken::Eof, C.remaining()); Token.reset(MIToken::Eof, C.remaining());
return C.remaining(); return C.remaining();
} }
C = skipMachineOperandComment(C);
if (Cursor R = maybeLexMachineBasicBlock(C, Token, ErrorCallback)) if (Cursor R = maybeLexMachineBasicBlock(C, Token, ErrorCallback))
return R.remaining(); return R.remaining();
if (Cursor R = maybeLexIdentifier(C, Token)) if (Cursor R = maybeLexIdentifier(C, Token))
return R.remaining(); return R.remaining();
if (Cursor R = maybeLexJumpTableIndex(C, Token)) if (Cursor R = maybeLexJumpTableIndex(C, Token))
return R.remaining(); return R.remaining();
if (Cursor R = maybeLexStackObject(C, Token)) if (Cursor R = maybeLexStackObject(C, Token))
return R.remaining(); return R.remaining();
Show All 38 Lines

llvm/lib/CodeGen/MIRPrinter.cpp

Show First 20 Lines • Show All 156 Lines • ▼ Show 20 Lines MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
: OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds), : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
StackObjectOperandMapping(StackObjectOperandMapping) {} StackObjectOperandMapping(StackObjectOperandMapping) {}
void print(const MachineBasicBlock &MBB); void print(const MachineBasicBlock &MBB);
void print(const MachineInstr &MI); void print(const MachineInstr &MI);
void printStackObjectReference(int FrameIndex); void printStackObjectReference(int FrameIndex);
void print(const MachineInstr &MI, unsigned OpIdx, void print(const MachineInstr &MI, unsigned OpIdx,
const TargetRegisterInfo *TRI, bool ShouldPrintRegisterTies, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII,
LLT TypeToPrint, bool PrintDef = true); bool ShouldPrintRegisterTies, LLT TypeToPrint,
bool PrintDef = true);
}; };
} // end namespace llvm } // end namespace llvm
namespace llvm { namespace llvm {
namespace yaml { namespace yaml {
/// This struct serializes the LLVM IR module. /// This struct serializes the LLVM IR module.
▲ Show 20 Lines • Show All 541 Lines • ▼ Show 20 Linesvoid MIPrinter::print(const MachineInstr &MI) {
SmallBitVector PrintedTypes(8); SmallBitVector PrintedTypes(8);
bool ShouldPrintRegisterTies = MI.hasComplexRegisterTies(); bool ShouldPrintRegisterTies = MI.hasComplexRegisterTies();
unsigned I = 0, E = MI.getNumOperands(); unsigned I = 0, E = MI.getNumOperands();
for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() && for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
!MI.getOperand(I).isImplicit(); !MI.getOperand(I).isImplicit();
++I) { ++I) {
if (I) if (I)
OS << ", "; OS << ", ";
print(MI, I, TRI, ShouldPrintRegisterTies, print(MI, I, TRI, TII, ShouldPrintRegisterTies,
MI.getTypeToPrint(I, PrintedTypes, MRI), MI.getTypeToPrint(I, PrintedTypes, MRI),
/*PrintDef=*/false); /*PrintDef=*/false);
} }
if (I) if (I)
OS << " = "; OS << " = ";
if (MI.getFlag(MachineInstr::FrameSetup)) if (MI.getFlag(MachineInstr::FrameSetup))
OS << "frame-setup "; OS << "frame-setup ";
Show All 25 Linesvoid MIPrinter::print(const MachineInstr &MI) {
OS << TII->getName(MI.getOpcode()); OS << TII->getName(MI.getOpcode());
if (I < E) if (I < E)
OS << ' '; OS << ' ';
bool NeedComma = false; bool NeedComma = false;
for (; I < E; ++I) { for (; I < E; ++I) {
if (NeedComma) if (NeedComma)
OS << ", "; OS << ", ";
print(MI, I, TRI, ShouldPrintRegisterTies, print(MI, I, TRI, TII, ShouldPrintRegisterTies,
MI.getTypeToPrint(I, PrintedTypes, MRI)); MI.getTypeToPrint(I, PrintedTypes, MRI));
NeedComma = true; NeedComma = true;
} }
// Print any optional symbols attached to this instruction as-if they were // Print any optional symbols attached to this instruction as-if they were
// operands. // operands.
if (MCSymbol *PreInstrSymbol = MI.getPreInstrSymbol()) { if (MCSymbol *PreInstrSymbol = MI.getPreInstrSymbol()) {
if (NeedComma) if (NeedComma)
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Linesvoid MIPrinter::printStackObjectReference(int FrameIndex) {
auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex); auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
assert(ObjectInfo != StackObjectOperandMapping.end() && assert(ObjectInfo != StackObjectOperandMapping.end() &&
"Invalid frame index"); "Invalid frame index");
const FrameIndexOperand &Operand = ObjectInfo->second; const FrameIndexOperand &Operand = ObjectInfo->second;
MachineOperand::printStackObjectReference(OS, Operand.ID, Operand.IsFixed, MachineOperand::printStackObjectReference(OS, Operand.ID, Operand.IsFixed,
Operand.Name); Operand.Name);
} }
static std::string formatOperandComment(std::string Comment) {
if (Comment.empty())
return Comment;
return std::string(" /* " + Comment + " */");
}
void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx, void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
const TargetRegisterInfo *TRI, const TargetRegisterInfo *TRI,
const TargetInstrInfo *TII,
bool ShouldPrintRegisterTies, LLT TypeToPrint, bool ShouldPrintRegisterTies, LLT TypeToPrint,
bool PrintDef) { bool PrintDef) {
const MachineOperand &Op = MI.getOperand(OpIdx); const MachineOperand &Op = MI.getOperand(OpIdx);
std::string MOComment = TII->createMIROperandComment(MI, Op, OpIdx);
switch (Op.getType()) { switch (Op.getType()) {
case MachineOperand::MO_Immediate: case MachineOperand::MO_Immediate:
if (MI.isOperandSubregIdx(OpIdx)) { if (MI.isOperandSubregIdx(OpIdx)) {
MachineOperand::printTargetFlags(OS, Op); MachineOperand::printTargetFlags(OS, Op);
MachineOperand::printSubRegIdx(OS, Op.getImm(), TRI); MachineOperand::printSubRegIdx(OS, Op.getImm(), TRI);
break; break;
} }
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
Show All 15 Linesvoid MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
case MachineOperand::MO_BlockAddress: case MachineOperand::MO_BlockAddress:
case MachineOperand::MO_ShuffleMask: { case MachineOperand::MO_ShuffleMask: {
unsigned TiedOperandIdx = 0; unsigned TiedOperandIdx = 0;
if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef()) if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx); TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
const TargetIntrinsicInfo *TII = MI.getMF()->getTarget().getIntrinsicInfo(); const TargetIntrinsicInfo *TII = MI.getMF()->getTarget().getIntrinsicInfo();
Op.print(OS, MST, TypeToPrint, OpIdx, PrintDef, /*IsStandalone=*/false, Op.print(OS, MST, TypeToPrint, OpIdx, PrintDef, /*IsStandalone=*/false,
ShouldPrintRegisterTies, TiedOperandIdx, TRI, TII); ShouldPrintRegisterTies, TiedOperandIdx, TRI, TII);
OS << formatOperandComment(MOComment);
break; break;
} }
case MachineOperand::MO_FrameIndex: case MachineOperand::MO_FrameIndex:
printStackObjectReference(Op.getIndex()); printStackObjectReference(Op.getIndex());
break; break;
case MachineOperand::MO_RegisterMask: { case MachineOperand::MO_RegisterMask: {
auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask()); auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
if (RegMaskInfo != RegisterMaskIds.end()) if (RegMaskInfo != RegisterMaskIds.end())
Show All 39 Lines

llvm/lib/Target/ARM/ARMBaseInstrInfo.h

Show First 20 Lines • Show All 140 Lines • ▼ Show 20 Lines unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
int *BytesAdded = nullptr) const override; int *BytesAdded = nullptr) const override;
bool bool
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
// Predication support. // Predication support.
bool isPredicated(const MachineInstr &MI) const override; bool isPredicated(const MachineInstr &MI) const override;
// MIR printer helper function to annotate Operands with a comment.
std::string createMIROperandComment(const MachineInstr &MI,
const MachineOperand &Op,
unsigned OpIdx) const override;
ARMCC::CondCodes getPredicate(const MachineInstr &MI) const { ARMCC::CondCodes getPredicate(const MachineInstr &MI) const {
int PIdx = MI.findFirstPredOperandIdx(); int PIdx = MI.findFirstPredOperandIdx();
return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm() return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm()
: ARMCC::AL; : ARMCC::AL;
} }
bool PredicateInstruction(MachineInstr &MI, bool PredicateInstruction(MachineInstr &MI,
ArrayRef<MachineOperand> Pred) const override; ArrayRef<MachineOperand> Pred) const override;
▲ Show 20 Lines • Show All 626 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

Show First 20 Lines • Show All 489 Lines • ▼ Show 20 Lines if (MI.isBundle()) {
} }
return false; return false;
} }
int PIdx = MI.findFirstPredOperandIdx(); int PIdx = MI.findFirstPredOperandIdx();
return PIdx != -1 && MI.getOperand(PIdx).getImm() != ARMCC::AL; return PIdx != -1 && MI.getOperand(PIdx).getImm() != ARMCC::AL;
} }
std::string ARMBaseInstrInfo::createMIROperandComment(const MachineInstr &MI,
const MachineOperand &Op,
unsigned OpIdx) const {
ostannardUnsubmitted
Not Done
ReplyInline Actions

I think it would be better to use the two-letter codes from the assembly syntax. They are more canonical, and easier to look up the exact meaning than these.

ostannard: I think it would be better to use the two-letter codes from the assembly syntax. They are more…
// Only support immediates for now.
ostannardUnsubmitted
Not Done
ReplyInline Actions

Comments should end with full stops.

ostannard: Comments should end with full stops.
if (Op.getType() != MachineOperand::MO_Immediate)
return std::string();
// And print its corresponding condition code if the immediate is a
// predicate.
int FirstPredOp = MI.findFirstPredOperandIdx();
if (FirstPredOp != (int) OpIdx)
return std::string();
std::string CC = "CC::";
CC += ARMCondCodeToString((ARMCC::CondCodes)Op.getImm());
return CC;
}
bool ARMBaseInstrInfo::PredicateInstruction( bool ARMBaseInstrInfo::PredicateInstruction(
MachineInstr &MI, ArrayRef<MachineOperand> Pred) const { MachineInstr &MI, ArrayRef<MachineOperand> Pred) const {
unsigned Opc = MI.getOpcode(); unsigned Opc = MI.getOpcode();
if (isUncondBranchOpcode(Opc)) { if (isUncondBranchOpcode(Opc)) {
MI.setDesc(get(getMatchingCondBranchOpcode(Opc))); MI.setDesc(get(getMatchingCondBranchOpcode(Opc)));
MachineInstrBuilder(*MI.getParent()->getParent(), MI) MachineInstrBuilder(*MI.getParent()->getParent(), MI)
.addImm(Pred[0].getImm()) .addImm(Pred[0].getImm())
.addReg(Pred[1].getReg()); .addReg(Pred[1].getReg());
return true; return true;
} }
int PIdx = MI.findFirstPredOperandIdx(); int PIdx = MI.findFirstPredOperandIdx();
if (PIdx != -1) { if (PIdx != -1) {
MachineOperand &PMO = MI.getOperand(PIdx); MachineOperand &PMO = MI.getOperand(PIdx);
PMO.setImm(Pred[0].getImm()); PMO.setImm(Pred[0].getImm());
MI.getOperand(PIdx+1).setReg(Pred[1].getReg()); MI.getOperand(PIdx+1).setReg(Pred[1].getReg());
ostannardUnsubmitted
Not Done
ReplyInline Actions

getPredicateByName can never return a null pointer.

ostannard: `getPredicateByName` can never return a null pointer.
return true; return true;
} }
return false; return false;
} }
bool ARMBaseInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1, bool ARMBaseInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
ArrayRef<MachineOperand> Pred2) const { ArrayRef<MachineOperand> Pred2) const {
if (Pred1.size() > 2 || Pred2.size() > 2) if (Pred1.size() > 2 || Pred2.size() > 2)
▲ Show 20 Lines • Show All 4,941 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple thumbv7 -verify-machineinstrs -run-pass arm-ldst-opt %s -o - | FileCheck %s # RUN: llc -mtriple thumbv7 -verify-machineinstrs -run-pass arm-ldst-opt %s -o - | FileCheck %s
--- | --- |
; ModuleID = '/Volumes/Data/llvm/test/CodeGen/ARM/sched-it-debug-nodes.ll' ; ModuleID = '/Volumes/Data/llvm/test/CodeGen/ARM/sched-it-debug-nodes.ll'
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv7" target triple = "thumbv7"
%struct.s = type opaque %struct.s = type opaque
▲ Show 20 Lines • Show All 103 Lines • ▼ Show 20 LinesframeInfo:
maxCallFrameSize: 0 maxCallFrameSize: 0
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
stack: stack:
- { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '$lr', callee-saved-restored: false } - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '$lr', callee-saved-restored: false }
- { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '$r7', callee-saved-restored: true } - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '$r7', callee-saved-restored: true }
body: | body: |
; CHECK-LABEL: name: f
; CHECK: bb.0.entry:
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK: liveins: $r0, $r1, $r2, $r3, $lr, $r7
; CHECK: DBG_VALUE $r0, $noreg, !22, !DIExpression(), debug-location !26
; CHECK: DBG_VALUE $r1, $noreg, !23, !DIExpression(), debug-location !26
; CHECK: DBG_VALUE $r2, $noreg, !24, !DIExpression(), debug-location !26
; CHECK: DBG_VALUE $r3, $noreg, !25, !DIExpression(), debug-location !26
; CHECK: t2CMPri $r3, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr, debug-location !29
; CHECK: t2Bcc %bb.2, 2 /* CC::hs */, killed $cpsr
; CHECK: bb.1:
; CHECK: liveins: $lr, $r7
; CHECK: DBG_VALUE $r1, $noreg, !23, !DIExpression(), debug-location !26
; CHECK: $r0 = t2MOVi -1, 14 /* CC::al */, $noreg, $noreg
; CHECK: DBG_VALUE $r1, $noreg, !23, !DIExpression(), debug-location !26
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0, debug-location !32
; CHECK: bb.2.if.end:
; CHECK: liveins: $r0, $r2, $r3, $r7, $lr
; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r7, killed $lr
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: DBG_VALUE $r0, $noreg, !22, !DIExpression(), debug-location !26
; CHECK: DBG_VALUE $r1, $noreg, !23, !DIExpression(), debug-location !26
; CHECK: DBG_VALUE $r2, $noreg, !24, !DIExpression(), debug-location !26
; CHECK: DBG_VALUE $r3, $noreg, !25, !DIExpression(), debug-location !26
; CHECK: $r1 = COPY killed $r2, debug-location !30
; CHECK: DBG_VALUE $r1, $noreg, !23, !DIExpression(), debug-location !26
; CHECK: $r2 = COPY killed $r3, debug-location !30
; CHECK: tBL 14 /* CC::al */, $noreg, @g, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp, debug-location !30
; CHECK: $r0 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r7, def $pc, implicit $r0
bb.0.entry: bb.0.entry:
liveins: $r0, $r1, $r2, $r3, $lr, $r7 liveins: $r0, $r1, $r2, $r3, $lr, $r7
DBG_VALUE $r0, $noreg, !18, !27, debug-location !28 DBG_VALUE $r0, $noreg, !18, !27, debug-location !28
DBG_VALUE $r1, $noreg, !19, !27, debug-location !28 DBG_VALUE $r1, $noreg, !19, !27, debug-location !28
DBG_VALUE $r2, $noreg, !20, !27, debug-location !28 DBG_VALUE $r2, $noreg, !20, !27, debug-location !28
DBG_VALUE $r3, $noreg, !21, !27, debug-location !28 DBG_VALUE $r3, $noreg, !21, !27, debug-location !28
t2CMPri $r3, 4, 14, $noreg, implicit-def $cpsr, debug-location !31 t2CMPri $r3, 4, 14, $noreg, implicit-def $cpsr, debug-location !31
Show All 21 Lines bb.2.if.end:
$r1 = COPY killed $r2, debug-location !32 $r1 = COPY killed $r2, debug-location !32
DBG_VALUE $r1, $noreg, !19, !27, debug-location !28 DBG_VALUE $r1, $noreg, !19, !27, debug-location !28
$r2 = COPY killed $r3, debug-location !32 $r2 = COPY killed $r3, debug-location !32
tBL 14, $noreg, @g, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp, debug-location !32 tBL 14, $noreg, @g, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp, debug-location !32
$r0 = t2MOVi 0, 14, $noreg, $noreg $r0 = t2MOVi 0, 14, $noreg, $noreg
$sp = t2LDMIA_UPD $sp, 14, $noreg, def $r7, def $lr $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r7, def $lr
tBX_RET 14, $noreg, implicit $r0, debug-location !34 tBX_RET 14, $noreg, implicit $r0, debug-location !34
# Verify that the DBG_VALUE is ignored. # Verify that the DBG_VALUE is ignored.
# CHECK: $sp = t2LDMIA_RET $sp, 14, $noreg, def $r7, def $pc, implicit $r0
... ...

llvm/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple arm-unknown -mattr=-v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,NOV4T,ARM ; RUN: llc -mtriple arm-unknown -mattr=-v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,NOV4T,ARM
; RUN: llc -mtriple arm-unknown -mattr=+v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,V4T,ARM ; RUN: llc -mtriple arm-unknown -mattr=+v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,V4T,ARM
; RUN: llc -mtriple arm-unknown -mattr=+v5t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,V5T,ARM ; RUN: llc -mtriple arm-unknown -mattr=+v5t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,V5T,ARM
; RUN: llc -mtriple thumb-unknown -mattr=+v6t2 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,THUMB ; RUN: llc -mtriple thumb-unknown -mattr=+v6t2 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,THUMB
define arm_aapcscc void @test_indirect_call(void() *%fptr) { define arm_aapcscc void @test_indirect_call(void() *%fptr) {
; CHECK-LABEL: name: test_indirect_call ; NOV4T-LABEL: name: test_indirect_call
; THUMB: %[[FPTR:[0-9]+]]:gpr(p0) = COPY $r0 ; NOV4T: bb.1.entry:
; V5T: %[[FPTR:[0-9]+]]:gpr(p0) = COPY $r0 ; NOV4T: liveins: $r0
; V4T: %[[FPTR:[0-9]+]]:tgpr(p0) = COPY $r0 ; NOV4T: [[COPY:%[0-9]+]]:tgpr(p0) = COPY $r0
; NOV4T: %[[FPTR:[0-9]+]]:tgpr(p0) = COPY $r0 ; NOV4T: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp ; NOV4T: BMOVPCRX_CALL [[COPY]](p0), csr_aapcs, implicit-def $lr, implicit $sp
; THUMB: tBLXr 14, $noreg, %[[FPTR]](p0), csr_aapcs, implicit-def $lr, implicit $sp ; NOV4T: ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; V5T: BLX %[[FPTR]](p0), csr_aapcs, implicit-def $lr, implicit $sp ; NOV4T: MOVPCLR 14 /* CC::al */, $noreg
; V4T: BX_CALL %[[FPTR]](p0), csr_aapcs, implicit-def $lr, implicit $sp ; V4T-LABEL: name: test_indirect_call
; NOV4T: BMOVPCRX_CALL %[[FPTR]](p0), csr_aapcs, implicit-def $lr, implicit $sp ; V4T: bb.1.entry:
; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp ; V4T: liveins: $r0
; V4T: [[COPY:%[0-9]+]]:tgpr(p0) = COPY $r0
; V4T: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; V4T: BX_CALL [[COPY]](p0), csr_aapcs, implicit-def $lr, implicit $sp
; V4T: ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; V4T: BX_RET 14 /* CC::al */, $noreg
; V5T-LABEL: name: test_indirect_call
; V5T: bb.1.entry:
; V5T: liveins: $r0
; V5T: [[COPY:%[0-9]+]]:gpr(p0) = COPY $r0
; V5T: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; V5T: BLX [[COPY]](p0), csr_aapcs, implicit-def $lr, implicit $sp
; V5T: ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; V5T: BX_RET 14 /* CC::al */, $noreg
; THUMB-LABEL: name: test_indirect_call
; THUMB: bb.1.entry:
; THUMB: liveins: $r0
; THUMB: [[COPY:%[0-9]+]]:gpr(p0) = COPY $r0
; THUMB: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; THUMB: tBLXr 14 /* CC::al */, $noreg, [[COPY]](p0), csr_aapcs, implicit-def $lr, implicit $sp
; THUMB: ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; THUMB: tBX_RET 14 /* CC::al */, $noreg
entry: entry:
notail call arm_aapcscc void %fptr() notail call arm_aapcscc void %fptr()
ret void ret void
} }
declare arm_aapcscc void @call_target() declare arm_aapcscc void @call_target()
define arm_aapcscc void @test_direct_call() { define arm_aapcscc void @test_direct_call() {
; CHECK-LABEL: name: test_direct_call ; NOV4T-LABEL: name: test_direct_call
; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp ; NOV4T: bb.1.entry:
; THUMB: tBL 14, $noreg, @call_target, csr_aapcs, implicit-def $lr, implicit $sp ; NOV4T: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; ARM: BL @call_target, csr_aapcs, implicit-def $lr, implicit $sp ; NOV4T: BL @call_target, csr_aapcs, implicit-def $lr, implicit $sp
; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp ; NOV4T: ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; NOV4T: MOVPCLR 14 /* CC::al */, $noreg
; V4T-LABEL: name: test_direct_call
; V4T: bb.1.entry:
; V4T: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; V4T: BL @call_target, csr_aapcs, implicit-def $lr, implicit $sp
; V4T: ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; V4T: BX_RET 14 /* CC::al */, $noreg
; V5T-LABEL: name: test_direct_call
; V5T: bb.1.entry:
; V5T: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; V5T: BL @call_target, csr_aapcs, implicit-def $lr, implicit $sp
; V5T: ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; V5T: BX_RET 14 /* CC::al */, $noreg
; THUMB-LABEL: name: test_direct_call
; THUMB: bb.1.entry:
; THUMB: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; THUMB: tBL 14 /* CC::al */, $noreg, @call_target, csr_aapcs, implicit-def $lr, implicit $sp
; THUMB: ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; THUMB: tBX_RET 14 /* CC::al */, $noreg
entry: entry:
notail call arm_aapcscc void @call_target() notail call arm_aapcscc void @call_target()
ret void ret void
} }

llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Linesregisters:
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_eq_s32 ; CHECK-LABEL: name: test_icmp_eq_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr ; CHECK: CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0 /* CC::eq */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(eq), %0(s32), %1 %2(s1) = G_ICMP intpred(eq), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_icmp_ne_s32 name: test_icmp_ne_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_ne_s32 ; CHECK-LABEL: name: test_icmp_ne_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr ; CHECK: CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1 /* CC::ne */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(ne), %0(s32), %1 %2(s1) = G_ICMP intpred(ne), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_icmp_ugt_s32 name: test_icmp_ugt_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_ugt_s32 ; CHECK-LABEL: name: test_icmp_ugt_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr ; CHECK: CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8 /* CC::hi */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(ugt), %0(s32), %1 %2(s1) = G_ICMP intpred(ugt), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_icmp_uge_s32 name: test_icmp_uge_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_uge_s32 ; CHECK-LABEL: name: test_icmp_uge_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr ; CHECK: CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 2, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 2 /* CC::hs */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(uge), %0(s32), %1 %2(s1) = G_ICMP intpred(uge), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_icmp_ult_s32 name: test_icmp_ult_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_ult_s32 ; CHECK-LABEL: name: test_icmp_ult_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr ; CHECK: CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 3, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 3 /* CC::lo */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(ult), %0(s32), %1 %2(s1) = G_ICMP intpred(ult), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_icmp_ule_s32 name: test_icmp_ule_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_ule_s32 ; CHECK-LABEL: name: test_icmp_ule_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr ; CHECK: CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9 /* CC::ls */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(ule), %0(s32), %1 %2(s1) = G_ICMP intpred(ule), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_icmp_sgt_s32 name: test_icmp_sgt_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_sgt_s32 ; CHECK-LABEL: name: test_icmp_sgt_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr ; CHECK: CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12 /* CC::gt */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(sgt), %0(s32), %1 %2(s1) = G_ICMP intpred(sgt), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_icmp_sge_s32 name: test_icmp_sge_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_sge_s32 ; CHECK-LABEL: name: test_icmp_sge_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr ; CHECK: CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10 /* CC::ge */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(sge), %0(s32), %1 %2(s1) = G_ICMP intpred(sge), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_icmp_slt_s32 name: test_icmp_slt_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_slt_s32 ; CHECK-LABEL: name: test_icmp_slt_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr ; CHECK: CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11 /* CC::lt */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(slt), %0(s32), %1 %2(s1) = G_ICMP intpred(slt), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_icmp_sle_s32 name: test_icmp_sle_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_sle_s32 ; CHECK-LABEL: name: test_icmp_sle_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr ; CHECK: CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13 /* CC::le */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(sle), %0(s32), %1 %2(s1) = G_ICMP intpred(sle), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_fcmp_true_s32 name: test_fcmp_true_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $s0, $s1 liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_true_s32 ; CHECK-LABEL: name: test_fcmp_true_s32
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 1, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $s0 %0(s32) = COPY $s0
%1(s32) = COPY $s1 %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(true), %0(s32), %1 %2(s1) = G_FCMP floatpred(true), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_fcmp_false_s32 name: test_fcmp_false_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $s0, $s1 liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_false_s32 ; CHECK-LABEL: name: test_fcmp_false_s32
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $s0 %0(s32) = COPY $s0
%1(s32) = COPY $s1 %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(false), %0(s32), %1 %2(s1) = G_FCMP floatpred(false), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_fcmp_oeq_s32 name: test_fcmp_oeq_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $s0, $s1 liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_oeq_s32 ; CHECK-LABEL: name: test_fcmp_oeq_s32
; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv ; CHECK: VCMPS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv
; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0 /* CC::eq */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $s0 %0(s32) = COPY $s0
%1(s32) = COPY $s1 %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(oeq), %0(s32), %1 %2(s1) = G_FCMP floatpred(oeq), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_fcmp_ogt_s32 name: test_fcmp_ogt_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $s0, $s1 liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_ogt_s32 ; CHECK-LABEL: name: test_fcmp_ogt_s32
; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv ; CHECK: VCMPS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv
; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12 /* CC::gt */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $s0 %0(s32) = COPY $s0
%1(s32) = COPY $s1 %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(ogt), %0(s32), %1 %2(s1) = G_FCMP floatpred(ogt), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_fcmp_oge_s32 name: test_fcmp_oge_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $s0, $s1 liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_oge_s32 ; CHECK-LABEL: name: test_fcmp_oge_s32
; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv ; CHECK: VCMPS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv
; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10 /* CC::ge */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $s0 %0(s32) = COPY $s0
%1(s32) = COPY $s1 %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(oge), %0(s32), %1 %2(s1) = G_FCMP floatpred(oge), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_fcmp_olt_s32 name: test_fcmp_olt_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $s0, $s1 liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_olt_s32 ; CHECK-LABEL: name: test_fcmp_olt_s32
; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv ; CHECK: VCMPS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv
; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 4, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 4 /* CC::mi */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $s0 %0(s32) = COPY $s0
%1(s32) = COPY $s1 %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(olt), %0(s32), %1 %2(s1) = G_FCMP floatpred(olt), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_fcmp_ole_s32 name: test_fcmp_ole_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $s0, $s1 liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_ole_s32 ; CHECK-LABEL: name: test_fcmp_ole_s32
; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv ; CHECK: VCMPS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv
; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9 /* CC::ls */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $s0 %0(s32) = COPY $s0
%1(s32) = COPY $s1 %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(ole), %0(s32), %1 %2(s1) = G_FCMP floatpred(ole), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_fcmp_ord_s32 name: test_fcmp_ord_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $s0, $s1 liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_ord_s32 ; CHECK-LABEL: name: test_fcmp_ord_s32
; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv ; CHECK: VCMPS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv
; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 7, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 7 /* CC::vc */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $s0 %0(s32) = COPY $s0
%1(s32) = COPY $s1 %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(ord), %0(s32), %1 %2(s1) = G_FCMP floatpred(ord), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_fcmp_ugt_s32 name: test_fcmp_ugt_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $s0, $s1 liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_ugt_s32 ; CHECK-LABEL: name: test_fcmp_ugt_s32
; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv ; CHECK: VCMPS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv
; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8 /* CC::hi */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $s0 %0(s32) = COPY $s0
%1(s32) = COPY $s1 %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(ugt), %0(s32), %1 %2(s1) = G_FCMP floatpred(ugt), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_fcmp_uge_s32 name: test_fcmp_uge_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $s0, $s1 liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_uge_s32 ; CHECK-LABEL: name: test_fcmp_uge_s32
; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv ; CHECK: VCMPS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv
; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 5, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 5 /* CC::pl */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $s0 %0(s32) = COPY $s0
%1(s32) = COPY $s1 %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(uge), %0(s32), %1 %2(s1) = G_FCMP floatpred(uge), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_fcmp_ult_s32 name: test_fcmp_ult_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $s0, $s1 liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_ult_s32 ; CHECK-LABEL: name: test_fcmp_ult_s32
; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv ; CHECK: VCMPS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv
; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11 /* CC::lt */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $s0 %0(s32) = COPY $s0
%1(s32) = COPY $s1 %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(ult), %0(s32), %1 %2(s1) = G_FCMP floatpred(ult), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_fcmp_ule_s32 name: test_fcmp_ule_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $s0, $s1 liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_ule_s32 ; CHECK-LABEL: name: test_fcmp_ule_s32
; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv ; CHECK: VCMPS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv
; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13 /* CC::le */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $s0 %0(s32) = COPY $s0
%1(s32) = COPY $s1 %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(ule), %0(s32), %1 %2(s1) = G_FCMP floatpred(ule), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_fcmp_une_s32 name: test_fcmp_une_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $s0, $s1 liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_une_s32 ; CHECK-LABEL: name: test_fcmp_une_s32
; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv ; CHECK: VCMPS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv
; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1 /* CC::ne */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $s0 %0(s32) = COPY $s0
%1(s32) = COPY $s1 %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(une), %0(s32), %1 %2(s1) = G_FCMP floatpred(une), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_fcmp_uno_s32 name: test_fcmp_uno_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $s0, $s1 liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_uno_s32 ; CHECK-LABEL: name: test_fcmp_uno_s32
; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv ; CHECK: VCMPS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv
; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 6, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 6 /* CC::vs */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $s0 %0(s32) = COPY $s0
%1(s32) = COPY $s1 %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(uno), %0(s32), %1 %2(s1) = G_FCMP floatpred(uno), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_fcmp_one_s32 name: test_fcmp_one_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $s0, $s1 liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_one_s32 ; CHECK-LABEL: name: test_fcmp_one_s32
; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv ; CHECK: VCMPS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv
; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12 /* CC::gt */, $cpsr
; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv ; CHECK: VCMPS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv
; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 4, $cpsr ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 4 /* CC::mi */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $s0 %0(s32) = COPY $s0
%1(s32) = COPY $s1 %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(one), %0(s32), %1 %2(s1) = G_FCMP floatpred(one), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_fcmp_ueq_s32 name: test_fcmp_ueq_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $s0, $s1 liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_ueq_s32 ; CHECK-LABEL: name: test_fcmp_ueq_s32
; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv ; CHECK: VCMPS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv
; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0 /* CC::eq */, $cpsr
; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv ; CHECK: VCMPS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv
; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 6, $cpsr ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 6 /* CC::vs */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $s0 %0(s32) = COPY $s0
%1(s32) = COPY $s1 %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(ueq), %0(s32), %1 %2(s1) = G_FCMP floatpred(ueq), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_fcmp_true_s64 name: test_fcmp_true_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $d0, $d1 liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_true_s64 ; CHECK-LABEL: name: test_fcmp_true_s64
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 1, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s64) = COPY $d0 %0(s64) = COPY $d0
%1(s64) = COPY $d1 %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(true), %0(s64), %1 %2(s1) = G_FCMP floatpred(true), %0(s64), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_fcmp_false_s64 name: test_fcmp_false_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $d0, $d1 liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_false_s64 ; CHECK-LABEL: name: test_fcmp_false_s64
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s64) = COPY $d0 %0(s64) = COPY $d0
%1(s64) = COPY $d1 %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(false), %0(s64), %1 %2(s1) = G_FCMP floatpred(false), %0(s64), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_fcmp_oeq_s64 name: test_fcmp_oeq_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $d0, $d1 liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_oeq_s64 ; CHECK-LABEL: name: test_fcmp_oeq_s64
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv ; CHECK: VCMPD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv
; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0 /* CC::eq */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s64) = COPY $d0 %0(s64) = COPY $d0
%1(s64) = COPY $d1 %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(oeq), %0(s64), %1 %2(s1) = G_FCMP floatpred(oeq), %0(s64), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_fcmp_ogt_s64 name: test_fcmp_ogt_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $d0, $d1 liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_ogt_s64 ; CHECK-LABEL: name: test_fcmp_ogt_s64
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv ; CHECK: VCMPD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv
; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12 /* CC::gt */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s64) = COPY $d0 %0(s64) = COPY $d0
%1(s64) = COPY $d1 %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(ogt), %0(s64), %1 %2(s1) = G_FCMP floatpred(ogt), %0(s64), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_fcmp_oge_s64 name: test_fcmp_oge_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $d0, $d1 liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_oge_s64 ; CHECK-LABEL: name: test_fcmp_oge_s64
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv ; CHECK: VCMPD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv
; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10 /* CC::ge */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s64) = COPY $d0 %0(s64) = COPY $d0
%1(s64) = COPY $d1 %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(oge), %0(s64), %1 %2(s1) = G_FCMP floatpred(oge), %0(s64), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_fcmp_olt_s64 name: test_fcmp_olt_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $d0, $d1 liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_olt_s64 ; CHECK-LABEL: name: test_fcmp_olt_s64
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv ; CHECK: VCMPD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv
; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 4, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 4 /* CC::mi */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s64) = COPY $d0 %0(s64) = COPY $d0
%1(s64) = COPY $d1 %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(olt), %0(s64), %1 %2(s1) = G_FCMP floatpred(olt), %0(s64), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_fcmp_ole_s64 name: test_fcmp_ole_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $d0, $d1 liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_ole_s64 ; CHECK-LABEL: name: test_fcmp_ole_s64
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv ; CHECK: VCMPD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv
; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9 /* CC::ls */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s64) = COPY $d0 %0(s64) = COPY $d0
%1(s64) = COPY $d1 %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(ole), %0(s64), %1 %2(s1) = G_FCMP floatpred(ole), %0(s64), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_fcmp_ord_s64 name: test_fcmp_ord_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $d0, $d1 liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_ord_s64 ; CHECK-LABEL: name: test_fcmp_ord_s64
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv ; CHECK: VCMPD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv
; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 7, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 7 /* CC::vc */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s64) = COPY $d0 %0(s64) = COPY $d0
%1(s64) = COPY $d1 %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(ord), %0(s64), %1 %2(s1) = G_FCMP floatpred(ord), %0(s64), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_fcmp_ugt_s64 name: test_fcmp_ugt_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $d0, $d1 liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_ugt_s64 ; CHECK-LABEL: name: test_fcmp_ugt_s64
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv ; CHECK: VCMPD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv
; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8 /* CC::hi */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s64) = COPY $d0 %0(s64) = COPY $d0
%1(s64) = COPY $d1 %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(ugt), %0(s64), %1 %2(s1) = G_FCMP floatpred(ugt), %0(s64), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_fcmp_uge_s64 name: test_fcmp_uge_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $d0, $d1 liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_uge_s64 ; CHECK-LABEL: name: test_fcmp_uge_s64
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv ; CHECK: VCMPD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv
; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 5, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 5 /* CC::pl */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s64) = COPY $d0 %0(s64) = COPY $d0
%1(s64) = COPY $d1 %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(uge), %0(s64), %1 %2(s1) = G_FCMP floatpred(uge), %0(s64), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_fcmp_ult_s64 name: test_fcmp_ult_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $d0, $d1 liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_ult_s64 ; CHECK-LABEL: name: test_fcmp_ult_s64
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv ; CHECK: VCMPD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv
; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11 /* CC::lt */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s64) = COPY $d0 %0(s64) = COPY $d0
%1(s64) = COPY $d1 %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(ult), %0(s64), %1 %2(s1) = G_FCMP floatpred(ult), %0(s64), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_fcmp_ule_s64 name: test_fcmp_ule_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $d0, $d1 liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_ule_s64 ; CHECK-LABEL: name: test_fcmp_ule_s64
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv ; CHECK: VCMPD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv
; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13 /* CC::le */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s64) = COPY $d0 %0(s64) = COPY $d0
%1(s64) = COPY $d1 %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(ule), %0(s64), %1 %2(s1) = G_FCMP floatpred(ule), %0(s64), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_fcmp_une_s64 name: test_fcmp_une_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $d0, $d1 liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_une_s64 ; CHECK-LABEL: name: test_fcmp_une_s64
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv ; CHECK: VCMPD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv
; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1 /* CC::ne */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s64) = COPY $d0 %0(s64) = COPY $d0
%1(s64) = COPY $d1 %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(une), %0(s64), %1 %2(s1) = G_FCMP floatpred(une), %0(s64), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_fcmp_uno_s64 name: test_fcmp_uno_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $d0, $d1 liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_uno_s64 ; CHECK-LABEL: name: test_fcmp_uno_s64
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv ; CHECK: VCMPD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv
; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 6, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 6 /* CC::vs */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s64) = COPY $d0 %0(s64) = COPY $d0
%1(s64) = COPY $d1 %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(uno), %0(s64), %1 %2(s1) = G_FCMP floatpred(uno), %0(s64), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_fcmp_one_s64 name: test_fcmp_one_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $d0, $d1 liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_one_s64 ; CHECK-LABEL: name: test_fcmp_one_s64
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv ; CHECK: VCMPD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv
; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12 /* CC::gt */, $cpsr
; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv ; CHECK: VCMPD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv
; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 4, $cpsr ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 4 /* CC::mi */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s64) = COPY $d0 %0(s64) = COPY $d0
%1(s64) = COPY $d1 %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(one), %0(s64), %1 %2(s1) = G_FCMP floatpred(one), %0(s64), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_fcmp_ueq_s64 name: test_fcmp_ueq_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $d0, $d1 liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_ueq_s64 ; CHECK-LABEL: name: test_fcmp_ueq_s64
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv ; CHECK: VCMPD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv
; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, $cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0 /* CC::eq */, $cpsr
; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv ; CHECK: VCMPD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv
; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 6, $cpsr ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 6 /* CC::vs */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, $noreg, $noreg ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s64) = COPY $d0 %0(s64) = COPY $d0
%1(s64) = COPY $d1 %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(ueq), %0(s64), %1 %2(s1) = G_FCMP floatpred(ueq), %0(s64), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...

llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple arm-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -O0 -mtriple arm-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- | --- |
define void @test_mla() #0 { ret void } define void @test_mla() #0 { ret void }
define void @test_mla_commutative() #0 { ret void } define void @test_mla_commutative() #0 { ret void }
define void @test_mla_v5() #1 { ret void } define void @test_mla_v5() #1 { ret void }
define void @test_mls() #2 { ret void } define void @test_mls() #2 { ret void }
define void @test_no_mls() { ret void } define void @test_no_mls() { ret void }
Show All 26 Lines--- |
attributes #0 = { "target-features"="+v6" } attributes #0 = { "target-features"="+v6" }
attributes #1 = { "target-features"="-v6" } attributes #1 = { "target-features"="-v6" }
attributes #2 = { "target-features"="+v6t2" } attributes #2 = { "target-features"="+v6t2" }
attributes #3 = { "target-features"="+vfp2" } attributes #3 = { "target-features"="+vfp2" }
attributes #4 = { "target-features"="+vfp4" } attributes #4 = { "target-features"="+vfp4" }
... ...
--- ---
name: test_mla name: test_mla
# CHECK-LABEL: name: test_mla
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
- { id: 4, class: gprb } - { id: 4, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1, $r2 liveins: $r0, $r1, $r2
; CHECK-LABEL: name: test_mla
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gprnopc = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:gprnopc = COPY $r2
; CHECK: [[MLA:%[0-9]+]]:gprnopc = MLA [[COPY]], [[COPY1]], [[COPY2]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[MLA]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
%2(s32) = COPY $r2 %2(s32) = COPY $r2
; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY $r2
%3(s32) = G_MUL %0, %1 %3(s32) = G_MUL %0, %1
%4(s32) = G_ADD %3, %2 %4(s32) = G_ADD %3, %2
; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, $noreg, $noreg
$r0 = COPY %4(s32) $r0 = COPY %4(s32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_mla_commutative name: test_mla_commutative
# CHECK-LABEL: name: test_mla_commutative
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
- { id: 4, class: gprb } - { id: 4, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1, $r2 liveins: $r0, $r1, $r2
; CHECK-LABEL: name: test_mla_commutative
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gprnopc = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:gprnopc = COPY $r2
; CHECK: [[MLA:%[0-9]+]]:gprnopc = MLA [[COPY]], [[COPY1]], [[COPY2]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[MLA]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
%2(s32) = COPY $r2 %2(s32) = COPY $r2
; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY $r2
%3(s32) = G_MUL %0, %1 %3(s32) = G_MUL %0, %1
%4(s32) = G_ADD %2, %3 %4(s32) = G_ADD %2, %3
; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, $noreg, $noreg
$r0 = COPY %4(s32) $r0 = COPY %4(s32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_mla_v5 name: test_mla_v5
# CHECK-LABEL: name: test_mla_v5
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
- { id: 4, class: gprb } - { id: 4, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1, $r2 liveins: $r0, $r1, $r2
; CHECK-LABEL: name: test_mla_v5
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gprnopc = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:gprnopc = COPY $r2
; CHECK: early-clobber %4:gprnopc = MLAv5 [[COPY]], [[COPY1]], [[COPY2]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY %4
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
%2(s32) = COPY $r2 %2(s32) = COPY $r2
; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY $r2
%3(s32) = G_MUL %0, %1 %3(s32) = G_MUL %0, %1
%4(s32) = G_ADD %3, %2 %4(s32) = G_ADD %3, %2
; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLAv5 [[VREGX]], [[VREGY]], [[VREGZ]], 14, $noreg, $noreg
$r0 = COPY %4(s32) $r0 = COPY %4(s32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_mls name: test_mls
# CHECK-LABEL: name: test_mls
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
- { id: 4, class: gprb } - { id: 4, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1, $r2 liveins: $r0, $r1, $r2
; CHECK-LABEL: name: test_mls
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:gpr = COPY $r2
; CHECK: [[MLS:%[0-9]+]]:gpr = MLS [[COPY]], [[COPY1]], [[COPY2]], 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[MLS]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
%2(s32) = COPY $r2 %2(s32) = COPY $r2
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[VREGZ:%[0-9]+]]:gpr = COPY $r2
%3(s32) = G_MUL %0, %1 %3(s32) = G_MUL %0, %1
%4(s32) = G_SUB %2, %3 %4(s32) = G_SUB %2, %3
; CHECK: [[VREGR:%[0-9]+]]:gpr = MLS [[VREGX]], [[VREGY]], [[VREGZ]], 14, $noreg
$r0 = COPY %4(s32) $r0 = COPY %4(s32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_no_mls name: test_no_mls
# CHECK-LABEL: name: test_no_mls
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
- { id: 4, class: gprb } - { id: 4, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1, $r2 liveins: $r0, $r1, $r2
; CHECK-LABEL: name: test_no_mls
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gprnopc = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:gpr = COPY $r2
; CHECK: early-clobber %3:gprnopc = MULv5 [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
; CHECK: [[SUBrr:%[0-9]+]]:gpr = SUBrr [[COPY2]], %3, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[SUBrr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
%2(s32) = COPY $r2 %2(s32) = COPY $r2
; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
; CHECK: [[VREGZ:%[0-9]+]]:gpr = COPY $r2
%3(s32) = G_MUL %0, %1 %3(s32) = G_MUL %0, %1
%4(s32) = G_SUB %2, %3 %4(s32) = G_SUB %2, %3
; CHECK: [[VREGM:%[0-9]+]]:gprnopc = MULv5 [[VREGX]], [[VREGY]], 14, $noreg, $noreg
; CHECK: [[VREGR:%[0-9]+]]:gpr = SUBrr [[VREGZ]], [[VREGM]], 14, $noreg, $noreg
$r0 = COPY %4(s32) $r0 = COPY %4(s32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_bicrr name: test_bicrr
# CHECK-LABEL: name: test_bicrr
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
- { id: 4, class: gprb } - { id: 4, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_bicrr
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[BICrr:%[0-9]+]]:gpr = BICrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[BICrr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
%2(s32) = G_CONSTANT i32 -1 %2(s32) = G_CONSTANT i32 -1
%3(s32) = G_XOR %1, %2 %3(s32) = G_XOR %1, %2
%4(s32) = G_AND %0, %3 %4(s32) = G_AND %0, %3
; CHECK: [[VREGR:%[0-9]+]]:gpr = BICrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
$r0 = COPY %4(s32) $r0 = COPY %4(s32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_bicrr_commutative name: test_bicrr_commutative
# CHECK-LABEL: name: test_bicrr_commutative
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
- { id: 4, class: gprb } - { id: 4, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_bicrr_commutative
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[BICrr:%[0-9]+]]:gpr = BICrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[BICrr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
%2(s32) = G_CONSTANT i32 -1 %2(s32) = G_CONSTANT i32 -1
%3(s32) = G_XOR %1, %2 %3(s32) = G_XOR %1, %2
%4(s32) = G_AND %3, %0 %4(s32) = G_AND %3, %0
; CHECK: [[VREGR:%[0-9]+]]:gpr = BICrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
$r0 = COPY %4(s32) $r0 = COPY %4(s32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_bicri name: test_bicri
# CHECK-LABEL: name: test_bicri
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
- { id: 4, class: gprb } - { id: 4, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_bicri
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[BICri:%[0-9]+]]:gpr = BICri [[COPY]], 192, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[BICri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
; This test and the following ones are a bit contrived, since they use a ; This test and the following ones are a bit contrived, since they use a
; G_XOR that can be constant-folded. They exist mostly to validate the ; G_XOR that can be constant-folded. They exist mostly to validate the
; TableGen pattern that defines BICri. We also have a pattern for matching a ; TableGen pattern that defines BICri. We also have a pattern for matching a
; G_AND with a G_CONSTANT operand directly, which is the more common case, ; G_AND with a G_CONSTANT operand directly, which is the more common case,
; but that will be covered by different tests. ; but that will be covered by different tests.
%1(s32) = G_CONSTANT i32 192 %1(s32) = G_CONSTANT i32 192
%2(s32) = G_CONSTANT i32 -1 %2(s32) = G_CONSTANT i32 -1
%3(s32) = G_XOR %1, %2 %3(s32) = G_XOR %1, %2
%4(s32) = G_AND %0, %3 %4(s32) = G_AND %0, %3
; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, $noreg, $noreg
$r0 = COPY %4(s32) $r0 = COPY %4(s32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_bicri_commutative_xor name: test_bicri_commutative_xor
# CHECK-LABEL: name: test_bicri_commutative_xor
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
- { id: 4, class: gprb } - { id: 4, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_bicri_commutative_xor
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[BICri:%[0-9]+]]:gpr = BICri [[COPY]], 192, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[BICri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_CONSTANT i32 192 %1(s32) = G_CONSTANT i32 192
%2(s32) = G_CONSTANT i32 -1 %2(s32) = G_CONSTANT i32 -1
%3(s32) = G_XOR %2, %1 %3(s32) = G_XOR %2, %1
%4(s32) = G_AND %0, %3 %4(s32) = G_AND %0, %3
; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, $noreg, $noreg
$r0 = COPY %4(s32) $r0 = COPY %4(s32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_bicri_commutative_and name: test_bicri_commutative_and
# CHECK-LABEL: name: test_bicri_commutative_and
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
- { id: 4, class: gprb } - { id: 4, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_bicri_commutative_and
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[BICri:%[0-9]+]]:gpr = BICri [[COPY]], 192, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[BICri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_CONSTANT i32 192 %1(s32) = G_CONSTANT i32 192
%2(s32) = G_CONSTANT i32 -1 %2(s32) = G_CONSTANT i32 -1
%3(s32) = G_XOR %1, %2 %3(s32) = G_XOR %1, %2
%4(s32) = G_AND %3, %0 %4(s32) = G_AND %3, %0
; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, $noreg, $noreg
$r0 = COPY %4(s32) $r0 = COPY %4(s32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_bicri_commutative_both name: test_bicri_commutative_both
# CHECK-LABEL: name: test_bicri_commutative_both
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
- { id: 4, class: gprb } - { id: 4, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_bicri_commutative_both
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[BICri:%[0-9]+]]:gpr = BICri [[COPY]], 192, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[BICri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_CONSTANT i32 192 %1(s32) = G_CONSTANT i32 192
%2(s32) = G_CONSTANT i32 -1 %2(s32) = G_CONSTANT i32 -1
%3(s32) = G_XOR %2, %1 %3(s32) = G_XOR %2, %1
%4(s32) = G_AND %3, %0 %4(s32) = G_AND %3, %0
; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, $noreg, $noreg
$r0 = COPY %4(s32) $r0 = COPY %4(s32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_movti16_0xffff name: test_movti16_0xffff
# CHECK-LABEL: name: test_movti16_0xffff
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_movti16_0xffff
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[MOVTi16_:%[0-9]+]]:gprnopc = MOVTi16 [[COPY]], 65535, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[MOVTi16_]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000 %1(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
%2(s32) = G_OR %0, %1 %2(s32) = G_OR %0, %1
; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MOVTi16 [[VREGX]], 65535, 14, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_vnmuls name: test_vnmuls
# CHECK-LABEL: name: test_vnmuls
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: fprb } - { id: 2, class: fprb }
- { id: 3, class: fprb } - { id: 3, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: $s0, $s1 liveins: $s0, $s1
; CHECK-LABEL: name: test_vnmuls
; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
; CHECK: [[VNMULS:%[0-9]+]]:spr = VNMULS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
; CHECK: $s0 = COPY [[VNMULS]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0
%0(s32) = COPY $s0 %0(s32) = COPY $s0
%1(s32) = COPY $s1 %1(s32) = COPY $s1
; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY $s0
; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY $s1
%2(s32) = G_FMUL %0, %1 %2(s32) = G_FMUL %0, %1
%3(s32) = G_FNEG %2 %3(s32) = G_FNEG %2
; CHECK: [[VREGR:%[0-9]+]]:spr = VNMULS [[VREGX]], [[VREGY]], 14, $noreg
$s0 = COPY %3(s32) $s0 = COPY %3(s32)
; CHECK: $s0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $s0 BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0
... ...
--- ---
name: test_vnmuls_reassociate name: test_vnmuls_reassociate
# CHECK-LABEL: name: test_vnmuls_reassociate
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: fprb } - { id: 2, class: fprb }
- { id: 3, class: fprb } - { id: 3, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: $s0, $s1 liveins: $s0, $s1
; CHECK-LABEL: name: test_vnmuls_reassociate
; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
; CHECK: [[VNMULS:%[0-9]+]]:spr = VNMULS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
; CHECK: $s0 = COPY [[VNMULS]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0
%0(s32) = COPY $s0 %0(s32) = COPY $s0
%1(s32) = COPY $s1 %1(s32) = COPY $s1
; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY $s0
; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY $s1
%2(s32) = G_FNEG %0 %2(s32) = G_FNEG %0
%3(s32) = G_FMUL %1, %2 %3(s32) = G_FMUL %1, %2
; CHECK: [[VREGR:%[0-9]+]]:spr = VNMULS [[VREGX]], [[VREGY]], 14, $noreg
$s0 = COPY %3(s32) $s0 = COPY %3(s32)
; CHECK: $s0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $s0 BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0
... ...
--- ---
name: test_vnmuld name: test_vnmuld
# CHECK-LABEL: name: test_vnmuld
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: fprb } - { id: 2, class: fprb }
- { id: 3, class: fprb } - { id: 3, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: $d0, $d1 liveins: $d0, $d1
; CHECK-LABEL: name: test_vnmuld
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
; CHECK: [[VNMULD:%[0-9]+]]:dpr = VNMULD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
; CHECK: $d0 = COPY [[VNMULD]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0
%0(s64) = COPY $d0 %0(s64) = COPY $d0
%1(s64) = COPY $d1 %1(s64) = COPY $d1
; CHECK-DAG: [[VREGX:%[0-9]+]]:dpr = COPY $d0
; CHECK-DAG: [[VREGY:%[0-9]+]]:dpr = COPY $d1
%2(s64) = G_FMUL %0, %1 %2(s64) = G_FMUL %0, %1
%3(s64) = G_FNEG %2 %3(s64) = G_FNEG %2
; CHECK: [[VREGR:%[0-9]+]]:dpr = VNMULD [[VREGX]], [[VREGY]], 14, $noreg
$d0 = COPY %3(s64) $d0 = COPY %3(s64)
; CHECK: $d0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $d0 BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0
... ...
--- ---
name: test_vfnmas name: test_vfnmas
# CHECK-LABEL: name: test_vfnmas
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: fprb } - { id: 2, class: fprb }
- { id: 3, class: fprb } - { id: 3, class: fprb }
- { id: 4, class: fprb } - { id: 4, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: $s0, $s1, $s2 liveins: $s0, $s1, $s2
; CHECK-LABEL: name: test_vfnmas
; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
; CHECK: [[COPY2:%[0-9]+]]:spr = COPY $s2
; CHECK: [[VFNMAS:%[0-9]+]]:spr = VFNMAS [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
; CHECK: $s0 = COPY [[VFNMAS]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0
%0(s32) = COPY $s0 %0(s32) = COPY $s0
%1(s32) = COPY $s1 %1(s32) = COPY $s1
%2(s32) = COPY $s2 %2(s32) = COPY $s2
; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY $s0
; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY $s1
; CHECK-DAG: [[VREGZ:%[0-9]+]]:spr = COPY $s2
%3(s32) = G_FMA %0, %1, %2 %3(s32) = G_FMA %0, %1, %2
%4(s32) = G_FNEG %3 %4(s32) = G_FNEG %3
; CHECK: [[VREGR:%[0-9]+]]:spr = VFNMAS [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg
$s0 = COPY %4(s32) $s0 = COPY %4(s32)
; CHECK: $s0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $s0 BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0
... ...
--- ---
name: test_vfnmad name: test_vfnmad
# CHECK-LABEL: name: test_vfnmad
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: fprb } - { id: 2, class: fprb }
- { id: 3, class: fprb } - { id: 3, class: fprb }
- { id: 4, class: fprb } - { id: 4, class: fprb }
- { id: 5, class: fprb } - { id: 5, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: $d0, $d1, $d2 liveins: $d0, $d1, $d2
; CHECK-LABEL: name: test_vfnmad
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:dpr = COPY $d2
; CHECK: [[VFNMAD:%[0-9]+]]:dpr = VFNMAD [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
; CHECK: $d0 = COPY [[VFNMAD]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0
%0(s64) = COPY $d0 %0(s64) = COPY $d0
%1(s64) = COPY $d1 %1(s64) = COPY $d1
%2(s64) = COPY $d2 %2(s64) = COPY $d2
; CHECK-DAG: [[VREGX:%[0-9]+]]:dpr = COPY $d0
; CHECK-DAG: [[VREGY:%[0-9]+]]:dpr = COPY $d1
; CHECK-DAG: [[VREGZ:%[0-9]+]]:dpr = COPY $d2
%3(s64) = G_FNEG %0 %3(s64) = G_FNEG %0
%4(s64) = G_FNEG %2 %4(s64) = G_FNEG %2
%5(s64) = G_FMA %3, %1, %4 %5(s64) = G_FMA %3, %1, %4
; CHECK: [[VREGR:%[0-9]+]]:dpr = VFNMAD [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg
$d0 = COPY %5(s64) $d0 = COPY %5(s64)
; CHECK: $d0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $d0 BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0
... ...
--- ---
name: test_vfmss name: test_vfmss
# CHECK-LABEL: name: test_vfmss
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: fprb } - { id: 2, class: fprb }
- { id: 3, class: fprb } - { id: 3, class: fprb }
- { id: 4, class: fprb } - { id: 4, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: $s0, $s1, $s2 liveins: $s0, $s1, $s2
; CHECK-LABEL: name: test_vfmss
; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
; CHECK: [[COPY2:%[0-9]+]]:spr = COPY $s2
; CHECK: [[VFMSS:%[0-9]+]]:spr = VFMSS [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
; CHECK: $s0 = COPY [[VFMSS]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0
%0(s32) = COPY $s0 %0(s32) = COPY $s0
%1(s32) = COPY $s1 %1(s32) = COPY $s1
%2(s32) = COPY $s2 %2(s32) = COPY $s2
; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY $s0
; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY $s1
; CHECK-DAG: [[VREGZ:%[0-9]+]]:spr = COPY $s2
%3(s32) = G_FNEG %0 %3(s32) = G_FNEG %0
%4(s32) = G_FMA %3, %1, %2 %4(s32) = G_FMA %3, %1, %2
; CHECK: [[VREGR:%[0-9]+]]:spr = VFMSS [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg
$s0 = COPY %4(s32) $s0 = COPY %4(s32)
; CHECK: $s0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $s0 BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0
... ...
--- ---
name: test_vfmsd name: test_vfmsd
# CHECK-LABEL: name: test_vfmsd
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: fprb } - { id: 2, class: fprb }
- { id: 3, class: fprb } - { id: 3, class: fprb }
- { id: 4, class: fprb } - { id: 4, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: $d0, $d1, $d2 liveins: $d0, $d1, $d2
; CHECK-LABEL: name: test_vfmsd
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:dpr = COPY $d2
; CHECK: [[VFMSD:%[0-9]+]]:dpr = VFMSD [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
; CHECK: $d0 = COPY [[VFMSD]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0
%0(s64) = COPY $d0 %0(s64) = COPY $d0
%1(s64) = COPY $d1 %1(s64) = COPY $d1
%2(s64) = COPY $d2 %2(s64) = COPY $d2
; CHECK-DAG: [[VREGX:%[0-9]+]]:dpr = COPY $d0
; CHECK-DAG: [[VREGY:%[0-9]+]]:dpr = COPY $d1
; CHECK-DAG: [[VREGZ:%[0-9]+]]:dpr = COPY $d2
%3(s64) = G_FNEG %1 %3(s64) = G_FNEG %1
%4(s64) = G_FMA %0, %3, %2 %4(s64) = G_FMA %0, %3, %2
; CHECK: [[VREGR:%[0-9]+]]:dpr = VFMSD [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg
$d0 = COPY %4(s64) $d0 = COPY %4(s64)
; CHECK: $d0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $d0 BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0
... ...
--- ---
name: test_vfnmss name: test_vfnmss
# CHECK-LABEL: name: test_vfnmss
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: fprb } - { id: 2, class: fprb }
- { id: 3, class: fprb } - { id: 3, class: fprb }
- { id: 4, class: fprb } - { id: 4, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: $s0, $s1, $s2 liveins: $s0, $s1, $s2
; CHECK-LABEL: name: test_vfnmss
; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
; CHECK: [[COPY2:%[0-9]+]]:spr = COPY $s2
; CHECK: [[VFNMSS:%[0-9]+]]:spr = VFNMSS [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
; CHECK: $s0 = COPY [[VFNMSS]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0
%0(s32) = COPY $s0 %0(s32) = COPY $s0
%1(s32) = COPY $s1 %1(s32) = COPY $s1
%2(s32) = COPY $s2 %2(s32) = COPY $s2
; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY $s0
; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY $s1
; CHECK-DAG: [[VREGZ:%[0-9]+]]:spr = COPY $s2
%3(s32) = G_FNEG %2 %3(s32) = G_FNEG %2
%4(s32) = G_FMA %0, %1, %3 %4(s32) = G_FMA %0, %1, %3
; CHECK: [[VREGR:%[0-9]+]]:spr = VFNMSS [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg
$s0 = COPY %4(s32) $s0 = COPY %4(s32)
; CHECK: $s0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $s0 BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0
... ...
--- ---
name: test_bfc name: test_bfc
# CHECK-LABEL: name: test_bfc
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_bfc
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[BFC:%[0-9]+]]:gpr = BFC [[COPY]], -65529, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[BFC]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = G_CONSTANT i32 -65529 ; 0xFFFF0007 %1(s32) = G_CONSTANT i32 -65529 ; 0xFFFF0007
%2(s32) = G_AND %0, %1 %2(s32) = G_AND %0, %1
; CHECK: [[RS:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[RD:%[0-9]+]]:gpr = BFC [[RS]], -65529, 14, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[RD]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_no_bfc_bad_mask name: test_no_bfc_bad_mask
# CHECK-LABEL: name: test_no_bfc_bad_mask
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_no_bfc_bad_mask
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[COPY]], 6, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = G_CONSTANT i32 6 ; 0x00000006 %1(s32) = G_CONSTANT i32 6 ; 0x00000006
%2(s32) = G_AND %0, %1 %2(s32) = G_AND %0, %1
; CHECK: [[RS:%[0-9]+]]:gpr = COPY $r0
; CHECK-NOT: BFC
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[RD]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...

llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple arm-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -O0 -mtriple arm-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- | --- |
define void @test_trunc_and_zext_s1_to_s32() { ret void } define void @test_trunc_and_zext_s1_to_s32() { ret void }
define void @test_trunc_and_sext_s1_to_s32() { ret void } define void @test_trunc_and_sext_s1_to_s32() { ret void }
define void @test_trunc_and_sext_s8_to_s32() { ret void } define void @test_trunc_and_sext_s8_to_s32() { ret void }
define void @test_trunc_and_zext_s16_to_s32() { ret void } define void @test_trunc_and_zext_s16_to_s32() { ret void }
define void @test_trunc_and_anyext_s8_to_s32() { ret void } define void @test_trunc_and_anyext_s8_to_s32() { ret void }
define void @test_trunc_and_anyext_s16_to_s32() { ret void } define void @test_trunc_and_anyext_s16_to_s32() { ret void }
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines--- |
define void @test_phi_s32() { ret void } define void @test_phi_s32() { ret void }
attributes #0 = { "target-features"="+v6" } attributes #0 = { "target-features"="+v6" }
attributes #1 = { "target-features"="+hwdiv-arm" } attributes #1 = { "target-features"="+hwdiv-arm" }
attributes #2 = { "target-features"="+v6t2" } attributes #2 = { "target-features"="+v6t2" }
... ...
--- ---
name: test_trunc_and_zext_s1_to_s32 name: test_trunc_and_zext_s1_to_s32
# CHECK-LABEL: name: test_trunc_and_zext_s1_to_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_trunc_and_zext_s1_to_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[COPY]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
%1(s1) = G_TRUNC %0(s32) %1(s1) = G_TRUNC %0(s32)
%2(s32) = G_ZEXT %1(s1) %2(s32) = G_ZEXT %1(s1)
; CHECK: [[VREGEXT:%[0-9]+]]:gpr = ANDri [[VREG]], 1, 14, $noreg, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGEXT]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_trunc_and_sext_s1_to_s32 name: test_trunc_and_sext_s1_to_s32
# CHECK-LABEL: name: test_trunc_and_sext_s1_to_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_trunc_and_sext_s1_to_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[COPY]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[RSBri:%[0-9]+]]:gpr = RSBri [[ANDri]], 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[RSBri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
%1(s1) = G_TRUNC %0(s32) %1(s1) = G_TRUNC %0(s32)
%2(s32) = G_SEXT %1(s1) %2(s32) = G_SEXT %1(s1)
; CHECK: [[VREGAND:%[0-9]+]]:gpr = ANDri [[VREG]], 1, 14, $noreg, $noreg
; CHECK: [[VREGEXT:%[0-9]+]]:gpr = RSBri [[VREGAND]], 0, 14, $noreg, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGEXT]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_trunc_and_sext_s8_to_s32 name: test_trunc_and_sext_s8_to_s32
# CHECK-LABEL: name: test_trunc_and_sext_s8_to_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_trunc_and_sext_s8_to_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gprnopc = COPY [[COPY]]
; CHECK: [[SXTB:%[0-9]+]]:gprnopc = SXTB [[COPY1]], 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[SXTB]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
%1(s8) = G_TRUNC %0(s32) %1(s8) = G_TRUNC %0(s32)
; CHECK: [[VREGTRUNC:%[0-9]+]]:gprnopc = COPY [[VREG]]
%2(s32) = G_SEXT %1(s8) %2(s32) = G_SEXT %1(s8)
; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = SXTB [[VREGTRUNC]], 0, 14, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGEXT]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_trunc_and_zext_s16_to_s32 name: test_trunc_and_zext_s16_to_s32
# CHECK-LABEL: name: test_trunc_and_zext_s16_to_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_trunc_and_zext_s16_to_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gprnopc = COPY [[COPY]]
; CHECK: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[COPY1]], 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[UXTH]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
%1(s16) = G_TRUNC %0(s32) %1(s16) = G_TRUNC %0(s32)
; CHECK: [[VREGTRUNC:%[0-9]+]]:gprnopc = COPY [[VREG]]
%2(s32) = G_ZEXT %1(s16) %2(s32) = G_ZEXT %1(s16)
; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = UXTH [[VREGTRUNC]], 0, 14, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGEXT]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_trunc_and_anyext_s8_to_s32 name: test_trunc_and_anyext_s8_to_s32
# CHECK-LABEL: name: test_trunc_and_anyext_s8_to_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_trunc_and_anyext_s8_to_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: $r0 = COPY [[COPY]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
%1(s8) = G_TRUNC %0(s32) %1(s8) = G_TRUNC %0(s32)
%2(s32) = G_ANYEXT %1(s8) %2(s32) = G_ANYEXT %1(s8)
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREG]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_trunc_and_anyext_s16_to_s32 name: test_trunc_and_anyext_s16_to_s32
# CHECK-LABEL: name: test_trunc_and_anyext_s16_to_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_trunc_and_anyext_s16_to_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: $r0 = COPY [[COPY]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
%1(s16) = G_TRUNC %0(s32) %1(s16) = G_TRUNC %0(s32)
%2(s32) = G_ANYEXT %1(s16) %2(s32) = G_ANYEXT %1(s16)
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREG]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_trunc_and_zext_s1_to_s16 name: test_trunc_and_zext_s1_to_s16
# CHECK-LABEL: name: test_trunc_and_zext_s1_to_s16
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_trunc_and_zext_s1_to_s16
; CHECK: liveins: $r0, $r1
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[COPY1]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: STRH [[ANDri]], [[COPY]], $noreg, 0, 14 /* CC::al */, $noreg :: (store 2)
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0 %0(p0) = COPY $r0
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
%2(s1) = G_TRUNC %1(s32) %2(s1) = G_TRUNC %1(s32)
%3(s16) = G_ZEXT %2(s1) %3(s16) = G_ZEXT %2(s1)
; CHECK: [[VREGEXT:%[0-9]+]]:gpr = ANDri [[VREG]], 1, 14, $noreg, $noreg
G_STORE %3(s16), %0(p0) :: (store 2) G_STORE %3(s16), %0(p0) :: (store 2)
; CHECK: STRH [[VREGEXT]], [[PTR]], $noreg, 0, 14, $noreg :: (store 2)
BX_RET 14, $noreg BX_RET 14, $noreg
; CHECK: BX_RET 14, $noreg
... ...
--- ---
name: test_trunc_and_sext_s1_to_s16 name: test_trunc_and_sext_s1_to_s16
# CHECK-LABEL: name: test_trunc_and_sext_s1_to_s16
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_trunc_and_sext_s1_to_s16
; CHECK: liveins: $r0, $r1
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[COPY1]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[RSBri:%[0-9]+]]:gpr = RSBri [[ANDri]], 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: STRH [[RSBri]], [[COPY]], $noreg, 0, 14 /* CC::al */, $noreg :: (store 2)
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0 %0(p0) = COPY $r0
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
%2(s1) = G_TRUNC %1(s32) %2(s1) = G_TRUNC %1(s32)
%3(s16) = G_SEXT %2(s1) %3(s16) = G_SEXT %2(s1)
; CHECK: [[VREGAND:%[0-9]+]]:gpr = ANDri [[VREG]], 1, 14, $noreg, $noreg
; CHECK: [[VREGEXT:%[0-9]+]]:gpr = RSBri [[VREGAND]], 0, 14, $noreg, $noreg
G_STORE %3(s16), %0(p0) :: (store 2) G_STORE %3(s16), %0(p0) :: (store 2)
; CHECK: STRH [[VREGEXT]], [[PTR]], $noreg, 0, 14, $noreg :: (store 2)
BX_RET 14, $noreg BX_RET 14, $noreg
; CHECK: BX_RET 14, $noreg
... ...
--- ---
name: test_trunc_and_anyext_s1_to_s16 name: test_trunc_and_anyext_s1_to_s16
# CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s16
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s16
; CHECK: liveins: $r0, $r1
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: STRH [[COPY1]], [[COPY]], $noreg, 0, 14 /* CC::al */, $noreg :: (store 2)
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0 %0(p0) = COPY $r0
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
%2(s1) = G_TRUNC %1(s32) %2(s1) = G_TRUNC %1(s32)
%3(s16) = G_ANYEXT %2(s1) %3(s16) = G_ANYEXT %2(s1)
G_STORE %3(s16), %0(p0) :: (store 2) G_STORE %3(s16), %0(p0) :: (store 2)
; CHECK: STRH [[VREG]], [[PTR]], $noreg, 0, 14, $noreg :: (store 2)
BX_RET 14, $noreg BX_RET 14, $noreg
; CHECK: BX_RET 14, $noreg
... ...
--- ---
name: test_trunc_and_zext_s8_to_s16 name: test_trunc_and_zext_s8_to_s16
# CHECK-LABEL: name: test_trunc_and_zext_s8_to_s16
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_trunc_and_zext_s8_to_s16
; CHECK: liveins: $r0, $r1
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:gprnopc = COPY [[COPY1]]
; CHECK: [[UXTB:%[0-9]+]]:gprnopc = UXTB [[COPY2]], 0, 14 /* CC::al */, $noreg
; CHECK: STRH [[UXTB]], [[COPY]], $noreg, 0, 14 /* CC::al */, $noreg :: (store 2)
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0 %0(p0) = COPY $r0
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
%2(s8) = G_TRUNC %1(s32) %2(s8) = G_TRUNC %1(s32)
; CHECK: [[VREGTRUNC:%[0-9]+]]:gprnopc = COPY [[VREG]]
%3(s16) = G_ZEXT %2(s8) %3(s16) = G_ZEXT %2(s8)
; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = UXTB [[VREGTRUNC]], 0, 14, $noreg
G_STORE %3(s16), %0(p0) :: (store 2) G_STORE %3(s16), %0(p0) :: (store 2)
; CHECK: STRH [[VREGEXT]], [[PTR]], $noreg, 0, 14, $noreg :: (store 2)
BX_RET 14, $noreg BX_RET 14, $noreg
; CHECK: BX_RET 14, $noreg
... ...
--- ---
name: test_trunc_and_sext_s8_to_s16 name: test_trunc_and_sext_s8_to_s16
# CHECK-LABEL: name: test_trunc_and_sext_s8_to_s16
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_trunc_and_sext_s8_to_s16
; CHECK: liveins: $r0, $r1
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:gprnopc = COPY [[COPY1]]
; CHECK: [[SXTB:%[0-9]+]]:gprnopc = SXTB [[COPY2]], 0, 14 /* CC::al */, $noreg
; CHECK: STRH [[SXTB]], [[COPY]], $noreg, 0, 14 /* CC::al */, $noreg :: (store 2)
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0 %0(p0) = COPY $r0
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
%2(s8) = G_TRUNC %1(s32) %2(s8) = G_TRUNC %1(s32)
; CHECK: [[VREGTRUNC:%[0-9]+]]:gprnopc = COPY [[VREG]]
%3(s16) = G_SEXT %2(s8) %3(s16) = G_SEXT %2(s8)
; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = SXTB [[VREGTRUNC]], 0, 14, $noreg
G_STORE %3(s16), %0(p0) :: (store 2) G_STORE %3(s16), %0(p0) :: (store 2)
; CHECK: STRH [[VREGEXT]], [[PTR]], $noreg, 0, 14, $noreg :: (store 2)
BX_RET 14, $noreg BX_RET 14, $noreg
; CHECK: BX_RET 14, $noreg
... ...
--- ---
name: test_trunc_and_anyext_s8_to_s16 name: test_trunc_and_anyext_s8_to_s16
# CHECK-LABEL: name: test_trunc_and_anyext_s8_to_s16
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_trunc_and_anyext_s8_to_s16
; CHECK: liveins: $r0, $r1
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: STRH [[COPY1]], [[COPY]], $noreg, 0, 14 /* CC::al */, $noreg :: (store 2)
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0 %0(p0) = COPY $r0
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
%2(s8) = G_TRUNC %1(s32) %2(s8) = G_TRUNC %1(s32)
%3(s16) = G_ANYEXT %2(s8) %3(s16) = G_ANYEXT %2(s8)
G_STORE %3(s16), %0(p0) :: (store 2) G_STORE %3(s16), %0(p0) :: (store 2)
; CHECK: STRH [[VREG]], [[PTR]], $noreg, 0, 14, $noreg :: (store 2)
BX_RET 14, $noreg BX_RET 14, $noreg
; CHECK: BX_RET 14, $noreg
... ...
--- ---
name: test_trunc_and_zext_s1_to_s8 name: test_trunc_and_zext_s1_to_s8
# CHECK-LABEL: name: test_trunc_and_zext_s1_to_s8
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_trunc_and_zext_s1_to_s8
; CHECK: liveins: $r0, $r1
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[ANDri:%[0-9]+]]:gprnopc = ANDri [[COPY1]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: STRBi12 [[ANDri]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 1)
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0 %0(p0) = COPY $r0
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
%2(s1) = G_TRUNC %1(s32) %2(s1) = G_TRUNC %1(s32)
%3(s8) = G_ZEXT %2(s1) %3(s8) = G_ZEXT %2(s1)
; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = ANDri [[VREG]], 1, 14, $noreg, $noreg
G_STORE %3(s8), %0(p0) :: (store 1) G_STORE %3(s8), %0(p0) :: (store 1)
; CHECK: STRBi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 1)
BX_RET 14, $noreg BX_RET 14, $noreg
; CHECK: BX_RET 14, $noreg
... ...
--- ---
name: test_trunc_and_sext_s1_to_s8 name: test_trunc_and_sext_s1_to_s8
# CHECK-LABEL: name: test_trunc_and_sext_s1_to_s8
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_trunc_and_sext_s1_to_s8
; CHECK: liveins: $r0, $r1
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[COPY1]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[RSBri:%[0-9]+]]:gprnopc = RSBri [[ANDri]], 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: STRBi12 [[RSBri]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 1)
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0 %0(p0) = COPY $r0
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
%2(s1) = G_TRUNC %1(s32) %2(s1) = G_TRUNC %1(s32)
%3(s8) = G_SEXT %2(s1) %3(s8) = G_SEXT %2(s1)
; CHECK: [[VREGAND:%[0-9]+]]:gpr = ANDri [[VREG]], 1, 14, $noreg, $noreg
; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = RSBri [[VREGAND]], 0, 14, $noreg, $noreg
G_STORE %3(s8), %0(p0) :: (store 1) G_STORE %3(s8), %0(p0) :: (store 1)
; CHECK: STRBi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 1)
BX_RET 14, $noreg BX_RET 14, $noreg
; CHECK: BX_RET 14, $noreg
... ...
--- ---
name: test_trunc_and_anyext_s1_to_s8 name: test_trunc_and_anyext_s1_to_s8
# CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s8
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s8
; CHECK: liveins: $r0, $r1
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:gprnopc = COPY [[COPY1]]
; CHECK: STRBi12 [[COPY2]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 1)
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0 %0(p0) = COPY $r0
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
%2(s1) = G_TRUNC %1(s32) %2(s1) = G_TRUNC %1(s32)
%3(s8) = G_ANYEXT %2(s1) %3(s8) = G_ANYEXT %2(s1)
G_STORE %3(s8), %0(p0) :: (store 1) G_STORE %3(s8), %0(p0) :: (store 1)
; CHECK: [[RVREG:%[0-9]+]]:gprnopc = COPY [[VREG]]
; CHECK: STRBi12 [[RVREG]], [[PTR]], 0, 14, $noreg :: (store 1)
BX_RET 14, $noreg BX_RET 14, $noreg
; CHECK: BX_RET 14, $noreg
... ...
--- ---
name: test_add_s32 name: test_add_s32
# CHECK-LABEL: name: test_add_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_add_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[ADDrr:%[0-9]+]]:gpr = ADDrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ADDrr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
%2(s32) = G_ADD %0, %1 %2(s32) = G_ADD %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_add_fold_imm_s32 name: test_add_fold_imm_s32
# CHECK-LABEL: name: test_add_fold_imm_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_add_fold_imm_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[ADDri:%[0-9]+]]:gpr = ADDri [[COPY]], 255, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ADDri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_CONSTANT i32 255 %1(s32) = G_CONSTANT i32 255
%2(s32) = G_ADD %0, %1 %2(s32) = G_ADD %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDri [[VREGX]], 255, 14, $noreg, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_add_no_fold_imm_s32 name: test_add_no_fold_imm_s32
# CHECK-LABEL: name: test_add_no_fold_imm_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_add_no_fold_imm_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[MOVi16_:%[0-9]+]]:gpr = MOVi16 65535, 14 /* CC::al */, $noreg
; CHECK: [[ADDrr:%[0-9]+]]:gpr = ADDrr [[COPY]], [[MOVi16_]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ADDrr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_CONSTANT i32 65535 %1(s32) = G_CONSTANT i32 65535
; CHECK: [[VREGY:%[0-9]+]]:gpr = MOVi16 65535, 14, $noreg
%2(s32) = G_ADD %0, %1 %2(s32) = G_ADD %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_sub_s32 name: test_sub_s32
# CHECK-LABEL: name: test_sub_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_sub_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[SUBrr:%[0-9]+]]:gpr = SUBrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[SUBrr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
%2(s32) = G_SUB %0, %1 %2(s32) = G_SUB %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:gpr = SUBrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGRES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_sub_imm_s32 name: test_sub_imm_s32
# CHECK-LABEL: name: test_sub_imm_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_sub_imm_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[SUBri:%[0-9]+]]:gpr = SUBri [[COPY]], 17, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[SUBri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_CONSTANT i32 17 %1(s32) = G_CONSTANT i32 17
%2(s32) = G_SUB %0, %1 %2(s32) = G_SUB %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:gpr = SUBri [[VREGX]], 17, 14, $noreg, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGRES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_sub_rev_imm_s32 name: test_sub_rev_imm_s32
# CHECK-LABEL: name: test_sub_rev_imm_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_sub_rev_imm_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[RSBri:%[0-9]+]]:gpr = RSBri [[COPY]], 17, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[RSBri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_CONSTANT i32 17 %1(s32) = G_CONSTANT i32 17
%2(s32) = G_SUB %1, %0 %2(s32) = G_SUB %1, %0
; CHECK: [[VREGRES:%[0-9]+]]:gpr = RSBri [[VREGX]], 17, 14, $noreg, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGRES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_mul_s32 name: test_mul_s32
# CHECK-LABEL: name: test_mul_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_mul_s32
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gprnopc = COPY $r1
; CHECK: [[MUL:%[0-9]+]]:gprnopc = MUL [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[MUL]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
%2(s32) = G_MUL %0, %1 %2(s32) = G_MUL %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MUL [[VREGX]], [[VREGY]], 14, $noreg, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGRES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_mulv5_s32 name: test_mulv5_s32
# CHECK-LABEL: name: test_mulv5_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_mulv5_s32
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gprnopc = COPY $r1
; CHECK: early-clobber %2:gprnopc = MULv5 [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY %2
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
%2(s32) = G_MUL %0, %1 %2(s32) = G_MUL %0, %1
; CHECK: early-clobber [[VREGRES:%[0-9]+]]:gprnopc = MULv5 [[VREGX]], [[VREGY]], 14, $noreg, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGRES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_sdiv_s32 name: test_sdiv_s32
# CHECK-LABEL: name: test_sdiv_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_sdiv_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[SDIV:%[0-9]+]]:gpr = SDIV [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[SDIV]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
%2(s32) = G_SDIV %0, %1 %2(s32) = G_SDIV %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:gpr = SDIV [[VREGX]], [[VREGY]], 14, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGRES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_udiv_s32 name: test_udiv_s32
# CHECK-LABEL: name: test_udiv_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_udiv_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[UDIV:%[0-9]+]]:gpr = UDIV [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[UDIV]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
%2(s32) = G_UDIV %0, %1 %2(s32) = G_UDIV %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:gpr = UDIV [[VREGX]], [[VREGY]], 14, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGRES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_lshr_s32 name: test_lshr_s32
# CHECK-LABEL: name: test_lshr_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_lshr_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[MOVsr:%[0-9]+]]:gprnopc = MOVsr [[COPY]], [[COPY1]], 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[MOVsr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
%2(s32) = G_LSHR %0, %1 %2(s32) = G_LSHR %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 3, 14, $noreg, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGRES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_ashr_s32 name: test_ashr_s32
# CHECK-LABEL: name: test_ashr_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_ashr_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[MOVsr:%[0-9]+]]:gprnopc = MOVsr [[COPY]], [[COPY1]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[MOVsr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
%2(s32) = G_ASHR %0, %1 %2(s32) = G_ASHR %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 1, 14, $noreg, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGRES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_shl_s32 name: test_shl_s32
# CHECK-LABEL: name: test_shl_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_shl_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[MOVsr:%[0-9]+]]:gprnopc = MOVsr [[COPY]], [[COPY1]], 2, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[MOVsr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
%2(s32) = G_SHL %0, %1 %2(s32) = G_SHL %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 2, 14, $noreg, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGRES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_load_from_stack name: test_load_from_stack
# CHECK-LABEL: name: test_load_from_stack
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
- { id: 4, class: gprb } - { id: 4, class: gprb }
fixedStack: fixedStack:
- { id: 0, offset: 0, size: 1, alignment: 4, isImmutable: true, isAliased: false } - { id: 0, offset: 0, size: 1, alignment: 4, isImmutable: true, isAliased: false }
- { id: 1, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false } - { id: 1, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
- { id: 2, offset: 8, size: 4, alignment: 4, isImmutable: true, isAliased: false } - { id: 2, offset: 8, size: 4, alignment: 4, isImmutable: true, isAliased: false }
# CHECK-DAG: id: [[FI1:[0-9]+]], type: default, offset: 0, size: 1
# CHECK-DAG: id: [[FI32:[0-9]+]], type: default, offset: 8
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1, $r2, $r3 liveins: $r0, $r1, $r2, $r3
; CHECK-LABEL: name: test_load_from_stack
; CHECK: [[ADDri:%[0-9]+]]:gpr = ADDri %fixed-stack.0, 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[LDRi12_:%[0-9]+]]:gpr = LDRi12 [[ADDri]], 0, 14 /* CC::al */, $noreg :: (load 4)
; CHECK: $r0 = COPY [[LDRi12_]]
; CHECK: [[ADDri1:%[0-9]+]]:gpr = ADDri %fixed-stack.2, 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[LDRBi12_:%[0-9]+]]:gprnopc = LDRBi12 [[ADDri1]], 0, 14 /* CC::al */, $noreg :: (load 1)
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY [[LDRBi12_]]
; CHECK: $r0 = COPY [[COPY]]
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = G_FRAME_INDEX %fixed-stack.2 %0(p0) = G_FRAME_INDEX %fixed-stack.2
; CHECK: [[FI32VREG:%[0-9]+]]:gpr = ADDri %fixed-stack.[[FI32]], 0, 14, $noreg, $noreg
%1(s32) = G_LOAD %0(p0) :: (load 4) %1(s32) = G_LOAD %0(p0) :: (load 4)
; CHECK: [[LD32VREG:%[0-9]+]]:gpr = LDRi12 [[FI32VREG]], 0, 14, $noreg
$r0 = COPY %1 $r0 = COPY %1
; CHECK: $r0 = COPY [[LD32VREG]]
%2(p0) = G_FRAME_INDEX %fixed-stack.0 %2(p0) = G_FRAME_INDEX %fixed-stack.0
; CHECK: [[FI1VREG:%[0-9]+]]:gpr = ADDri %fixed-stack.[[FI1]], 0, 14, $noreg, $noreg
%3(s1) = G_LOAD %2(p0) :: (load 1) %3(s1) = G_LOAD %2(p0) :: (load 1)
; CHECK: [[LD1VREG:%[0-9]+]]:gprnopc = LDRBi12 [[FI1VREG]], 0, 14, $noreg
%4(s32) = G_ANYEXT %3(s1) %4(s32) = G_ANYEXT %3(s1)
; CHECK: [[RES:%[0-9]+]]:gpr = COPY [[LD1VREG]]
$r0 = COPY %4 $r0 = COPY %4
; CHECK: $r0 = COPY [[RES]]
BX_RET 14, $noreg BX_RET 14, $noreg
; CHECK: BX_RET 14, $noreg
... ...
--- ---
name: test_stores name: test_stores
# CHECK-LABEL: name: test_stores
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
- { id: 4, class: gprb } - { id: 4, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_stores
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:gprnopc = COPY [[COPY1]]
; CHECK: [[ANDri:%[0-9]+]]:gprnopc = ANDri [[COPY1]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: STRBi12 [[ANDri]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 1)
; CHECK: STRBi12 [[COPY2]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 1)
; CHECK: STRH [[COPY1]], [[COPY]], $noreg, 0, 14 /* CC::al */, $noreg :: (store 2)
; CHECK: STRi12 [[COPY1]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 4)
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0 %0(p0) = COPY $r0
; CHECK: [[P:%[0-9]+]]:gpr = COPY $r0
%3(s32) = COPY $r1 %3(s32) = COPY $r1
; CHECK: [[V32:%[0-9]+]]:gpr = COPY $r1
%4(s1) = G_TRUNC %3(s32) %4(s1) = G_TRUNC %3(s32)
%1(s8) = G_TRUNC %3(s32) %1(s8) = G_TRUNC %3(s32)
; CHECK: [[V8:%[0-9]+]]:gprnopc = COPY [[V32]]
%2(s16) = G_TRUNC %3(s32) %2(s16) = G_TRUNC %3(s32)
G_STORE %4(s1), %0(p0) :: (store 1) G_STORE %4(s1), %0(p0) :: (store 1)
; CHECK: [[V1:%[0-9]+]]:gprnopc = ANDri [[V32]], 1, 14, $noreg, $noreg
; CHECK: STRBi12 [[V1]], [[P]], 0, 14, $noreg
G_STORE %1(s8), %0(p0) :: (store 1) G_STORE %1(s8), %0(p0) :: (store 1)
; CHECK: STRBi12 [[V8]], [[P]], 0, 14, $noreg
G_STORE %2(s16), %0(p0) :: (store 2) G_STORE %2(s16), %0(p0) :: (store 2)
; CHECK: STRH [[V32]], [[P]], $noreg, 0, 14, $noreg
G_STORE %3(s32), %0(p0) :: (store 4) G_STORE %3(s32), %0(p0) :: (store 4)
; CHECK: STRi12 [[V32]], [[P]], 0, 14, $noreg
BX_RET 14, $noreg BX_RET 14, $noreg
... ...
--- ---
name: test_gep name: test_gep
# CHECK-LABEL: name: test_gep
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_gep
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[ADDrr:%[0-9]+]]:gpr = ADDrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ADDrr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(p0) = COPY $r0 %0(p0) = COPY $r0
; CHECK: %[[PTR:[0-9]+]]:gpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: %[[OFF:[0-9]+]]:gpr = COPY $r1
%2(p0) = G_PTR_ADD %0, %1(s32) %2(p0) = G_PTR_ADD %0, %1(s32)
; CHECK: %[[GEP:[0-9]+]]:gpr = ADDrr %[[PTR]], %[[OFF]], 14, $noreg, $noreg
$r0 = COPY %2(p0) $r0 = COPY %2(p0)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_MOVi32imm name: test_MOVi32imm
# CHECK-LABEL: name: test_MOVi32imm
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: test_MOVi32imm
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr = MOVi32imm 65537
; CHECK: $r0 = COPY [[MOVi32imm]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = G_CONSTANT i32 65537 %0(s32) = G_CONSTANT i32 65537
; CHECK: %[[C:[0-9]+]]:gpr = MOVi32imm 65537
$r0 = COPY %0(s32) $r0 = COPY %0(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_constant_imm name: test_constant_imm
# CHECK-LABEL: name: test_constant_imm
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: test_constant_imm
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 42, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[MOVi]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = G_CONSTANT i32 42 %0(s32) = G_CONSTANT i32 42
; CHECK: %[[C:[0-9]+]]:gpr = MOVi 42, 14, $noreg, $noreg
$r0 = COPY %0(s32) $r0 = COPY %0(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_constant_cimm name: test_constant_cimm
# CHECK-LABEL: name: test_constant_cimm
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
body: | body: |
bb.0: bb.0:
; Adding a type on G_CONSTANT changes its operand from an Imm into a CImm. ; Adding a type on G_CONSTANT changes its operand from an Imm into a CImm.
; We still want to see the same thing in the output though. ; We still want to see the same thing in the output though.
; CHECK-LABEL: name: test_constant_cimm
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 42, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[MOVi]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = G_CONSTANT i32 42 %0(s32) = G_CONSTANT i32 42
; CHECK: %[[C:[0-9]+]]:gpr = MOVi 42, 14, $noreg, $noreg
$r0 = COPY %0(s32) $r0 = COPY %0(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_pointer_constant_unconstrained name: test_pointer_constant_unconstrained
# CHECK-LABEL: name: test_pointer_constant_unconstrained
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: test_pointer_constant_unconstrained
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[MOVi]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(p0) = G_CONSTANT i32 0 %0(p0) = G_CONSTANT i32 0
; CHECK: %[[C:[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
; This leaves %0 unconstrained before the G_CONSTANT is selected. ; This leaves %0 unconstrained before the G_CONSTANT is selected.
$r0 = COPY %0(p0) $r0 = COPY %0(p0)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_pointer_constant_constrained name: test_pointer_constant_constrained
# CHECK-LABEL: name: test_pointer_constant_constrained
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: test_pointer_constant_constrained
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: STRi12 [[MOVi]], [[MOVi]], 0, 14 /* CC::al */, $noreg :: (store 4)
%0(p0) = G_CONSTANT i32 0 %0(p0) = G_CONSTANT i32 0
; CHECK: %[[C:[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
; This constrains %0 before the G_CONSTANT is selected. ; This constrains %0 before the G_CONSTANT is selected.
G_STORE %0(p0), %0(p0) :: (store 4) G_STORE %0(p0), %0(p0) :: (store 4)
... ...
--- ---
name: test_inttoptr_s32 name: test_inttoptr_s32
# CHECK-LABEL: name: test_inttoptr_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_inttoptr_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: $r0 = COPY [[COPY]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(p0) = G_INTTOPTR %0(s32) %1(p0) = G_INTTOPTR %0(s32)
; CHECK: [[INT:%[0-9]+]]:gpr = COPY $r0
$r0 = COPY %1(p0) $r0 = COPY %1(p0)
; CHECK: $r0 = COPY [[INT]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_ptrtoint_s32 name: test_ptrtoint_s32
# CHECK-LABEL: name: test_ptrtoint_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_ptrtoint_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: $r0 = COPY [[COPY]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(p0) = COPY $r0 %0(p0) = COPY $r0
%1(s32) = G_PTRTOINT %0(p0) %1(s32) = G_PTRTOINT %0(p0)
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
$r0 = COPY %1(s32) $r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[PTR]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_select_s32 name: test_select_s32
# CHECK-LABEL: name: test_select_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_select_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: TSTri [[COPY1]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[MOVCCr:%[0-9]+]]:gpr = MOVCCr [[COPY]], [[COPY1]], 0 /* CC::eq */, $cpsr
; CHECK: $r0 = COPY [[MOVCCr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
%2(s1) = G_TRUNC %1(s32) %2(s1) = G_TRUNC %1(s32)
%3(s32) = G_SELECT %2(s1), %0, %1 %3(s32) = G_SELECT %2(s1), %0, %1
; CHECK: TSTri [[VREGY]], 1, 14, $noreg, implicit-def $cpsr
; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, $cpsr
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
; CHECK: $r0 = COPY [[RES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_select_ptr name: test_select_ptr
# CHECK-LABEL: name: test_select_ptr
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
- { id: 4, class: gprb } - { id: 4, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1, $r2 liveins: $r0, $r1, $r2
; CHECK-LABEL: name: test_select_ptr
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:gpr = COPY $r2
; CHECK: TSTri [[COPY2]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[MOVCCr:%[0-9]+]]:gpr = MOVCCr [[COPY]], [[COPY1]], 0 /* CC::eq */, $cpsr
; CHECK: $r0 = COPY [[MOVCCr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(p0) = COPY $r0 %0(p0) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(p0) = COPY $r1 %1(p0) = COPY $r1
; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
%2(s32) = COPY $r2 %2(s32) = COPY $r2
; CHECK: [[VREGC:%[0-9]+]]:gpr = COPY $r2
%3(s1) = G_TRUNC %2(s32) %3(s1) = G_TRUNC %2(s32)
%4(p0) = G_SELECT %3(s1), %0, %1 %4(p0) = G_SELECT %3(s1), %0, %1
; CHECK: TSTri [[VREGC]], 1, 14, $noreg, implicit-def $cpsr
; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, $cpsr
$r0 = COPY %4(p0) $r0 = COPY %4(p0)
; CHECK: $r0 = COPY [[RES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_br name: test_br
# CHECK-LABEL: name: test_br
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
body: | body: |
; CHECK-LABEL: name: test_br
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: TSTri [[COPY]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: Bcc %bb.1, 1 /* CC::ne */, $cpsr
; CHECK: B %bb.2
; CHECK: bb.1:
; CHECK: successors: %bb.2(0x80000000)
; CHECK: B %bb.2
; CHECK: bb.2:
; CHECK: BX_RET 14 /* CC::al */, $noreg
bb.0: bb.0:
; CHECK: bb.0
successors: %bb.1(0x40000000), %bb.2(0x40000000) successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $r0 liveins: $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[COND32:%[0-9]+]]:gpr = COPY $r0
%1(s1) = G_TRUNC %0(s32) %1(s1) = G_TRUNC %0(s32)
G_BRCOND %1(s1), %bb.1 G_BRCOND %1(s1), %bb.1
; CHECK: TSTri [[COND32]], 1, 14, $noreg, implicit-def $cpsr
; CHECK: Bcc %bb.1, 1, $cpsr
G_BR %bb.2 G_BR %bb.2
; CHECK: B %bb.2
bb.1: bb.1:
; CHECK: bb.1
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
G_BR %bb.2 G_BR %bb.2
; CHECK: B %bb.2
bb.2: bb.2:
; CHECK: bb.2
BX_RET 14, $noreg BX_RET 14, $noreg
; CHECK: BX_RET 14, $noreg
... ...
--- ---
name: test_phi_s32 name: test_phi_s32
# CHECK-LABEL: name: test_phi_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
- { id: 4, class: gprb } - { id: 4, class: gprb }
body: | body: |
; CHECK-LABEL: name: test_phi_s32
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK: liveins: $r0, $r1, $r2
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:gpr = COPY $r2
; CHECK: TSTri [[COPY]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: Bcc %bb.1, 1 /* CC::ne */, $cpsr
; CHECK: B %bb.2
; CHECK: bb.1:
; CHECK: successors: %bb.2(0x80000000)
; CHECK: B %bb.2
; CHECK: bb.2:
; CHECK: [[PHI:%[0-9]+]]:gpr = PHI [[COPY1]], %bb.0, [[COPY2]], %bb.1
; CHECK: $r0 = COPY [[PHI]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
bb.0: bb.0:
; CHECK: [[BB1:bb.0]]:
successors: %bb.1(0x40000000), %bb.2(0x40000000) successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $r0, $r1, $r2 liveins: $r0, $r1, $r2
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s1) = G_TRUNC %0(s32) %1(s1) = G_TRUNC %0(s32)
%2(s32) = COPY $r1 %2(s32) = COPY $r1
%3(s32) = COPY $r2 %3(s32) = COPY $r2
; CHECK: [[V1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[V2:%[0-9]+]]:gpr = COPY $r2
G_BRCOND %1(s1), %bb.1 G_BRCOND %1(s1), %bb.1
G_BR %bb.2 G_BR %bb.2
bb.1: bb.1:
; CHECK: [[BB2:bb.1]]:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
G_BR %bb.2 G_BR %bb.2
; CHECK: B %bb.2
bb.2: bb.2:
; CHECK: bb.2
%4(s32) = G_PHI %2(s32), %bb.0, %3(s32), %bb.1 %4(s32) = G_PHI %2(s32), %bb.0, %3(s32), %bb.1
; CHECK: {{%[0-9]+}}:gpr = PHI [[V1]], %[[BB1]], [[V2]], %[[BB2]]
$r0 = COPY %4(s32) $r0 = COPY %4(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...

llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll

; RUN: llc -mtriple arm-unknown -mattr=+vfp2,+v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=LITTLE ; RUN: llc -mtriple arm-unknown -mattr=+vfp2,+v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=LITTLE
; RUN: llc -mtriple armeb-unknown -mattr=+vfp2,+v4t -global-isel -global-isel-abort=0 -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=BIG ; RUN: llc -mtriple armeb-unknown -mattr=+vfp2,+v4t -global-isel -global-isel-abort=0 -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=BIG
define void @test_void_return() { define void @test_void_return() {
; CHECK-LABEL: name: test_void_return ; CHECK-LABEL: name: test_void_return
; CHECK: BX_RET 14, $noreg ; CHECK: BX_RET 14 /* CC::al */, $noreg
entry: entry:
ret void ret void
} }
define signext i1 @test_add_i1(i1 %x, i1 %y) { define signext i1 @test_add_i1(i1 %x, i1 %y) {
; CHECK-LABEL: name: test_add_i1 ; CHECK-LABEL: name: test_add_i1
; CHECK: liveins: $r0, $r1 ; CHECK: liveins: $r0, $r1
; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s1) = G_TRUNC [[VREGR0]] ; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s1) = G_TRUNC [[VREGR0]]
; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s1) = G_TRUNC [[VREGR1]] ; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s1) = G_TRUNC [[VREGR1]]
; CHECK: [[SUM:%[0-9]+]]:_(s1) = G_ADD [[VREGX]], [[VREGY]] ; CHECK: [[SUM:%[0-9]+]]:_(s1) = G_ADD [[VREGX]], [[VREGY]]
; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_SEXT [[SUM]] ; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_SEXT [[SUM]]
; CHECK: $r0 = COPY [[EXT]](s32) ; CHECK: $r0 = COPY [[EXT]](s32)
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry: entry:
%sum = add i1 %x, %y %sum = add i1 %x, %y
ret i1 %sum ret i1 %sum
} }
define i8 @test_add_i8(i8 %x, i8 %y) { define i8 @test_add_i8(i8 %x, i8 %y) {
; CHECK-LABEL: name: test_add_i8 ; CHECK-LABEL: name: test_add_i8
; CHECK: liveins: $r0, $r1 ; CHECK: liveins: $r0, $r1
; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR0]] ; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR0]]
; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR1]] ; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR1]]
; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGX]], [[VREGY]] ; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGX]], [[VREGY]]
; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]] ; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
; CHECK: $r0 = COPY [[SUM_EXT]](s32) ; CHECK: $r0 = COPY [[SUM_EXT]](s32)
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry: entry:
%sum = add i8 %x, %y %sum = add i8 %x, %y
ret i8 %sum ret i8 %sum
} }
define i8 @test_sub_i8(i8 %x, i8 %y) { define i8 @test_sub_i8(i8 %x, i8 %y) {
; CHECK-LABEL: name: test_sub_i8 ; CHECK-LABEL: name: test_sub_i8
; CHECK: liveins: $r0, $r1 ; CHECK: liveins: $r0, $r1
; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR0]] ; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR0]]
; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR1]] ; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR1]]
; CHECK: [[RES:%[0-9]+]]:_(s8) = G_SUB [[VREGX]], [[VREGY]] ; CHECK: [[RES:%[0-9]+]]:_(s8) = G_SUB [[VREGX]], [[VREGY]]
; CHECK: [[RES_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]] ; CHECK: [[RES_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]]
; CHECK: $r0 = COPY [[RES_EXT]](s32) ; CHECK: $r0 = COPY [[RES_EXT]](s32)
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry: entry:
%res = sub i8 %x, %y %res = sub i8 %x, %y
ret i8 %res ret i8 %res
} }
define signext i8 @test_return_sext_i8(i8 %x) { define signext i8 @test_return_sext_i8(i8 %x) {
; CHECK-LABEL: name: test_return_sext_i8 ; CHECK-LABEL: name: test_return_sext_i8
; CHECK: liveins: $r0 ; CHECK: liveins: $r0
; CHECK: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK: [[VREG:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR0]] ; CHECK: [[VREG:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR0]]
; CHECK: [[VREGEXT:%[0-9]+]]:_(s32) = G_SEXT [[VREG]] ; CHECK: [[VREGEXT:%[0-9]+]]:_(s32) = G_SEXT [[VREG]]
; CHECK: $r0 = COPY [[VREGEXT]](s32) ; CHECK: $r0 = COPY [[VREGEXT]](s32)
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry: entry:
ret i8 %x ret i8 %x
} }
define i16 @test_add_i16(i16 %x, i16 %y) { define i16 @test_add_i16(i16 %x, i16 %y) {
; CHECK-LABEL: name: test_add_i16 ; CHECK-LABEL: name: test_add_i16
; CHECK: liveins: $r0, $r1 ; CHECK: liveins: $r0, $r1
; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR0]] ; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR0]]
; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR1]] ; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR1]]
; CHECK: [[SUM:%[0-9]+]]:_(s16) = G_ADD [[VREGX]], [[VREGY]] ; CHECK: [[SUM:%[0-9]+]]:_(s16) = G_ADD [[VREGX]], [[VREGY]]
; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]] ; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
; CHECK: $r0 = COPY [[SUM_EXT]](s32) ; CHECK: $r0 = COPY [[SUM_EXT]](s32)
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry: entry:
%sum = add i16 %x, %y %sum = add i16 %x, %y
ret i16 %sum ret i16 %sum
} }
define i16 @test_sub_i16(i16 %x, i16 %y) { define i16 @test_sub_i16(i16 %x, i16 %y) {
; CHECK-LABEL: name: test_sub_i16 ; CHECK-LABEL: name: test_sub_i16
; CHECK: liveins: $r0, $r1 ; CHECK: liveins: $r0, $r1
; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR0]] ; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR0]]
; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR1]] ; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR1]]
; CHECK: [[RES:%[0-9]+]]:_(s16) = G_SUB [[VREGX]], [[VREGY]] ; CHECK: [[RES:%[0-9]+]]:_(s16) = G_SUB [[VREGX]], [[VREGY]]
; CHECK: [[RES_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]] ; CHECK: [[RES_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]]
; CHECK: $r0 = COPY [[RES_EXT]](s32) ; CHECK: $r0 = COPY [[RES_EXT]](s32)
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry: entry:
%res = sub i16 %x, %y %res = sub i16 %x, %y
ret i16 %res ret i16 %res
} }
define zeroext i16 @test_return_zext_i16(i16 %x) { define zeroext i16 @test_return_zext_i16(i16 %x) {
; CHECK-LABEL: name: test_return_zext_i16 ; CHECK-LABEL: name: test_return_zext_i16
; CHECK: liveins: $r0 ; CHECK: liveins: $r0
; CHECK: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK: [[VREG:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR0]] ; CHECK: [[VREG:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR0]]
; CHECK: [[VREGEXT:%[0-9]+]]:_(s32) = G_ZEXT [[VREG]] ; CHECK: [[VREGEXT:%[0-9]+]]:_(s32) = G_ZEXT [[VREG]]
; CHECK: $r0 = COPY [[VREGEXT]](s32) ; CHECK: $r0 = COPY [[VREGEXT]](s32)
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry: entry:
ret i16 %x ret i16 %x
} }
define i32 @test_add_i32(i32 %x, i32 %y) { define i32 @test_add_i32(i32 %x, i32 %y) {
; CHECK-LABEL: name: test_add_i32 ; CHECK-LABEL: name: test_add_i32
; CHECK: liveins: $r0, $r1 ; CHECK: liveins: $r0, $r1
; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: [[SUM:%[0-9]+]]:_(s32) = G_ADD [[VREGX]], [[VREGY]] ; CHECK: [[SUM:%[0-9]+]]:_(s32) = G_ADD [[VREGX]], [[VREGY]]
; CHECK: $r0 = COPY [[SUM]](s32) ; CHECK: $r0 = COPY [[SUM]](s32)
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry: entry:
%sum = add i32 %x, %y %sum = add i32 %x, %y
ret i32 %sum ret i32 %sum
} }
define i32 @test_sub_i32(i32 %x, i32 %y) { define i32 @test_sub_i32(i32 %x, i32 %y) {
; CHECK-LABEL: name: test_sub_i32 ; CHECK-LABEL: name: test_sub_i32
; CHECK: liveins: $r0, $r1 ; CHECK: liveins: $r0, $r1
; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SUB [[VREGX]], [[VREGY]] ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SUB [[VREGX]], [[VREGY]]
; CHECK: $r0 = COPY [[RES]](s32) ; CHECK: $r0 = COPY [[RES]](s32)
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry: entry:
%res = sub i32 %x, %y %res = sub i32 %x, %y
ret i32 %res ret i32 %res
} }
define i32 @test_stack_args(i32 %p0, i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5) { define i32 @test_stack_args(i32 %p0, i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5) {
; CHECK-LABEL: name: test_stack_args ; CHECK-LABEL: name: test_stack_args
; CHECK: fixedStack: ; CHECK: fixedStack:
; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 4 ; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 4
; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 4 ; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 4
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: [[VREGP2:%[0-9]+]]:_(s32) = COPY $r2 ; CHECK: [[VREGP2:%[0-9]+]]:_(s32) = COPY $r2
; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]] ; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
; CHECK: [[VREGP5:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]]{{.*}}load 4 ; CHECK: [[VREGP5:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]]{{.*}}load 4
; CHECK: [[SUM:%[0-9]+]]:_(s32) = G_ADD [[VREGP2]], [[VREGP5]] ; CHECK: [[SUM:%[0-9]+]]:_(s32) = G_ADD [[VREGP2]], [[VREGP5]]
; CHECK: $r0 = COPY [[SUM]] ; CHECK: $r0 = COPY [[SUM]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry: entry:
%sum = add i32 %p2, %p5 %sum = add i32 %p2, %p5
ret i32 %sum ret i32 %sum
} }
define i16 @test_stack_args_signext(i32 %p0, i16 %p1, i8 %p2, i1 %p3, define i16 @test_stack_args_signext(i32 %p0, i16 %p1, i8 %p2, i1 %p3,
i8 signext %p4, i16 signext %p5) { i8 signext %p4, i16 signext %p5) {
; CHECK-LABEL: name: test_stack_args_signext ; CHECK-LABEL: name: test_stack_args_signext
; CHECK: fixedStack: ; CHECK: fixedStack:
; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 1 ; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 1
; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 2 ; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 2
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: [[VREGP1:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR1]] ; CHECK: [[VREGP1:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR1]]
; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]] ; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
; CHECK: [[VREGP5EXT:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]](p0){{.*}}load 4 ; CHECK: [[VREGP5EXT:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]](p0){{.*}}load 4
; CHECK: [[VREGP5:%[0-9]+]]:_(s16) = G_TRUNC [[VREGP5EXT]] ; CHECK: [[VREGP5:%[0-9]+]]:_(s16) = G_TRUNC [[VREGP5EXT]]
; CHECK: [[SUM:%[0-9]+]]:_(s16) = G_ADD [[VREGP1]], [[VREGP5]] ; CHECK: [[SUM:%[0-9]+]]:_(s16) = G_ADD [[VREGP1]], [[VREGP5]]
; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]] ; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
; CHECK: $r0 = COPY [[SUM_EXT]](s32) ; CHECK: $r0 = COPY [[SUM_EXT]](s32)
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry: entry:
%sum = add i16 %p1, %p5 %sum = add i16 %p1, %p5
ret i16 %sum ret i16 %sum
} }
define i8 @test_stack_args_zeroext(i32 %p0, i16 %p1, i8 %p2, i1 %p3, define i8 @test_stack_args_zeroext(i32 %p0, i16 %p1, i8 %p2, i1 %p3,
i8 zeroext %p4, i16 zeroext %p5) { i8 zeroext %p4, i16 zeroext %p5) {
; CHECK-LABEL: name: test_stack_args_zeroext ; CHECK-LABEL: name: test_stack_args_zeroext
; CHECK: fixedStack: ; CHECK: fixedStack:
; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 1 ; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 1
; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 2 ; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 2
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: [[VREGR2:%[0-9]+]]:_(s32) = COPY $r2 ; CHECK: [[VREGR2:%[0-9]+]]:_(s32) = COPY $r2
; CHECK: [[VREGP2:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR2]] ; CHECK: [[VREGP2:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR2]]
; CHECK: [[FIP4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P4]] ; CHECK: [[FIP4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P4]]
; CHECK: [[VREGP4EXT:%[0-9]+]]:_(s32) = G_LOAD [[FIP4]](p0){{.*}}load 4 ; CHECK: [[VREGP4EXT:%[0-9]+]]:_(s32) = G_LOAD [[FIP4]](p0){{.*}}load 4
; CHECK: [[VREGP4:%[0-9]+]]:_(s8) = G_TRUNC [[VREGP4EXT]] ; CHECK: [[VREGP4:%[0-9]+]]:_(s8) = G_TRUNC [[VREGP4EXT]]
; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGP2]], [[VREGP4]] ; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGP2]], [[VREGP4]]
; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]] ; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
; CHECK: $r0 = COPY [[SUM_EXT]](s32) ; CHECK: $r0 = COPY [[SUM_EXT]](s32)
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry: entry:
%sum = add i8 %p2, %p4 %sum = add i8 %p2, %p4
ret i8 %sum ret i8 %sum
} }
define i8 @test_stack_args_noext(i32 %p0, i16 %p1, i8 %p2, i1 %p3, define i8 @test_stack_args_noext(i32 %p0, i16 %p1, i8 %p2, i1 %p3,
i8 %p4, i16 %p5) { i8 %p4, i16 %p5) {
; CHECK-LABEL: name: test_stack_args_noext ; CHECK-LABEL: name: test_stack_args_noext
; CHECK: fixedStack: ; CHECK: fixedStack:
; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 1 ; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 1
; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 2 ; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 2
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: [[VREGR2:%[0-9]+]]:_(s32) = COPY $r2 ; CHECK: [[VREGR2:%[0-9]+]]:_(s32) = COPY $r2
; CHECK: [[VREGP2:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR2]] ; CHECK: [[VREGP2:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR2]]
; CHECK: [[FIP4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P4]] ; CHECK: [[FIP4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P4]]
; CHECK: [[VREGP4:%[0-9]+]]:_(s8) = G_LOAD [[FIP4]](p0){{.*}}load 1 ; CHECK: [[VREGP4:%[0-9]+]]:_(s8) = G_LOAD [[FIP4]](p0){{.*}}load 1
; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGP2]], [[VREGP4]] ; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGP2]], [[VREGP4]]
; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]] ; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
; CHECK: $r0 = COPY [[SUM_EXT]](s32) ; CHECK: $r0 = COPY [[SUM_EXT]](s32)
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry: entry:
%sum = add i8 %p2, %p4 %sum = add i8 %p2, %p4
ret i8 %sum ret i8 %sum
} }
define zeroext i16 @test_stack_args_extend_the_extended(i32 %p0, i16 %p1, i8 %p2, i1 %p3, define zeroext i16 @test_stack_args_extend_the_extended(i32 %p0, i16 %p1, i8 %p2, i1 %p3,
i8 signext %p4, i16 signext %p5) { i8 signext %p4, i16 signext %p5) {
; CHECK-LABEL: name: test_stack_args_extend_the_extended ; CHECK-LABEL: name: test_stack_args_extend_the_extended
; CHECK: fixedStack: ; CHECK: fixedStack:
; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 1 ; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 1
; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 2 ; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 2
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]] ; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
; CHECK: [[VREGP5SEXT:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]](p0){{.*}}load 4 ; CHECK: [[VREGP5SEXT:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]](p0){{.*}}load 4
; CHECK: [[VREGP5:%[0-9]+]]:_(s16) = G_TRUNC [[VREGP5SEXT]] ; CHECK: [[VREGP5:%[0-9]+]]:_(s16) = G_TRUNC [[VREGP5SEXT]]
; CHECK: [[VREGP5ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[VREGP5]] ; CHECK: [[VREGP5ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[VREGP5]]
; CHECK: $r0 = COPY [[VREGP5ZEXT]] ; CHECK: $r0 = COPY [[VREGP5ZEXT]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry: entry:
ret i16 %p5 ret i16 %p5
} }
define i16 @test_ptr_arg(i16* %p) { define i16 @test_ptr_arg(i16* %p) {
; CHECK-LABEL: name: test_ptr_arg ; CHECK-LABEL: name: test_ptr_arg
; CHECK: liveins: $r0 ; CHECK: liveins: $r0
; CHECK: [[VREGP:%[0-9]+]]:_(p0) = COPY $r0 ; CHECK: [[VREGP:%[0-9]+]]:_(p0) = COPY $r0
; CHECK: [[VREGV:%[0-9]+]]:_(s16) = G_LOAD [[VREGP]](p0){{.*}}load 2 ; CHECK: [[VREGV:%[0-9]+]]:_(s16) = G_LOAD [[VREGP]](p0){{.*}}load 2
entry: entry:
%v = load i16, i16* %p %v = load i16, i16* %p
ret i16 %v ret i16 %v
} }
define i32* @test_ptr_ret(i32** %p) { define i32* @test_ptr_ret(i32** %p) {
; Test pointer returns and pointer-to-pointer arguments ; Test pointer returns and pointer-to-pointer arguments
; CHECK-LABEL: name: test_ptr_ret ; CHECK-LABEL: name: test_ptr_ret
; CHECK: liveins: $r0 ; CHECK: liveins: $r0
; CHECK: [[VREGP:%[0-9]+]]:_(p0) = COPY $r0 ; CHECK: [[VREGP:%[0-9]+]]:_(p0) = COPY $r0
; CHECK: [[VREGV:%[0-9]+]]:_(p0) = G_LOAD [[VREGP]](p0){{.*}}load 4 ; CHECK: [[VREGV:%[0-9]+]]:_(p0) = G_LOAD [[VREGP]](p0){{.*}}load 4
; CHECK: $r0 = COPY [[VREGV]] ; CHECK: $r0 = COPY [[VREGV]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry: entry:
%v = load i32*, i32** %p %v = load i32*, i32** %p
ret i32* %v ret i32* %v
} }
define i32 @test_ptr_arg_on_stack(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32* %p) { define i32 @test_ptr_arg_on_stack(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32* %p) {
; CHECK-LABEL: name: test_ptr_arg_on_stack ; CHECK-LABEL: name: test_ptr_arg_on_stack
; CHECK: fixedStack: ; CHECK: fixedStack:
; CHECK: id: [[P:[0-9]+]]{{.*}}offset: 0{{.*}}size: 4 ; CHECK: id: [[P:[0-9]+]]{{.*}}offset: 0{{.*}}size: 4
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: [[FIP:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P]] ; CHECK: [[FIP:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P]]
; CHECK: [[VREGP:%[0-9]+]]:_(p0) = G_LOAD [[FIP]](p0){{.*}}load 4 ; CHECK: [[VREGP:%[0-9]+]]:_(p0) = G_LOAD [[FIP]](p0){{.*}}load 4
; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_LOAD [[VREGP]](p0){{.*}}load 4 ; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_LOAD [[VREGP]](p0){{.*}}load 4
; CHECK: $r0 = COPY [[VREGV]] ; CHECK: $r0 = COPY [[VREGV]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry: entry:
%v = load i32, i32* %p %v = load i32, i32* %p
ret i32 %v ret i32 %v
} }
define arm_aapcscc float @test_float_aapcscc(float %p0, float %p1, float %p2, define arm_aapcscc float @test_float_aapcscc(float %p0, float %p1, float %p2,
float %p3, float %p4, float %p5) { float %p3, float %p4, float %p5) {
; CHECK-LABEL: name: test_float_aapcscc ; CHECK-LABEL: name: test_float_aapcscc
; CHECK: fixedStack: ; CHECK: fixedStack:
; CHECK-DAG: id: [[P4:[0-9]+]]{{.*}}offset: 0{{.*}}size: 4 ; CHECK-DAG: id: [[P4:[0-9]+]]{{.*}}offset: 0{{.*}}size: 4
; CHECK-DAG: id: [[P5:[0-9]+]]{{.*}}offset: 4{{.*}}size: 4 ; CHECK-DAG: id: [[P5:[0-9]+]]{{.*}}offset: 4{{.*}}size: 4
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: [[VREGP1:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK: [[VREGP1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]] ; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
; CHECK: [[VREGP5:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]](p0){{.*}}load 4 ; CHECK: [[VREGP5:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]](p0){{.*}}load 4
; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_FADD [[VREGP1]], [[VREGP5]] ; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_FADD [[VREGP1]], [[VREGP5]]
; CHECK: $r0 = COPY [[VREGV]] ; CHECK: $r0 = COPY [[VREGV]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry: entry:
%v = fadd float %p1, %p5 %v = fadd float %p1, %p5
ret float %v ret float %v
} }
define arm_aapcs_vfpcc float @test_float_vfpcc(float %p0, float %p1, float %p2, define arm_aapcs_vfpcc float @test_float_vfpcc(float %p0, float %p1, float %p2,
float %p3, float %p4, float %p5, float %p3, float %p4, float %p5,
float %ridiculous, float %ridiculous,
Show All 12 Lines
; CHECK-DAG: id: [[Q0:[0-9]+]]{{.*}}offset: 0{{.*}}size: 4 ; CHECK-DAG: id: [[Q0:[0-9]+]]{{.*}}offset: 0{{.*}}size: 4
; CHECK-DAG: id: [[Q1:[0-9]+]]{{.*}}offset: 4{{.*}}size: 4 ; CHECK-DAG: id: [[Q1:[0-9]+]]{{.*}}offset: 4{{.*}}size: 4
; CHECK: liveins: $s0, $s1, $s2, $s3, $s4, $s5, $s6, $s7, $s8, $s9, $s10, $s11, $s12, $s13, $s14, $s15 ; CHECK: liveins: $s0, $s1, $s2, $s3, $s4, $s5, $s6, $s7, $s8, $s9, $s10, $s11, $s12, $s13, $s14, $s15
; CHECK: [[VREGP1:%[0-9]+]]:_(s32) = COPY $s1 ; CHECK: [[VREGP1:%[0-9]+]]:_(s32) = COPY $s1
; CHECK: [[FIQ1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Q1]] ; CHECK: [[FIQ1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Q1]]
; CHECK: [[VREGQ1:%[0-9]+]]:_(s32) = G_LOAD [[FIQ1]](p0){{.*}}load 4 ; CHECK: [[VREGQ1:%[0-9]+]]:_(s32) = G_LOAD [[FIQ1]](p0){{.*}}load 4
; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_FADD [[VREGP1]], [[VREGQ1]] ; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_FADD [[VREGP1]], [[VREGQ1]]
; CHECK: $s0 = COPY [[VREGV]] ; CHECK: $s0 = COPY [[VREGV]]
; CHECK: BX_RET 14, $noreg, implicit $s0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0
entry: entry:
%v = fadd float %p1, %q1 %v = fadd float %p1, %q1
ret float %v ret float %v
} }
define arm_aapcs_vfpcc double @test_double_vfpcc(double %p0, double %p1, double %p2, define arm_aapcs_vfpcc double @test_double_vfpcc(double %p0, double %p1, double %p2,
double %p3, double %p4, double %p5, double %p3, double %p4, double %p5,
double %reasonable, double %reasonable,
double %parameters, double %parameters,
double %q0, double %q1) { double %q0, double %q1) {
; CHECK-LABEL: name: test_double_vfpcc ; CHECK-LABEL: name: test_double_vfpcc
; CHECK: fixedStack: ; CHECK: fixedStack:
; CHECK-DAG: id: [[Q0:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8 ; CHECK-DAG: id: [[Q0:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8
; CHECK-DAG: id: [[Q1:[0-9]+]]{{.*}}offset: 8{{.*}}size: 8 ; CHECK-DAG: id: [[Q1:[0-9]+]]{{.*}}offset: 8{{.*}}size: 8
; CHECK: liveins: $d0, $d1, $d2, $d3, $d4, $d5, $d6, $d7 ; CHECK: liveins: $d0, $d1, $d2, $d3, $d4, $d5, $d6, $d7
; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = COPY $d1 ; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = COPY $d1
; CHECK: [[FIQ1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Q1]] ; CHECK: [[FIQ1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Q1]]
; CHECK: [[VREGQ1:%[0-9]+]]:_(s64) = G_LOAD [[FIQ1]](p0){{.*}}load 8 ; CHECK: [[VREGQ1:%[0-9]+]]:_(s64) = G_LOAD [[FIQ1]](p0){{.*}}load 8
; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGQ1]] ; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGQ1]]
; CHECK: $d0 = COPY [[VREGV]] ; CHECK: $d0 = COPY [[VREGV]]
; CHECK: BX_RET 14, $noreg, implicit $d0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0
entry: entry:
%v = fadd double %p1, %q1 %v = fadd double %p1, %q1
ret double %v ret double %v
} }
define arm_aapcscc double @test_double_aapcscc(double %p0, double %p1, double %p2, define arm_aapcscc double @test_double_aapcscc(double %p0, double %p1, double %p2,
double %p3, double %p4, double %p5) { double %p3, double %p4, double %p5) {
; CHECK-LABEL: name: test_double_aapcscc ; CHECK-LABEL: name: test_double_aapcscc
Show All 9 Lines
; BIG: [[VREGP1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP1HI]](s32), [[VREGP1LO]](s32) ; BIG: [[VREGP1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP1HI]](s32), [[VREGP1LO]](s32)
; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]] ; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
; CHECK: [[VREGP5:%[0-9]+]]:_(s64) = G_LOAD [[FIP5]](p0){{.*}}load 8 ; CHECK: [[VREGP5:%[0-9]+]]:_(s64) = G_LOAD [[FIP5]](p0){{.*}}load 8
; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGP5]] ; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGP5]]
; LITTLE: [[VREGVLO:%[0-9]+]]:_(s32), [[VREGVHI:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64) ; LITTLE: [[VREGVLO:%[0-9]+]]:_(s32), [[VREGVHI:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64) ; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
; CHECK-DAG: $r0 = COPY [[VREGVLO]] ; CHECK-DAG: $r0 = COPY [[VREGVLO]]
; CHECK-DAG: $r1 = COPY [[VREGVHI]] ; CHECK-DAG: $r1 = COPY [[VREGVHI]]
; CHECK: BX_RET 14, $noreg, implicit $r0, implicit $r1 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
entry: entry:
%v = fadd double %p1, %p5 %v = fadd double %p1, %p5
ret double %v ret double %v
} }
define arm_aapcs_vfpcc double @test_double_gap_vfpcc(double %p0, float %filler, define arm_aapcs_vfpcc double @test_double_gap_vfpcc(double %p0, float %filler,
double %p1, double %p2, double %p1, double %p2,
double %p3, double %p4, double %p3, double %p4,
double %reasonable, double %reasonable,
double %parameters, double %parameters,
double %q0, double %q1) { double %q0, double %q1) {
; CHECK-LABEL: name: test_double_gap_vfpcc ; CHECK-LABEL: name: test_double_gap_vfpcc
; CHECK: fixedStack: ; CHECK: fixedStack:
; CHECK-DAG: id: [[Q0:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8 ; CHECK-DAG: id: [[Q0:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8
; CHECK-DAG: id: [[Q1:[0-9]+]]{{.*}}offset: 8{{.*}}size: 8 ; CHECK-DAG: id: [[Q1:[0-9]+]]{{.*}}offset: 8{{.*}}size: 8
; CHECK: liveins: $d0, $d2, $d3, $d4, $d5, $d6, $d7, $s2 ; CHECK: liveins: $d0, $d2, $d3, $d4, $d5, $d6, $d7, $s2
; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = COPY $d2 ; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = COPY $d2
; CHECK: [[FIQ1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Q1]] ; CHECK: [[FIQ1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Q1]]
; CHECK: [[VREGQ1:%[0-9]+]]:_(s64) = G_LOAD [[FIQ1]](p0){{.*}}load 8 ; CHECK: [[VREGQ1:%[0-9]+]]:_(s64) = G_LOAD [[FIQ1]](p0){{.*}}load 8
; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGQ1]] ; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGQ1]]
; CHECK: $d0 = COPY [[VREGV]] ; CHECK: $d0 = COPY [[VREGV]]
; CHECK: BX_RET 14, $noreg, implicit $d0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0
entry: entry:
%v = fadd double %p1, %q1 %v = fadd double %p1, %q1
ret double %v ret double %v
} }
define arm_aapcscc double @test_double_gap_aapcscc(float %filler, double %p0, define arm_aapcscc double @test_double_gap_aapcscc(float %filler, double %p0,
double %p1) { double %p1) {
; CHECK-LABEL: name: test_double_gap_aapcscc ; CHECK-LABEL: name: test_double_gap_aapcscc
; CHECK: fixedStack: ; CHECK: fixedStack:
; CHECK-DAG: id: [[P1:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8 ; CHECK-DAG: id: [[P1:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8
; CHECK: liveins: $r0, $r2, $r3 ; CHECK: liveins: $r0, $r2, $r3
; CHECK-DAG: [[VREGP0LO:%[0-9]+]]:_(s32) = COPY $r2 ; CHECK-DAG: [[VREGP0LO:%[0-9]+]]:_(s32) = COPY $r2
; CHECK-DAG: [[VREGP0HI:%[0-9]+]]:_(s32) = COPY $r3 ; CHECK-DAG: [[VREGP0HI:%[0-9]+]]:_(s32) = COPY $r3
; LITTLE: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0LO]](s32), [[VREGP0HI]](s32) ; LITTLE: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0LO]](s32), [[VREGP0HI]](s32)
; BIG: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0HI]](s32), [[VREGP0LO]](s32) ; BIG: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0HI]](s32), [[VREGP0LO]](s32)
; CHECK: [[FIP1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P1]] ; CHECK: [[FIP1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P1]]
; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = G_LOAD [[FIP1]](p0){{.*}}load 8 ; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = G_LOAD [[FIP1]](p0){{.*}}load 8
; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP0]], [[VREGP1]] ; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP0]], [[VREGP1]]
; LITTLE: [[VREGVLO:%[0-9]+]]:_(s32), [[VREGVHI:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64) ; LITTLE: [[VREGVLO:%[0-9]+]]:_(s32), [[VREGVHI:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64) ; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
; CHECK-DAG: $r0 = COPY [[VREGVLO]] ; CHECK-DAG: $r0 = COPY [[VREGVLO]]
; CHECK-DAG: $r1 = COPY [[VREGVHI]] ; CHECK-DAG: $r1 = COPY [[VREGVHI]]
; CHECK: BX_RET 14, $noreg, implicit $r0, implicit $r1 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
entry: entry:
%v = fadd double %p0, %p1 %v = fadd double %p0, %p1
ret double %v ret double %v
} }
define arm_aapcscc double @test_double_gap2_aapcscc(double %p0, float %filler, define arm_aapcscc double @test_double_gap2_aapcscc(double %p0, float %filler,
double %p1) { double %p1) {
; CHECK-LABEL: name: test_double_gap2_aapcscc ; CHECK-LABEL: name: test_double_gap2_aapcscc
; CHECK: fixedStack: ; CHECK: fixedStack:
; CHECK-DAG: id: [[P1:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8 ; CHECK-DAG: id: [[P1:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK-DAG: [[VREGP0LO:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK-DAG: [[VREGP0LO:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[VREGP0HI:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK-DAG: [[VREGP0HI:%[0-9]+]]:_(s32) = COPY $r1
; LITTLE: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0LO]](s32), [[VREGP0HI]](s32) ; LITTLE: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0LO]](s32), [[VREGP0HI]](s32)
; BIG: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0HI]](s32), [[VREGP0LO]](s32) ; BIG: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0HI]](s32), [[VREGP0LO]](s32)
; CHECK: [[FIP1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P1]] ; CHECK: [[FIP1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P1]]
; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = G_LOAD [[FIP1]](p0){{.*}}load 8 ; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = G_LOAD [[FIP1]](p0){{.*}}load 8
; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP0]], [[VREGP1]] ; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP0]], [[VREGP1]]
; LITTLE: [[VREGVLO:%[0-9]+]]:_(s32), [[VREGVHI:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64) ; LITTLE: [[VREGVLO:%[0-9]+]]:_(s32), [[VREGVHI:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64) ; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
; CHECK-DAG: $r0 = COPY [[VREGVLO]] ; CHECK-DAG: $r0 = COPY [[VREGVLO]]
; CHECK-DAG: $r1 = COPY [[VREGVHI]] ; CHECK-DAG: $r1 = COPY [[VREGVHI]]
; CHECK: BX_RET 14, $noreg, implicit $r0, implicit $r1 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
entry: entry:
%v = fadd double %p0, %p1 %v = fadd double %p0, %p1
ret double %v ret double %v
} }
define i32 @test_shufflevector_s32_v2s32(i32 %arg) { define i32 @test_shufflevector_s32_v2s32(i32 %arg) {
; CHECK-LABEL: name: test_shufflevector_s32_v2s32 ; CHECK-LABEL: name: test_shufflevector_s32_v2s32
; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $r0
▲ Show 20 Lines • Show All 129 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines bb.0:
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; HWDIV: [[R:%[0-9]+]]:_(s32) = G_SDIV [[X]], [[Y]] ; HWDIV: [[R:%[0-9]+]]:_(s32) = G_SDIV [[X]], [[Y]]
; SOFT-NOT: G_SDIV ; SOFT-NOT: G_SDIV
; SOFT: ADJCALLSTACKDOWN ; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X]] ; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-DAG: $r1 = COPY [[Y]] ; SOFT-DAG: $r1 = COPY [[Y]]
; ARM-AEABI: BL &__aeabi_idiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; ARM-AEABI: BL &__aeabi_idiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; THUMB-AEABI: tBL 14, $noreg, &__aeabi_idiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; THUMB-AEABI: tBL 14 /* CC::al */, $noreg, &__aeabi_idiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; ARM-DEFAULT: BL &__divsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; ARM-DEFAULT: BL &__divsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; THUMB-DEFAULT: tBL 14, $noreg, &__divsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; THUMB-DEFAULT: tBL 14 /* CC::al */, $noreg, &__divsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0 ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SDIV ; SOFT-NOT: G_SDIV
%2(s32) = G_SDIV %0, %1 %2(s32) = G_SDIV %0, %1
; CHECK: $r0 = COPY [[R]] ; CHECK: $r0 = COPY [[R]]
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_udiv_i32 name: test_udiv_i32
# CHECK-LABEL: name: test_udiv_i32 # CHECK-LABEL: name: test_udiv_i32
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 11 Lines bb.0:
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; HWDIV: [[R:%[0-9]+]]:_(s32) = G_UDIV [[X]], [[Y]] ; HWDIV: [[R:%[0-9]+]]:_(s32) = G_UDIV [[X]], [[Y]]
; SOFT-NOT: G_UDIV ; SOFT-NOT: G_UDIV
; SOFT: ADJCALLSTACKDOWN ; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X]] ; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-DAG: $r1 = COPY [[Y]] ; SOFT-DAG: $r1 = COPY [[Y]]
; ARM-AEABI: BL &__aeabi_uidiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; ARM-AEABI: BL &__aeabi_uidiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; THUMB-AEABI: tBL 14, $noreg, &__aeabi_uidiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; THUMB-AEABI: tBL 14 /* CC::al */, $noreg, &__aeabi_uidiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; ARM-DEFAULT: BL &__udivsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; ARM-DEFAULT: BL &__udivsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; THUMB-DEFAULT: tBL 14, $noreg, &__udivsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; THUMB-DEFAULT: tBL 14 /* CC::al */, $noreg, &__udivsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0 ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UDIV ; SOFT-NOT: G_UDIV
%2(s32) = G_UDIV %0, %1 %2(s32) = G_UDIV %0, %1
; CHECK: $r0 = COPY [[R]] ; CHECK: $r0 = COPY [[R]]
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_sdiv_i16 name: test_sdiv_i16
# CHECK-LABEL: name: test_sdiv_i16 # CHECK-LABEL: name: test_sdiv_i16
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 25 Lines bb.0:
%2(s32) = COPY $r1 %2(s32) = COPY $r1
%3(s16) = G_TRUNC %2(s32) %3(s16) = G_TRUNC %2(s32)
; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]] ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]]
; SOFT-NOT: G_SDIV ; SOFT-NOT: G_SDIV
; SOFT: ADJCALLSTACKDOWN ; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X32]] ; SOFT-DAG: $r0 = COPY [[X32]]
; SOFT-DAG: $r1 = COPY [[Y32]] ; SOFT-DAG: $r1 = COPY [[Y32]]
; ARM-AEABI: BL &__aeabi_idiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; ARM-AEABI: BL &__aeabi_idiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; THUMB-AEABI: tBL 14, $noreg, &__aeabi_idiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; THUMB-AEABI: tBL 14 /* CC::al */, $noreg, &__aeabi_idiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; ARM-DEFAULT: BL &__divsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; ARM-DEFAULT: BL &__divsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; THUMB-DEFAULT: tBL 14, $noreg, &__divsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; THUMB-DEFAULT: tBL 14 /* CC::al */, $noreg, &__divsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT: [[R32:%[0-9]+]]:_(s32) = COPY $r0 ; SOFT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SDIV ; SOFT-NOT: G_SDIV
; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR ; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR
; SOFT-NOT: G_SDIV ; SOFT-NOT: G_SDIV
%4(s16) = G_SDIV %1, %3 %4(s16) = G_SDIV %1, %3
; CHECK: $r0 = COPY [[R]] ; CHECK: $r0 = COPY [[R]]
%5(s32) = G_SEXT %4(s16) %5(s32) = G_SEXT %4(s16)
$r0 = COPY %5(s32) $r0 = COPY %5(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_udiv_i16 name: test_udiv_i16
# CHECK-LABEL: name: test_udiv_i16 # CHECK-LABEL: name: test_udiv_i16
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 23 Lines bb.0:
%2(s32) = COPY $r1 %2(s32) = COPY $r1
%3(s16) = G_TRUNC %2(s32) %3(s16) = G_TRUNC %2(s32)
; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]] ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]]
; SOFT-NOT: G_UDIV ; SOFT-NOT: G_UDIV
; SOFT: ADJCALLSTACKDOWN ; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X32]] ; SOFT-DAG: $r0 = COPY [[X32]]
; SOFT-DAG: $r1 = COPY [[Y32]] ; SOFT-DAG: $r1 = COPY [[Y32]]
; ARM-AEABI: BL &__aeabi_uidiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; ARM-AEABI: BL &__aeabi_uidiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; THUMB-AEABI: tBL 14, $noreg, &__aeabi_uidiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; THUMB-AEABI: tBL 14 /* CC::al */, $noreg, &__aeabi_uidiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; ARM-DEFAULT: BL &__udivsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; ARM-DEFAULT: BL &__udivsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; THUMB-DEFAULT: tBL 14, $noreg, &__udivsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; THUMB-DEFAULT: tBL 14 /* CC::al */, $noreg, &__udivsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT: [[R32:%[0-9]+]]:_(s32) = COPY $r0 ; SOFT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UDIV ; SOFT-NOT: G_UDIV
; CHECK: [[R:%[0-9]+]]:_(s32) = G_AND ; CHECK: [[R:%[0-9]+]]:_(s32) = G_AND
; SOFT-NOT: G_UDIV ; SOFT-NOT: G_UDIV
%4(s16) = G_UDIV %1, %3 %4(s16) = G_UDIV %1, %3
; CHECK: $r0 = COPY [[R]] ; CHECK: $r0 = COPY [[R]]
%5(s32) = G_ZEXT %4(s16) %5(s32) = G_ZEXT %4(s16)
$r0 = COPY %5(s32) $r0 = COPY %5(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_sdiv_i8 name: test_sdiv_i8
# CHECK-LABEL: name: test_sdiv_i8 # CHECK-LABEL: name: test_sdiv_i8
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 25 Lines bb.0:
%2(s32) = COPY $r1 %2(s32) = COPY $r1
%3(s8) = G_TRUNC %2(s32) %3(s8) = G_TRUNC %2(s32)
; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]] ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]]
; SOFT-NOT: G_SDIV ; SOFT-NOT: G_SDIV
; SOFT: ADJCALLSTACKDOWN ; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X32]] ; SOFT-DAG: $r0 = COPY [[X32]]
; SOFT-DAG: $r1 = COPY [[Y32]] ; SOFT-DAG: $r1 = COPY [[Y32]]
; ARM-AEABI: BL &__aeabi_idiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; ARM-AEABI: BL &__aeabi_idiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; THUMB-AEABI: tBL 14, $noreg, &__aeabi_idiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; THUMB-AEABI: tBL 14 /* CC::al */, $noreg, &__aeabi_idiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; ARM-DEFAULT: BL &__divsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; ARM-DEFAULT: BL &__divsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; THUMB-DEFAULT: tBL 14, $noreg, &__divsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; THUMB-DEFAULT: tBL 14 /* CC::al */, $noreg, &__divsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT: [[R32:%[0-9]+]]:_(s32) = COPY $r0 ; SOFT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SDIV ; SOFT-NOT: G_SDIV
; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR ; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR
; SOFT-NOT: G_SDIV ; SOFT-NOT: G_SDIV
%4(s8) = G_SDIV %1, %3 %4(s8) = G_SDIV %1, %3
; CHECK: $r0 = COPY [[R]] ; CHECK: $r0 = COPY [[R]]
%5(s32) = G_SEXT %4(s8) %5(s32) = G_SEXT %4(s8)
$r0 = COPY %5(s32) $r0 = COPY %5(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_udiv_i8 name: test_udiv_i8
# CHECK-LABEL: name: test_udiv_i8 # CHECK-LABEL: name: test_udiv_i8
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 23 Lines bb.0:
%2(s32) = COPY $r1 %2(s32) = COPY $r1
%3(s8) = G_TRUNC %2(s32) %3(s8) = G_TRUNC %2(s32)
; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]] ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]]
; SOFT-NOT: G_UDIV ; SOFT-NOT: G_UDIV
; SOFT: ADJCALLSTACKDOWN ; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X32]] ; SOFT-DAG: $r0 = COPY [[X32]]
; SOFT-DAG: $r1 = COPY [[Y32]] ; SOFT-DAG: $r1 = COPY [[Y32]]
; ARM-AEABI: BL &__aeabi_uidiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; ARM-AEABI: BL &__aeabi_uidiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; THUMB-AEABI: tBL 14, $noreg, &__aeabi_uidiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; THUMB-AEABI: tBL 14 /* CC::al */, $noreg, &__aeabi_uidiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; ARM-DEFAULT: BL &__udivsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; ARM-DEFAULT: BL &__udivsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; THUMB-DEFAULT: tBL 14, $noreg, &__udivsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; THUMB-DEFAULT: tBL 14 /* CC::al */, $noreg, &__udivsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT: [[R32:%[0-9]+]]:_(s32) = COPY $r0 ; SOFT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UDIV ; SOFT-NOT: G_UDIV
; CHECK: [[R:%[0-9]+]]:_(s32) = G_AND ; CHECK: [[R:%[0-9]+]]:_(s32) = G_AND
; SOFT-NOT: G_UDIV ; SOFT-NOT: G_UDIV
%4(s8) = G_UDIV %1, %3 %4(s8) = G_UDIV %1, %3
; CHECK: $r0 = COPY [[R]] ; CHECK: $r0 = COPY [[R]]
%5(s32) = G_ZEXT %4(s8) %5(s32) = G_ZEXT %4(s8)
$r0 = COPY %5(s32) $r0 = COPY %5(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_srem_i32 name: test_srem_i32
# CHECK-LABEL: name: test_srem_i32 # CHECK-LABEL: name: test_srem_i32
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 13 Lines bb.0:
; HWDIV: [[Q:%[0-9]+]]:_(s32) = G_SDIV [[X]], [[Y]] ; HWDIV: [[Q:%[0-9]+]]:_(s32) = G_SDIV [[X]], [[Y]]
; HWDIV: [[P:%[0-9]+]]:_(s32) = G_MUL [[Q]], [[Y]] ; HWDIV: [[P:%[0-9]+]]:_(s32) = G_MUL [[Q]], [[Y]]
; HWDIV: [[R:%[0-9]+]]:_(s32) = G_SUB [[X]], [[P]] ; HWDIV: [[R:%[0-9]+]]:_(s32) = G_SUB [[X]], [[P]]
; SOFT-NOT: G_SREM ; SOFT-NOT: G_SREM
; SOFT: ADJCALLSTACKDOWN ; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X]] ; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-DAG: $r1 = COPY [[Y]] ; SOFT-DAG: $r1 = COPY [[Y]]
; ARM-AEABI: BL &__aeabi_idivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1 ; ARM-AEABI: BL &__aeabi_idivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1
; THUMB-AEABI: tBL 14, $noreg, &__aeabi_idivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1 ; THUMB-AEABI: tBL 14 /* CC::al */, $noreg, &__aeabi_idivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1
; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY $r1 ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY $r1
; ARM-DEFAULT: BL &__modsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; ARM-DEFAULT: BL &__modsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; THUMB-DEFAULT: tBL 14, $noreg, &__modsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; THUMB-DEFAULT: tBL 14 /* CC::al */, $noreg, &__modsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY $r0 ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SREM ; SOFT-NOT: G_SREM
%2(s32) = G_SREM %0, %1 %2(s32) = G_SREM %0, %1
; CHECK: $r0 = COPY [[R]] ; CHECK: $r0 = COPY [[R]]
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_urem_i32 name: test_urem_i32
# CHECK-LABEL: name: test_urem_i32 # CHECK-LABEL: name: test_urem_i32
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 13 Lines bb.0:
; HWDIV: [[Q:%[0-9]+]]:_(s32) = G_UDIV [[X]], [[Y]] ; HWDIV: [[Q:%[0-9]+]]:_(s32) = G_UDIV [[X]], [[Y]]
; HWDIV: [[P:%[0-9]+]]:_(s32) = G_MUL [[Q]], [[Y]] ; HWDIV: [[P:%[0-9]+]]:_(s32) = G_MUL [[Q]], [[Y]]
; HWDIV: [[R:%[0-9]+]]:_(s32) = G_SUB [[X]], [[P]] ; HWDIV: [[R:%[0-9]+]]:_(s32) = G_SUB [[X]], [[P]]
; SOFT-NOT: G_UREM ; SOFT-NOT: G_UREM
; SOFT: ADJCALLSTACKDOWN ; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X]] ; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-DAG: $r1 = COPY [[Y]] ; SOFT-DAG: $r1 = COPY [[Y]]
; ARM-AEABI: BL &__aeabi_uidivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1 ; ARM-AEABI: BL &__aeabi_uidivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1
; THUMB-AEABI: tBL 14, $noreg, &__aeabi_uidivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1 ; THUMB-AEABI: tBL 14 /* CC::al */, $noreg, &__aeabi_uidivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1
; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY $r1 ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY $r1
; ARM-DEFAULT: BL &__umodsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; ARM-DEFAULT: BL &__umodsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; THUMB-DEFAULT: tBL 14, $noreg, &__umodsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; THUMB-DEFAULT: tBL 14 /* CC::al */, $noreg, &__umodsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY $r0 ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UREM ; SOFT-NOT: G_UREM
%2(s32) = G_UREM %0, %1 %2(s32) = G_UREM %0, %1
; CHECK: $r0 = COPY [[R]] ; CHECK: $r0 = COPY [[R]]
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_srem_i16 name: test_srem_i16
# CHECK-LABEL: name: test_srem_i16 # CHECK-LABEL: name: test_srem_i16
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 27 Lines bb.0:
; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]] ; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]]
; HWDIV: [[P32:%[0-9]+]]:_(s32) = G_MUL [[Q32]], [[Y32]] ; HWDIV: [[P32:%[0-9]+]]:_(s32) = G_MUL [[Q32]], [[Y32]]
; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SUB [[X32]], [[P32]] ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SUB [[X32]], [[P32]]
; SOFT-NOT: G_SREM ; SOFT-NOT: G_SREM
; SOFT: ADJCALLSTACKDOWN ; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X32]] ; SOFT-DAG: $r0 = COPY [[X32]]
; SOFT-DAG: $r1 = COPY [[Y32]] ; SOFT-DAG: $r1 = COPY [[Y32]]
; ARM-AEABI: BL &__aeabi_idivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; ARM-AEABI: BL &__aeabi_idivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; THUMB-AEABI: tBL 14, $noreg, &__aeabi_idivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; THUMB-AEABI: tBL 14 /* CC::al */, $noreg, &__aeabi_idivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r1 ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r1
; ARM-DEFAULT: BL &__modsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; ARM-DEFAULT: BL &__modsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; THUMB-DEFAULT: tBL 14, $noreg, &__modsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; THUMB-DEFAULT: tBL 14 /* CC::al */, $noreg, &__modsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0 ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SREM ; SOFT-NOT: G_SREM
; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR ; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR
; SOFT-NOT: G_SREM ; SOFT-NOT: G_SREM
%4(s16) = G_SREM %1, %3 %4(s16) = G_SREM %1, %3
; CHECK: $r0 = COPY [[R]] ; CHECK: $r0 = COPY [[R]]
%5(s32) = G_SEXT %4(s16) %5(s32) = G_SEXT %4(s16)
$r0 = COPY %5(s32) $r0 = COPY %5(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_urem_i16 name: test_urem_i16
# CHECK-LABEL: name: test_urem_i16 # CHECK-LABEL: name: test_urem_i16
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 25 Lines bb.0:
; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]] ; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]]
; HWDIV: [[P32:%[0-9]+]]:_(s32) = G_MUL [[Q32]], [[Y32]] ; HWDIV: [[P32:%[0-9]+]]:_(s32) = G_MUL [[Q32]], [[Y32]]
; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SUB [[X32]], [[P32]] ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SUB [[X32]], [[P32]]
; SOFT-NOT: G_UREM ; SOFT-NOT: G_UREM
; SOFT: ADJCALLSTACKDOWN ; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X32]] ; SOFT-DAG: $r0 = COPY [[X32]]
; SOFT-DAG: $r1 = COPY [[Y32]] ; SOFT-DAG: $r1 = COPY [[Y32]]
; ARM-AEABI: BL &__aeabi_uidivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; ARM-AEABI: BL &__aeabi_uidivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; THUMB-AEABI: tBL 14, $noreg, &__aeabi_uidivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; THUMB-AEABI: tBL 14 /* CC::al */, $noreg, &__aeabi_uidivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r1 ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r1
; ARM-DEFAULT: BL &__umodsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; ARM-DEFAULT: BL &__umodsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; THUMB-DEFAULT: tBL 14, $noreg, &__umodsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; THUMB-DEFAULT: tBL 14 /* CC::al */, $noreg, &__umodsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0 ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UREM ; SOFT-NOT: G_UREM
; CHECK: [[R:%[0-9]+]]:_(s32) = G_AND ; CHECK: [[R:%[0-9]+]]:_(s32) = G_AND
; SOFT-NOT: G_UREM ; SOFT-NOT: G_UREM
%4(s16) = G_UREM %1, %3 %4(s16) = G_UREM %1, %3
; CHECK: $r0 = COPY [[R]] ; CHECK: $r0 = COPY [[R]]
%5(s32) = G_ZEXT %4(s16) %5(s32) = G_ZEXT %4(s16)
$r0 = COPY %5(s32) $r0 = COPY %5(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_srem_i8 name: test_srem_i8
# CHECK-LABEL: name: test_srem_i8 # CHECK-LABEL: name: test_srem_i8
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 27 Lines bb.0:
; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]] ; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]]
; HWDIV: [[P32:%[0-9]+]]:_(s32) = G_MUL [[Q32]], [[Y32]] ; HWDIV: [[P32:%[0-9]+]]:_(s32) = G_MUL [[Q32]], [[Y32]]
; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SUB [[X32]], [[P32]] ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SUB [[X32]], [[P32]]
; SOFT-NOT: G_SREM ; SOFT-NOT: G_SREM
; SOFT: ADJCALLSTACKDOWN ; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X32]] ; SOFT-DAG: $r0 = COPY [[X32]]
; SOFT-DAG: $r1 = COPY [[Y32]] ; SOFT-DAG: $r1 = COPY [[Y32]]
; ARM-AEABI: BL &__aeabi_idivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; ARM-AEABI: BL &__aeabi_idivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; THUMB-AEABI: tBL 14, $noreg, &__aeabi_idivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; THUMB-AEABI: tBL 14 /* CC::al */, $noreg, &__aeabi_idivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r1 ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r1
; ARM-DEFAULT: BL &__modsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; ARM-DEFAULT: BL &__modsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; THUMB-DEFAULT: tBL 14, $noreg, &__modsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; THUMB-DEFAULT: tBL 14 /* CC::al */, $noreg, &__modsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0 ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SREM ; SOFT-NOT: G_SREM
; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR ; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR
; SOFT-NOT: G_SREM ; SOFT-NOT: G_SREM
%4(s8) = G_SREM %1, %3 %4(s8) = G_SREM %1, %3
; CHECK: $r0 = COPY [[R]] ; CHECK: $r0 = COPY [[R]]
%5(s32) = G_SEXT %4(s8) %5(s32) = G_SEXT %4(s8)
$r0 = COPY %5(s32) $r0 = COPY %5(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_urem_i8 name: test_urem_i8
# CHECK-LABEL: name: test_urem_i8 # CHECK-LABEL: name: test_urem_i8
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 25 Lines bb.0:
; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]] ; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]]
; HWDIV: [[P32:%[0-9]+]]:_(s32) = G_MUL [[Q32]], [[Y32]] ; HWDIV: [[P32:%[0-9]+]]:_(s32) = G_MUL [[Q32]], [[Y32]]
; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SUB [[X32]], [[P32]] ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SUB [[X32]], [[P32]]
; SOFT-NOT: G_UREM ; SOFT-NOT: G_UREM
; SOFT: ADJCALLSTACKDOWN ; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X32]] ; SOFT-DAG: $r0 = COPY [[X32]]
; SOFT-DAG: $r1 = COPY [[Y32]] ; SOFT-DAG: $r1 = COPY [[Y32]]
; ARM-AEABI: BL &__aeabi_uidivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; ARM-AEABI: BL &__aeabi_uidivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; THUMB-AEABI: tBL 14, $noreg, &__aeabi_uidivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; THUMB-AEABI: tBL 14 /* CC::al */, $noreg, &__aeabi_uidivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r1 ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r1
; ARM-DEFAULT: BL &__umodsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; ARM-DEFAULT: BL &__umodsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; THUMB-DEFAULT: tBL 14, $noreg, &__umodsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; THUMB-DEFAULT: tBL 14 /* CC::al */, $noreg, &__umodsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0 ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UREM ; SOFT-NOT: G_UREM
; CHECK: [[R:%[0-9]+]]:_(s32) = G_AND ; CHECK: [[R:%[0-9]+]]:_(s32) = G_AND
; SOFT-NOT: G_UREM ; SOFT-NOT: G_UREM
%4(s8) = G_UREM %1, %3 %4(s8) = G_UREM %1, %3
; CHECK: $r0 = COPY [[R]] ; CHECK: $r0 = COPY [[R]]
%5(s32) = G_ZEXT %4(s8) %5(s32) = G_ZEXT %4(s8)
$r0 = COPY %5(s32) $r0 = COPY %5(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...

llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll

; RUN: llc -O0 -mtriple arm-unknown -mattr=+vfp2,+v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=ARM -check-prefix=LITTLE ; RUN: llc -O0 -mtriple arm-unknown -mattr=+vfp2,+v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=ARM -check-prefix=LITTLE
; RUN: llc -O0 -mtriple armeb-unknown -mattr=+vfp2,+v4t -global-isel -global-isel-abort=0 -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=ARM -check-prefix=BIG ; RUN: llc -O0 -mtriple armeb-unknown -mattr=+vfp2,+v4t -global-isel -global-isel-abort=0 -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=ARM -check-prefix=BIG
; RUN: llc -O0 -mtriple thumb-unknown -mattr=+vfp2,+v6t2 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=LITTLE -check-prefix=THUMB ; RUN: llc -O0 -mtriple thumb-unknown -mattr=+vfp2,+v6t2 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=LITTLE -check-prefix=THUMB
declare arm_aapcscc i32* @simple_reg_params_target(i32, i32*) declare arm_aapcscc i32* @simple_reg_params_target(i32, i32*)
define arm_aapcscc i32* @test_call_simple_reg_params(i32 *%a, i32 %b) { define arm_aapcscc i32* @test_call_simple_reg_params(i32 *%a, i32 %b) {
; CHECK-LABEL: name: test_call_simple_reg_params ; CHECK-LABEL: name: test_call_simple_reg_params
; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY $r0 ; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY $r0
; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK-DAG: $r0 = COPY [[BVREG]] ; CHECK-DAG: $r0 = COPY [[BVREG]]
; CHECK-DAG: $r1 = COPY [[AVREG]] ; CHECK-DAG: $r1 = COPY [[AVREG]]
; ARM: BL @simple_reg_params_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0 ; ARM: BL @simple_reg_params_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0
; THUMB: tBL 14, $noreg, @simple_reg_params_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0 ; THUMB: tBL 14 /* CC::al */, $noreg, @simple_reg_params_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0
; CHECK: [[RVREG:%[0-9]+]]:_(p0) = COPY $r0 ; CHECK: [[RVREG:%[0-9]+]]:_(p0) = COPY $r0
; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK: $r0 = COPY [[RVREG]] ; CHECK: $r0 = COPY [[RVREG]]
; ARM: BX_RET 14, $noreg, implicit $r0 ; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $r0
; THUMB: tBX_RET 14, $noreg, implicit $r0 ; THUMB: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
entry: entry:
%r = notail call arm_aapcscc i32 *@simple_reg_params_target(i32 %b, i32 *%a) %r = notail call arm_aapcscc i32 *@simple_reg_params_target(i32 %b, i32 *%a)
ret i32 *%r ret i32 *%r
} }
declare arm_aapcscc i32* @simple_stack_params_target(i32, i32*, i32, i32*, i32, i32*) declare arm_aapcscc i32* @simple_stack_params_target(i32, i32*, i32, i32*, i32, i32*)
define arm_aapcscc i32* @test_call_simple_stack_params(i32 *%a, i32 %b) { define arm_aapcscc i32* @test_call_simple_stack_params(i32 *%a, i32 %b) {
; CHECK-LABEL: name: test_call_simple_stack_params ; CHECK-LABEL: name: test_call_simple_stack_params
; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY $r0 ; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY $r0
; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: ADJCALLSTACKDOWN 8, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKDOWN 8, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK-DAG: $r0 = COPY [[BVREG]] ; CHECK-DAG: $r0 = COPY [[BVREG]]
; CHECK-DAG: $r1 = COPY [[AVREG]] ; CHECK-DAG: $r1 = COPY [[AVREG]]
; CHECK-DAG: $r2 = COPY [[BVREG]] ; CHECK-DAG: $r2 = COPY [[BVREG]]
; CHECK-DAG: $r3 = COPY [[AVREG]] ; CHECK-DAG: $r3 = COPY [[AVREG]]
; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP1]], [[OFF1]](s32) ; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP1]], [[OFF1]](s32)
; CHECK: G_STORE [[BVREG]](s32), [[FI1]](p0){{.*}}store 4 ; CHECK: G_STORE [[BVREG]](s32), [[FI1]](p0){{.*}}store 4
; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP2]], [[OFF2]](s32) ; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP2]], [[OFF2]](s32)
; CHECK: G_STORE [[AVREG]](p0), [[FI2]](p0){{.*}}store 4 ; CHECK: G_STORE [[AVREG]](p0), [[FI2]](p0){{.*}}store 4
; ARM: BL @simple_stack_params_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0 ; ARM: BL @simple_stack_params_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; THUMB: tBL 14, $noreg, @simple_stack_params_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0 ; THUMB: tBL 14 /* CC::al */, $noreg, @simple_stack_params_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; CHECK: [[RVREG:%[0-9]+]]:_(p0) = COPY $r0 ; CHECK: [[RVREG:%[0-9]+]]:_(p0) = COPY $r0
; CHECK: ADJCALLSTACKUP 8, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKUP 8, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK: $r0 = COPY [[RVREG]] ; CHECK: $r0 = COPY [[RVREG]]
; ARM: BX_RET 14, $noreg, implicit $r0 ; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $r0
; THUMB: tBX_RET 14, $noreg, implicit $r0 ; THUMB: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
entry: entry:
%r = notail call arm_aapcscc i32 *@simple_stack_params_target(i32 %b, i32 *%a, i32 %b, i32 *%a, i32 %b, i32 *%a) %r = notail call arm_aapcscc i32 *@simple_stack_params_target(i32 %b, i32 *%a, i32 %b, i32 *%a, i32 %b, i32 *%a)
ret i32 *%r ret i32 *%r
} }
declare arm_aapcscc signext i16 @ext_target(i8 signext, i8 zeroext, i16 signext, i16 zeroext, i8 signext, i8 zeroext, i16 signext, i16 zeroext, i1 zeroext) declare arm_aapcscc signext i16 @ext_target(i8 signext, i8 zeroext, i16 signext, i16 zeroext, i8 signext, i8 zeroext, i16 signext, i16 zeroext, i1 zeroext)
define arm_aapcscc signext i16 @test_call_ext_params(i8 %a, i16 %b, i1 %c) { define arm_aapcscc signext i16 @test_call_ext_params(i8 %a, i16 %b, i1 %c) {
; CHECK-LABEL: name: test_call_ext_params ; CHECK-LABEL: name: test_call_ext_params
; CHECK-DAG: [[R0VREG:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK-DAG: [[R0VREG:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s8) = G_TRUNC [[R0VREG]] ; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s8) = G_TRUNC [[R0VREG]]
; CHECK-DAG: [[R1VREG:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK-DAG: [[R1VREG:%[0-9]+]]:_(s32) = COPY $r1
; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s16) = G_TRUNC [[R1VREG]] ; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s16) = G_TRUNC [[R1VREG]]
; CHECK-DAG: [[R2VREG:%[0-9]+]]:_(s32) = COPY $r2 ; CHECK-DAG: [[R2VREG:%[0-9]+]]:_(s32) = COPY $r2
; CHECK-DAG: [[CVREG:%[0-9]+]]:_(s1) = G_TRUNC [[R2VREG]] ; CHECK-DAG: [[CVREG:%[0-9]+]]:_(s1) = G_TRUNC [[R2VREG]]
; CHECK: ADJCALLSTACKDOWN 20, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKDOWN 20, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[SEXTA:%[0-9]+]]:_(s32) = G_SEXT [[AVREG]](s8) ; CHECK: [[SEXTA:%[0-9]+]]:_(s32) = G_SEXT [[AVREG]](s8)
; CHECK: $r0 = COPY [[SEXTA]] ; CHECK: $r0 = COPY [[SEXTA]]
; CHECK: [[ZEXTA:%[0-9]+]]:_(s32) = G_ZEXT [[AVREG]](s8) ; CHECK: [[ZEXTA:%[0-9]+]]:_(s32) = G_ZEXT [[AVREG]](s8)
; CHECK: $r1 = COPY [[ZEXTA]] ; CHECK: $r1 = COPY [[ZEXTA]]
; CHECK: [[SEXTB:%[0-9]+]]:_(s32) = G_SEXT [[BVREG]](s16) ; CHECK: [[SEXTB:%[0-9]+]]:_(s32) = G_SEXT [[BVREG]](s16)
; CHECK: $r2 = COPY [[SEXTB]] ; CHECK: $r2 = COPY [[SEXTB]]
; CHECK: [[ZEXTB:%[0-9]+]]:_(s32) = G_ZEXT [[BVREG]](s16) ; CHECK: [[ZEXTB:%[0-9]+]]:_(s32) = G_ZEXT [[BVREG]](s16)
; CHECK: $r3 = COPY [[ZEXTB]] ; CHECK: $r3 = COPY [[ZEXTB]]
Show All 18 Lines
; CHECK: [[ZEXTB2:%[0-9]+]]:_(s32) = G_ZEXT [[BVREG]] ; CHECK: [[ZEXTB2:%[0-9]+]]:_(s32) = G_ZEXT [[BVREG]]
; CHECK: G_STORE [[ZEXTB2]](s32), [[FI4]](p0){{.*}}store 4 ; CHECK: G_STORE [[ZEXTB2]](s32), [[FI4]](p0){{.*}}store 4
; CHECK: [[SP5:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[SP5:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[OFF5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[FI5:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP5]], [[OFF5]](s32) ; CHECK: [[FI5:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP5]], [[OFF5]](s32)
; CHECK: [[ZEXTC:%[0-9]+]]:_(s32) = G_ZEXT [[CVREG]] ; CHECK: [[ZEXTC:%[0-9]+]]:_(s32) = G_ZEXT [[CVREG]]
; CHECK: G_STORE [[ZEXTC]](s32), [[FI5]](p0){{.*}}store 4 ; CHECK: G_STORE [[ZEXTC]](s32), [[FI5]](p0){{.*}}store 4
; ARM: BL @ext_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0 ; ARM: BL @ext_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; THUMB: tBL 14, $noreg, @ext_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0 ; THUMB: tBL 14 /* CC::al */, $noreg, @ext_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; CHECK: [[R0VREG:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK: [[R0VREG:%[0-9]+]]:_(s32) = COPY $r0
; CHECK: [[RVREG:%[0-9]+]]:_(s16) = G_TRUNC [[R0VREG]] ; CHECK: [[RVREG:%[0-9]+]]:_(s16) = G_TRUNC [[R0VREG]]
; CHECK: ADJCALLSTACKUP 20, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKUP 20, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[RExtVREG:%[0-9]+]]:_(s32) = G_SEXT [[RVREG]] ; CHECK: [[RExtVREG:%[0-9]+]]:_(s32) = G_SEXT [[RVREG]]
; CHECK: $r0 = COPY [[RExtVREG]] ; CHECK: $r0 = COPY [[RExtVREG]]
; ARM: BX_RET 14, $noreg, implicit $r0 ; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $r0
; THUMB: tBX_RET 14, $noreg, implicit $r0 ; THUMB: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
entry: entry:
%r = notail call arm_aapcscc signext i16 @ext_target(i8 signext %a, i8 zeroext %a, i16 signext %b, i16 zeroext %b, i8 signext %a, i8 zeroext %a, i16 signext %b, i16 zeroext %b, i1 zeroext %c) %r = notail call arm_aapcscc signext i16 @ext_target(i8 signext %a, i8 zeroext %a, i16 signext %b, i16 zeroext %b, i8 signext %a, i8 zeroext %a, i16 signext %b, i16 zeroext %b, i1 zeroext %c)
ret i16 %r ret i16 %r
} }
declare arm_aapcs_vfpcc double @vfpcc_fp_target(float, double) declare arm_aapcs_vfpcc double @vfpcc_fp_target(float, double)
define arm_aapcs_vfpcc double @test_call_vfpcc_fp_params(double %a, float %b) { define arm_aapcs_vfpcc double @test_call_vfpcc_fp_params(double %a, float %b) {
; CHECK-LABEL: name: test_call_vfpcc_fp_params ; CHECK-LABEL: name: test_call_vfpcc_fp_params
; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s64) = COPY $d0 ; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s64) = COPY $d0
; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $s2 ; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $s2
; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK-DAG: $s0 = COPY [[BVREG]] ; CHECK-DAG: $s0 = COPY [[BVREG]]
; CHECK-DAG: $d1 = COPY [[AVREG]] ; CHECK-DAG: $d1 = COPY [[AVREG]]
; ARM: BL @vfpcc_fp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $d1, implicit-def $d0 ; ARM: BL @vfpcc_fp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $d1, implicit-def $d0
; THUMB: tBL 14, $noreg, @vfpcc_fp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $d1, implicit-def $d0 ; THUMB: tBL 14 /* CC::al */, $noreg, @vfpcc_fp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $d1, implicit-def $d0
; CHECK: [[RVREG:%[0-9]+]]:_(s64) = COPY $d0 ; CHECK: [[RVREG:%[0-9]+]]:_(s64) = COPY $d0
; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK: $d0 = COPY [[RVREG]] ; CHECK: $d0 = COPY [[RVREG]]
; ARM: BX_RET 14, $noreg, implicit $d0 ; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $d0
; THUMB: tBX_RET 14, $noreg, implicit $d0 ; THUMB: tBX_RET 14 /* CC::al */, $noreg, implicit $d0
entry: entry:
%r = notail call arm_aapcs_vfpcc double @vfpcc_fp_target(float %b, double %a) %r = notail call arm_aapcs_vfpcc double @vfpcc_fp_target(float %b, double %a)
ret double %r ret double %r
} }
declare arm_aapcscc double @aapcscc_fp_target(float, double, float, double) declare arm_aapcscc double @aapcscc_fp_target(float, double, float, double)
define arm_aapcscc double @test_call_aapcs_fp_params(double %a, float %b) { define arm_aapcscc double @test_call_aapcs_fp_params(double %a, float %b) {
; CHECK-LABEL: name: test_call_aapcs_fp_params ; CHECK-LABEL: name: test_call_aapcs_fp_params
; CHECK-DAG: [[A1:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK-DAG: [[A1:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[A2:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK-DAG: [[A2:%[0-9]+]]:_(s32) = COPY $r1
; LITTLE-DAG: [[AVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[A1]](s32), [[A2]](s32) ; LITTLE-DAG: [[AVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[A1]](s32), [[A2]](s32)
; BIG-DAG: [[AVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[A2]](s32), [[A1]](s32) ; BIG-DAG: [[AVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[A2]](s32), [[A1]](s32)
; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $r2 ; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $r2
; CHECK: ADJCALLSTACKDOWN 16, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKDOWN 16, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK-DAG: $r0 = COPY [[BVREG]] ; CHECK-DAG: $r0 = COPY [[BVREG]]
; CHECK-DAG: [[A1:%[0-9]+]]:_(s32), [[A2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AVREG]](s64) ; CHECK-DAG: [[A1:%[0-9]+]]:_(s32), [[A2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AVREG]](s64)
; LITTLE-DAG: $r2 = COPY [[A1]] ; LITTLE-DAG: $r2 = COPY [[A1]]
; LITTLE-DAG: $r3 = COPY [[A2]] ; LITTLE-DAG: $r3 = COPY [[A2]]
; BIG-DAG: $r2 = COPY [[A2]] ; BIG-DAG: $r2 = COPY [[A2]]
; BIG-DAG: $r3 = COPY [[A1]] ; BIG-DAG: $r3 = COPY [[A1]]
; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP1]], [[OFF1]](s32) ; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP1]], [[OFF1]](s32)
; CHECK: G_STORE [[BVREG]](s32), [[FI1]](p0){{.*}}store 4 ; CHECK: G_STORE [[BVREG]](s32), [[FI1]](p0){{.*}}store 4
; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP2]], [[OFF2]](s32) ; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP2]], [[OFF2]](s32)
; CHECK: G_STORE [[AVREG]](s64), [[FI2]](p0){{.*}}store 8 ; CHECK: G_STORE [[AVREG]](s64), [[FI2]](p0){{.*}}store 8
; ARM: BL @aapcscc_fp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1 ; ARM: BL @aapcscc_fp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; THUMB: tBL 14, $noreg, @aapcscc_fp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1 ; THUMB: tBL 14 /* CC::al */, $noreg, @aapcscc_fp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY $r1
; LITTLE: [[RVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R1]](s32), [[R2]](s32) ; LITTLE: [[RVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R1]](s32), [[R2]](s32)
; BIG: [[RVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R2]](s32), [[R1]](s32) ; BIG: [[RVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R2]](s32), [[R1]](s32)
; CHECK: ADJCALLSTACKUP 16, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKUP 16, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[RVREG]](s64) ; CHECK: [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[RVREG]](s64)
; LITTLE-DAG: $r0 = COPY [[R1]] ; LITTLE-DAG: $r0 = COPY [[R1]]
; LITTLE-DAG: $r1 = COPY [[R2]] ; LITTLE-DAG: $r1 = COPY [[R2]]
; BIG-DAG: $r0 = COPY [[R2]] ; BIG-DAG: $r0 = COPY [[R2]]
; BIG-DAG: $r1 = COPY [[R1]] ; BIG-DAG: $r1 = COPY [[R1]]
; ARM: BX_RET 14, $noreg, implicit $r0, implicit $r1 ; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
; THUMB: tBX_RET 14, $noreg, implicit $r0, implicit $r1 ; THUMB: tBX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
entry: entry:
%r = notail call arm_aapcscc double @aapcscc_fp_target(float %b, double %a, float %b, double %a) %r = notail call arm_aapcscc double @aapcscc_fp_target(float %b, double %a, float %b, double %a)
ret double %r ret double %r
} }
declare arm_aapcscc float @different_call_conv_target(float) declare arm_aapcscc float @different_call_conv_target(float)
define arm_aapcs_vfpcc float @test_call_different_call_conv(float %x) { define arm_aapcs_vfpcc float @test_call_different_call_conv(float %x) {
; CHECK-LABEL: name: test_call_different_call_conv ; CHECK-LABEL: name: test_call_different_call_conv
; CHECK: [[X:%[0-9]+]]:_(s32) = COPY $s0 ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK: $r0 = COPY [[X]] ; CHECK: $r0 = COPY [[X]]
; ARM: BL @different_call_conv_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit-def $r0 ; ARM: BL @different_call_conv_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit-def $r0
; THUMB: tBL 14, $noreg, @different_call_conv_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit-def $r0 ; THUMB: tBL 14 /* CC::al */, $noreg, @different_call_conv_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit-def $r0
; CHECK: [[R:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK: [[R:%[0-9]+]]:_(s32) = COPY $r0
; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK: $s0 = COPY [[R]] ; CHECK: $s0 = COPY [[R]]
; ARM: BX_RET 14, $noreg, implicit $s0 ; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $s0
; THUMB: tBX_RET 14, $noreg, implicit $s0 ; THUMB: tBX_RET 14 /* CC::al */, $noreg, implicit $s0
entry: entry:
%r = notail call arm_aapcscc float @different_call_conv_target(float %x) %r = notail call arm_aapcscc float @different_call_conv_target(float %x)
ret float %r ret float %r
} }
declare arm_aapcscc [3 x i32] @tiny_int_arrays_target([2 x i32]) declare arm_aapcscc [3 x i32] @tiny_int_arrays_target([2 x i32])
define arm_aapcscc [3 x i32] @test_tiny_int_arrays([2 x i32] %arr) { define arm_aapcscc [3 x i32] @test_tiny_int_arrays([2 x i32] %arr) {
; CHECK-LABEL: name: test_tiny_int_arrays ; CHECK-LABEL: name: test_tiny_int_arrays
; CHECK: liveins: $r0, $r1 ; CHECK: liveins: $r0, $r1
; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK: $r0 = COPY [[R0]] ; CHECK: $r0 = COPY [[R0]]
; CHECK: $r1 = COPY [[R1]] ; CHECK: $r1 = COPY [[R1]]
; ARM: BL @tiny_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1 ; ARM: BL @tiny_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1
; THUMB: tBL 14, $noreg, @tiny_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1 ; THUMB: tBL 14 /* CC::al */, $noreg, @tiny_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1
; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY $r2 ; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY $r2
; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; FIXME: This doesn't seem correct with regard to the AAPCS docs (which say ; FIXME: This doesn't seem correct with regard to the AAPCS docs (which say
; that composite types larger than 4 bytes should be passed through memory), ; that composite types larger than 4 bytes should be passed through memory),
; but it's what DAGISel does. We should fix it in the common code for both. ; but it's what DAGISel does. We should fix it in the common code for both.
; CHECK: $r0 = COPY [[R0]] ; CHECK: $r0 = COPY [[R0]]
; CHECK: $r1 = COPY [[R1]] ; CHECK: $r1 = COPY [[R1]]
; CHECK: $r2 = COPY [[R2]] ; CHECK: $r2 = COPY [[R2]]
; ARM: BX_RET 14, $noreg, implicit $r0, implicit $r1, implicit $r2 ; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1, implicit $r2
; THUMB: tBX_RET 14, $noreg, implicit $r0, implicit $r1, implicit $r2 ; THUMB: tBX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1, implicit $r2
entry: entry:
%r = notail call arm_aapcscc [3 x i32] @tiny_int_arrays_target([2 x i32] %arr) %r = notail call arm_aapcscc [3 x i32] @tiny_int_arrays_target([2 x i32] %arr)
ret [3 x i32] %r ret [3 x i32] %r
} }
declare arm_aapcscc void @multiple_int_arrays_target([2 x i32], [2 x i32]) declare arm_aapcscc void @multiple_int_arrays_target([2 x i32], [2 x i32])
define arm_aapcscc void @test_multiple_int_arrays([2 x i32] %arr0, [2 x i32] %arr1) { define arm_aapcscc void @test_multiple_int_arrays([2 x i32] %arr0, [2 x i32] %arr1) {
; CHECK-LABEL: name: test_multiple_int_arrays ; CHECK-LABEL: name: test_multiple_int_arrays
; CHECK: liveins: $r0, $r1 ; CHECK: liveins: $r0, $r1
; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY $r2 ; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY $r2
; CHECK: [[R3:%[0-9]+]]:_(s32) = COPY $r3 ; CHECK: [[R3:%[0-9]+]]:_(s32) = COPY $r3
; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK: $r0 = COPY [[R0]] ; CHECK: $r0 = COPY [[R0]]
; CHECK: $r1 = COPY [[R1]] ; CHECK: $r1 = COPY [[R1]]
; CHECK: $r2 = COPY [[R2]] ; CHECK: $r2 = COPY [[R2]]
; CHECK: $r3 = COPY [[R3]] ; CHECK: $r3 = COPY [[R3]]
; ARM: BL @multiple_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3 ; ARM: BL @multiple_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3
; THUMB: tBL 14, $noreg, @multiple_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3 ; THUMB: tBL 14 /* CC::al */, $noreg, @multiple_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3
; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; ARM: BX_RET 14, $noreg ; ARM: BX_RET 14 /* CC::al */, $noreg
; THUMB: tBX_RET 14, $noreg ; THUMB: tBX_RET 14 /* CC::al */, $noreg
entry: entry:
notail call arm_aapcscc void @multiple_int_arrays_target([2 x i32] %arr0, [2 x i32] %arr1) notail call arm_aapcscc void @multiple_int_arrays_target([2 x i32] %arr0, [2 x i32] %arr1)
ret void ret void
} }
declare arm_aapcscc void @large_int_arrays_target([20 x i32]) declare arm_aapcscc void @large_int_arrays_target([20 x i32])
define arm_aapcscc void @test_large_int_arrays([20 x i32] %arr) { define arm_aapcscc void @test_large_int_arrays([20 x i32] %arr) {
; CHECK-LABEL: name: test_large_int_arrays ; CHECK-LABEL: name: test_large_int_arrays
; CHECK: fixedStack: ; CHECK: fixedStack:
; The parameters live in separate stack locations, one for each element that ; The parameters live in separate stack locations, one for each element that
; doesn't fit in the registers. ; doesn't fit in the registers.
; CHECK-DAG: id: [[FIRST_STACK_ID:[0-9]+]], type: default, offset: 0, size: 4, ; CHECK-DAG: id: [[FIRST_STACK_ID:[0-9]+]], type: default, offset: 0, size: 4,
; CHECK-DAG: id: [[LAST_STACK_ID:[-0]+]], type: default, offset: 60, size: 4 ; CHECK-DAG: id: [[LAST_STACK_ID:[-0]+]], type: default, offset: 60, size: 4
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY $r2 ; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY $r2
; CHECK-DAG: [[R3:%[0-9]+]]:_(s32) = COPY $r3 ; CHECK-DAG: [[R3:%[0-9]+]]:_(s32) = COPY $r3
; CHECK: [[FIRST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[FIRST_STACK_ID]] ; CHECK: [[FIRST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[FIRST_STACK_ID]]
; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]] ; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]]
; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]] ; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]]
; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]] ; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]]
; CHECK: ADJCALLSTACKDOWN 64, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKDOWN 64, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK: $r0 = COPY [[R0]] ; CHECK: $r0 = COPY [[R0]]
; CHECK: $r1 = COPY [[R1]] ; CHECK: $r1 = COPY [[R1]]
; CHECK: $r2 = COPY [[R2]] ; CHECK: $r2 = COPY [[R2]]
; CHECK: $r3 = COPY [[R3]] ; CHECK: $r3 = COPY [[R3]]
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF_FIRST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[OFF_FIRST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[FIRST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[OFF_FIRST_ELEMENT]](s32) ; CHECK: [[FIRST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[OFF_FIRST_ELEMENT]](s32)
; CHECK: G_STORE [[FIRST_STACK_ELEMENT]](s32), [[FIRST_STACK_ARG_ADDR]]{{.*}}store 4 ; CHECK: G_STORE [[FIRST_STACK_ELEMENT]](s32), [[FIRST_STACK_ARG_ADDR]]{{.*}}store 4
; Match the second-to-last offset, so we can get the correct SP for the last element ; Match the second-to-last offset, so we can get the correct SP for the last element
; CHECK: G_CONSTANT i32 56 ; CHECK: G_CONSTANT i32 56
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF_LAST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 60 ; CHECK: [[OFF_LAST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 60
; CHECK: [[LAST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[OFF_LAST_ELEMENT]](s32) ; CHECK: [[LAST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[OFF_LAST_ELEMENT]](s32)
; CHECK: G_STORE [[LAST_STACK_ELEMENT]](s32), [[LAST_STACK_ARG_ADDR]]{{.*}}store 4 ; CHECK: G_STORE [[LAST_STACK_ELEMENT]](s32), [[LAST_STACK_ARG_ADDR]]{{.*}}store 4
; ARM: BL @large_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3 ; ARM: BL @large_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3
; THUMB: tBL 14, $noreg, @large_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3 ; THUMB: tBL 14 /* CC::al */, $noreg, @large_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3
; CHECK: ADJCALLSTACKUP 64, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKUP 64, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; ARM: BX_RET 14, $noreg ; ARM: BX_RET 14 /* CC::al */, $noreg
; THUMB: tBX_RET 14, $noreg ; THUMB: tBX_RET 14 /* CC::al */, $noreg
entry: entry:
notail call arm_aapcscc void @large_int_arrays_target([20 x i32] %arr) notail call arm_aapcscc void @large_int_arrays_target([20 x i32] %arr)
ret void ret void
} }
declare arm_aapcscc [2 x float] @fp_arrays_aapcs_target([3 x double]) declare arm_aapcscc [2 x float] @fp_arrays_aapcs_target([3 x double])
define arm_aapcscc [2 x float] @test_fp_arrays_aapcs([3 x double] %arr) { define arm_aapcscc [2 x float] @test_fp_arrays_aapcs([3 x double] %arr) {
; CHECK-LABEL: name: test_fp_arrays_aapcs ; CHECK-LABEL: name: test_fp_arrays_aapcs
; CHECK: fixedStack: ; CHECK: fixedStack:
; CHECK: id: [[ARR2_ID:[0-9]+]], type: default, offset: 0, size: 8, ; CHECK: id: [[ARR2_ID:[0-9]+]], type: default, offset: 0, size: 8,
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: [[ARR0_0:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK: [[ARR0_0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK: [[ARR0_1:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK: [[ARR0_1:%[0-9]+]]:_(s32) = COPY $r1
; LITTLE: [[ARR0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR0_0]](s32), [[ARR0_1]](s32) ; LITTLE: [[ARR0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR0_0]](s32), [[ARR0_1]](s32)
; BIG: [[ARR0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR0_1]](s32), [[ARR0_0]](s32) ; BIG: [[ARR0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR0_1]](s32), [[ARR0_0]](s32)
; CHECK: [[ARR1_0:%[0-9]+]]:_(s32) = COPY $r2 ; CHECK: [[ARR1_0:%[0-9]+]]:_(s32) = COPY $r2
; CHECK: [[ARR1_1:%[0-9]+]]:_(s32) = COPY $r3 ; CHECK: [[ARR1_1:%[0-9]+]]:_(s32) = COPY $r3
; LITTLE: [[ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR1_0]](s32), [[ARR1_1]](s32) ; LITTLE: [[ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR1_0]](s32), [[ARR1_1]](s32)
; BIG: [[ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR1_1]](s32), [[ARR1_0]](s32) ; BIG: [[ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR1_1]](s32), [[ARR1_0]](s32)
; CHECK: [[ARR2_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[ARR2_ID]] ; CHECK: [[ARR2_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[ARR2_ID]]
; CHECK: [[ARR2:%[0-9]+]]:_(s64) = G_LOAD [[ARR2_FI]]{{.*}}load 8 from %fixed-stack.[[ARR2_ID]] ; CHECK: [[ARR2:%[0-9]+]]:_(s64) = G_LOAD [[ARR2_FI]]{{.*}}load 8 from %fixed-stack.[[ARR2_ID]]
; CHECK: ADJCALLSTACKDOWN 8, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKDOWN 8, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[ARR0_0:%[0-9]+]]:_(s32), [[ARR0_1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARR0]](s64) ; CHECK: [[ARR0_0:%[0-9]+]]:_(s32), [[ARR0_1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARR0]](s64)
; LITTLE: $r0 = COPY [[ARR0_0]](s32) ; LITTLE: $r0 = COPY [[ARR0_0]](s32)
; LITTLE: $r1 = COPY [[ARR0_1]](s32) ; LITTLE: $r1 = COPY [[ARR0_1]](s32)
; BIG: $r0 = COPY [[ARR0_1]](s32) ; BIG: $r0 = COPY [[ARR0_1]](s32)
; BIG: $r1 = COPY [[ARR0_0]](s32) ; BIG: $r1 = COPY [[ARR0_0]](s32)
; CHECK: [[ARR1_0:%[0-9]+]]:_(s32), [[ARR1_1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARR1]](s64) ; CHECK: [[ARR1_0:%[0-9]+]]:_(s32), [[ARR1_1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARR1]](s64)
; LITTLE: $r2 = COPY [[ARR1_0]](s32) ; LITTLE: $r2 = COPY [[ARR1_0]](s32)
; LITTLE: $r3 = COPY [[ARR1_1]](s32) ; LITTLE: $r3 = COPY [[ARR1_1]](s32)
; BIG: $r2 = COPY [[ARR1_1]](s32) ; BIG: $r2 = COPY [[ARR1_1]](s32)
; BIG: $r3 = COPY [[ARR1_0]](s32) ; BIG: $r3 = COPY [[ARR1_0]](s32)
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[ARR2_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[ARR2_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ARR2_ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[ARR2_OFFSET]](s32) ; CHECK: [[ARR2_ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[ARR2_OFFSET]](s32)
; CHECK: G_STORE [[ARR2]](s64), [[ARR2_ADDR]](p0){{.*}}store 8 ; CHECK: G_STORE [[ARR2]](s64), [[ARR2_ADDR]](p0){{.*}}store 8
; ARM: BL @fp_arrays_aapcs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1 ; ARM: BL @fp_arrays_aapcs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; THUMB: tBL 14, $noreg, @fp_arrays_aapcs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1 ; THUMB: tBL 14 /* CC::al */, $noreg, @fp_arrays_aapcs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: ADJCALLSTACKUP 8, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKUP 8, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK: $r0 = COPY [[R0]] ; CHECK: $r0 = COPY [[R0]]
; CHECK: $r1 = COPY [[R1]] ; CHECK: $r1 = COPY [[R1]]
; ARM: BX_RET 14, $noreg, implicit $r0, implicit $r1 ; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
; THUMB: tBX_RET 14, $noreg, implicit $r0, implicit $r1 ; THUMB: tBX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
entry: entry:
%r = notail call arm_aapcscc [2 x float] @fp_arrays_aapcs_target([3 x double] %arr) %r = notail call arm_aapcscc [2 x float] @fp_arrays_aapcs_target([3 x double] %arr)
ret [2 x float] %r ret [2 x float] %r
} }
declare arm_aapcs_vfpcc [4 x float] @fp_arrays_aapcs_vfp_target([3 x double], [3 x float], [4 x double]) declare arm_aapcs_vfpcc [4 x float] @fp_arrays_aapcs_vfp_target([3 x double], [3 x float], [4 x double])
define arm_aapcs_vfpcc [4 x float] @test_fp_arrays_aapcs_vfp([3 x double] %x, [3 x float] %y, [4 x double] %z) { define arm_aapcs_vfpcc [4 x float] @test_fp_arrays_aapcs_vfp([3 x double] %x, [3 x float] %y, [4 x double] %z) {
Show All 13 Lines
; CHECK: [[Z0_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z0_ID]] ; CHECK: [[Z0_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z0_ID]]
; CHECK: [[Z0:%[0-9]+]]:_(s64) = G_LOAD [[Z0_FI]]{{.*}}load 8 ; CHECK: [[Z0:%[0-9]+]]:_(s64) = G_LOAD [[Z0_FI]]{{.*}}load 8
; CHECK: [[Z1_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z1_ID]] ; CHECK: [[Z1_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z1_ID]]
; CHECK: [[Z1:%[0-9]+]]:_(s64) = G_LOAD [[Z1_FI]]{{.*}}load 8 ; CHECK: [[Z1:%[0-9]+]]:_(s64) = G_LOAD [[Z1_FI]]{{.*}}load 8
; CHECK: [[Z2_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z2_ID]] ; CHECK: [[Z2_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z2_ID]]
; CHECK: [[Z2:%[0-9]+]]:_(s64) = G_LOAD [[Z2_FI]]{{.*}}load 8 ; CHECK: [[Z2:%[0-9]+]]:_(s64) = G_LOAD [[Z2_FI]]{{.*}}load 8
; CHECK: [[Z3_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z3_ID]] ; CHECK: [[Z3_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z3_ID]]
; CHECK: [[Z3:%[0-9]+]]:_(s64) = G_LOAD [[Z3_FI]]{{.*}}load 8 ; CHECK: [[Z3:%[0-9]+]]:_(s64) = G_LOAD [[Z3_FI]]{{.*}}load 8
; CHECK: ADJCALLSTACKDOWN 32, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKDOWN 32, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK: $d0 = COPY [[X0]](s64) ; CHECK: $d0 = COPY [[X0]](s64)
; CHECK: $d1 = COPY [[X1]](s64) ; CHECK: $d1 = COPY [[X1]](s64)
; CHECK: $d2 = COPY [[X2]](s64) ; CHECK: $d2 = COPY [[X2]](s64)
; CHECK: $s6 = COPY [[Y0]](s32) ; CHECK: $s6 = COPY [[Y0]](s32)
; CHECK: $s7 = COPY [[Y1]](s32) ; CHECK: $s7 = COPY [[Y1]](s32)
; CHECK: $s8 = COPY [[Y2]](s32) ; CHECK: $s8 = COPY [[Y2]](s32)
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[Z0_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[Z0_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[Z0_ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[Z0_OFFSET]](s32) ; CHECK: [[Z0_ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[Z0_OFFSET]](s32)
; CHECK: G_STORE [[Z0]](s64), [[Z0_ADDR]](p0){{.*}}store 8 ; CHECK: G_STORE [[Z0]](s64), [[Z0_ADDR]](p0){{.*}}store 8
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[Z1_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[Z1_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[Z1_ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[Z1_OFFSET]](s32) ; CHECK: [[Z1_ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[Z1_OFFSET]](s32)
; CHECK: G_STORE [[Z1]](s64), [[Z1_ADDR]](p0){{.*}}store 8 ; CHECK: G_STORE [[Z1]](s64), [[Z1_ADDR]](p0){{.*}}store 8
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[Z2_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[Z2_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[Z2_ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[Z2_OFFSET]](s32) ; CHECK: [[Z2_ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[Z2_OFFSET]](s32)
; CHECK: G_STORE [[Z2]](s64), [[Z2_ADDR]](p0){{.*}}store 8 ; CHECK: G_STORE [[Z2]](s64), [[Z2_ADDR]](p0){{.*}}store 8
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[Z3_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; CHECK: [[Z3_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[Z3_ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[Z3_OFFSET]](s32) ; CHECK: [[Z3_ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[Z3_OFFSET]](s32)
; CHECK: G_STORE [[Z3]](s64), [[Z3_ADDR]](p0){{.*}}store 8 ; CHECK: G_STORE [[Z3]](s64), [[Z3_ADDR]](p0){{.*}}store 8
; ARM: BL @fp_arrays_aapcs_vfp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $d1, implicit $d2, implicit $s6, implicit $s7, implicit $s8, implicit-def $s0, implicit-def $s1, implicit-def $s2, implicit-def $s3 ; ARM: BL @fp_arrays_aapcs_vfp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $d1, implicit $d2, implicit $s6, implicit $s7, implicit $s8, implicit-def $s0, implicit-def $s1, implicit-def $s2, implicit-def $s3
; THUMB: tBL 14, $noreg, @fp_arrays_aapcs_vfp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $d1, implicit $d2, implicit $s6, implicit $s7, implicit $s8, implicit-def $s0, implicit-def $s1, implicit-def $s2, implicit-def $s3 ; THUMB: tBL 14 /* CC::al */, $noreg, @fp_arrays_aapcs_vfp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $d1, implicit $d2, implicit $s6, implicit $s7, implicit $s8, implicit-def $s0, implicit-def $s1, implicit-def $s2, implicit-def $s3
; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $s0 ; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $s1 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $s1
; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY $s2 ; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY $s2
; CHECK: [[R3:%[0-9]+]]:_(s32) = COPY $s3 ; CHECK: [[R3:%[0-9]+]]:_(s32) = COPY $s3
; CHECK: ADJCALLSTACKUP 32, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKUP 32, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK: $s0 = COPY [[R0]] ; CHECK: $s0 = COPY [[R0]]
; CHECK: $s1 = COPY [[R1]] ; CHECK: $s1 = COPY [[R1]]
; CHECK: $s2 = COPY [[R2]] ; CHECK: $s2 = COPY [[R2]]
; CHECK: $s3 = COPY [[R3]] ; CHECK: $s3 = COPY [[R3]]
; ARM: BX_RET 14, $noreg, implicit $s0, implicit $s1, implicit $s2, implicit $s3 ; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $s0, implicit $s1, implicit $s2, implicit $s3
; THUMB: tBX_RET 14, $noreg, implicit $s0, implicit $s1, implicit $s2, implicit $s3 ; THUMB: tBX_RET 14 /* CC::al */, $noreg, implicit $s0, implicit $s1, implicit $s2, implicit $s3
entry: entry:
%r = notail call arm_aapcs_vfpcc [4 x float] @fp_arrays_aapcs_vfp_target([3 x double] %x, [3 x float] %y, [4 x double] %z) %r = notail call arm_aapcs_vfpcc [4 x float] @fp_arrays_aapcs_vfp_target([3 x double] %x, [3 x float] %y, [4 x double] %z)
ret [4 x float] %r ret [4 x float] %r
} }
declare arm_aapcscc [2 x i32*] @tough_arrays_target([6 x [4 x i32]] %arr) declare arm_aapcscc [2 x i32*] @tough_arrays_target([6 x [4 x i32]] %arr)
define arm_aapcscc [2 x i32*] @test_tough_arrays([6 x [4 x i32]] %arr) { define arm_aapcscc [2 x i32*] @test_tough_arrays([6 x [4 x i32]] %arr) {
; CHECK-LABEL: name: test_tough_arrays ; CHECK-LABEL: name: test_tough_arrays
; CHECK: fixedStack: ; CHECK: fixedStack:
; The parameters live in separate stack locations, one for each element that ; The parameters live in separate stack locations, one for each element that
; doesn't fit in the registers. ; doesn't fit in the registers.
; CHECK-DAG: id: [[FIRST_STACK_ID:[0-9]+]], type: default, offset: 0, size: 4, ; CHECK-DAG: id: [[FIRST_STACK_ID:[0-9]+]], type: default, offset: 0, size: 4,
; CHECK-DAG: id: [[LAST_STACK_ID:[-0]+]], type: default, offset: 76, size: 4 ; CHECK-DAG: id: [[LAST_STACK_ID:[-0]+]], type: default, offset: 76, size: 4
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY $r2 ; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY $r2
; CHECK-DAG: [[R3:%[0-9]+]]:_(s32) = COPY $r3 ; CHECK-DAG: [[R3:%[0-9]+]]:_(s32) = COPY $r3
; CHECK: [[FIRST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[FIRST_STACK_ID]] ; CHECK: [[FIRST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[FIRST_STACK_ID]]
; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]] ; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]]
; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]] ; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]]
; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]] ; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]]
; CHECK: ADJCALLSTACKDOWN 80, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKDOWN 80, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK: $r0 = COPY [[R0]] ; CHECK: $r0 = COPY [[R0]]
; CHECK: $r1 = COPY [[R1]] ; CHECK: $r1 = COPY [[R1]]
; CHECK: $r2 = COPY [[R2]] ; CHECK: $r2 = COPY [[R2]]
; CHECK: $r3 = COPY [[R3]] ; CHECK: $r3 = COPY [[R3]]
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF_FIRST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[OFF_FIRST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[FIRST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[OFF_FIRST_ELEMENT]](s32) ; CHECK: [[FIRST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[OFF_FIRST_ELEMENT]](s32)
; CHECK: G_STORE [[FIRST_STACK_ELEMENT]](s32), [[FIRST_STACK_ARG_ADDR]]{{.*}}store 4 ; CHECK: G_STORE [[FIRST_STACK_ELEMENT]](s32), [[FIRST_STACK_ARG_ADDR]]{{.*}}store 4
; Match the second-to-last offset, so we can get the correct SP for the last element ; Match the second-to-last offset, so we can get the correct SP for the last element
; CHECK: G_CONSTANT i32 72 ; CHECK: G_CONSTANT i32 72
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF_LAST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 76 ; CHECK: [[OFF_LAST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 76
; CHECK: [[LAST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[OFF_LAST_ELEMENT]](s32) ; CHECK: [[LAST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[OFF_LAST_ELEMENT]](s32)
; CHECK: G_STORE [[LAST_STACK_ELEMENT]](s32), [[LAST_STACK_ARG_ADDR]]{{.*}}store 4 ; CHECK: G_STORE [[LAST_STACK_ELEMENT]](s32), [[LAST_STACK_ARG_ADDR]]{{.*}}store 4
; ARM: BL @tough_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1 ; ARM: BL @tough_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; THUMB: tBL 14, $noreg, @tough_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1 ; THUMB: tBL 14 /* CC::al */, $noreg, @tough_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; CHECK: [[R0:%[0-9]+]]:_(p0) = COPY $r0 ; CHECK: [[R0:%[0-9]+]]:_(p0) = COPY $r0
; CHECK: [[R1:%[0-9]+]]:_(p0) = COPY $r1 ; CHECK: [[R1:%[0-9]+]]:_(p0) = COPY $r1
; CHECK: ADJCALLSTACKUP 80, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKUP 80, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK: $r0 = COPY [[R0]] ; CHECK: $r0 = COPY [[R0]]
; CHECK: $r1 = COPY [[R1]] ; CHECK: $r1 = COPY [[R1]]
; ARM: BX_RET 14, $noreg, implicit $r0, implicit $r1 ; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
; THUMB: tBX_RET 14, $noreg, implicit $r0, implicit $r1 ; THUMB: tBX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
entry: entry:
%r = notail call arm_aapcscc [2 x i32*] @tough_arrays_target([6 x [4 x i32]] %arr) %r = notail call arm_aapcscc [2 x i32*] @tough_arrays_target([6 x [4 x i32]] %arr)
ret [2 x i32*] %r ret [2 x i32*] %r
} }
declare arm_aapcscc {i32, i32} @structs_target({i32, i32}) declare arm_aapcscc {i32, i32} @structs_target({i32, i32})
define arm_aapcscc {i32, i32} @test_structs({i32, i32} %x) { define arm_aapcscc {i32, i32} @test_structs({i32, i32} %x) {
; CHECK-LABEL: test_structs ; CHECK-LABEL: test_structs
; CHECK: liveins: $r0, $r1 ; CHECK: liveins: $r0, $r1
; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK-DAG: $r0 = COPY [[X0]](s32) ; CHECK-DAG: $r0 = COPY [[X0]](s32)
; CHECK-DAG: $r1 = COPY [[X1]](s32) ; CHECK-DAG: $r1 = COPY [[X1]](s32)
; ARM: BL @structs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1 ; ARM: BL @structs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1
; THUMB: tBL 14, $noreg, @structs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1 ; THUMB: tBL 14 /* CC::al */, $noreg, @structs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1
; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK: $r0 = COPY [[R0]](s32) ; CHECK: $r0 = COPY [[R0]](s32)
; CHECK: $r1 = COPY [[R1]](s32) ; CHECK: $r1 = COPY [[R1]](s32)
; ARM: BX_RET 14, $noreg, implicit $r0, implicit $r1 ; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
; THUMB: tBX_RET 14, $noreg, implicit $r0, implicit $r1 ; THUMB: tBX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
%r = notail call arm_aapcscc {i32, i32} @structs_target({i32, i32} %x) %r = notail call arm_aapcscc {i32, i32} @structs_target({i32, i32} %x)
ret {i32, i32} %r ret {i32, i32} %r
} }

llvm/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir

Show All 13 Lines
# https://bugs.llvm.org/show_bug.cgi?id=35965 # https://bugs.llvm.org/show_bug.cgi?id=35965
name: test_fptosi name: test_fptosi
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.1: bb.1:
; CHECK-LABEL: name: test_fptosi ; CHECK-LABEL: name: test_fptosi
; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
; CHECK: [[VTOSIZS:%[0-9]+]]:spr = VTOSIZS [[COPY]], 14, $noreg ; CHECK: [[VTOSIZS:%[0-9]+]]:spr = VTOSIZS [[COPY]], 14 /* CC::al */, $noreg
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY [[VTOSIZS]] ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY [[VTOSIZS]]
; CHECK: $r0 = COPY [[COPY1]] ; CHECK: $r0 = COPY [[COPY1]]
; CHECK: MOVPCLR 14, $noreg, implicit $r0 ; CHECK: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
%0:fprb(s32) = COPY $s0 %0:fprb(s32) = COPY $s0
%1:gprb(s32) = G_FPTOSI %0(s32) %1:gprb(s32) = G_FPTOSI %0(s32)
$r0 = COPY %1(s32) $r0 = COPY %1(s32)
MOVPCLR 14, $noreg, implicit $r0 MOVPCLR 14, $noreg, implicit $r0
... ...

llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-pic.mir

Show All 27 Lines
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @internal_global %0(p0) = G_GLOBAL_VALUE @internal_global
; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel target-flags(arm-nonlazy) @internal_global ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel target-flags(arm-nonlazy) @internal_global
; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel target-flags(arm-nonlazy) @internal_global ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel target-flags(arm-nonlazy) @internal_global
; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel @internal_global ; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel @internal_global
%1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global) %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global)
; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @internal_global) ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14 /* CC::al */, $noreg :: (load 4 from @internal_global)
$r0 = COPY %1(s32) $r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[V]] ; CHECK: $r0 = COPY [[V]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_external_global name: test_external_global
# CHECK-LABEL: name: test_external_global # CHECK-LABEL: name: test_external_global
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @external_global %0(p0) = G_GLOBAL_VALUE @external_global
; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel_ldr target-flags(arm-nonlazy) @external_global :: (load 4 from got) ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel_ldr target-flags(arm-nonlazy) @external_global :: (load 4 from got)
; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr target-flags(arm-nonlazy) @external_global :: (load 4 from got) ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr target-flags(arm-nonlazy) @external_global :: (load 4 from got)
; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr target-flags(arm-got) @external_global :: (load 4 from got) ; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr target-flags(arm-got) @external_global :: (load 4 from got)
%1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global) %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global)
; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @external_global) ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14 /* CC::al */, $noreg :: (load 4 from @external_global)
$r0 = COPY %1(s32) $r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[V]] ; CHECK: $r0 = COPY [[V]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_internal_constant name: test_internal_constant
# CHECK-LABEL: name: test_internal_constant # CHECK-LABEL: name: test_internal_constant
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @internal_constant %0(p0) = G_GLOBAL_VALUE @internal_constant
; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel target-flags(arm-nonlazy) @internal_constant ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel target-flags(arm-nonlazy) @internal_constant
; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel target-flags(arm-nonlazy) @internal_constant ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel target-flags(arm-nonlazy) @internal_constant
; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel @internal_constant ; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel @internal_constant
%1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_constant) %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_constant)
; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @internal_constant) ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14 /* CC::al */, $noreg :: (load 4 from @internal_constant)
$r0 = COPY %1(s32) $r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[V]] ; CHECK: $r0 = COPY [[V]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_external_constant name: test_external_constant
# CHECK-LABEL: name: test_external_constant # CHECK-LABEL: name: test_external_constant
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @external_constant %0(p0) = G_GLOBAL_VALUE @external_constant
; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel_ldr target-flags(arm-nonlazy) @external_constant :: (load 4 from got) ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel_ldr target-flags(arm-nonlazy) @external_constant :: (load 4 from got)
; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr target-flags(arm-nonlazy) @external_constant :: (load 4 from got) ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr target-flags(arm-nonlazy) @external_constant :: (load 4 from got)
; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr target-flags(arm-got) @external_constant :: (load 4 from got) ; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr target-flags(arm-got) @external_constant :: (load 4 from got)
%1(s32) = G_LOAD %0(p0) :: (load 4 from @external_constant) %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_constant)
; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @external_constant) ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14 /* CC::al */, $noreg :: (load 4 from @external_constant)
$r0 = COPY %1(s32) $r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[V]] ; CHECK: $r0 = COPY [[V]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...

llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-ropi-rwpi.mir

Show All 31 Lines
# RW-DEFAULT-NOMOVT: value: 'i32* @internal_global' # RW-DEFAULT-NOMOVT: value: 'i32* @internal_global'
# RWPI-NOMOVT: constants: # RWPI-NOMOVT: constants:
# RWPI-NOMOVT: id: 0 # RWPI-NOMOVT: id: 0
# RWPI-NOMOVT: value: 'internal_global(SBREL)' # RWPI-NOMOVT: value: 'internal_global(SBREL)'
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @internal_global %0(p0) = G_GLOBAL_VALUE @internal_global
; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global ; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global
; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, $noreg :: (load 4 from constant-pool) ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14 /* CC::al */, $noreg :: (load 4 from constant-pool)
; RWPI-MOVT: [[OFF:%[0-9]+]]:gpr = MOVi32imm target-flags(arm-sbrel) @internal_global ; RWPI-MOVT: [[OFF:%[0-9]+]]:gpr = MOVi32imm target-flags(arm-sbrel) @internal_global
; RWPI-NOMOVT: [[OFF:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, $noreg :: (load 4 from constant-pool) ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14 /* CC::al */, $noreg :: (load 4 from constant-pool)
; RWPI: [[G:%[0-9]+]]:gpr = ADDrr $r9, [[OFF]], 14, $noreg, $noreg ; RWPI: [[G:%[0-9]+]]:gpr = ADDrr $r9, [[OFF]], 14 /* CC::al */, $noreg, $noreg
%1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global) %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global)
; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @internal_global) ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14 /* CC::al */, $noreg :: (load 4 from @internal_global)
$r0 = COPY %1(s32) $r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[V]] ; CHECK: $r0 = COPY [[V]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_external_global name: test_external_global
# CHECK-LABEL: name: test_external_global # CHECK-LABEL: name: test_external_global
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
# RW-DEFAULT-NOMOVT: constants: # RW-DEFAULT-NOMOVT: constants:
# RW-DEFAULT-NOMOVT: id: 0 # RW-DEFAULT-NOMOVT: id: 0
# RW-DEFAULT-NOMOVT: value: 'i32* @external_global' # RW-DEFAULT-NOMOVT: value: 'i32* @external_global'
# RWPI-NOMOVT: constants: # RWPI-NOMOVT: constants:
# RWPI-NOMOVT: id: 0 # RWPI-NOMOVT: id: 0
# RWPI-NOMOVT: value: 'external_global(SBREL)' # RWPI-NOMOVT: value: 'external_global(SBREL)'
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @external_global %0(p0) = G_GLOBAL_VALUE @external_global
; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global ; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global
; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, $noreg :: (load 4 from constant-pool) ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14 /* CC::al */, $noreg :: (load 4 from constant-pool)
; RWPI-MOVT: [[OFF:%[0-9]+]]:gpr = MOVi32imm target-flags(arm-sbrel) @external_global ; RWPI-MOVT: [[OFF:%[0-9]+]]:gpr = MOVi32imm target-flags(arm-sbrel) @external_global
; RWPI-NOMOVT: [[OFF:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, $noreg :: (load 4 from constant-pool) ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14 /* CC::al */, $noreg :: (load 4 from constant-pool)
; RWPI: [[G:%[0-9]+]]:gpr = ADDrr $r9, [[OFF]], 14, $noreg, $noreg ; RWPI: [[G:%[0-9]+]]:gpr = ADDrr $r9, [[OFF]], 14 /* CC::al */, $noreg, $noreg
%1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global) %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global)
; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @external_global) ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14 /* CC::al */, $noreg :: (load 4 from @external_global)
$r0 = COPY %1(s32) $r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[V]] ; CHECK: $r0 = COPY [[V]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_internal_constant name: test_internal_constant
# CHECK-LABEL: name: test_internal_constant # CHECK-LABEL: name: test_internal_constant
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
# RO-DEFAULT-NOMOVT: constants: # RO-DEFAULT-NOMOVT: constants:
# RO-DEFAULT-NOMOVT: id: 0 # RO-DEFAULT-NOMOVT: id: 0
# RO-DEFAULT-NOMOVT: value: 'i32* @internal_constant' # RO-DEFAULT-NOMOVT: value: 'i32* @internal_constant'
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @internal_constant %0(p0) = G_GLOBAL_VALUE @internal_constant
; ROPI-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel @internal_constant ; ROPI-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel @internal_constant
; ROPI-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel @internal_constant ; ROPI-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel @internal_constant
; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_constant ; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_constant
; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, $noreg :: (load 4 from constant-pool) ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14 /* CC::al */, $noreg :: (load 4 from constant-pool)
%1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_constant) %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_constant)
; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @internal_constant) ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14 /* CC::al */, $noreg :: (load 4 from @internal_constant)
$r0 = COPY %1(s32) $r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[V]] ; CHECK: $r0 = COPY [[V]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_external_constant name: test_external_constant
# CHECK-LABEL: name: test_external_constant # CHECK-LABEL: name: test_external_constant
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
# RO-DEFAULT-NOMOVT: constants: # RO-DEFAULT-NOMOVT: constants:
# RO-DEFAULT-NOMOVT: id: 0 # RO-DEFAULT-NOMOVT: id: 0
# RO-DEFAULT-NOMOVT: value: 'i32* @external_constant' # RO-DEFAULT-NOMOVT: value: 'i32* @external_constant'
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @external_constant %0(p0) = G_GLOBAL_VALUE @external_constant
; ROPI-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel @external_constant ; ROPI-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel @external_constant
; ROPI-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel @external_constant ; ROPI-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel @external_constant
; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_constant ; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_constant
; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, $noreg :: (load 4 from constant-pool) ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14 /* CC::al */, $noreg :: (load 4 from constant-pool)
%1(s32) = G_LOAD %0(p0) :: (load 4 from @external_constant) %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_constant)
; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @external_constant) ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14 /* CC::al */, $noreg :: (load 4 from @external_constant)
$r0 = COPY %1(s32) $r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[V]] ; CHECK: $r0 = COPY [[V]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...

llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-static.mir

Show All 20 Linesregisters:
- { id: 1, class: gprb } - { id: 1, class: gprb }
# ELF-NOMOVT: constants: # ELF-NOMOVT: constants:
# ELF-NOMOVT: id: 0 # ELF-NOMOVT: id: 0
# ELF-NOMOVT: value: 'i32* @internal_global' # ELF-NOMOVT: value: 'i32* @internal_global'
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @internal_global %0(p0) = G_GLOBAL_VALUE @internal_global
; ELF-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global ; ELF-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global
; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, $noreg :: (load 4 from constant-pool) ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14 /* CC::al */, $noreg :: (load 4 from constant-pool)
; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global
; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_abs @internal_global ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_abs @internal_global
%1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global) %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global)
; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14 /* CC::al */, $noreg
$r0 = COPY %1(s32) $r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[V]] ; CHECK: $r0 = COPY [[V]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_external_global name: test_external_global
# CHECK-LABEL: name: test_external_global # CHECK-LABEL: name: test_external_global
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
# ELF-NOMOVT: constants: # ELF-NOMOVT: constants:
# ELF-NOMOVT: id: 0 # ELF-NOMOVT: id: 0
# ELF-NOMOVT: value: 'i32* @external_global' # ELF-NOMOVT: value: 'i32* @external_global'
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @external_global %0(p0) = G_GLOBAL_VALUE @external_global
; ELF-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global ; ELF-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global
; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, $noreg :: (load 4 from constant-pool) ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14 /* CC::al */, $noreg :: (load 4 from constant-pool)
; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global
; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_abs @external_global ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_abs @external_global
%1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global) %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global)
; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14 /* CC::al */, $noreg
$r0 = COPY %1(s32) $r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[V]] ; CHECK: $r0 = COPY [[V]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...

llvm/test/CodeGen/ARM/GlobalISel/irtranslator-varargs-lowering.ll

; RUN: llc -mtriple arm-unknown -mattr=+vfp2,+v6t2 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=ARM ; RUN: llc -mtriple arm-unknown -mattr=+vfp2,+v6t2 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=ARM
; RUN: llc -mtriple thumb-unknown -mattr=+vfp2,+v6t2 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=THUMB ; RUN: llc -mtriple thumb-unknown -mattr=+vfp2,+v6t2 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=THUMB
declare arm_aapcscc i32 @int_varargs_target(i32, ...) declare arm_aapcscc i32 @int_varargs_target(i32, ...)
define arm_aapcscc i32 @test_call_to_varargs_with_ints(i32 *%a, i32 %b) { define arm_aapcscc i32 @test_call_to_varargs_with_ints(i32 *%a, i32 %b) {
; CHECK-LABEL: name: test_call_to_varargs_with_ints ; CHECK-LABEL: name: test_call_to_varargs_with_ints
; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY $r0 ; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY $r0
; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: ADJCALLSTACKDOWN 8, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKDOWN 8, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK-DAG: $r0 = COPY [[BVREG]] ; CHECK-DAG: $r0 = COPY [[BVREG]]
; CHECK-DAG: $r1 = COPY [[AVREG]] ; CHECK-DAG: $r1 = COPY [[AVREG]]
; CHECK-DAG: $r2 = COPY [[BVREG]] ; CHECK-DAG: $r2 = COPY [[BVREG]]
; CHECK-DAG: $r3 = COPY [[AVREG]] ; CHECK-DAG: $r3 = COPY [[AVREG]]
; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP1]], [[OFF1]](s32) ; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP1]], [[OFF1]](s32)
; CHECK: G_STORE [[BVREG]](s32), [[FI1]](p0){{.*}}store 4 ; CHECK: G_STORE [[BVREG]](s32), [[FI1]](p0){{.*}}store 4
; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP2]], [[OFF2]](s32) ; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP2]], [[OFF2]](s32)
; CHECK: G_STORE [[AVREG]](p0), [[FI2]](p0){{.*}}store 4 ; CHECK: G_STORE [[AVREG]](p0), [[FI2]](p0){{.*}}store 4
; ARM: BL @int_varargs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0 ; ARM: BL @int_varargs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; THUMB: tBL 14, $noreg, @int_varargs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0 ; THUMB: tBL 14 /* CC::al */, $noreg, @int_varargs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; CHECK: [[RVREG:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK: [[RVREG:%[0-9]+]]:_(s32) = COPY $r0
; CHECK: ADJCALLSTACKUP 8, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKUP 8, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK: $r0 = COPY [[RVREG]] ; CHECK: $r0 = COPY [[RVREG]]
; ARM: BX_RET 14, $noreg, implicit $r0 ; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $r0
; THUMB: tBX_RET 14, $noreg, implicit $r0 ; THUMB: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
entry: entry:
%r = notail call arm_aapcscc i32(i32, ...) @int_varargs_target(i32 %b, i32 *%a, i32 %b, i32 *%a, i32 %b, i32 *%a) %r = notail call arm_aapcscc i32(i32, ...) @int_varargs_target(i32 %b, i32 *%a, i32 %b, i32 *%a, i32 %b, i32 *%a)
ret i32 %r ret i32 %r
} }
declare arm_aapcs_vfpcc float @float_varargs_target(float, double, ...) declare arm_aapcs_vfpcc float @float_varargs_target(float, double, ...)
define arm_aapcs_vfpcc float @test_call_to_varargs_with_floats(float %a, double %b) { define arm_aapcs_vfpcc float @test_call_to_varargs_with_floats(float %a, double %b) {
; CHECK-LABEL: name: test_call_to_varargs_with_floats ; CHECK-LABEL: name: test_call_to_varargs_with_floats
; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s32) = COPY $s0 ; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s64) = COPY $d1 ; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s64) = COPY $d1
; CHECK: ADJCALLSTACKDOWN 8, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKDOWN 8, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK-DAG: $r0 = COPY [[AVREG]] ; CHECK-DAG: $r0 = COPY [[AVREG]]
; CHECK-DAG: [[B1:%[0-9]+]]:_(s32), [[B2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BVREG]](s64) ; CHECK-DAG: [[B1:%[0-9]+]]:_(s32), [[B2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BVREG]](s64)
; CHECK-DAG: $r2 = COPY [[B1]] ; CHECK-DAG: $r2 = COPY [[B1]]
; CHECK-DAG: $r3 = COPY [[B2]] ; CHECK-DAG: $r3 = COPY [[B2]]
; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP1]], [[OFF1]](s32) ; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP1]], [[OFF1]](s32)
; CHECK: G_STORE [[BVREG]](s64), [[FI1]](p0){{.*}}store 8 ; CHECK: G_STORE [[BVREG]](s64), [[FI1]](p0){{.*}}store 8
; ARM: BL @float_varargs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0 ; ARM: BL @float_varargs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0
; THUMB: tBL 14, $noreg, @float_varargs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0 ; THUMB: tBL 14 /* CC::al */, $noreg, @float_varargs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0
; CHECK: [[RVREG:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK: [[RVREG:%[0-9]+]]:_(s32) = COPY $r0
; CHECK: ADJCALLSTACKUP 8, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKUP 8, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK: $s0 = COPY [[RVREG]] ; CHECK: $s0 = COPY [[RVREG]]
; ARM: BX_RET 14, $noreg, implicit $s0 ; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $s0
; THUMB: tBX_RET 14, $noreg, implicit $s0 ; THUMB: tBX_RET 14 /* CC::al */, $noreg, implicit $s0
entry: entry:
%r = notail call arm_aapcs_vfpcc float(float, double, ...) @float_varargs_target(float %a, double %b, double %b) %r = notail call arm_aapcs_vfpcc float(float, double, ...) @float_varargs_target(float %a, double %b, double %b)
ret float %r ret float %r
} }
define arm_aapcs_vfpcc float @test_indirect_call_to_varargs(float (float, double, ...) *%fptr, float %a, double %b) { define arm_aapcs_vfpcc float @test_indirect_call_to_varargs(float (float, double, ...) *%fptr, float %a, double %b) {
; CHECK-LABEL: name: test_indirect_call_to_varargs ; CHECK-LABEL: name: test_indirect_call_to_varargs
; CHECK-DAG: [[FPTRVREG:%[0-9]+]]:gpr(p0) = COPY $r0 ; CHECK-DAG: [[FPTRVREG:%[0-9]+]]:gpr(p0) = COPY $r0
; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s32) = COPY $s0 ; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s64) = COPY $d1 ; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s64) = COPY $d1
; CHECK: ADJCALLSTACKDOWN 8, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKDOWN 8, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK-DAG: $r0 = COPY [[AVREG]] ; CHECK-DAG: $r0 = COPY [[AVREG]]
; CHECK-DAG: [[B1:%[0-9]+]]:_(s32), [[B2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BVREG]](s64) ; CHECK-DAG: [[B1:%[0-9]+]]:_(s32), [[B2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BVREG]](s64)
; CHECK-DAG: $r2 = COPY [[B1]] ; CHECK-DAG: $r2 = COPY [[B1]]
; CHECK-DAG: $r3 = COPY [[B2]] ; CHECK-DAG: $r3 = COPY [[B2]]
; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP1]], [[OFF1]](s32) ; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP1]], [[OFF1]](s32)
; CHECK: G_STORE [[BVREG]](s64), [[FI1]](p0){{.*}}store 8 ; CHECK: G_STORE [[BVREG]](s64), [[FI1]](p0){{.*}}store 8
; ARM: BLX [[FPTRVREG]](p0), csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0 ; ARM: BLX [[FPTRVREG]](p0), csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0
; THUMB: tBLXr 14, $noreg, [[FPTRVREG]](p0), csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0 ; THUMB: tBLXr 14 /* CC::al */, $noreg, [[FPTRVREG]](p0), csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0
; CHECK: [[RVREG:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK: [[RVREG:%[0-9]+]]:_(s32) = COPY $r0
; CHECK: ADJCALLSTACKUP 8, 0, 14, $noreg, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKUP 8, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK: $s0 = COPY [[RVREG]] ; CHECK: $s0 = COPY [[RVREG]]
; ARM: BX_RET 14, $noreg, implicit $s0 ; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $s0
; THUMB: tBX_RET 14, $noreg, implicit $s0 ; THUMB: tBX_RET 14 /* CC::al */, $noreg, implicit $s0
entry: entry:
%r = notail call arm_aapcs_vfpcc float(float, double, ...) %fptr(float %a, double %b, double %b) %r = notail call arm_aapcs_vfpcc float(float, double, ...) %fptr(float %a, double %b, double %b)
ret float %r ret float %r
} }

llvm/test/CodeGen/ARM/GlobalISel/select-clz.mir

Show All 16 Linesbody: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; ARM: [[VREGX:%[0-9]+]]:gpr = COPY $r0 ; ARM: [[VREGX:%[0-9]+]]:gpr = COPY $r0
; THUMB: [[VREGX:%[0-9]+]]:rgpr = COPY $r0 ; THUMB: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
%1(s32) = G_CTLZ %0(s32) %1(s32) = G_CTLZ %0(s32)
; ARM: [[VREGR:%[0-9]+]]:gpr = CLZ [[VREGX]], 14, $noreg ; ARM: [[VREGR:%[0-9]+]]:gpr = CLZ [[VREGX]], 14 /* CC::al */, $noreg
; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2CLZ [[VREGX]], 14, $noreg ; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2CLZ [[VREGX]], 14 /* CC::al */, $noreg
$r0 = COPY %1(s32) $r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[VREGR]] ; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...

llvm/test/CodeGen/ARM/GlobalISel/select-fp-const.mir

Show All 26 Lines
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
%0(p0) = COPY $r0 %0(p0) = COPY $r0
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0 ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_FCONSTANT float 0.0 %1(s32) = G_FCONSTANT float 0.0
; CHECK: [[VREG:%[0-9]+]]:spr = VLDRS %const.0, 0, 14, $noreg :: (load 4 from constant-pool) ; CHECK: [[VREG:%[0-9]+]]:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load 4 from constant-pool)
G_STORE %1(s32), %0 :: (store 4) G_STORE %1(s32), %0 :: (store 4)
; CHECK: VSTRS [[VREG]], [[PTR]], 0, 14, $noreg ; CHECK: VSTRS [[VREG]], [[PTR]], 0, 14 /* CC::al */, $noreg
BX_RET 14, $noreg BX_RET 14, $noreg
; CHECK: BX_RET 14, $noreg ; CHECK: BX_RET 14 /* CC::al */, $noreg
... ...
--- ---
name: test_fpconst_zero_s64 name: test_fpconst_zero_s64
# CHECK-LABEL: name: test_fpconst_zero_s64 # CHECK-LABEL: name: test_fpconst_zero_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
# CHECK: constants: # CHECK: constants:
# CHECK-NEXT: id: 0 # CHECK-NEXT: id: 0
# CHECK-NEXT: value: 'double 0.000000e+00' # CHECK-NEXT: value: 'double 0.000000e+00'
# CHECK-NEXT: alignment: 8 # CHECK-NEXT: alignment: 8
# CHECK-NEXT: isTargetSpecific: false # CHECK-NEXT: isTargetSpecific: false
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
%0(p0) = COPY $r0 %0(p0) = COPY $r0
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0 ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
%1(s64) = G_FCONSTANT double 0.0 %1(s64) = G_FCONSTANT double 0.0
; CHECK: [[VREG:%[0-9]+]]:dpr = VLDRD %const.0, 0, 14, $noreg :: (load 8 from constant-pool) ; CHECK: [[VREG:%[0-9]+]]:dpr = VLDRD %const.0, 0, 14 /* CC::al */, $noreg :: (load 8 from constant-pool)
G_STORE %1(s64), %0 :: (store 8) G_STORE %1(s64), %0 :: (store 8)
; CHECK: VSTRD [[VREG]], [[PTR]], 0, 14, $noreg ; CHECK: VSTRD [[VREG]], [[PTR]], 0, 14 /* CC::al */, $noreg
BX_RET 14, $noreg BX_RET 14, $noreg
; CHECK: BX_RET 14, $noreg ; CHECK: BX_RET 14 /* CC::al */, $noreg
... ...
--- ---
name: test_fpconst_8bit_s32 name: test_fpconst_8bit_s32
# CHECK-LABEL: name: test_fpconst_8bit_s32 # CHECK-LABEL: name: test_fpconst_8bit_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
%0(p0) = COPY $r0 %0(p0) = COPY $r0
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0 ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_FCONSTANT float -2.0 %1(s32) = G_FCONSTANT float -2.0
; VFP3: [[VREG:%[0-9]+]]:spr = FCONSTS 128, 14, $noreg ; VFP3: [[VREG:%[0-9]+]]:spr = FCONSTS 128, 14 /* CC::al */, $noreg
; VFP2: [[VREG:%[0-9]+]]:spr = VLDRS %const.0, 0, 14, $noreg :: (load 4 from constant-pool) ; VFP2: [[VREG:%[0-9]+]]:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load 4 from constant-pool)
G_STORE %1(s32), %0 :: (store 4) G_STORE %1(s32), %0 :: (store 4)
; CHECK: VSTRS [[VREG]], [[PTR]], 0, 14, $noreg ; CHECK: VSTRS [[VREG]], [[PTR]], 0, 14 /* CC::al */, $noreg
BX_RET 14, $noreg BX_RET 14, $noreg
; CHECK: BX_RET 14, $noreg ; CHECK: BX_RET 14 /* CC::al */, $noreg
... ...
--- ---
name: test_fpconst_8bit_s64 name: test_fpconst_8bit_s64
# CHECK-LABEL: name: test_fpconst_8bit_s64 # CHECK-LABEL: name: test_fpconst_8bit_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
%0(p0) = COPY $r0 %0(p0) = COPY $r0
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0 ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
%1(s64) = G_FCONSTANT double 5.0e-1 %1(s64) = G_FCONSTANT double 5.0e-1
; VFP3: [[VREG:%[0-9]+]]:dpr = FCONSTD 96, 14, $noreg ; VFP3: [[VREG:%[0-9]+]]:dpr = FCONSTD 96, 14 /* CC::al */, $noreg
; VFP2: [[VREG:%[0-9]+]]:dpr = VLDRD %const.0, 0, 14, $noreg :: (load 8 from constant-pool) ; VFP2: [[VREG:%[0-9]+]]:dpr = VLDRD %const.0, 0, 14 /* CC::al */, $noreg :: (load 8 from constant-pool)
G_STORE %1(s64), %0 :: (store 8) G_STORE %1(s64), %0 :: (store 8)
; CHECK: VSTRD [[VREG]], [[PTR]], 0, 14, $noreg ; CHECK: VSTRD [[VREG]], [[PTR]], 0, 14 /* CC::al */, $noreg
BX_RET 14, $noreg BX_RET 14, $noreg
; CHECK: BX_RET 14, $noreg ; CHECK: BX_RET 14 /* CC::al */, $noreg
... ...

llvm/test/CodeGen/ARM/GlobalISel/select-fp.mir

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Lines bb.0:
%2(p0) = COPY $r0 %2(p0) = COPY $r0
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0 ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_TRUNC %0(s64) %1(s32) = G_TRUNC %0(s64)
; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr, [[UNINTERESTING:%[0-9]+]]:gpr = VMOVRRD [[VREG]] ; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr, [[UNINTERESTING:%[0-9]+]]:gpr = VMOVRRD [[VREG]]
G_STORE %1(s32), %2 :: (store 4) G_STORE %1(s32), %2 :: (store 4)
; CHECK: STRi12 [[VREGTRUNC]], [[PTR]], 0, 14, $noreg ; CHECK: STRi12 [[VREGTRUNC]], [[PTR]], 0, 14 /* CC::al */, $noreg
BX_RET 14, $noreg BX_RET 14, $noreg
; CHECK: BX_RET 14, $noreg ; CHECK: BX_RET 14 /* CC::al */, $noreg
... ...
--- ---
name: test_fadd_s32 name: test_fadd_s32
# CHECK-LABEL: name: test_fadd_s32 # CHECK-LABEL: name: test_fadd_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: fprb } - { id: 2, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: $s0, $s1 liveins: $s0, $s1
%0(s32) = COPY $s0 %0(s32) = COPY $s0
; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s32) = COPY $s1 %1(s32) = COPY $s1
; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1 ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1
%2(s32) = G_FADD %0, %1 %2(s32) = G_FADD %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:spr = VADDS [[VREGX]], [[VREGY]], 14, $noreg ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VADDS [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg
$s0 = COPY %2(s32) $s0 = COPY %2(s32)
; CHECK: $s0 = COPY [[VREGSUM]] ; CHECK: $s0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $s0 BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0
... ...
--- ---
name: test_fadd_s64 name: test_fadd_s64
# CHECK-LABEL: name: test_fadd_s64 # CHECK-LABEL: name: test_fadd_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: fprb } - { id: 2, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: $d0, $d1 liveins: $d0, $d1
%0(s64) = COPY $d0 %0(s64) = COPY $d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s64) = COPY $d1 %1(s64) = COPY $d1
; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1 ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1
%2(s64) = G_FADD %0, %1 %2(s64) = G_FADD %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VADDD [[VREGX]], [[VREGY]], 14, $noreg ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VADDD [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg
$d0 = COPY %2(s64) $d0 = COPY %2(s64)
; CHECK: $d0 = COPY [[VREGSUM]] ; CHECK: $d0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $d0 BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0
... ...
--- ---
name: test_fsub_s32 name: test_fsub_s32
# CHECK-LABEL: name: test_fsub_s32 # CHECK-LABEL: name: test_fsub_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: fprb } - { id: 2, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: $s0, $s1 liveins: $s0, $s1
%0(s32) = COPY $s0 %0(s32) = COPY $s0
; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s32) = COPY $s1 %1(s32) = COPY $s1
; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1 ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1
%2(s32) = G_FSUB %0, %1 %2(s32) = G_FSUB %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:spr = VSUBS [[VREGX]], [[VREGY]], 14, $noreg ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VSUBS [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg
$s0 = COPY %2(s32) $s0 = COPY %2(s32)
; CHECK: $s0 = COPY [[VREGSUM]] ; CHECK: $s0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $s0 BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0
... ...
--- ---
name: test_fsub_s64 name: test_fsub_s64
# CHECK-LABEL: name: test_fsub_s64 # CHECK-LABEL: name: test_fsub_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: fprb } - { id: 2, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: $d0, $d1 liveins: $d0, $d1
%0(s64) = COPY $d0 %0(s64) = COPY $d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s64) = COPY $d1 %1(s64) = COPY $d1
; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1 ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1
%2(s64) = G_FSUB %0, %1 %2(s64) = G_FSUB %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VSUBD [[VREGX]], [[VREGY]], 14, $noreg ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VSUBD [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg
$d0 = COPY %2(s64) $d0 = COPY %2(s64)
; CHECK: $d0 = COPY [[VREGSUM]] ; CHECK: $d0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $d0 BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0
... ...
--- ---
name: test_fmul_s32 name: test_fmul_s32
# CHECK-LABEL: name: test_fmul_s32 # CHECK-LABEL: name: test_fmul_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: fprb } - { id: 2, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: $s0, $s1 liveins: $s0, $s1
%0(s32) = COPY $s0 %0(s32) = COPY $s0
; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s32) = COPY $s1 %1(s32) = COPY $s1
; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1 ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1
%2(s32) = G_FMUL %0, %1 %2(s32) = G_FMUL %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:spr = VMULS [[VREGX]], [[VREGY]], 14, $noreg ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VMULS [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg
$s0 = COPY %2(s32) $s0 = COPY %2(s32)
; CHECK: $s0 = COPY [[VREGSUM]] ; CHECK: $s0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $s0 BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0
... ...
--- ---
name: test_fmul_s64 name: test_fmul_s64
# CHECK-LABEL: name: test_fmul_s64 # CHECK-LABEL: name: test_fmul_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: fprb } - { id: 2, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: $d0, $d1 liveins: $d0, $d1
%0(s64) = COPY $d0 %0(s64) = COPY $d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s64) = COPY $d1 %1(s64) = COPY $d1
; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1 ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1
%2(s64) = G_FMUL %0, %1 %2(s64) = G_FMUL %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VMULD [[VREGX]], [[VREGY]], 14, $noreg ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VMULD [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg
$d0 = COPY %2(s64) $d0 = COPY %2(s64)
; CHECK: $d0 = COPY [[VREGSUM]] ; CHECK: $d0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $d0 BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0
... ...
--- ---
name: test_fdiv_s32 name: test_fdiv_s32
# CHECK-LABEL: name: test_fdiv_s32 # CHECK-LABEL: name: test_fdiv_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: fprb } - { id: 2, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: $s0, $s1 liveins: $s0, $s1
%0(s32) = COPY $s0 %0(s32) = COPY $s0
; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s32) = COPY $s1 %1(s32) = COPY $s1
; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1 ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1
%2(s32) = G_FDIV %0, %1 %2(s32) = G_FDIV %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:spr = VDIVS [[VREGX]], [[VREGY]], 14, $noreg ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VDIVS [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg
$s0 = COPY %2(s32) $s0 = COPY %2(s32)
; CHECK: $s0 = COPY [[VREGSUM]] ; CHECK: $s0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $s0 BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0
... ...
--- ---
name: test_fdiv_s64 name: test_fdiv_s64
# CHECK-LABEL: name: test_fdiv_s64 # CHECK-LABEL: name: test_fdiv_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: fprb } - { id: 2, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: $d0, $d1 liveins: $d0, $d1
%0(s64) = COPY $d0 %0(s64) = COPY $d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s64) = COPY $d1 %1(s64) = COPY $d1
; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1 ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1
%2(s64) = G_FDIV %0, %1 %2(s64) = G_FDIV %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VDIVD [[VREGX]], [[VREGY]], 14, $noreg ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VDIVD [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg
$d0 = COPY %2(s64) $d0 = COPY %2(s64)
; CHECK: $d0 = COPY [[VREGSUM]] ; CHECK: $d0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $d0 BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0
... ...
--- ---
name: test_fneg_s32 name: test_fneg_s32
# CHECK-LABEL: name: test_fneg_s32 # CHECK-LABEL: name: test_fneg_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: $s0 liveins: $s0
%0(s32) = COPY $s0 %0(s32) = COPY $s0
; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s32) = G_FNEG %0 %1(s32) = G_FNEG %0
; CHECK: [[VREGSUM:%[0-9]+]]:spr = VNEGS [[VREGX]], 14, $noreg ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VNEGS [[VREGX]], 14 /* CC::al */, $noreg
$s0 = COPY %1(s32) $s0 = COPY %1(s32)
; CHECK: $s0 = COPY [[VREGSUM]] ; CHECK: $s0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $s0 BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0
... ...
--- ---
name: test_fneg_s64 name: test_fneg_s64
# CHECK-LABEL: name: test_fneg_s64 # CHECK-LABEL: name: test_fneg_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: fprb } - { id: 2, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: $d0 liveins: $d0
%0(s64) = COPY $d0 %0(s64) = COPY $d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s64) = G_FNEG %0 %1(s64) = G_FNEG %0
; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VNEGD [[VREGX]], 14, $noreg ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VNEGD [[VREGX]], 14 /* CC::al */, $noreg
$d0 = COPY %1(s64) $d0 = COPY %1(s64)
; CHECK: $d0 = COPY [[VREGSUM]] ; CHECK: $d0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $d0 BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0
... ...
--- ---
name: test_fma_s32 name: test_fma_s32
# CHECK-LABEL: name: test_fma_s32 # CHECK-LABEL: name: test_fma_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
Show All 11 Lines bb.0:
%1(s32) = COPY $s1 %1(s32) = COPY $s1
; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1 ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1
%2(s32) = COPY $s2 %2(s32) = COPY $s2
; CHECK: [[VREGZ:%[0-9]+]]:spr = COPY $s2 ; CHECK: [[VREGZ:%[0-9]+]]:spr = COPY $s2
%3(s32) = G_FMA %0, %1, %2 %3(s32) = G_FMA %0, %1, %2
; CHECK: [[VREGR:%[0-9]+]]:spr = VFMAS [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg ; CHECK: [[VREGR:%[0-9]+]]:spr = VFMAS [[VREGZ]], [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg
$s0 = COPY %3(s32) $s0 = COPY %3(s32)
; CHECK: $s0 = COPY [[VREGR]] ; CHECK: $s0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $s0 BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0
... ...
--- ---
name: test_fma_s64 name: test_fma_s64
# CHECK-LABEL: name: test_fma_s64 # CHECK-LABEL: name: test_fma_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
Show All 11 Lines bb.0:
%1(s64) = COPY $d1 %1(s64) = COPY $d1
; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1 ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1
%2(s64) = COPY $d2 %2(s64) = COPY $d2
; CHECK: [[VREGZ:%[0-9]+]]:dpr = COPY $d2 ; CHECK: [[VREGZ:%[0-9]+]]:dpr = COPY $d2
%3(s64) = G_FMA %0, %1, %2 %3(s64) = G_FMA %0, %1, %2
; CHECK: [[VREGR:%[0-9]+]]:dpr = VFMAD [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg ; CHECK: [[VREGR:%[0-9]+]]:dpr = VFMAD [[VREGZ]], [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg
$d0 = COPY %3(s64) $d0 = COPY %3(s64)
; CHECK: $d0 = COPY [[VREGR]] ; CHECK: $d0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $d0 BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0
... ...
--- ---
name: test_fpext_s32_to_s64 name: test_fpext_s32_to_s64
# CHECK-LABEL: name: test_fpext_s32_to_s64 # CHECK-LABEL: name: test_fpext_s32_to_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: $s0 liveins: $s0
%0(s32) = COPY $s0 %0(s32) = COPY $s0
; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s64) = G_FPEXT %0(s32) %1(s64) = G_FPEXT %0(s32)
; CHECK: [[VREGR:%[0-9]+]]:dpr = VCVTDS [[VREGX]], 14, $noreg ; CHECK: [[VREGR:%[0-9]+]]:dpr = VCVTDS [[VREGX]], 14 /* CC::al */, $noreg
$d0 = COPY %1(s64) $d0 = COPY %1(s64)
; CHECK: $d0 = COPY [[VREGR]] ; CHECK: $d0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $d0 BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0
... ...
--- ---
name: test_fptrunc_s64_to_s32 name: test_fptrunc_s64_to_s32
# CHECK-LABEL: name: test_fptrunc_s64_to_s32 # CHECK-LABEL: name: test_fptrunc_s64_to_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: $d0 liveins: $d0
%0(s64) = COPY $d0 %0(s64) = COPY $d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s32) = G_FPTRUNC %0(s64) %1(s32) = G_FPTRUNC %0(s64)
; CHECK: [[VREGR:%[0-9]+]]:spr = VCVTSD [[VREGX]], 14, $noreg ; CHECK: [[VREGR:%[0-9]+]]:spr = VCVTSD [[VREGX]], 14 /* CC::al */, $noreg
$s0 = COPY %1(s32) $s0 = COPY %1(s32)
; CHECK: $s0 = COPY [[VREGR]] ; CHECK: $s0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $s0 BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0
... ...
--- ---
name: test_fptosi_s32 name: test_fptosi_s32
# CHECK-LABEL: name: test_fptosi_s32 # CHECK-LABEL: name: test_fptosi_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $s0 liveins: $s0
%0(s32) = COPY $s0 %0(s32) = COPY $s0
; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s32) = G_FPTOSI %0(s32) %1(s32) = G_FPTOSI %0(s32)
; CHECK: [[VREGI:%[0-9]+]]:spr = VTOSIZS [[VREGX]], 14, $noreg ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOSIZS [[VREGX]], 14 /* CC::al */, $noreg
; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]] ; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]]
$r0 = COPY %1(s32) $r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[VREGR]] ; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_fptosi_s64 name: test_fptosi_s64
# CHECK-LABEL: name: test_fptosi_s64 # CHECK-LABEL: name: test_fptosi_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $d0 liveins: $d0
%0(s64) = COPY $d0 %0(s64) = COPY $d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s32) = G_FPTOSI %0(s64) %1(s32) = G_FPTOSI %0(s64)
; CHECK: [[VREGI:%[0-9]+]]:spr = VTOSIZD [[VREGX]], 14, $noreg ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOSIZD [[VREGX]], 14 /* CC::al */, $noreg
; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]] ; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]]
$r0 = COPY %1(s32) $r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[VREGR]] ; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_fptoui_s32 name: test_fptoui_s32
# CHECK-LABEL: name: test_fptoui_s32 # CHECK-LABEL: name: test_fptoui_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $s0 liveins: $s0
%0(s32) = COPY $s0 %0(s32) = COPY $s0
; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s32) = G_FPTOUI %0(s32) %1(s32) = G_FPTOUI %0(s32)
; CHECK: [[VREGI:%[0-9]+]]:spr = VTOUIZS [[VREGX]], 14, $noreg ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOUIZS [[VREGX]], 14 /* CC::al */, $noreg
; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]] ; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]]
$r0 = COPY %1(s32) $r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[VREGR]] ; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_fptoui_s64 name: test_fptoui_s64
# CHECK-LABEL: name: test_fptoui_s64 # CHECK-LABEL: name: test_fptoui_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $d0 liveins: $d0
%0(s64) = COPY $d0 %0(s64) = COPY $d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s32) = G_FPTOUI %0(s64) %1(s32) = G_FPTOUI %0(s64)
; CHECK: [[VREGI:%[0-9]+]]:spr = VTOUIZD [[VREGX]], 14, $noreg ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOUIZD [[VREGX]], 14 /* CC::al */, $noreg
; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]] ; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]]
$r0 = COPY %1(s32) $r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[VREGR]] ; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_sitofp_s32 name: test_sitofp_s32
# CHECK-LABEL: name: test_sitofp_s32 # CHECK-LABEL: name: test_sitofp_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_SITOFP %0(s32) %1(s32) = G_SITOFP %0(s32)
; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]] ; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]]
; CHECK: [[VREGR:%[0-9]+]]:spr = VSITOS [[VREGF]], 14, $noreg ; CHECK: [[VREGR:%[0-9]+]]:spr = VSITOS [[VREGF]], 14 /* CC::al */, $noreg
$s0 = COPY %1(s32) $s0 = COPY %1(s32)
; CHECK: $s0 = COPY [[VREGR]] ; CHECK: $s0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $s0 BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0
... ...
--- ---
name: test_sitofp_s64 name: test_sitofp_s64
# CHECK-LABEL: name: test_sitofp_s64 # CHECK-LABEL: name: test_sitofp_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s64) = G_SITOFP %0(s32) %1(s64) = G_SITOFP %0(s32)
; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]] ; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]]
; CHECK: [[VREGR:%[0-9]+]]:dpr = VSITOD [[VREGF]], 14, $noreg ; CHECK: [[VREGR:%[0-9]+]]:dpr = VSITOD [[VREGF]], 14 /* CC::al */, $noreg
$d0 = COPY %1(s64) $d0 = COPY %1(s64)
; CHECK: $d0 = COPY [[VREGR]] ; CHECK: $d0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $d0 BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0
... ...
--- ---
name: test_uitofp_s32 name: test_uitofp_s32
# CHECK-LABEL: name: test_uitofp_s32 # CHECK-LABEL: name: test_uitofp_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_UITOFP %0(s32) %1(s32) = G_UITOFP %0(s32)
; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]] ; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]]
; CHECK: [[VREGR:%[0-9]+]]:spr = VUITOS [[VREGF]], 14, $noreg ; CHECK: [[VREGR:%[0-9]+]]:spr = VUITOS [[VREGF]], 14 /* CC::al */, $noreg
$s0 = COPY %1(s32) $s0 = COPY %1(s32)
; CHECK: $s0 = COPY [[VREGR]] ; CHECK: $s0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $s0 BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0
... ...
--- ---
name: test_uitofp_s64 name: test_uitofp_s64
# CHECK-LABEL: name: test_uitofp_s64 # CHECK-LABEL: name: test_uitofp_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s64) = G_UITOFP %0(s32) %1(s64) = G_UITOFP %0(s32)
; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]] ; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]]
; CHECK: [[VREGR:%[0-9]+]]:dpr = VUITOD [[VREGF]], 14, $noreg ; CHECK: [[VREGR:%[0-9]+]]:dpr = VUITOD [[VREGF]], 14 /* CC::al */, $noreg
$d0 = COPY %1(s64) $d0 = COPY %1(s64)
; CHECK: $d0 = COPY [[VREGR]] ; CHECK: $d0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $d0 BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0
... ...
--- ---
name: test_load_f32 name: test_load_f32
# CHECK-LABEL: name: test_load_f32 # CHECK-LABEL: name: test_load_f32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
%0(p0) = COPY $r0 %0(p0) = COPY $r0
; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0 ; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0
%1(s32) = G_LOAD %0(p0) :: (load 4) %1(s32) = G_LOAD %0(p0) :: (load 4)
; CHECK: %[[V:[0-9]+]]:spr = VLDRS %[[P]], 0, 14, $noreg ; CHECK: %[[V:[0-9]+]]:spr = VLDRS %[[P]], 0, 14 /* CC::al */, $noreg
$s0 = COPY %1 $s0 = COPY %1
; CHECK: $s0 = COPY %[[V]] ; CHECK: $s0 = COPY %[[V]]
BX_RET 14, $noreg, implicit $s0 BX_RET 14, $noreg, implicit $s0
; CHECK: BX_RET 14, $noreg, implicit $s0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0
... ...
--- ---
name: test_load_f64 name: test_load_f64
# CHECK-LABEL: name: test_load_f64 # CHECK-LABEL: name: test_load_f64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
%0(p0) = COPY $r0 %0(p0) = COPY $r0
; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0 ; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0
%1(s64) = G_LOAD %0(p0) :: (load 8) %1(s64) = G_LOAD %0(p0) :: (load 8)
; CHECK: %[[V:[0-9]+]]:dpr = VLDRD %[[P]], 0, 14, $noreg ; CHECK: %[[V:[0-9]+]]:dpr = VLDRD %[[P]], 0, 14 /* CC::al */, $noreg
$d0 = COPY %1 $d0 = COPY %1
; CHECK: $d0 = COPY %[[V]] ; CHECK: $d0 = COPY %[[V]]
BX_RET 14, $noreg, implicit $d0 BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0
... ...
--- ---
name: test_stores name: test_stores
# CHECK-LABEL: name: test_stores # CHECK-LABEL: name: test_stores
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: fprb } - { id: 2, class: fprb }
# CHECK: id: [[P:[0-9]+]], class: gpr # CHECK: id: [[P:[0-9]+]], class: gpr
# CHECK: id: [[F32:[0-9]+]], class: spr # CHECK: id: [[F32:[0-9]+]], class: spr
# CHECK: id: [[F64:[0-9]+]], class: dpr # CHECK: id: [[F64:[0-9]+]], class: dpr
body: | body: |
bb.0: bb.0:
liveins: $r0, $s0, $d0 liveins: $r0, $s0, $d0
%0(p0) = COPY $r0 %0(p0) = COPY $r0
%1(s32) = COPY $s0 %1(s32) = COPY $s0
%2(s64) = COPY $d2 %2(s64) = COPY $d2
G_STORE %1(s32), %0(p0) :: (store 4) G_STORE %1(s32), %0(p0) :: (store 4)
; CHECK: VSTRS %[[F32]], %[[P]], 0, 14, $noreg ; CHECK: VSTRS %[[F32]], %[[P]], 0, 14 /* CC::al */, $noreg
G_STORE %2(s64), %0(p0) :: (store 8) G_STORE %2(s64), %0(p0) :: (store 8)
; CHECK: VSTRD %[[F64]], %[[P]], 0, 14, $noreg ; CHECK: VSTRD %[[F64]], %[[P]], 0, 14 /* CC::al */, $noreg
BX_RET 14, $noreg BX_RET 14, $noreg
... ...
--- ---
name: test_phi_s64 name: test_phi_s64
# CHECK-LABEL: name: test_phi_s64 # CHECK-LABEL: name: test_phi_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
Show All 31 Lines ; CHECK: [[BB2:bb.1]]:
; CHECK: B %bb.2 ; CHECK: B %bb.2
bb.2: bb.2:
; CHECK: bb.2 ; CHECK: bb.2
%4(s64) = G_PHI %2(s64), %bb.0, %3(s64), %bb.1 %4(s64) = G_PHI %2(s64), %bb.0, %3(s64), %bb.1
; CHECK: {{%[0-9]+}}:dpr = PHI [[V1]], %[[BB1]], [[V2]], %[[BB2]] ; CHECK: {{%[0-9]+}}:dpr = PHI [[V1]], %[[BB1]], [[V2]], %[[BB2]]
$d0 = COPY %4(s64) $d0 = COPY %4(s64)
BX_RET 14, $noreg, implicit $d0 BX_RET 14 /* CC::al */, $noreg, implicit $d0
... ...
--- ---
name: test_soft_fp_double name: test_soft_fp_double
# CHECK-LABEL: name: test_soft_fp_double # CHECK-LABEL: name: test_soft_fp_double
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
Show All 21 Lines bb.0:
$r0 = COPY %3 $r0 = COPY %3
; CHECK: $r0 = COPY [[OUT1]] ; CHECK: $r0 = COPY [[OUT1]]
$r1 = COPY %4 $r1 = COPY %4
; CHECK: $r1 = COPY [[OUT2]] ; CHECK: $r1 = COPY [[OUT2]]
BX_RET 14, $noreg, implicit $r0, implicit $r1 BX_RET 14, $noreg, implicit $r0, implicit $r1
; CHECK: BX_RET 14, $noreg, implicit $r0, implicit $r1 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
... ...

llvm/test/CodeGen/ARM/GlobalISel/select-neon.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple arm-- -mattr=+neon -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -O0 -mtriple arm-- -mattr=+neon -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- | --- |
define void @test_add_s64() { ret void } define void @test_add_s64() { ret void }
define void @test_sub_s64() { ret void } define void @test_sub_s64() { ret void }
... ...
--- ---
name: test_add_s64 name: test_add_s64
# CHECK-LABEL: name: test_add_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: fprb } - { id: 2, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: $d0, $d1 liveins: $d0, $d1
; CHECK-LABEL: name: test_add_s64
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
; CHECK: [[VADDv1i64_:%[0-9]+]]:dpr = VADDv1i64 [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
; CHECK: $d0 = COPY [[VADDv1i64_]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0
%0(s64) = COPY $d0 %0(s64) = COPY $d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s64) = COPY $d1 %1(s64) = COPY $d1
; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1
%2(s64) = G_ADD %0, %1 %2(s64) = G_ADD %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VADDv1i64 [[VREGX]], [[VREGY]], 14, $noreg
$d0 = COPY %2(s64) $d0 = COPY %2(s64)
; CHECK: $d0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $d0 BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0
... ...
--- ---
name: test_sub_s64 name: test_sub_s64
# CHECK-LABEL: name: test_sub_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: fprb } - { id: 2, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: $d0, $d1 liveins: $d0, $d1
; CHECK-LABEL: name: test_sub_s64
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
; CHECK: [[VSUBv1i64_:%[0-9]+]]:dpr = VSUBv1i64 [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
; CHECK: $d0 = COPY [[VSUBv1i64_]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0
%0(s64) = COPY $d0 %0(s64) = COPY $d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s64) = COPY $d1 %1(s64) = COPY $d1
; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1
%2(s64) = G_SUB %0, %1 %2(s64) = G_SUB %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VSUBv1i64 [[VREGX]], [[VREGY]], 14, $noreg
$d0 = COPY %2(s64) $d0 = COPY %2(s64)
; CHECK: $d0 = COPY [[VREGSUM]]
BX_RET 14, $noreg, implicit $d0 BX_RET 14, $noreg, implicit $d0
; CHECK: BX_RET 14, $noreg, implicit $d0

llvm/test/CodeGen/ARM/GlobalISel/select-pkhbt.mir

Show All 40 Lines bb.0:
%3(s32) = G_AND %0, %2 %3(s32) = G_AND %0, %2
%4(s32) = G_CONSTANT i32 7 %4(s32) = G_CONSTANT i32 7
%5(s32) = G_SHL %1, %4 %5(s32) = G_SHL %1, %4
%6(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000 %6(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
%7(s32) = G_AND %5, %6 %7(s32) = G_AND %5, %6
%8(s32) = G_OR %3, %7 %8(s32) = G_OR %3, %7
; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 7, 14, $noreg ; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 7, 14 /* CC::al */, $noreg
; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHBT [[VREGX]], [[VREGY]], 7, 14, $noreg ; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHBT [[VREGX]], [[VREGY]], 7, 14 /* CC::al */, $noreg
$r0 = COPY %8(s32) $r0 = COPY %8(s32)
; CHECK: $r0 = COPY [[VREGR]] ; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_pkhbt_commutative name: test_pkhbt_commutative
# CHECK-LABEL: name: test_pkhbt_commutative # CHECK-LABEL: name: test_pkhbt_commutative
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
Show All 22 Lines bb.0:
%3(s32) = G_AND %0, %2 %3(s32) = G_AND %0, %2
%4(s32) = G_CONSTANT i32 7 %4(s32) = G_CONSTANT i32 7
%5(s32) = G_SHL %1, %4 %5(s32) = G_SHL %1, %4
%6(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000 %6(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
%7(s32) = G_AND %5, %6 %7(s32) = G_AND %5, %6
%8(s32) = G_OR %7, %3 %8(s32) = G_OR %7, %3
; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 7, 14, $noreg ; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 7, 14 /* CC::al */, $noreg
; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHBT [[VREGX]], [[VREGY]], 7, 14, $noreg ; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHBT [[VREGX]], [[VREGY]], 7, 14 /* CC::al */, $noreg
$r0 = COPY %8(s32) $r0 = COPY %8(s32)
; CHECK: $r0 = COPY [[VREGR]] ; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_pkhbt_imm16_31 name: test_pkhbt_imm16_31
# CHECK-LABEL: name: test_pkhbt_imm16_31 # CHECK-LABEL: name: test_pkhbt_imm16_31
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
Show All 18 Lines bb.0:
%2(s32) = G_CONSTANT i32 65535 ; 0xFFFF %2(s32) = G_CONSTANT i32 65535 ; 0xFFFF
%3(s32) = G_AND %0, %2 %3(s32) = G_AND %0, %2
%4(s32) = G_CONSTANT i32 17 %4(s32) = G_CONSTANT i32 17
%5(s32) = G_SHL %1, %4 %5(s32) = G_SHL %1, %4
%6(s32) = G_OR %3, %5 %6(s32) = G_OR %3, %5
; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 17, 14, $noreg ; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 17, 14 /* CC::al */, $noreg
; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHBT [[VREGX]], [[VREGY]], 17, 14, $noreg ; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHBT [[VREGX]], [[VREGY]], 17, 14 /* CC::al */, $noreg
$r0 = COPY %6(s32) $r0 = COPY %6(s32)
; CHECK: $r0 = COPY [[VREGR]] ; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_pkhbt_unshifted name: test_pkhbt_unshifted
# CHECK-LABEL: name: test_pkhbt_unshifted # CHECK-LABEL: name: test_pkhbt_unshifted
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
Show All 18 Lines bb.0:
%2(s32) = G_CONSTANT i32 65535 ; 0xFFFF %2(s32) = G_CONSTANT i32 65535 ; 0xFFFF
%3(s32) = G_AND %0, %2 %3(s32) = G_AND %0, %2
%4(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000 %4(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
%5(s32) = G_AND %1, %4 %5(s32) = G_AND %1, %4
%6(s32) = G_OR %3, %5 %6(s32) = G_OR %3, %5
; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 0, 14, $noreg ; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 0, 14 /* CC::al */, $noreg
; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHBT [[VREGX]], [[VREGY]], 0, 14, $noreg ; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHBT [[VREGX]], [[VREGY]], 0, 14 /* CC::al */, $noreg
$r0 = COPY %6(s32) $r0 = COPY %6(s32)
; CHECK: $r0 = COPY [[VREGR]] ; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_pkhtb_imm16 name: test_pkhtb_imm16
# CHECK-LABEL: name: test_pkhtb_imm16 # CHECK-LABEL: name: test_pkhtb_imm16
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
Show All 18 Lines bb.0:
%2(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000 %2(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
%3(s32) = G_AND %0, %2 %3(s32) = G_AND %0, %2
%4(s32) = G_CONSTANT i32 16 %4(s32) = G_CONSTANT i32 16
%5(s32) = G_LSHR %1, %4 %5(s32) = G_LSHR %1, %4
%6(s32) = G_OR %3, %5 %6(s32) = G_OR %3, %5
; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHTB [[VREGX]], [[VREGY]], 16, 14, $noreg ; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHTB [[VREGX]], [[VREGY]], 16, 14 /* CC::al */, $noreg
; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHTB [[VREGX]], [[VREGY]], 16, 14, $noreg ; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHTB [[VREGX]], [[VREGY]], 16, 14 /* CC::al */, $noreg
$r0 = COPY %6(s32) $r0 = COPY %6(s32)
; CHECK: $r0 = COPY [[VREGR]] ; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_pkhtb_imm1_15 name: test_pkhtb_imm1_15
# CHECK-LABEL: name: test_pkhtb_imm1_15 # CHECK-LABEL: name: test_pkhtb_imm1_15
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
Show All 22 Lines bb.0:
%3(s32) = G_AND %0, %2 %3(s32) = G_AND %0, %2
%4(s32) = G_CONSTANT i32 7 %4(s32) = G_CONSTANT i32 7
%5(s32) = G_LSHR %1, %4 %5(s32) = G_LSHR %1, %4
%6(s32) = G_CONSTANT i32 65535 ; 0xFFFF %6(s32) = G_CONSTANT i32 65535 ; 0xFFFF
%7(s32) = G_AND %5, %6 %7(s32) = G_AND %5, %6
%8(s32) = G_OR %3, %7 %8(s32) = G_OR %3, %7
; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHTB [[VREGX]], [[VREGY]], 7, 14, $noreg ; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHTB [[VREGX]], [[VREGY]], 7, 14 /* CC::al */, $noreg
; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHTB [[VREGX]], [[VREGY]], 7, 14, $noreg ; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHTB [[VREGX]], [[VREGY]], 7, 14 /* CC::al */, $noreg
$r0 = COPY %8(s32) $r0 = COPY %8(s32)
; CHECK: $r0 = COPY [[VREGR]] ; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...

llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple arm-gnueabihf -mattr=+vfp4 -run-pass=instruction-select -o - %s | FileCheck %s # RUN: llc -mtriple arm-gnueabihf -mattr=+vfp4 -run-pass=instruction-select -o - %s | FileCheck %s
--- | --- |
declare double @llvm.fma.f64(double, double, double) #0 declare double @llvm.fma.f64(double, double, double) #0
define double @vfnmsd(double %x, double %y, double %z) #1 { define double @vfnmsd(double %x, double %y, double %z) #1 {
%minus.y = fsub double -0.000000e+00, %y %minus.y = fsub double -0.000000e+00, %y
%fma = tail call double @llvm.fma.f64(double %x, double %minus.y, double %z) %fma = tail call double @llvm.fma.f64(double %x, double %minus.y, double %z)
%minus.fma = fsub double -0.000000e+00, %fma %minus.fma = fsub double -0.000000e+00, %fma
ret double %minus.fma ret double %minus.fma
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
declare void @llvm.stackprotector(i8*, i8**) #2 declare void @llvm.stackprotector(i8*, i8**) #2
attributes #0 = { nounwind readnone speculatable "target-features"="+vfp4" } attributes #0 = { nounwind readnone speculatable "target-features"="+vfp4" }
attributes #1 = { "target-features"="+vfp4" } attributes #1 = { "target-features"="+vfp4" }
attributes #2 = { nounwind } attributes #2 = { nounwind }
... ...
--- ---
name: vfnmsd name: vfnmsd
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: $d0, $d1, $d2 liveins: $d0, $d1, $d2
; CHECK-LABEL: name: vfnmsd
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:dpr = COPY $d2
; CHECK: [[VFNMSD:%[0-9]+]]:dpr = VFNMSD [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
; CHECK: $d0 = COPY [[VFNMSD]]
; CHECK: MOVPCLR 14 /* CC::al */, $noreg, implicit $d0
%0:fprb(s64) = COPY $d0 %0:fprb(s64) = COPY $d0
%1:fprb(s64) = COPY $d1 %1:fprb(s64) = COPY $d1
%2:fprb(s64) = COPY $d2 %2:fprb(s64) = COPY $d2
%3:fprb(s64) = G_FNEG %1 %3:fprb(s64) = G_FNEG %1
%4:fprb(s64) = G_FMA %0, %3, %2 %4:fprb(s64) = G_FMA %0, %3, %2
%5:fprb(s64) = G_FNEG %4 %5:fprb(s64) = G_FNEG %4
$d0 = COPY %5(s64) $d0 = COPY %5(s64)
MOVPCLR 14, $noreg, implicit $d0 MOVPCLR 14, $noreg, implicit $d0
# CHECK: %{{[0-9]+}}:dpr = VFNMSD %{{[0-9]+}}, %{{[0-9]+}}, %{{[0-9]+}}, 14, $noreg
... ...

llvm/test/CodeGen/ARM/GlobalISel/select-revsh.mir

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines bb.0:
%9(s32) = G_OR %4(s32), %8(s32) %9(s32) = G_OR %4(s32), %8(s32)
; ARM: [[VREGR:%[0-9]+]]:gpr = REVSH [[VREGX]] ; ARM: [[VREGR:%[0-9]+]]:gpr = REVSH [[VREGX]]
; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2REVSH [[VREGX]] ; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2REVSH [[VREGX]]
$r0 = COPY %9(s32) $r0 = COPY %9(s32)
; CHECK: $r0 = COPY [[VREGR]] ; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_shifts_to_revsh_commutative name: test_shifts_to_revsh_commutative
# CHECK-LABEL: name: test_shifts_to_revsh_commutative # CHECK-LABEL: name: test_shifts_to_revsh_commutative
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
Show All 31 Lines bb.0:
%9(s32) = G_OR %8(s32), %4(s32) %9(s32) = G_OR %8(s32), %4(s32)
; ARM: [[VREGR:%[0-9]+]]:gpr = REVSH [[VREGX]] ; ARM: [[VREGR:%[0-9]+]]:gpr = REVSH [[VREGX]]
; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2REVSH [[VREGX]] ; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2REVSH [[VREGX]]
$r0 = COPY %9(s32) $r0 = COPY %9(s32)
; CHECK: $r0 = COPY [[VREGR]] ; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_shifts_no_revsh_constants name: test_shifts_no_revsh_constants
# CHECK-LABEL: name: test_shifts_no_revsh_constants # CHECK-LABEL: name: test_shifts_no_revsh_constants
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
Show All 37 Lines

llvm/test/CodeGen/ARM/GlobalISel/thumb-instruction-select-cmp.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- | --- |
define void @test_icmp_eq_s32() { ret void } define void @test_icmp_eq_s32() { ret void }
define void @test_icmp_ne_s32() { ret void } define void @test_icmp_ne_s32() { ret void }
define void @test_icmp_ugt_s32() { ret void } define void @test_icmp_ugt_s32() { ret void }
define void @test_icmp_uge_s32() { ret void } define void @test_icmp_uge_s32() { ret void }
define void @test_icmp_ult_s32() { ret void } define void @test_icmp_ult_s32() { ret void }
define void @test_icmp_ule_s32() { ret void } define void @test_icmp_ule_s32() { ret void }
Show All 14 Linesregisters:
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_eq_s32 ; CHECK-LABEL: name: test_icmp_eq_s32
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14, $noreg, $noreg ; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[MOVi]], 1, 0, $cpsr ; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 0 /* CC::eq */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:rgpr = t2ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[t2ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(eq), %0(s32), %1 %2(s1) = G_ICMP intpred(eq), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_icmp_ne_s32 name: test_icmp_ne_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_ne_s32 ; CHECK-LABEL: name: test_icmp_ne_s32
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14, $noreg, $noreg ; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[MOVi]], 1, 1, $cpsr ; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 1 /* CC::ne */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:rgpr = t2ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[t2ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(ne), %0(s32), %1 %2(s1) = G_ICMP intpred(ne), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_icmp_ugt_s32 name: test_icmp_ugt_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_ugt_s32 ; CHECK-LABEL: name: test_icmp_ugt_s32
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14, $noreg, $noreg ; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[MOVi]], 1, 8, $cpsr ; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 8 /* CC::hi */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:rgpr = t2ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[t2ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(ugt), %0(s32), %1 %2(s1) = G_ICMP intpred(ugt), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_icmp_uge_s32 name: test_icmp_uge_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_uge_s32 ; CHECK-LABEL: name: test_icmp_uge_s32
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14, $noreg, $noreg ; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[MOVi]], 1, 2, $cpsr ; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 2 /* CC::hs */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:rgpr = t2ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[t2ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(uge), %0(s32), %1 %2(s1) = G_ICMP intpred(uge), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_icmp_ult_s32 name: test_icmp_ult_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_ult_s32 ; CHECK-LABEL: name: test_icmp_ult_s32
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14, $noreg, $noreg ; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[MOVi]], 1, 3, $cpsr ; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 3 /* CC::lo */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:rgpr = t2ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[t2ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(ult), %0(s32), %1 %2(s1) = G_ICMP intpred(ult), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_icmp_ule_s32 name: test_icmp_ule_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_ule_s32 ; CHECK-LABEL: name: test_icmp_ule_s32
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14, $noreg, $noreg ; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[MOVi]], 1, 9, $cpsr ; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 9 /* CC::ls */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:rgpr = t2ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[t2ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(ule), %0(s32), %1 %2(s1) = G_ICMP intpred(ule), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_icmp_sgt_s32 name: test_icmp_sgt_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_sgt_s32 ; CHECK-LABEL: name: test_icmp_sgt_s32
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14, $noreg, $noreg ; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[MOVi]], 1, 12, $cpsr ; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 12 /* CC::gt */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:rgpr = t2ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[t2ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(sgt), %0(s32), %1 %2(s1) = G_ICMP intpred(sgt), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_icmp_sge_s32 name: test_icmp_sge_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_sge_s32 ; CHECK-LABEL: name: test_icmp_sge_s32
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14, $noreg, $noreg ; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[MOVi]], 1, 10, $cpsr ; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 10 /* CC::ge */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:rgpr = t2ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[t2ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(sge), %0(s32), %1 %2(s1) = G_ICMP intpred(sge), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_icmp_slt_s32 name: test_icmp_slt_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_slt_s32 ; CHECK-LABEL: name: test_icmp_slt_s32
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14, $noreg, $noreg ; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[MOVi]], 1, 11, $cpsr ; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 11 /* CC::lt */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:rgpr = t2ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[t2ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(slt), %0(s32), %1 %2(s1) = G_ICMP intpred(slt), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_icmp_sle_s32 name: test_icmp_sle_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_sle_s32 ; CHECK-LABEL: name: test_icmp_sle_s32
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14, $noreg, $noreg ; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[MOVi]], 1, 13, $cpsr ; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 13 /* CC::le */, $cpsr
; CHECK: [[ANDri:%[0-9]+]]:rgpr = t2ANDri [[MOVCCi]], 1, 14, $noreg, $noreg ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]] ; CHECK: $r0 = COPY [[t2ANDri]]
; CHECK: BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(sle), %0(s32), %1 %2(s1) = G_ICMP intpred(sle), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...

llvm/test/CodeGen/ARM/GlobalISel/thumb-select-arithmetic-ops.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2,+hwdiv -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2,+hwdiv -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- | --- |
define void @test_add_regs() { ret void } define void @test_add_regs() { ret void }
define void @test_add_fold_imm() { ret void } define void @test_add_fold_imm() { ret void }
define void @test_add_fold_imm12() { ret void } define void @test_add_fold_imm12() { ret void }
define void @test_add_no_fold_imm() { ret void } define void @test_add_no_fold_imm() { ret void }
define void @test_sub_imm_lhs() { ret void } define void @test_sub_imm_lhs() { ret void }
define void @test_sub_imm_rhs() { ret void } define void @test_sub_imm_rhs() { ret void }
define void @test_mul() { ret void } define void @test_mul() { ret void }
define void @test_mla() { ret void } define void @test_mla() { ret void }
define void @test_sdiv() { ret void } define void @test_sdiv() { ret void }
define void @test_udiv() { ret void } define void @test_udiv() { ret void }
... ...
--- ---
name: test_add_regs name: test_add_regs
# CHECK-LABEL: name: test_add_regs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_add_regs
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[t2ADDrr:%[0-9]+]]:gprnopc = t2ADDrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2ADDrr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
%2(s32) = G_ADD %0, %1 %2(s32) = G_ADD %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = t2ADDrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGRES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_add_fold_imm name: test_add_fold_imm
# CHECK-LABEL: name: test_add_fold_imm
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_add_fold_imm
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 786444, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2ADDri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
%1(s32) = G_CONSTANT i32 786444 ; 0x000c000c %1(s32) = G_CONSTANT i32 786444 ; 0x000c000c
%2(s32) = G_ADD %0, %1 %2(s32) = G_ADD %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2ADDri [[VREGX]], 786444, 14, $noreg, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGRES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_add_fold_imm12 name: test_add_fold_imm12
# CHECK-LABEL: name: test_add_fold_imm12
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_add_fold_imm12
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[t2ADDri12_:%[0-9]+]]:rgpr = t2ADDri12 [[COPY]], 4093, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[t2ADDri12_]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_CONSTANT i32 4093 %1(s32) = G_CONSTANT i32 4093
%2(s32) = G_ADD %0, %1 %2(s32) = G_ADD %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2ADDri12 [[VREGX]], 4093, 14, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGRES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_add_no_fold_imm name: test_add_no_fold_imm
# CHECK-LABEL: name: test_add_no_fold_imm
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_add_no_fold_imm
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm 185470479
; CHECK: [[t2ADDrr:%[0-9]+]]:gprnopc = t2ADDrr [[COPY]], [[t2MOVi32imm]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2ADDrr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
%1(s32) = G_CONSTANT i32 185470479 ; 0x0b0e0e0f %1(s32) = G_CONSTANT i32 185470479 ; 0x0b0e0e0f
; CHECK: [[VREGY:%[0-9]+]]:rgpr = t2MOVi32imm 185470479
%2(s32) = G_ADD %0, %1 %2(s32) = G_ADD %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = t2ADDrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGRES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_sub_imm_lhs name: test_sub_imm_lhs
# CHECK-LABEL: name: test_sub_imm_lhs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_sub_imm_lhs
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[t2RSBri:%[0-9]+]]:rgpr = t2RSBri [[COPY]], 786444, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2RSBri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
%1(s32) = G_CONSTANT i32 786444 ; 0x000c000c %1(s32) = G_CONSTANT i32 786444 ; 0x000c000c
%2(s32) = G_SUB %1, %0 %2(s32) = G_SUB %1, %0
; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2RSBri [[VREGX]], 786444, 14, $noreg, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGRES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_sub_imm_rhs name: test_sub_imm_rhs
# CHECK-LABEL: name: test_sub_imm_rhs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_sub_imm_rhs
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[COPY]], 786444, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2SUBri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
%1(s32) = G_CONSTANT i32 786444 ; 0x000c000c %1(s32) = G_CONSTANT i32 786444 ; 0x000c000c
%2(s32) = G_SUB %0, %1 %2(s32) = G_SUB %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2SUBri [[VREGX]], 786444, 14, $noreg, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGRES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_mul name: test_mul
# CHECK-LABEL: name: test_mul
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_mul
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[t2MUL:%[0-9]+]]:rgpr = t2MUL [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[t2MUL]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
%2(s32) = G_MUL %0, %1 %2(s32) = G_MUL %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2MUL [[VREGX]], [[VREGY]], 14, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGRES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_mla name: test_mla
# CHECK-LABEL: name: test_mla
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
- { id: 4, class: gprb } - { id: 4, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1, $r2 liveins: $r0, $r1, $r2
; CHECK-LABEL: name: test_mla
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY $r2
; CHECK: [[t2MLA:%[0-9]+]]:rgpr = t2MLA [[COPY]], [[COPY1]], [[COPY2]], 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[t2MLA]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
%2(s32) = COPY $r2 %2(s32) = COPY $r2
; CHECK: [[VREGZ:%[0-9]+]]:rgpr = COPY $r2
%3(s32) = G_MUL %0, %1 %3(s32) = G_MUL %0, %1
%4(s32) = G_ADD %3, %2 %4(s32) = G_ADD %3, %2
; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, $noreg
$r0 = COPY %4(s32) $r0 = COPY %4(s32)
; CHECK: $r0 = COPY [[VREGRES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_sdiv name: test_sdiv
# CHECK-LABEL: name: test_sdiv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_sdiv
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[t2SDIV:%[0-9]+]]:rgpr = t2SDIV [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[t2SDIV]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
%2(s32) = G_SDIV %0, %1 %2(s32) = G_SDIV %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2SDIV [[VREGX]], [[VREGY]], 14, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGRES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_udiv name: test_udiv
# CHECK-LABEL: name: test_udiv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_udiv
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[t2UDIV:%[0-9]+]]:rgpr = t2UDIV [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[t2UDIV]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
%2(s32) = G_UDIV %0, %1 %2(s32) = G_UDIV %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2UDIV [[VREGX]], [[VREGY]], 14, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGRES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...

llvm/test/CodeGen/ARM/GlobalISel/thumb-select-br.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- | --- |
define void @test_br() { ret void } define void @test_br() { ret void }
... ...
--- ---
name: test_br name: test_br
# CHECK-LABEL: name: test_br
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
body: | body: |
; CHECK-LABEL: name: test_br
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]]
; CHECK: t2TSTri [[COPY1]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2Bcc %bb.1, 1 /* CC::ne */, $cpsr
; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg
; CHECK: bb.1:
; CHECK: successors: %bb.2(0x80000000)
; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg
; CHECK: bb.2:
; CHECK: tBX_RET 14 /* CC::al */, $noreg
bb.0: bb.0:
; CHECK: bb.0
successors: %bb.1(0x40000000), %bb.2(0x40000000) successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $r0 liveins: $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[COND32:%[0-9]+]]:gpr = COPY $r0
%1(s1) = G_TRUNC %0(s32) %1(s1) = G_TRUNC %0(s32)
; CHECK: [[COND:%[0-9]+]]:rgpr = COPY [[COND32]]
G_BRCOND %1(s1), %bb.1 G_BRCOND %1(s1), %bb.1
; CHECK: t2TSTri [[COND]], 1, 14, $noreg, implicit-def $cpsr
; CHECK: t2Bcc %bb.1, 1, $cpsr
G_BR %bb.2 G_BR %bb.2
; CHECK: t2B %bb.2, 14, $noreg
bb.1: bb.1:
; CHECK: bb.1
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
G_BR %bb.2 G_BR %bb.2
; CHECK: t2B %bb.2, 14, $noreg
bb.2: bb.2:
; CHECK: bb.2
tBX_RET 14, $noreg tBX_RET 14, $noreg
; CHECK: tBX_RET 14, $noreg
... ...

llvm/test/CodeGen/ARM/GlobalISel/thumb-select-exts.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- | --- |
define void @test_trunc_and_zext_s1_to_s32() { ret void } define void @test_trunc_and_zext_s1_to_s32() { ret void }
define void @test_trunc_and_sext_s1_to_s32() { ret void } define void @test_trunc_and_sext_s1_to_s32() { ret void }
define void @test_trunc_and_anyext_s1_to_s32() { ret void } define void @test_trunc_and_anyext_s1_to_s32() { ret void }
define void @test_trunc_and_zext_s8_to_s32() { ret void } define void @test_trunc_and_zext_s8_to_s32() { ret void }
define void @test_trunc_and_sext_s8_to_s32() { ret void } define void @test_trunc_and_sext_s8_to_s32() { ret void }
Show All 12 Lines--- |
define void @test_trunc_and_anyext_s8_to_s16() { ret void } define void @test_trunc_and_anyext_s8_to_s16() { ret void }
define void @test_trunc_and_zext_s1_to_s8() { ret void } define void @test_trunc_and_zext_s1_to_s8() { ret void }
define void @test_trunc_and_sext_s1_to_s8() { ret void } define void @test_trunc_and_sext_s1_to_s8() { ret void }
define void @test_trunc_and_anyext_s1_to_s8() { ret void } define void @test_trunc_and_anyext_s1_to_s8() { ret void }
... ...
--- ---
name: test_trunc_and_zext_s1_to_s32 name: test_trunc_and_zext_s1_to_s32
# CHECK-LABEL: name: test_trunc_and_zext_s1_to_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_trunc_and_zext_s1_to_s32
; CHECK: liveins: $r0
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]]
; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY1]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2ANDri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
%1(s1) = G_TRUNC %0(s32) %1(s1) = G_TRUNC %0(s32)
%2(s32) = G_ZEXT %1(s1) %2(s32) = G_ZEXT %1(s1)
; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]]
; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2ANDri [[RVREG]], 1, 14, $noreg, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGEXT]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_trunc_and_sext_s1_to_s32 name: test_trunc_and_sext_s1_to_s32
# CHECK-LABEL: name: test_trunc_and_sext_s1_to_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_trunc_and_sext_s1_to_s32
; CHECK: liveins: $r0
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]]
; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY1]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[t2RSBri:%[0-9]+]]:rgpr = t2RSBri [[t2ANDri]], 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2RSBri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
%1(s1) = G_TRUNC %0(s32) %1(s1) = G_TRUNC %0(s32)
%2(s32) = G_SEXT %1(s1) %2(s32) = G_SEXT %1(s1)
; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]]
; CHECK: [[VREGAND:%[0-9]+]]:rgpr = t2ANDri [[RVREG]], 1, 14, $noreg, $noreg
; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2RSBri [[VREGAND]], 0, 14, $noreg, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGEXT]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_trunc_and_anyext_s1_to_s32 name: test_trunc_and_anyext_s1_to_s32
# CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s32
; CHECK: liveins: $r0
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: $r0 = COPY [[COPY]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
%1(s1) = G_TRUNC %0(s32) %1(s1) = G_TRUNC %0(s32)
%2(s32) = G_ANYEXT %1(s1) %2(s32) = G_ANYEXT %1(s1)
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREG]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_trunc_and_zext_s8_to_s32 name: test_trunc_and_zext_s8_to_s32
# CHECK-LABEL: name: test_trunc_and_zext_s8_to_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_trunc_and_zext_s8_to_s32
; CHECK: liveins: $r0
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]]
; CHECK: [[t2UXTB:%[0-9]+]]:rgpr = t2UXTB [[COPY1]], 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[t2UXTB]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
%1(s8) = G_TRUNC %0(s32) %1(s8) = G_TRUNC %0(s32)
; CHECK: [[VREGTRUNC:%[0-9]+]]:rgpr = COPY [[VREG]]
%2(s32) = G_ZEXT %1(s8) %2(s32) = G_ZEXT %1(s8)
; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2UXTB [[VREGTRUNC]], 0, 14, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGEXT]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_trunc_and_sext_s8_to_s32 name: test_trunc_and_sext_s8_to_s32
# CHECK-LABEL: name: test_trunc_and_sext_s8_to_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_trunc_and_sext_s8_to_s32
; CHECK: liveins: $r0
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]]
; CHECK: [[t2SXTB:%[0-9]+]]:rgpr = t2SXTB [[COPY1]], 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[t2SXTB]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
%1(s8) = G_TRUNC %0(s32) %1(s8) = G_TRUNC %0(s32)
; CHECK: [[VREGTRUNC:%[0-9]+]]:rgpr = COPY [[VREG]]
%2(s32) = G_SEXT %1(s8) %2(s32) = G_SEXT %1(s8)
; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2SXTB [[VREGTRUNC]], 0, 14, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGEXT]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_trunc_and_anyext_s8_to_s32 name: test_trunc_and_anyext_s8_to_s32
# CHECK-LABEL: name: test_trunc_and_anyext_s8_to_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_trunc_and_anyext_s8_to_s32
; CHECK: liveins: $r0
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: $r0 = COPY [[COPY]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
%1(s8) = G_TRUNC %0(s32) %1(s8) = G_TRUNC %0(s32)
%2(s32) = G_ANYEXT %1(s8) %2(s32) = G_ANYEXT %1(s8)
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREG]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_trunc_and_zext_s16_to_s32 name: test_trunc_and_zext_s16_to_s32
# CHECK-LABEL: name: test_trunc_and_zext_s16_to_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_trunc_and_zext_s16_to_s32
; CHECK: liveins: $r0
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]]
; CHECK: [[t2UXTH:%[0-9]+]]:rgpr = t2UXTH [[COPY1]], 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[t2UXTH]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
%1(s16) = G_TRUNC %0(s32) %1(s16) = G_TRUNC %0(s32)
; CHECK: [[VREGTRUNC:%[0-9]+]]:rgpr = COPY [[VREG]]
%2(s32) = G_ZEXT %1(s16) %2(s32) = G_ZEXT %1(s16)
; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2UXTH [[VREGTRUNC]], 0, 14, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGEXT]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_trunc_and_sext_s16_to_s32 name: test_trunc_and_sext_s16_to_s32
# CHECK-LABEL: name: test_trunc_and_sext_s16_to_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_trunc_and_sext_s16_to_s32
; CHECK: liveins: $r0
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]]
; CHECK: [[t2SXTH:%[0-9]+]]:rgpr = t2SXTH [[COPY1]], 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[t2SXTH]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
%1(s16) = G_TRUNC %0(s32) %1(s16) = G_TRUNC %0(s32)
; CHECK: [[VREGTRUNC:%[0-9]+]]:rgpr = COPY [[VREG]]
%2(s32) = G_SEXT %1(s16) %2(s32) = G_SEXT %1(s16)
; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2SXTH [[VREGTRUNC]], 0, 14, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGEXT]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_trunc_and_anyext_s16_to_s32 name: test_trunc_and_anyext_s16_to_s32
# CHECK-LABEL: name: test_trunc_and_anyext_s16_to_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_trunc_and_anyext_s16_to_s32
; CHECK: liveins: $r0
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: $r0 = COPY [[COPY]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
%1(s16) = G_TRUNC %0(s32) %1(s16) = G_TRUNC %0(s32)
%2(s32) = G_ANYEXT %1(s16) %2(s32) = G_ANYEXT %1(s16)
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREG]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_trunc_and_zext_s1_to_s16 name: test_trunc_and_zext_s1_to_s16
# CHECK-LABEL: name: test_trunc_and_zext_s1_to_s16
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_trunc_and_zext_s1_to_s16
; CHECK: liveins: $r0, $r1
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY2]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2STRHi12 [[t2ANDri]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 2)
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0 %0(p0) = COPY $r0
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
%2(s1) = G_TRUNC %1(s32) %2(s1) = G_TRUNC %1(s32)
%3(s16) = G_ZEXT %2(s1) %3(s16) = G_ZEXT %2(s1)
; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]]
; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2ANDri [[RVREG]], 1, 14, $noreg, $noreg
G_STORE %3(s16), %0(p0) :: (store 2) G_STORE %3(s16), %0(p0) :: (store 2)
; CHECK: t2STRHi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 2)
BX_RET 14, $noreg BX_RET 14, $noreg
; CHECK: BX_RET 14, $noreg
... ...
--- ---
name: test_trunc_and_sext_s1_to_s16 name: test_trunc_and_sext_s1_to_s16
# CHECK-LABEL: name: test_trunc_and_sext_s1_to_s16
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_trunc_and_sext_s1_to_s16
; CHECK: liveins: $r0, $r1
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY2]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[t2RSBri:%[0-9]+]]:rgpr = t2RSBri [[t2ANDri]], 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2STRHi12 [[t2RSBri]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 2)
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0 %0(p0) = COPY $r0
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
%2(s1) = G_TRUNC %1(s32) %2(s1) = G_TRUNC %1(s32)
%3(s16) = G_SEXT %2(s1) %3(s16) = G_SEXT %2(s1)
; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]]
; CHECK: [[VREGAND:%[0-9]+]]:rgpr = t2ANDri [[RVREG]], 1, 14, $noreg, $noreg
; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2RSBri [[VREGAND]], 0, 14, $noreg, $noreg
G_STORE %3(s16), %0(p0) :: (store 2) G_STORE %3(s16), %0(p0) :: (store 2)
; CHECK: t2STRHi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 2)
BX_RET 14, $noreg BX_RET 14, $noreg
; CHECK: BX_RET 14, $noreg
... ...
--- ---
name: test_trunc_and_anyext_s1_to_s16 name: test_trunc_and_anyext_s1_to_s16
# CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s16
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s16
; CHECK: liveins: $r0, $r1
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
; CHECK: t2STRHi12 [[COPY2]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 2)
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0 %0(p0) = COPY $r0
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
%2(s1) = G_TRUNC %1(s32) %2(s1) = G_TRUNC %1(s32)
%3(s16) = G_ANYEXT %2(s1) %3(s16) = G_ANYEXT %2(s1)
G_STORE %3(s16), %0(p0) :: (store 2) G_STORE %3(s16), %0(p0) :: (store 2)
; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]]
; CHECK: t2STRHi12 [[RVREG]], [[PTR]], 0, 14, $noreg :: (store 2)
BX_RET 14, $noreg BX_RET 14, $noreg
; CHECK: BX_RET 14, $noreg
... ...
--- ---
name: test_trunc_and_zext_s8_to_s16 name: test_trunc_and_zext_s8_to_s16
# CHECK-LABEL: name: test_trunc_and_zext_s8_to_s16
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_trunc_and_zext_s8_to_s16
; CHECK: liveins: $r0, $r1
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
; CHECK: [[t2UXTB:%[0-9]+]]:rgpr = t2UXTB [[COPY2]], 0, 14 /* CC::al */, $noreg
; CHECK: t2STRHi12 [[t2UXTB]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 2)
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0 %0(p0) = COPY $r0
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
%2(s8) = G_TRUNC %1(s32) %2(s8) = G_TRUNC %1(s32)
; CHECK: [[VREGTRUNC:%[1-9]+]]:rgpr = COPY [[VREG]]
%3(s16) = G_ZEXT %2(s8) %3(s16) = G_ZEXT %2(s8)
; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2UXTB [[VREGTRUNC]], 0, 14, $noreg
G_STORE %3(s16), %0(p0) :: (store 2) G_STORE %3(s16), %0(p0) :: (store 2)
; CHECK: t2STRHi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 2)
BX_RET 14, $noreg BX_RET 14, $noreg
; CHECK: BX_RET 14, $noreg
... ...
--- ---
name: test_trunc_and_sext_s8_to_s16 name: test_trunc_and_sext_s8_to_s16
# CHECK-LABEL: name: test_trunc_and_sext_s8_to_s16
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_trunc_and_sext_s8_to_s16
; CHECK: liveins: $r0, $r1
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
; CHECK: [[t2SXTB:%[0-9]+]]:rgpr = t2SXTB [[COPY2]], 0, 14 /* CC::al */, $noreg
; CHECK: t2STRHi12 [[t2SXTB]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 2)
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0 %0(p0) = COPY $r0
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
%2(s8) = G_TRUNC %1(s32) %2(s8) = G_TRUNC %1(s32)
; CHECK: [[VREGTRUNC:%[1-9]+]]:rgpr = COPY [[VREG]]
%3(s16) = G_SEXT %2(s8) %3(s16) = G_SEXT %2(s8)
; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2SXTB [[VREGTRUNC]], 0, 14, $noreg
G_STORE %3(s16), %0(p0) :: (store 2) G_STORE %3(s16), %0(p0) :: (store 2)
; CHECK: t2STRHi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 2)
BX_RET 14, $noreg BX_RET 14, $noreg
; CHECK: BX_RET 14, $noreg
... ...
--- ---
name: test_trunc_and_anyext_s8_to_s16 name: test_trunc_and_anyext_s8_to_s16
# CHECK-LABEL: name: test_trunc_and_anyext_s8_to_s16
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_trunc_and_anyext_s8_to_s16
; CHECK: liveins: $r0, $r1
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
; CHECK: t2STRHi12 [[COPY2]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 2)
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0 %0(p0) = COPY $r0
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
%2(s8) = G_TRUNC %1(s32) %2(s8) = G_TRUNC %1(s32)
%3(s16) = G_ANYEXT %2(s8) %3(s16) = G_ANYEXT %2(s8)
G_STORE %3(s16), %0(p0) :: (store 2) G_STORE %3(s16), %0(p0) :: (store 2)
; CHECK: [[VREGR:%[0-9]+]]:rgpr = COPY [[VREG]]
; CHECK: t2STRHi12 [[VREGR]], [[PTR]], 0, 14, $noreg :: (store 2)
BX_RET 14, $noreg BX_RET 14, $noreg
; CHECK: BX_RET 14, $noreg
... ...
--- ---
name: test_trunc_and_zext_s1_to_s8 name: test_trunc_and_zext_s1_to_s8
# CHECK-LABEL: name: test_trunc_and_zext_s1_to_s8
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_trunc_and_zext_s1_to_s8
; CHECK: liveins: $r0, $r1
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY2]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2STRBi12 [[t2ANDri]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 1)
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0 %0(p0) = COPY $r0
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
%2(s1) = G_TRUNC %1(s32) %2(s1) = G_TRUNC %1(s32)
%3(s8) = G_ZEXT %2(s1) %3(s8) = G_ZEXT %2(s1)
; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]]
; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2ANDri [[RVREG]], 1, 14, $noreg, $noreg
G_STORE %3(s8), %0(p0) :: (store 1) G_STORE %3(s8), %0(p0) :: (store 1)
; CHECK: t2STRBi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 1)
BX_RET 14, $noreg BX_RET 14, $noreg
; CHECK: BX_RET 14, $noreg
... ...
--- ---
name: test_trunc_and_sext_s1_to_s8 name: test_trunc_and_sext_s1_to_s8
# CHECK-LABEL: name: test_trunc_and_sext_s1_to_s8
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_trunc_and_sext_s1_to_s8
; CHECK: liveins: $r0, $r1
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY2]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[t2RSBri:%[0-9]+]]:rgpr = t2RSBri [[t2ANDri]], 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2STRBi12 [[t2RSBri]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 1)
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0 %0(p0) = COPY $r0
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
%2(s1) = G_TRUNC %1(s32) %2(s1) = G_TRUNC %1(s32)
%3(s8) = G_SEXT %2(s1) %3(s8) = G_SEXT %2(s1)
; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]]
; CHECK: [[VREGAND:%[0-9]+]]:rgpr = t2ANDri [[RVREG]], 1, 14, $noreg, $noreg
; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2RSBri [[VREGAND]], 0, 14, $noreg, $noreg
G_STORE %3(s8), %0(p0) :: (store 1) G_STORE %3(s8), %0(p0) :: (store 1)
; CHECK: t2STRBi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 1)
BX_RET 14, $noreg BX_RET 14, $noreg
; CHECK: BX_RET 14, $noreg
... ...
--- ---
name: test_trunc_and_anyext_s1_to_s8 name: test_trunc_and_anyext_s1_to_s8
# CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s8
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s8
; CHECK: liveins: $r0, $r1
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
; CHECK: t2STRBi12 [[COPY2]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 1)
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0 %0(p0) = COPY $r0
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
%2(s1) = G_TRUNC %1(s32) %2(s1) = G_TRUNC %1(s32)
%3(s8) = G_ANYEXT %2(s1) %3(s8) = G_ANYEXT %2(s1)
G_STORE %3(s8), %0(p0) :: (store 1) G_STORE %3(s8), %0(p0) :: (store 1)
; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]]
; CHECK: t2STRBi12 [[RVREG]], [[PTR]], 0, 14, $noreg :: (store 1)
BX_RET 14, $noreg BX_RET 14, $noreg
; CHECK: BX_RET 14, $noreg
... ...

llvm/test/CodeGen/ARM/GlobalISel/thumb-select-globals-pic.mir

Show All 27 Lines
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @internal_global %0(p0) = G_GLOBAL_VALUE @internal_global
; DARWIN-MOVT: [[G:%[0-9]+]]:rgpr = t2MOV_ga_pcrel target-flags(arm-nonlazy) @internal_global ; DARWIN-MOVT: [[G:%[0-9]+]]:rgpr = t2MOV_ga_pcrel target-flags(arm-nonlazy) @internal_global
; DARWIN-NOMOVT: [[G:%[0-9]+]]:tgpr = tLDRLIT_ga_pcrel target-flags(arm-nonlazy) @internal_global ; DARWIN-NOMOVT: [[G:%[0-9]+]]:tgpr = tLDRLIT_ga_pcrel target-flags(arm-nonlazy) @internal_global
; ELF: [[G:%[0-9]+]]:tgpr = tLDRLIT_ga_pcrel @internal_global ; ELF: [[G:%[0-9]+]]:tgpr = tLDRLIT_ga_pcrel @internal_global
%1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global) %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global)
; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @internal_global) ; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14 /* CC::al */, $noreg :: (load 4 from @internal_global)
$r0 = COPY %1(s32) $r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[V]] ; CHECK: $r0 = COPY [[V]]
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
; CHECK: tBX_RET 14, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_external_global name: test_external_global
# CHECK-LABEL: name: test_external_global # CHECK-LABEL: name: test_external_global
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @external_global %0(p0) = G_GLOBAL_VALUE @external_global
; DARWIN-MOVT: [[G_GOT:%[0-9]+]]:rgpr = t2MOV_ga_pcrel target-flags(arm-nonlazy) @external_global ; DARWIN-MOVT: [[G_GOT:%[0-9]+]]:rgpr = t2MOV_ga_pcrel target-flags(arm-nonlazy) @external_global
; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = t2LDRi12 [[G_GOT]], 0, 14, $noreg :: (load 4 from got) ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = t2LDRi12 [[G_GOT]], 0, 14 /* CC::al */, $noreg :: (load 4 from got)
; DARWIN-NOMOVT: [[G_GOT:%[0-9]+]]:tgpr = tLDRLIT_ga_pcrel target-flags(arm-nonlazy) @external_global ; DARWIN-NOMOVT: [[G_GOT:%[0-9]+]]:tgpr = tLDRLIT_ga_pcrel target-flags(arm-nonlazy) @external_global
; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRi12 [[G_GOT]], 0, 14, $noreg :: (load 4 from got) ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRi12 [[G_GOT]], 0, 14 /* CC::al */, $noreg :: (load 4 from got)
; ELF: [[G_GOT:%[0-9]+]]:tgpr = tLDRLIT_ga_pcrel target-flags(arm-got) @external_global ; ELF: [[G_GOT:%[0-9]+]]:tgpr = tLDRLIT_ga_pcrel target-flags(arm-got) @external_global
; ELF: [[G:%[0-9]+]]:gpr = t2LDRi12 [[G_GOT]], 0, 14, $noreg :: (load 4 from got) ; ELF: [[G:%[0-9]+]]:gpr = t2LDRi12 [[G_GOT]], 0, 14 /* CC::al */, $noreg :: (load 4 from got)
%1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global) %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global)
; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @external_global) ; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14 /* CC::al */, $noreg :: (load 4 from @external_global)
$r0 = COPY %1(s32) $r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[V]] ; CHECK: $r0 = COPY [[V]]
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
; CHECK: tBX_RET 14, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_internal_constant name: test_internal_constant
# CHECK-LABEL: name: test_internal_constant # CHECK-LABEL: name: test_internal_constant
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @internal_constant %0(p0) = G_GLOBAL_VALUE @internal_constant
; DARWIN-MOVT: [[G:%[0-9]+]]:rgpr = t2MOV_ga_pcrel target-flags(arm-nonlazy) @internal_constant ; DARWIN-MOVT: [[G:%[0-9]+]]:rgpr = t2MOV_ga_pcrel target-flags(arm-nonlazy) @internal_constant
; DARWIN-NOMOVT: [[G:%[0-9]+]]:tgpr = tLDRLIT_ga_pcrel target-flags(arm-nonlazy) @internal_constant ; DARWIN-NOMOVT: [[G:%[0-9]+]]:tgpr = tLDRLIT_ga_pcrel target-flags(arm-nonlazy) @internal_constant
; ELF: [[G:%[0-9]+]]:tgpr = tLDRLIT_ga_pcrel @internal_constant ; ELF: [[G:%[0-9]+]]:tgpr = tLDRLIT_ga_pcrel @internal_constant
%1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_constant) %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_constant)
; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @internal_constant) ; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14 /* CC::al */, $noreg :: (load 4 from @internal_constant)
$r0 = COPY %1(s32) $r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[V]] ; CHECK: $r0 = COPY [[V]]
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
; CHECK: tBX_RET 14, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_external_constant name: test_external_constant
# CHECK-LABEL: name: test_external_constant # CHECK-LABEL: name: test_external_constant
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @external_constant %0(p0) = G_GLOBAL_VALUE @external_constant
; DARWIN-MOVT: [[G_GOT:%[0-9]+]]:rgpr = t2MOV_ga_pcrel target-flags(arm-nonlazy) @external_constant ; DARWIN-MOVT: [[G_GOT:%[0-9]+]]:rgpr = t2MOV_ga_pcrel target-flags(arm-nonlazy) @external_constant
; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = t2LDRi12 [[G_GOT]], 0, 14, $noreg :: (load 4 from got) ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = t2LDRi12 [[G_GOT]], 0, 14 /* CC::al */, $noreg :: (load 4 from got)
; DARWIN-NOMOVT: [[G_GOT:%[0-9]+]]:tgpr = tLDRLIT_ga_pcrel target-flags(arm-nonlazy) @external_constant ; DARWIN-NOMOVT: [[G_GOT:%[0-9]+]]:tgpr = tLDRLIT_ga_pcrel target-flags(arm-nonlazy) @external_constant
; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRi12 [[G_GOT]], 0, 14, $noreg :: (load 4 from got) ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRi12 [[G_GOT]], 0, 14 /* CC::al */, $noreg :: (load 4 from got)
; ELF: [[G_GOT:%[0-9]+]]:tgpr = tLDRLIT_ga_pcrel target-flags(arm-got) @external_constant ; ELF: [[G_GOT:%[0-9]+]]:tgpr = tLDRLIT_ga_pcrel target-flags(arm-got) @external_constant
; ELF: [[G:%[0-9]+]]:gpr = t2LDRi12 [[G_GOT]], 0, 14, $noreg :: (load 4 from got) ; ELF: [[G:%[0-9]+]]:gpr = t2LDRi12 [[G_GOT]], 0, 14 /* CC::al */, $noreg :: (load 4 from got)
%1(s32) = G_LOAD %0(p0) :: (load 4 from @external_constant) %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_constant)
; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @external_constant) ; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14 /* CC::al */, $noreg :: (load 4 from @external_constant)
$r0 = COPY %1(s32) $r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[V]] ; CHECK: $r0 = COPY [[V]]
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
; CHECK: tBX_RET 14, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...

llvm/test/CodeGen/ARM/GlobalISel/thumb-select-globals-ropi-rwpi.mir

Show All 31 Lines
# RW-DEFAULT-NOMOVT: value: 'i32* @internal_global' # RW-DEFAULT-NOMOVT: value: 'i32* @internal_global'
# RWPI-NOMOVT: constants: # RWPI-NOMOVT: constants:
# RWPI-NOMOVT: id: 0 # RWPI-NOMOVT: id: 0
# RWPI-NOMOVT: value: 'internal_global(SBREL)' # RWPI-NOMOVT: value: 'internal_global(SBREL)'
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @internal_global %0(p0) = G_GLOBAL_VALUE @internal_global
; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @internal_global ; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @internal_global
; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14, $noreg :: (load 4 from constant-pool) ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14 /* CC::al */, $noreg :: (load 4 from constant-pool)
; RWPI-MOVT: [[OFF:%[0-9]+]]:rgpr = t2MOVi32imm target-flags(arm-sbrel) @internal_global ; RWPI-MOVT: [[OFF:%[0-9]+]]:rgpr = t2MOVi32imm target-flags(arm-sbrel) @internal_global
; RWPI-NOMOVT: [[OFF:%[0-9]+]]:rgpr = t2LDRpci %const.0, 14, $noreg :: (load 4 from constant-pool) ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:rgpr = t2LDRpci %const.0, 14 /* CC::al */, $noreg :: (load 4 from constant-pool)
; RWPI: [[G:%[0-9]+]]:gprnopc = t2ADDrr $r9, [[OFF]], 14, $noreg, $noreg ; RWPI: [[G:%[0-9]+]]:gprnopc = t2ADDrr $r9, [[OFF]], 14 /* CC::al */, $noreg, $noreg
%1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global) %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global)
; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @internal_global) ; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14 /* CC::al */, $noreg :: (load 4 from @internal_global)
$r0 = COPY %1(s32) $r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[V]] ; CHECK: $r0 = COPY [[V]]
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
; CHECK: tBX_RET 14, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_external_global name: test_external_global
# CHECK-LABEL: name: test_external_global # CHECK-LABEL: name: test_external_global
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
# RW-DEFAULT-NOMOVT: constants: # RW-DEFAULT-NOMOVT: constants:
# RW-DEFAULT-NOMOVT: id: 0 # RW-DEFAULT-NOMOVT: id: 0
# RW-DEFAULT-NOMOVT: value: 'i32* @external_global' # RW-DEFAULT-NOMOVT: value: 'i32* @external_global'
# RWPI-NOMOVT: constants: # RWPI-NOMOVT: constants:
# RWPI-NOMOVT: id: 0 # RWPI-NOMOVT: id: 0
# RWPI-NOMOVT: value: 'external_global(SBREL)' # RWPI-NOMOVT: value: 'external_global(SBREL)'
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @external_global %0(p0) = G_GLOBAL_VALUE @external_global
; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @external_global ; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @external_global
; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14, $noreg :: (load 4 from constant-pool) ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14 /* CC::al */, $noreg :: (load 4 from constant-pool)
; RWPI-MOVT: [[OFF:%[0-9]+]]:rgpr = t2MOVi32imm target-flags(arm-sbrel) @external_global ; RWPI-MOVT: [[OFF:%[0-9]+]]:rgpr = t2MOVi32imm target-flags(arm-sbrel) @external_global
; RWPI-NOMOVT: [[OFF:%[0-9]+]]:rgpr = t2LDRpci %const.0, 14, $noreg :: (load 4 from constant-pool) ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:rgpr = t2LDRpci %const.0, 14 /* CC::al */, $noreg :: (load 4 from constant-pool)
; RWPI: [[G:%[0-9]+]]:gprnopc = t2ADDrr $r9, [[OFF]], 14, $noreg, $noreg ; RWPI: [[G:%[0-9]+]]:gprnopc = t2ADDrr $r9, [[OFF]], 14 /* CC::al */, $noreg, $noreg
%1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global) %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global)
; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @external_global) ; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14 /* CC::al */, $noreg :: (load 4 from @external_global)
$r0 = COPY %1(s32) $r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[V]] ; CHECK: $r0 = COPY [[V]]
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
; CHECK: tBX_RET 14, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_internal_constant name: test_internal_constant
# CHECK-LABEL: name: test_internal_constant # CHECK-LABEL: name: test_internal_constant
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
# RO-DEFAULT-NOMOVT: constants: # RO-DEFAULT-NOMOVT: constants:
# RO-DEFAULT-NOMOVT: id: 0 # RO-DEFAULT-NOMOVT: id: 0
# RO-DEFAULT-NOMOVT: value: 'i32* @internal_constant' # RO-DEFAULT-NOMOVT: value: 'i32* @internal_constant'
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @internal_constant %0(p0) = G_GLOBAL_VALUE @internal_constant
; ROPI-MOVT: [[G:%[0-9]+]]:rgpr = t2MOV_ga_pcrel @internal_constant ; ROPI-MOVT: [[G:%[0-9]+]]:rgpr = t2MOV_ga_pcrel @internal_constant
; ROPI-NOMOVT: [[G:%[0-9]+]]:tgpr = tLDRLIT_ga_pcrel @internal_constant ; ROPI-NOMOVT: [[G:%[0-9]+]]:tgpr = tLDRLIT_ga_pcrel @internal_constant
; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @internal_constant ; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @internal_constant
; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14, $noreg :: (load 4 from constant-pool) ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14 /* CC::al */, $noreg :: (load 4 from constant-pool)
%1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_constant) %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_constant)
; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @internal_constant) ; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14 /* CC::al */, $noreg :: (load 4 from @internal_constant)
$r0 = COPY %1(s32) $r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[V]] ; CHECK: $r0 = COPY [[V]]
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
; CHECK: tBX_RET 14, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_external_constant name: test_external_constant
# CHECK-LABEL: name: test_external_constant # CHECK-LABEL: name: test_external_constant
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
# RO-DEFAULT-NOMOVT: constants: # RO-DEFAULT-NOMOVT: constants:
# RO-DEFAULT-NOMOVT: id: 0 # RO-DEFAULT-NOMOVT: id: 0
# RO-DEFAULT-NOMOVT: value: 'i32* @external_constant' # RO-DEFAULT-NOMOVT: value: 'i32* @external_constant'
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @external_constant %0(p0) = G_GLOBAL_VALUE @external_constant
; ROPI-MOVT: [[G:%[0-9]+]]:rgpr = t2MOV_ga_pcrel @external_constant ; ROPI-MOVT: [[G:%[0-9]+]]:rgpr = t2MOV_ga_pcrel @external_constant
; ROPI-NOMOVT: [[G:%[0-9]+]]:tgpr = tLDRLIT_ga_pcrel @external_constant ; ROPI-NOMOVT: [[G:%[0-9]+]]:tgpr = tLDRLIT_ga_pcrel @external_constant
; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @external_constant ; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @external_constant
; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14, $noreg :: (load 4 from constant-pool) ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14 /* CC::al */, $noreg :: (load 4 from constant-pool)
%1(s32) = G_LOAD %0(p0) :: (load 4 from @external_constant) %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_constant)
; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @external_constant) ; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14 /* CC::al */, $noreg :: (load 4 from @external_constant)
$r0 = COPY %1(s32) $r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[V]] ; CHECK: $r0 = COPY [[V]]
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
; CHECK: tBX_RET 14, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...

llvm/test/CodeGen/ARM/GlobalISel/thumb-select-globals-static.mir

Show All 20 Linesregisters:
- { id: 1, class: gprb } - { id: 1, class: gprb }
# ELF-NOMOVT: constants: # ELF-NOMOVT: constants:
# ELF-NOMOVT: id: 0 # ELF-NOMOVT: id: 0
# ELF-NOMOVT: value: 'i32* @internal_global' # ELF-NOMOVT: value: 'i32* @internal_global'
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @internal_global %0(p0) = G_GLOBAL_VALUE @internal_global
; ELF-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @internal_global ; ELF-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @internal_global
; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14, $noreg :: (load 4 from constant-pool) ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14 /* CC::al */, $noreg :: (load 4 from constant-pool)
; DARWIN-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @internal_global ; DARWIN-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @internal_global
; DARWIN-NOMOVT: [[G:%[0-9]+]]:tgpr = tLDRLIT_ga_abs @internal_global ; DARWIN-NOMOVT: [[G:%[0-9]+]]:tgpr = tLDRLIT_ga_abs @internal_global
%1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global) %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global)
; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @internal_global) ; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14 /* CC::al */, $noreg :: (load 4 from @internal_global)
$r0 = COPY %1(s32) $r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[V]] ; CHECK: $r0 = COPY [[V]]
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
; CHECK: tBX_RET 14, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...
--- ---
name: test_external_global name: test_external_global
# CHECK-LABEL: name: test_external_global # CHECK-LABEL: name: test_external_global
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
# ELF-NOMOVT: constants: # ELF-NOMOVT: constants:
# ELF-NOMOVT: id: 0 # ELF-NOMOVT: id: 0
# ELF-NOMOVT: value: 'i32* @external_global' # ELF-NOMOVT: value: 'i32* @external_global'
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @external_global %0(p0) = G_GLOBAL_VALUE @external_global
; ELF-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @external_global ; ELF-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @external_global
; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14, $noreg :: (load 4 from constant-pool) ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14 /* CC::al */, $noreg :: (load 4 from constant-pool)
; DARWIN-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @external_global ; DARWIN-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @external_global
; DARWIN-NOMOVT: [[G:%[0-9]+]]:tgpr = tLDRLIT_ga_abs @external_global ; DARWIN-NOMOVT: [[G:%[0-9]+]]:tgpr = tLDRLIT_ga_abs @external_global
%1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global) %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global)
; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @external_global) ; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14 /* CC::al */, $noreg :: (load 4 from @external_global)
$r0 = COPY %1(s32) $r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[V]] ; CHECK: $r0 = COPY [[V]]
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
; CHECK: tBX_RET 14, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...

llvm/test/CodeGen/ARM/GlobalISel/thumb-select-imm.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- | --- |
define void @test_movi() { ret void } define void @test_movi() { ret void }
define void @test_movi16() { ret void } define void @test_movi16() { ret void }
define void @test_movi32() { ret void } define void @test_movi32() { ret void }
... ...
--- ---
name: test_movi name: test_movi
# CHECK-LABEL: name: test_movi
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: test_movi
; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 786444, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2MOVi]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = G_CONSTANT i32 786444 ; 0x000c000c %0(s32) = G_CONSTANT i32 786444 ; 0x000c000c
; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2MOVi 786444, 14, $noreg, $noreg
$r0 = COPY %0(s32) $r0 = COPY %0(s32)
; CHECK: $r0 = COPY [[VREGRES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_movi16 name: test_movi16
# CHECK-LABEL: name: test_movi16
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: test_movi16
; CHECK: [[t2MOVi16_:%[0-9]+]]:rgpr = t2MOVi16 65533, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[t2MOVi16_]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = G_CONSTANT i32 65533 %0(s32) = G_CONSTANT i32 65533
; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2MOVi16 65533, 14, $noreg
$r0 = COPY %0(s32) $r0 = COPY %0(s32)
; CHECK: $r0 = COPY [[VREGRES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_movi32 name: test_movi32
# CHECK-LABEL: name: test_movi32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: test_movi32
; CHECK: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm 185470479
; CHECK: $r0 = COPY [[t2MOVi32imm]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = G_CONSTANT i32 185470479 ; 0x0b0e0e0f %0(s32) = G_CONSTANT i32 185470479 ; 0x0b0e0e0f
; CHECK: [[VREGY:%[0-9]+]]:rgpr = t2MOVi32imm 185470479
$r0 = COPY %0(s32) $r0 = COPY %0(s32)
; CHECK: $r0 = COPY [[VREGRES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...

llvm/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- | --- |
define void @test_s1() { ret void } define void @test_s1() { ret void }
define void @test_s8() { ret void } define void @test_s8() { ret void }
define void @test_s16() { ret void } define void @test_s16() { ret void }
define void @test_s32() { ret void } define void @test_s32() { ret void }
define void @test_gep() { ret void } define void @test_gep() { ret void }
define void @test_load_from_stack() { ret void } define void @test_load_from_stack() { ret void }
... ...
--- ---
name: test_s1 name: test_s1
# CHECK-LABEL: name: test_s1
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_s1
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[t2LDRBi12_:%[0-9]+]]:rgpr = t2LDRBi12 [[COPY]], 0, 14 /* CC::al */, $noreg :: (load 1)
; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2LDRBi12_]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2STRBi12 [[t2ANDri]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 1)
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0 %0(p0) = COPY $r0
; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0
%1(s1) = G_LOAD %0(p0) :: (load 1) %1(s1) = G_LOAD %0(p0) :: (load 1)
; CHECK: %[[V8:[0-9]+]]:rgpr = t2LDRBi12 %[[P]], 0, 14, $noreg :: (load 1)
G_STORE %1(s1), %0(p0) :: (store 1) G_STORE %1(s1), %0(p0) :: (store 1)
; CHECK: %[[V1:[0-9]+]]:rgpr = t2ANDri %[[V8]], 1, 14, $noreg
; CHECK: t2STRBi12 %[[V1]], %[[P]], 0, 14, $noreg :: (store 1)
BX_RET 14, $noreg BX_RET 14, $noreg
; CHECK: BX_RET 14, $noreg
... ...
--- ---
name: test_s8 name: test_s8
# CHECK-LABEL: name: test_s8
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_s8
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[t2LDRBi12_:%[0-9]+]]:rgpr = t2LDRBi12 [[COPY]], 0, 14 /* CC::al */, $noreg :: (load 1)
; CHECK: t2STRBi12 [[t2LDRBi12_]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 1)
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0 %0(p0) = COPY $r0
; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0
%1(s8) = G_LOAD %0(p0) :: (load 1) %1(s8) = G_LOAD %0(p0) :: (load 1)
; CHECK: %[[V:[0-9]+]]:rgpr = t2LDRBi12 %[[P]], 0, 14, $noreg :: (load 1)
G_STORE %1(s8), %0(p0) :: (store 1) G_STORE %1(s8), %0(p0) :: (store 1)
; CHECK: t2STRBi12 %[[V]], %[[P]], 0, 14, $noreg :: (store 1)
BX_RET 14, $noreg BX_RET 14, $noreg
; CHECK: BX_RET 14, $noreg
... ...
--- ---
name: test_s16 name: test_s16
# CHECK-LABEL: name: test_s16
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_s16
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[t2LDRHi12_:%[0-9]+]]:rgpr = t2LDRHi12 [[COPY]], 0, 14 /* CC::al */, $noreg :: (load 2)
; CHECK: t2STRHi12 [[t2LDRHi12_]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 2)
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0 %0(p0) = COPY $r0
; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0
%1(s16) = G_LOAD %0(p0) :: (load 2) %1(s16) = G_LOAD %0(p0) :: (load 2)
; CHECK: %[[V:[0-9]+]]:rgpr = t2LDRHi12 %[[P]], 0, 14, $noreg :: (load 2)
G_STORE %1(s16), %0(p0) :: (store 2) G_STORE %1(s16), %0(p0) :: (store 2)
; CHECK: t2STRHi12 %[[V]], %[[P]], 0, 14, $noreg :: (store 2)
BX_RET 14, $noreg BX_RET 14, $noreg
; CHECK: BX_RET 14, $noreg
... ...
--- ---
name: test_s32 name: test_s32
# CHECK-LABEL: name: test_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[t2LDRi12_:%[0-9]+]]:gpr = t2LDRi12 [[COPY]], 0, 14 /* CC::al */, $noreg :: (load 4)
; CHECK: t2STRi12 [[t2LDRi12_]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 4)
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0 %0(p0) = COPY $r0
; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0
%1(s32) = G_LOAD %0(p0) :: (load 4) %1(s32) = G_LOAD %0(p0) :: (load 4)
; CHECK: %[[V:[0-9]+]]:gpr = t2LDRi12 %[[P]], 0, 14, $noreg :: (load 4)
G_STORE %1(s32), %0(p0) :: (store 4) G_STORE %1(s32), %0(p0) :: (store 4)
; CHECK: t2STRi12 %[[V]], %[[P]], 0, 14, $noreg :: (store 4)
BX_RET 14, $noreg BX_RET 14, $noreg
; CHECK: BX_RET 14, $noreg
... ...
--- ---
name: test_gep name: test_gep
# CHECK-LABEL: name: test_gep
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_gep
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[t2ADDrr:%[0-9]+]]:gprnopc = t2ADDrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2ADDrr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(p0) = COPY $r0 %0(p0) = COPY $r0
; CHECK: [[PTR:%[0-9]+]]:gprnopc = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[OFF:%[0-9]+]]:rgpr = COPY $r1
%2(p0) = G_PTR_ADD %0, %1(s32) %2(p0) = G_PTR_ADD %0, %1(s32)
; CHECK: [[GEP:%[0-9]+]]:gprnopc = t2ADDrr [[PTR]], [[OFF]], 14, $noreg, $noreg
$r0 = COPY %2(p0) $r0 = COPY %2(p0)
; CHECK: $r0 = COPY [[GEP]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_load_from_stack name: test_load_from_stack
# CHECK-LABEL: name: test_load_from_stack
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
- { id: 4, class: gprb } - { id: 4, class: gprb }
fixedStack: fixedStack:
- { id: 0, offset: 0, size: 1, alignment: 4, isImmutable: true, isAliased: false } - { id: 0, offset: 0, size: 1, alignment: 4, isImmutable: true, isAliased: false }
- { id: 1, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false } - { id: 1, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
- { id: 2, offset: 8, size: 4, alignment: 4, isImmutable: true, isAliased: false } - { id: 2, offset: 8, size: 4, alignment: 4, isImmutable: true, isAliased: false }
# CHECK-DAG: id: [[FI1:[0-9]+]], type: default, offset: 0, size: 1
# CHECK-DAG: id: [[FI32:[0-9]+]], type: default, offset: 8
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1, $r2, $r3 liveins: $r0, $r1, $r2, $r3
; CHECK-LABEL: name: test_load_from_stack
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri %fixed-stack.0, 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[t2LDRi12_:%[0-9]+]]:gpr = t2LDRi12 [[t2ADDri]], 0, 14 /* CC::al */, $noreg :: (load 4)
; CHECK: $r0 = COPY [[t2LDRi12_]]
; CHECK: [[t2ADDri1:%[0-9]+]]:rgpr = t2ADDri %fixed-stack.2, 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[t2LDRBi12_:%[0-9]+]]:gprnopc = t2LDRBi12 [[t2ADDri1]], 0, 14 /* CC::al */, $noreg :: (load 1)
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY [[t2LDRBi12_]]
; CHECK: $r0 = COPY [[COPY]]
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = G_FRAME_INDEX %fixed-stack.2 %0(p0) = G_FRAME_INDEX %fixed-stack.2
; CHECK: [[FI32VREG:%[0-9]+]]:rgpr = t2ADDri %fixed-stack.[[FI32]], 0, 14, $noreg, $noreg
%1(s32) = G_LOAD %0(p0) :: (load 4) %1(s32) = G_LOAD %0(p0) :: (load 4)
; CHECK: [[LD32VREG:%[0-9]+]]:gpr = t2LDRi12 [[FI32VREG]], 0, 14, $noreg
$r0 = COPY %1 $r0 = COPY %1
; CHECK: $r0 = COPY [[LD32VREG]]
%2(p0) = G_FRAME_INDEX %fixed-stack.0 %2(p0) = G_FRAME_INDEX %fixed-stack.0
; CHECK: [[FI1VREG:%[0-9]+]]:rgpr = t2ADDri %fixed-stack.[[FI1]], 0, 14, $noreg, $noreg
%3(s1) = G_LOAD %2(p0) :: (load 1) %3(s1) = G_LOAD %2(p0) :: (load 1)
; CHECK: [[LD1VREG:%[0-9]+]]:gprnopc = t2LDRBi12 [[FI1VREG]], 0, 14, $noreg
%4(s32) = G_ANYEXT %3(s1) %4(s32) = G_ANYEXT %3(s1)
; CHECK: [[RES:%[0-9]+]]:gpr = COPY [[LD1VREG]]
$r0 = COPY %4 $r0 = COPY %4
; CHECK: $r0 = COPY [[RES]]
BX_RET 14, $noreg BX_RET 14, $noreg
; CHECK: BX_RET 14, $noreg
... ...

llvm/test/CodeGen/ARM/GlobalISel/thumb-select-logical-ops.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- | --- |
define void @test_and_regs() { ret void } define void @test_and_regs() { ret void }
define void @test_and_imm() { ret void } define void @test_and_imm() { ret void }
define void @test_bfc() { ret void } define void @test_bfc() { ret void }
define void @test_no_bfc_bad_mask() { ret void } define void @test_no_bfc_bad_mask() { ret void }
define void @test_mvn() { ret void } define void @test_mvn() { ret void }
define void @test_bic() { ret void } define void @test_bic() { ret void }
define void @test_orn() { ret void } define void @test_orn() { ret void }
... ...
--- ---
name: test_and_regs name: test_and_regs
# CHECK-LABEL: name: test_and_regs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_and_regs
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[t2ANDrr:%[0-9]+]]:rgpr = t2ANDrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2ANDrr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
%2(s32) = G_AND %0, %1 %2(s32) = G_AND %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2ANDrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGRES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_and_imm name: test_and_imm
# CHECK-LABEL: name: test_and_imm
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_and_imm
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY]], 786444, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2ANDri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
%1(s32) = G_CONSTANT i32 786444 ; 0x000c000c %1(s32) = G_CONSTANT i32 786444 ; 0x000c000c
%2(s32) = G_AND %0, %1 %2(s32) = G_AND %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2ANDri [[VREGX]], 786444, 14, $noreg, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGRES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_bfc name: test_bfc
# CHECK-LABEL: name: test_bfc
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_bfc
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[t2BFC:%[0-9]+]]:rgpr = t2BFC [[COPY]], -65529, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[t2BFC]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
%1(s32) = G_CONSTANT i32 -65529 ; 0xFFFF0007 %1(s32) = G_CONSTANT i32 -65529 ; 0xFFFF0007
%2(s32) = G_AND %0, %1 %2(s32) = G_AND %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2BFC [[VREGX]], -65529, 14, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGRES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_no_bfc_bad_mask name: test_no_bfc_bad_mask
# CHECK-LABEL: name: test_no_bfc_bad_mask
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_no_bfc_bad_mask
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY]], 786444, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2ANDri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = G_CONSTANT i32 786444 ; 0x000c000c %1(s32) = G_CONSTANT i32 786444 ; 0x000c000c
%2(s32) = G_AND %0, %1 %2(s32) = G_AND %0, %1
; CHECK-NOT: t2BFC
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_mvn name: test_mvn
# CHECK-LABEL: name: test_mvn
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_mvn
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[t2MVNr:%[0-9]+]]:rgpr = t2MVNr [[COPY]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2MVNr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
%1(s32) = G_CONSTANT i32 -1 %1(s32) = G_CONSTANT i32 -1
%2(s32) = G_XOR %0, %1 %2(s32) = G_XOR %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2MVNr [[VREGX]], 14, $noreg, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGRES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_bic name: test_bic
# CHECK-LABEL: name: test_bic
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
- { id: 4, class: gprb } - { id: 4, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_bic
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[t2BICrr:%[0-9]+]]:rgpr = t2BICrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2BICrr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK-DAG: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
; CHECK-DAG: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
%2(s32) = G_CONSTANT i32 -1 %2(s32) = G_CONSTANT i32 -1
%3(s32) = G_XOR %1, %2 %3(s32) = G_XOR %1, %2
%4(s32) = G_AND %0, %3 %4(s32) = G_AND %0, %3
; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2BICrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
$r0 = COPY %4(s32) $r0 = COPY %4(s32)
; CHECK: $r0 = COPY [[VREGRES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_orn name: test_orn
# CHECK-LABEL: name: test_orn
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
- { id: 4, class: gprb } - { id: 4, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_orn
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[t2ORNrr:%[0-9]+]]:rgpr = t2ORNrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2ORNrr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK-DAG: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
; CHECK-DAG: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
%2(s32) = G_CONSTANT i32 -1 %2(s32) = G_CONSTANT i32 -1
%3(s32) = G_XOR %1, %2 %3(s32) = G_XOR %1, %2
%4(s32) = G_OR %0, %3 %4(s32) = G_OR %0, %3
; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2ORNrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
$r0 = COPY %4(s32) $r0 = COPY %4(s32)
; CHECK: $r0 = COPY [[VREGRES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...

llvm/test/CodeGen/ARM/GlobalISel/thumb-select-select.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- | --- |
define void @test_select_s32() { ret void } define void @test_select_s32() { ret void }
define void @test_select_ptr() { ret void } define void @test_select_ptr() { ret void }
... ...
--- ---
name: test_select_s32 name: test_select_s32
# CHECK-LABEL: name: test_select_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_select_s32
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: t2TSTri [[COPY1]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[t2MOVCCr:%[0-9]+]]:rgpr = t2MOVCCr [[COPY]], [[COPY1]], 0 /* CC::eq */, $cpsr
; CHECK: $r0 = COPY [[t2MOVCCr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
%2(s1) = G_TRUNC %1(s32) %2(s1) = G_TRUNC %1(s32)
%3(s32) = G_SELECT %2(s1), %0, %1 %3(s32) = G_SELECT %2(s1), %0, %1
; CHECK: t2TSTri [[VREGY]], 1, 14, $noreg, implicit-def $cpsr
; CHECK: [[RES:%[0-9]+]]:rgpr = t2MOVCCr [[VREGX]], [[VREGY]], 0, $cpsr
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
; CHECK: $r0 = COPY [[RES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_select_ptr name: test_select_ptr
# CHECK-LABEL: name: test_select_ptr
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
- { id: 4, class: gprb } - { id: 4, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1, $r2 liveins: $r0, $r1, $r2
; CHECK-LABEL: name: test_select_ptr
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:gpr = COPY $r2
; CHECK: [[COPY3:%[0-9]+]]:rgpr = COPY [[COPY2]]
; CHECK: t2TSTri [[COPY3]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: [[t2MOVCCr:%[0-9]+]]:rgpr = t2MOVCCr [[COPY]], [[COPY1]], 0 /* CC::eq */, $cpsr
; CHECK: $r0 = COPY [[t2MOVCCr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(p0) = COPY $r0 %0(p0) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
%1(p0) = COPY $r1 %1(p0) = COPY $r1
; CHECK: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
%2(s32) = COPY $r2 %2(s32) = COPY $r2
; CHECK: [[VREGC32:%[0-9]+]]:gpr = COPY $r2
%3(s1) = G_TRUNC %2(s32) %3(s1) = G_TRUNC %2(s32)
; CHECK: [[VREGC:%[0-9]+]]:rgpr = COPY [[VREGC32]]
%4(p0) = G_SELECT %3(s1), %0, %1 %4(p0) = G_SELECT %3(s1), %0, %1
; CHECK: t2TSTri [[VREGC]], 1, 14, $noreg, implicit-def $cpsr
; CHECK: [[RES:%[0-9]+]]:rgpr = t2MOVCCr [[VREGX]], [[VREGY]], 0, $cpsr
$r0 = COPY %4(p0) $r0 = COPY %4(p0)
; CHECK: $r0 = COPY [[RES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...

llvm/test/CodeGen/ARM/GlobalISel/thumb-select-shifts.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- | --- |
define void @test_ashr_rr() { ret void } define void @test_ashr_rr() { ret void }
define void @test_shl_ri() { ret void } define void @test_shl_ri() { ret void }
define void @test_shl_ri_bad_imm() { ret void } define void @test_shl_ri_bad_imm() { ret void }
... ...
--- ---
name: test_ashr_rr name: test_ashr_rr
# CHECK-LABEL: name: test_ashr_rr
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test_ashr_rr
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[t2ASRrr:%[0-9]+]]:rgpr = t2ASRrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2ASRrr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
%1(s32) = COPY $r1 %1(s32) = COPY $r1
; CHECK: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
%2(s32) = G_ASHR %0, %1 %2(s32) = G_ASHR %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2ASRrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGRES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_shl_ri name: test_shl_ri
# CHECK-LABEL: name: test_shl_ri
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_shl_ri
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[t2LSLri:%[0-9]+]]:rgpr = t2LSLri [[COPY]], 31, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2LSLri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
%1(s32) = G_CONSTANT i32 31 %1(s32) = G_CONSTANT i32 31
%2(s32) = G_SHL %0, %1 %2(s32) = G_SHL %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2LSLri [[VREGX]], 31, 14, $noreg, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGRES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_shl_ri_bad_imm name: test_shl_ri_bad_imm
# CHECK-LABEL: name: test_shl_ri_bad_imm
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test_shl_ri_bad_imm
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 32, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[t2LSLrr:%[0-9]+]]:rgpr = t2LSLrr [[COPY]], [[t2MOVi]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2LSLrr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0 %0(s32) = COPY $r0
; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
%1(s32) = G_CONSTANT i32 32 %1(s32) = G_CONSTANT i32 32
; CHECK: [[VREGY:%[0-9]+]]:rgpr = t2MOVi 32, 14, $noreg, $noreg
%2(s32) = G_SHL %0, %1 %2(s32) = G_SHL %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2LSLrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
$r0 = COPY %2(s32) $r0 = COPY %2(s32)
; CHECK: $r0 = COPY [[VREGRES]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
... ...

llvm/test/CodeGen/ARM/cmp1-peephole-thumb.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=peephole-opt %s -o - | FileCheck %s # RUN: llc -run-pass=peephole-opt %s -o - | FileCheck %s
--- | --- |
; ModuleID = '<stdin>' ; ModuleID = '<stdin>'
source_filename = "<stdin>" source_filename = "<stdin>"
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumb-none--eabi" target triple = "thumb-none--eabi"
define i32 @f(i32 %a, i32 %b) { define i32 @f(i32 %a, i32 %b) {
entry: entry:
%mul = mul nsw i32 %b, %a %mul = mul nsw i32 %b, %a
%cmp = icmp eq i32 %mul, 0 %cmp = icmp eq i32 %mul, 0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
... ...
--- ---
name: f name: f
# CHECK-LABEL: name: f
alignment: 2 alignment: 2
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
selected: false selected: false
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr } - { id: 0, class: tgpr }
Show All 15 LinesframeInfo:
maxAlignment: 0 maxAlignment: 0
adjustsStack: false adjustsStack: false
hasCalls: false hasCalls: false
maxCallFrameSize: 0 maxCallFrameSize: 0
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
# CHECK: tMOVi8 1, 14, $noreg
# CHECK: tMOVi8 0, 14, $noreg
# CHECK: tMUL %1, %0, 14, $noreg
# CHECK-NOT: tCMPi8
body: | body: |
; CHECK-LABEL: name: f
; CHECK: bb.0.entry:
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK: liveins: $r0, $r1
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
; CHECK: %3:tgpr, $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: %4:tgpr, $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: %2:tgpr, $cpsr = tMUL [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
; CHECK: tBcc %bb.2, 0 /* CC::eq */, $cpsr
; CHECK: bb.1.entry:
; CHECK: successors: %bb.2(0x80000000)
; CHECK: bb.2.entry:
; CHECK: [[PHI:%[0-9]+]]:tgpr = PHI %4, %bb.1, %3, %bb.0
; CHECK: $r0 = COPY [[PHI]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
bb.0.entry: bb.0.entry:
liveins: $r0, $r1 liveins: $r0, $r1
%1 = COPY $r1 %1 = COPY $r1
%0 = COPY $r0 %0 = COPY $r0
%2, $cpsr = tMUL %1, %0, 14, $noreg %2, $cpsr = tMUL %1, %0, 14, $noreg
%3, $cpsr = tMOVi8 1, 14, $noreg %3, $cpsr = tMOVi8 1, 14, $noreg
%4, $cpsr = tMOVi8 0, 14, $noreg %4, $cpsr = tMOVi8 0, 14, $noreg
Show All 11 Lines

llvm/test/CodeGen/ARM/cmpxchg.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - %s -mtriple=armv7-unknown-linux-gnu -verify-machineinstrs -run-pass=arm-pseudo | FileCheck %s # RUN: llc -o - %s -mtriple=armv7-unknown-linux-gnu -verify-machineinstrs -run-pass=arm-pseudo | FileCheck %s
--- ---
# CHECK-LABEL: name: func
name: func name: func
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $r0_r1, $r4_r5, $r3, $lr liveins: $r0_r1, $r4_r5, $r3, $lr
dead early-clobber renamable $r0_r1, dead early-clobber renamable $r2 = CMP_SWAP_64 killed renamable $r3, killed renamable $r4_r5, renamable $r4_r5 :: (volatile load store monotonic monotonic 8) ; CHECK-LABEL: name: func
; CHECK: bb.0: ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $r0_r1, $r4_r5, $r3, $lr ; CHECK: liveins: $r0_r1, $r4_r5, $r3, $lr
; CHECK: bb.1: ; CHECK: .1:
; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK: liveins: $r4_r5, $r3 ; CHECK: liveins: $r4_r5, $r3
; CHECK: $r0_r1 = LDREXD $r3, 14, $noreg ; CHECK: $r0_r1 = LDREXD $r3, 14 /* CC::al */, $noreg
; CHECK: CMPrr killed $r0, $r4, 14, $noreg, implicit-def $cpsr ; CHECK: CMPrr killed $r0, $r4, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: CMPrr killed $r1, $r5, 0, killed $cpsr, implicit-def $cpsr ; CHECK: CMPrr killed $r1, $r5, 0 /* CC::eq */, killed $cpsr, implicit-def $cpsr
; CHECK: Bcc %bb.3, 1, killed $cpsr ; CHECK: Bcc %bb.3, 1 /* CC::ne */, killed $cpsr
; CHECK: bb.2: ; CHECK: .2:
; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000)
; CHECK: liveins: $r4_r5, $r3 ; CHECK: liveins: $r4_r5, $r3
; CHECK: early-clobber $r2 = STREXD $r4_r5, $r3, 14, $noreg ; CHECK: early-clobber $r2 = STREXD $r4_r5, $r3, 14 /* CC::al */, $noreg
; CHECK: CMPri killed $r2, 0, 14, $noreg, implicit-def $cpsr ; CHECK: CMPri killed $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: Bcc %bb.1, 1, killed $cpsr ; CHECK: Bcc %bb.1, 1 /* CC::ne */, killed $cpsr
; CHECK: bb.3: ; CHECK: .3:
dead early-clobber renamable $r0_r1, dead early-clobber renamable $r2 = CMP_SWAP_64 killed renamable $r3, killed renamable $r4_r5, renamable $r4_r5 :: (volatile load store monotonic monotonic 8)
... ...

llvm/test/CodeGen/ARM/codesize-ifcvt.mir

Show First 20 Lines • Show All 153 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: test_nosize ; CHECK-LABEL: name: test_nosize
; CHECK: bb.0 (%ir-block.0): ; CHECK: bb.0 (%ir-block.0):
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK: liveins: $lr, $r7 ; CHECK: liveins: $lr, $r7
; CHECK: renamable $r0 = t2MOVi 1, 14, $noreg, $noreg ; CHECK: renamable $r0 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPri killed renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tTAILJMPdND @extfunc, 1, killed $cpsr, implicit $sp, implicit $sp ; CHECK: tTAILJMPdND @extfunc, 1 /* CC::ne */, killed $cpsr, implicit $sp, implicit $sp
; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r7, killed $lr ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r7, killed $lr
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: renamable $r0 = t2MOVi 0, 14, $noreg, $noreg ; CHECK: renamable $r0 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPri killed renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2Bcc %bb.2, 1, killed $cpsr ; CHECK: t2Bcc %bb.2, 1 /* CC::ne */, killed $cpsr
; CHECK: bb.1.b2: ; CHECK: bb.1.b2:
; CHECK: successors: %bb.3(0x80000000) ; CHECK: successors: %bb.3(0x80000000)
; CHECK: tBL 14, $noreg, @extfunc, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $r0 ; CHECK: tBL 14 /* CC::al */, $noreg, @extfunc, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $r0
; CHECK: t2B %bb.3, 14, $noreg ; CHECK: t2B %bb.3, 14 /* CC::al */, $noreg
; CHECK: bb.2.b3: ; CHECK: bb.2.b3:
; CHECK: successors: %bb.3(0x80000000) ; CHECK: successors: %bb.3(0x80000000)
; CHECK: renamable $r0 = t2LDRi12 undef renamable $r0, 0, 14, $noreg :: (load 4 from `i32* undef`) ; CHECK: renamable $r0 = t2LDRi12 undef renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from `i32* undef`)
; CHECK: renamable $r0 = t2ANDri killed renamable $r0, 256, 14, $noreg, $noreg ; CHECK: renamable $r0 = t2ANDri killed renamable $r0, 256, 14 /* CC::al */, $noreg, $noreg
; CHECK: bb.3.b5: ; CHECK: bb.3.b5:
; CHECK: liveins: $r0 ; CHECK: liveins: $r0
; CHECK: t2CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPri killed renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r7, def $lr ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr
; CHECK: tBX_RET 0, killed $cpsr ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr
; CHECK: tTAILJMPdND @extfunc, 14, $noreg, implicit $sp, implicit $sp ; CHECK: tTAILJMPdND @extfunc, 14 /* CC::al */, $noreg, implicit $sp, implicit $sp
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
successors: %bb.1(0x50000000), %bb.6(0x30000000) successors: %bb.1(0x50000000), %bb.6(0x30000000)
liveins: $lr, $r7 liveins: $lr, $r7
renamable $r0 = t2MOVi 1, 14, $noreg, $noreg renamable $r0 = t2MOVi 1, 14, $noreg, $noreg
t2CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr t2CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr
t2Bcc %bb.6, 1, killed $cpsr t2Bcc %bb.6, 1, killed $cpsr
▲ Show 20 Lines • Show All 82 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: test_optsize ; CHECK-LABEL: name: test_optsize
; CHECK: bb.0 (%ir-block.0): ; CHECK: bb.0 (%ir-block.0):
; CHECK: successors: %bb.1(0x50000000), %bb.6(0x30000000) ; CHECK: successors: %bb.1(0x50000000), %bb.6(0x30000000)
; CHECK: liveins: $lr, $r7 ; CHECK: liveins: $lr, $r7
; CHECK: renamable $r0 = t2MOVi 1, 14, $noreg, $noreg ; CHECK: renamable $r0 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPri killed renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2Bcc %bb.6, 1, killed $cpsr ; CHECK: t2Bcc %bb.6, 1 /* CC::ne */, killed $cpsr
; CHECK: bb.1.b1: ; CHECK: bb.1.b1:
; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000) ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK: liveins: $r7, $lr ; CHECK: liveins: $r7, $lr
; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r7, killed $lr ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r7, killed $lr
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: renamable $r0 = t2MOVi 0, 14, $noreg, $noreg ; CHECK: renamable $r0 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPri killed renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2Bcc %bb.3, 1, killed $cpsr ; CHECK: t2Bcc %bb.3, 1 /* CC::ne */, killed $cpsr
; CHECK: bb.2.b2: ; CHECK: bb.2.b2:
; CHECK: successors: %bb.4(0x80000000) ; CHECK: successors: %bb.4(0x80000000)
; CHECK: tBL 14, $noreg, @extfunc, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $r0 ; CHECK: tBL 14 /* CC::al */, $noreg, @extfunc, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $r0
; CHECK: t2B %bb.4, 14, $noreg ; CHECK: t2B %bb.4, 14 /* CC::al */, $noreg
; CHECK: bb.3.b3: ; CHECK: bb.3.b3:
; CHECK: successors: %bb.4(0x80000000) ; CHECK: successors: %bb.4(0x80000000)
; CHECK: renamable $r0 = t2LDRi12 undef renamable $r0, 0, 14, $noreg :: (load 4 from `i32* undef`) ; CHECK: renamable $r0 = t2LDRi12 undef renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from `i32* undef`)
; CHECK: renamable $r0 = t2ANDri killed renamable $r0, 256, 14, $noreg, $noreg ; CHECK: renamable $r0 = t2ANDri killed renamable $r0, 256, 14 /* CC::al */, $noreg, $noreg
; CHECK: bb.4.b5: ; CHECK: bb.4.b5:
; CHECK: successors: %bb.5(0x30000000), %bb.6(0x50000000) ; CHECK: successors: %bb.5(0x30000000), %bb.6(0x50000000)
; CHECK: liveins: $r0 ; CHECK: liveins: $r0
; CHECK: t2CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPri killed renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r7, def $lr ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr
; CHECK: t2Bcc %bb.6, 1, killed $cpsr ; CHECK: t2Bcc %bb.6, 1 /* CC::ne */, killed $cpsr
; CHECK: bb.5.b8: ; CHECK: bb.5.b8:
; CHECK: liveins: $lr, $r7 ; CHECK: liveins: $lr, $r7
; CHECK: tBX_RET 14, $noreg ; CHECK: tBX_RET 14 /* CC::al */, $noreg
; CHECK: bb.6.b7: ; CHECK: bb.6.b7:
; CHECK: liveins: $lr, $r7 ; CHECK: liveins: $lr, $r7
; CHECK: tTAILJMPdND @extfunc, 14, $noreg, implicit $sp, implicit $sp ; CHECK: tTAILJMPdND @extfunc, 14 /* CC::al */, $noreg, implicit $sp, implicit $sp
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
successors: %bb.1(0x50000000), %bb.6(0x30000000) successors: %bb.1(0x50000000), %bb.6(0x30000000)
liveins: $lr, $r7 liveins: $lr, $r7
renamable $r0 = t2MOVi 1, 14, $noreg, $noreg renamable $r0 = t2MOVi 1, 14, $noreg, $noreg
t2CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr t2CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr
t2Bcc %bb.6, 1, killed $cpsr t2Bcc %bb.6, 1, killed $cpsr
▲ Show 20 Lines • Show All 82 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: test_minsize ; CHECK-LABEL: name: test_minsize
; CHECK: bb.0 (%ir-block.0): ; CHECK: bb.0 (%ir-block.0):
; CHECK: successors: %bb.1(0x50000000), %bb.6(0x30000000) ; CHECK: successors: %bb.1(0x50000000), %bb.6(0x30000000)
; CHECK: liveins: $lr, $r7 ; CHECK: liveins: $lr, $r7
; CHECK: renamable $r0 = t2MOVi 1, 14, $noreg, $noreg ; CHECK: renamable $r0 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPri killed renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2Bcc %bb.6, 1, killed $cpsr ; CHECK: t2Bcc %bb.6, 1 /* CC::ne */, killed $cpsr
; CHECK: bb.1.b1: ; CHECK: bb.1.b1:
; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000) ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK: liveins: $r7, $lr ; CHECK: liveins: $r7, $lr
; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r7, killed $lr ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r7, killed $lr
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: renamable $r0 = t2MOVi 0, 14, $noreg, $noreg ; CHECK: renamable $r0 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPri killed renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2Bcc %bb.3, 1, killed $cpsr ; CHECK: t2Bcc %bb.3, 1 /* CC::ne */, killed $cpsr
; CHECK: bb.2.b2: ; CHECK: bb.2.b2:
; CHECK: successors: %bb.4(0x80000000) ; CHECK: successors: %bb.4(0x80000000)
; CHECK: tBL 14, $noreg, @extfunc, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $r0 ; CHECK: tBL 14 /* CC::al */, $noreg, @extfunc, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $r0
; CHECK: t2B %bb.4, 14, $noreg ; CHECK: t2B %bb.4, 14 /* CC::al */, $noreg
; CHECK: bb.3.b3: ; CHECK: bb.3.b3:
; CHECK: successors: %bb.4(0x80000000) ; CHECK: successors: %bb.4(0x80000000)
; CHECK: renamable $r0 = t2LDRi12 undef renamable $r0, 0, 14, $noreg :: (load 4 from `i32* undef`) ; CHECK: renamable $r0 = t2LDRi12 undef renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from `i32* undef`)
; CHECK: renamable $r0 = t2ANDri killed renamable $r0, 256, 14, $noreg, $noreg ; CHECK: renamable $r0 = t2ANDri killed renamable $r0, 256, 14 /* CC::al */, $noreg, $noreg
; CHECK: bb.4.b5: ; CHECK: bb.4.b5:
; CHECK: successors: %bb.5(0x30000000), %bb.6(0x50000000) ; CHECK: successors: %bb.5(0x30000000), %bb.6(0x50000000)
; CHECK: liveins: $r0 ; CHECK: liveins: $r0
; CHECK: t2CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPri killed renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r7, def $lr ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr
; CHECK: t2Bcc %bb.6, 1, killed $cpsr ; CHECK: t2Bcc %bb.6, 1 /* CC::ne */, killed $cpsr
; CHECK: bb.5.b8: ; CHECK: bb.5.b8:
; CHECK: liveins: $lr, $r7 ; CHECK: liveins: $lr, $r7
; CHECK: tBX_RET 14, $noreg ; CHECK: tBX_RET 14 /* CC::al */, $noreg
; CHECK: bb.6.b7: ; CHECK: bb.6.b7:
; CHECK: liveins: $lr, $r7 ; CHECK: liveins: $lr, $r7
; CHECK: tTAILJMPdND @extfunc, 14, $noreg, implicit $sp, implicit $sp ; CHECK: tTAILJMPdND @extfunc, 14 /* CC::al */, $noreg, implicit $sp, implicit $sp
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
successors: %bb.1(0x50000000), %bb.6(0x30000000) successors: %bb.1(0x50000000), %bb.6(0x30000000)
liveins: $lr, $r7 liveins: $lr, $r7
renamable $r0 = t2MOVi 1, 14, $noreg, $noreg renamable $r0 = t2MOVi 1, 14, $noreg, $noreg
t2CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr t2CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr
t2Bcc %bb.6, 1, killed $cpsr t2Bcc %bb.6, 1, killed $cpsr
▲ Show 20 Lines • Show All 43 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/constant-island-movwt.mir

Show First 20 Lines • Show All 882 Lines • ▼ Show 20 Lines
... ...
# Check that the constant island isn't emitted in the middle of the movw+movt # Check that the constant island isn't emitted in the middle of the movw+movt
# pair. On windows, the IMAGE_REL_ARM_MOV32T relocation on the movw instruction # pair. On windows, the IMAGE_REL_ARM_MOV32T relocation on the movw instruction
# covers both movw and movt, so we can't allow anything to be inserted between # covers both movw and movt, so we can't allow anything to be inserted between
# them. # them.
# #
# CHECK: $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.118, 14, $noreg # CHECK: $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.118, 14 /* CC::al */, $noreg
# CHECK-NEXT: renamable $q12 = VDUP32q killed renamable $r5, 14, $noreg # CHECK-NEXT: renamable $q12 = VDUP32q killed renamable $r5, 14 /* CC::al */, $noreg
# CHECK-NEXT: t2B %bb.2, 14, $noreg # CHECK-NEXT: t2B %bb.2, 14 /* CC::al */, $noreg
# CHECK-NEXT: {{^ $}} # CHECK-NEXT: {{^ $}}
# CHECK-NEXT: bb.1 (align 4): # CHECK-NEXT: bb.1 (align 4):
# CHECK-NEXT: successors:{{ }} # CHECK-NEXT: successors:{{ }}
# CHECK-NEXT: {{^ $}} # CHECK-NEXT: {{^ $}}
# CHECK-NEXT: CONSTPOOL_ENTRY 1, %const.0, 4 # CHECK-NEXT: CONSTPOOL_ENTRY 1, %const.0, 4
# CHECK-NEXT: {{^ $}} # CHECK-NEXT: {{^ $}}
# CHECK-NEXT: bb.2.entry (align 2): # CHECK-NEXT: bb.2.entry (align 2):
# CHECK-NEXT: liveins: $d13, $s27, $r10, $r9, $r8, $s26, $d12, $s25, $s24, # CHECK-NEXT: liveins: $d13, $s27, $r10, $r9, $r8, $s26, $d12, $s25, $s24,
# CHECK-SAME: $d15, $s30, $s31, $d14, $s28, $s29, $lr, $r0, $d21, # CHECK-SAME: $d15, $s30, $s31, $d14, $s28, $s29, $lr, $r0, $d21,
# CHECK-SAME: $r3, $q10, $d20, $d17, $r2, $d25, $q11, $d22, $d23, # CHECK-SAME: $r3, $q10, $d20, $d17, $r2, $d25, $q11, $d22, $d23,
# CHECK-SAME: $r1, $q8, $d16, $s3, $q14, $d28, $d29, $d19, $s17, # CHECK-SAME: $r1, $q8, $d16, $s3, $q14, $d28, $d29, $d19, $s17,
# CHECK-SAME: $d8, $s16, $r6, $r7, $r4, $q12, $q9, $d18, $s0, $q15, # CHECK-SAME: $d8, $s16, $r6, $r7, $r4, $q12, $q9, $d18, $s0, $q15,
# CHECK-SAME: $d30, $d31, $r12, $s1, $d0, $d24, $s2, $d1, $q0, $s6, # CHECK-SAME: $d30, $d31, $r12, $s1, $d0, $d24, $s2, $d1, $q0, $s6,
# CHECK-SAME: $d3, $d2, $s4, $q1, $s7, $s5, $d9, $s18, $s19, $q4 # CHECK-SAME: $d3, $d2, $s4, $q1, $s7, $s5, $d9, $s18, $s19, $q4
# CHECK-NEXT: {{^ $}} # CHECK-NEXT: {{^ $}}
# CHECK-NEXT: $r5 = t2MOVi16 target-flags(arm-lo16) @.str.84, 14, $noreg # CHECK-NEXT: $r5 = t2MOVi16 target-flags(arm-lo16) @.str.84, 14 /* CC::al */, $noreg
# CHECK-NEXT: $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.84, 14, $noreg # CHECK-NEXT: $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.84, 14 /* CC::al */, $noreg

llvm/test/CodeGen/ARM/constant-islands-cfg.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumbv6m-apple-ios -run-pass=arm-cp-islands --verify-machine-dom-info %s -o - | FileCheck %s # RUN: llc -mtriple=thumbv6m-apple-ios -run-pass=arm-cp-islands --verify-machine-dom-info %s -o - | FileCheck %s
--- | --- |
; Function Attrs: minsize nounwind optsize uwtable ; Function Attrs: minsize nounwind optsize uwtable
define arm_aapcscc double @test_split_cfg(double %a, double %b) local_unnamed_addr #0 { define arm_aapcscc double @test_split_cfg(double %a, double %b) local_unnamed_addr #0 {
ret double undef ret double undef
} }
... ...
--- ---
Show All 20 LinesframeInfo:
stackProtector: '' stackProtector: ''
maxCallFrameSize: 0 maxCallFrameSize: 0
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
savePoint: '' savePoint: ''
restorePoint: '' restorePoint: ''
fixedStack: fixedStack:
# CHECK-LABEL: name: test_split_cfg
# CHECK: bb.0:
# CHECK: successors: %[[LONG_BR_BB:bb.[0-9]+]](0x{{[0-9a-f]+}}), %[[DEST1:bb.[0-9]+]](0x{{[0-9a-f]+}}){{$}}
# CHECK: tBcc %[[LONG_BR_BB]], 0, $cpsr
# CHECK: tB %[[DEST1]]
# CHECK: [[LONG_BR_BB]]:
# CHECK: successors: %[[DEST2:bb.[0-9]+]](0x{{[0-9a-f]+}}){{$}}
# CHECK: tB %[[DEST2]]
# CHECK: [[DEST1]]:
# CHECK: [[DEST2]]:
body: | body: |
; CHECK-LABEL: name: test_split_cfg
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000)
; CHECK: liveins: $r0
; CHECK: tCMPi8 killed $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.1, 0 /* CC::eq */, $cpsr
; CHECK: tB %bb.3, 14 /* CC::al */, $noreg
; CHECK: bb.1:
; CHECK: successors: %bb.4(0x40000000)
; CHECK: liveins: $cpsr
; CHECK: tB %bb.4, 14 /* CC::al */, $noreg
; CHECK: bb.2:
; CHECK: successors: %bb.3(0x80000000)
; CHECK: dead $r0 = SPACE 256, undef $r0
; CHECK: bb.3:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $pc
; CHECK: bb.4:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $pc
bb.0: bb.0:
liveins: $r0 liveins: $r0
tCMPi8 killed $r0, 0, 14, $noreg, implicit-def $cpsr tCMPi8 killed $r0, 0, 14, $noreg, implicit-def $cpsr
tBcc %bb.2, 1, killed $cpsr tBcc %bb.2, 1, killed $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.1: bb.1:
dead $r0 = SPACE 256, undef $r0 dead $r0 = SPACE 256, undef $r0
bb.2: bb.2:
tPOP_RET 14, $noreg, def $pc tPOP_RET 14, $noreg, def $pc
bb.3: bb.3:
tPOP_RET 14, $noreg, def $pc tPOP_RET 14, $noreg, def $pc
... ...

llvm/test/CodeGen/ARM/constant-islands-split-IT.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=arm-cp-islands %s -o - | FileCheck %s # RUN: llc -run-pass=arm-cp-islands %s -o - | FileCheck %s
# This test make sure that the constant pool does not keep in the middle of an IT block # This test make sure that the constant pool does not keep in the middle of an IT block
# when needs to split a block to place them. # when needs to split a block to place them.
# #
--- | --- |
; ModuleID = '<stdin>' ; ModuleID = '<stdin>'
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines - id: 1
alignment: 8 alignment: 8
isTargetSpecific: false isTargetSpecific: false
- id: 2 - id: 2
value: 'double 2.020000e+02' value: 'double 2.020000e+02'
alignment: 8 alignment: 8
isTargetSpecific: false isTargetSpecific: false
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: h
; CHECK: bb.0:
; CHECK: successors: %bb.4(0x80000000)
; CHECK: renamable $d0 = VLDRD %const.3, 0, 14 /* CC::al */, $noreg :: (load 8 from constant-pool)
; CHECK: dead renamable $r0 = SPACE 40, undef renamable $r0
; CHECK: tB %bb.4, 14 /* CC::al */, $noreg
; CHECK: bb.1 (align 8):
; CHECK: successors:
; CHECK: CONSTPOOL_ENTRY 3, %const.0, 8
; CHECK: bb.2:
; CHECK: successors:
; CHECK: bb.3 (align 8):
; CHECK: successors:
; CHECK: CONSTPOOL_ENTRY 5, %const.2, 8
; CHECK: bb.4 (align 2):
; CHECK: successors: %bb.5(0x80000000)
; CHECK: dead renamable $r0 = SPACE 790, undef renamable $r0
; CHECK: bb.5:
; CHECK: successors: %bb.7(0x80000000)
; CHECK: renamable $r0 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2CMPri $r0, 32, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: renamable $r0 = SPACE 200, undef renamable $r0
; CHECK: t2IT 0, 1, implicit-def $itstate
; CHECK: renamable $d0 = VLDRD %const.7, 0, 0 /* CC::eq */, $cpsr, implicit $itstate :: (load 8 from constant-pool)
; CHECK: renamable $d1 = VLDRD %const.5, 0, 0 /* CC::eq */, $cpsr, implicit $itstate :: (load 8 from constant-pool)
; CHECK: renamable $d2 = VLDRD %const.6, 0, 0 /* CC::eq */, $cpsr, implicit $itstate :: (load 8 from constant-pool)
; CHECK: $r0 = t2SUBri $r0, 12, 0 /* CC::eq */, $cpsr, $noreg, implicit killed $itstate
; CHECK: t2B %bb.7, 14 /* CC::al */, $noreg
; CHECK: bb.6 (align 8):
; CHECK: successors:
; CHECK: CONSTPOOL_ENTRY 7, %const.1, 8
; CHECK: bb.7 (align 2):
; CHECK: successors:
; CHECK: liveins: $r0, $cpsr, $d0, $s0, $s1, $d1, $s2, $s3, $d2, $s4, $s5
; CHECK: t2IT 0, 4, implicit-def $itstate
; CHECK: $sp = tMOVr $r0, 0 /* CC::eq */, $cpsr, implicit $itstate
; CHECK: $sp = t2LDMIA_RET $sp, 0 /* CC::eq */, killed $cpsr, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc, implicit killed $d0, implicit killed $d1, implicit killed $d2, implicit $sp, implicit killed $itstate
; CHECK: tBL 14 /* CC::al */, $noreg, &__stack_chk_fail, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
; CHECK: bb.8 (align 8):
; CHECK: successors:
; CHECK: CONSTPOOL_ENTRY 6, %const.0, 8
; CHECK: bb.9 (align 2):
; CHECK: successors: %bb.9(0x80000000)
; CHECK: liveins: $r0
; CHECK: dead renamable $r0 = SPACE 4000, undef renamable $r0
; CHECK: t2B %bb.9, 14 /* CC::al */, $noreg
; CHECK: bb.10:
bb.0: bb.0:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
renamable $d0 = VLDRD %const.0, 0, 14, $noreg :: (load 8 from constant-pool) renamable $d0 = VLDRD %const.0, 0, 14, $noreg :: (load 8 from constant-pool)
dead renamable $r0 = SPACE 40, undef renamable $r0 dead renamable $r0 = SPACE 40, undef renamable $r0
bb.1: bb.1:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
dead renamable $r0 = SPACE 790, undef renamable $r0 dead renamable $r0 = SPACE 790, undef renamable $r0
bb.2: bb.2:
successors: successors:
renamable $r0 = t2MOVi 0, 14, _, _ renamable $r0 = t2MOVi 0, 14, _, _
t2CMPri $r0, 32, 14, $noreg, implicit-def $cpsr t2CMPri $r0, 32, 14, $noreg, implicit-def $cpsr
renamable $r0 = SPACE 200, undef renamable $r0 renamable $r0 = SPACE 200, undef renamable $r0
; CHECK: t2IT 0, 1, implicit-def $itstate
; CHECK-NEXT: renamable $d0 = VLDRD %const.7, 0, 0, $cpsr, implicit $itstate :: (load 8 from constant-pool)
; CHECK-NEXT: renamable $d1 = VLDRD %const.5, 0, 0, $cpsr, implicit $itstate :: (load 8 from constant-pool)
; CHECK-NEXT: renamable $d2 = VLDRD %const.6, 0, 0, $cpsr, implicit $itstate :: (load 8 from constant-pool)
; CHECK-NEXT: $r0 = t2SUBri $r0, 12, 0, $cpsr, $noreg, implicit killed $itstate
t2IT 0, 1, implicit-def $itstate t2IT 0, 1, implicit-def $itstate
renamable $d0 = VLDRD %const.1, 0, 0, $cpsr, implicit $itstate :: (load 8 from constant-pool) renamable $d0 = VLDRD %const.1, 0, 0, $cpsr, implicit $itstate :: (load 8 from constant-pool)
renamable $d1 = VLDRD %const.2, 0, 0, $cpsr, implicit $itstate :: (load 8 from constant-pool) renamable $d1 = VLDRD %const.2, 0, 0, $cpsr, implicit $itstate :: (load 8 from constant-pool)
renamable $d2 = VLDRD %const.0, 0, 0, $cpsr, implicit $itstate :: (load 8 from constant-pool) renamable $d2 = VLDRD %const.0, 0, 0, $cpsr, implicit $itstate :: (load 8 from constant-pool)
$r0 = t2SUBri $r0, 12, 0, $cpsr, $noreg, implicit killed $itstate $r0 = t2SUBri $r0, 12, 0, $cpsr, $noreg, implicit killed $itstate
t2IT 0, 4, implicit-def $itstate t2IT 0, 4, implicit-def $itstate
$sp = tMOVr $r0, 0, $cpsr, implicit $itstate $sp = tMOVr $r0, 0, $cpsr, implicit $itstate
$sp = t2LDMIA_RET $sp, 0, killed $cpsr, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc, implicit killed $d0, implicit killed $d1, implicit killed $d2, implicit $sp, implicit killed $itstate $sp = t2LDMIA_RET $sp, 0, killed $cpsr, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc, implicit killed $d0, implicit killed $d1, implicit killed $d2, implicit $sp, implicit killed $itstate
Show All 9 Lines

llvm/test/CodeGen/ARM/expand-pseudos.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=arm-pseudo -verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -run-pass=arm-pseudo -verify-machineinstrs %s -o - | FileCheck %s
--- | --- |
target triple = "armv7---gnueabi" target triple = "armv7---gnueabi"
define i32 @test1(i32 %x) { define i32 @test1(i32 %x) {
entry: entry:
unreachable unreachable
} }
Show All 11 Lines
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$r0', virtual-reg: '' } - { reg: '$r0', virtual-reg: '' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test1
; CHECK: liveins: $r0
; CHECK: $r1 = MOVi 2, 14 /* CC::al */, $noreg, $noreg
; CHECK: CMPri killed $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: $r1 = MOVi16 500, 0 /* CC::eq */, killed $cpsr, implicit killed $r1
; CHECK: $r0 = MOVr killed $r1, 14 /* CC::al */, $noreg, $noreg
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
$r1 = MOVi 2, 14, $noreg, $noreg $r1 = MOVi 2, 14, $noreg, $noreg
CMPri killed $r0, 0, 14, $noreg, implicit-def $cpsr CMPri killed $r0, 0, 14, $noreg, implicit-def $cpsr
$r1 = MOVCCi16 killed $r1, 500, 0, killed $cpsr $r1 = MOVCCi16 killed $r1, 500, 0, killed $cpsr
$r0 = MOVr killed $r1, 14, $noreg, $noreg $r0 = MOVr killed $r1, 14, $noreg, $noreg
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test2 name: test2
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$r0', virtual-reg: '' } - { reg: '$r0', virtual-reg: '' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test2
; CHECK: liveins: $r0
; CHECK: $r1 = MOVi 2, 14 /* CC::al */, $noreg, $noreg
; CHECK: CMPri killed $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: $r1 = MOVi16 2068, 0 /* CC::eq */, $cpsr, implicit killed $r1
; CHECK: $r1 = MOVTi16 $r1, 7637, 0 /* CC::eq */, $cpsr
; CHECK: $r0 = MOVr killed $r1, 14 /* CC::al */, $noreg, $noreg
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
$r1 = MOVi 2, 14, $noreg, $noreg $r1 = MOVi 2, 14, $noreg, $noreg
CMPri killed $r0, 0, 14, $noreg, implicit-def $cpsr CMPri killed $r0, 0, 14, $noreg, implicit-def $cpsr
$r1 = MOVCCi32imm killed $r1, 500500500, 0, killed $cpsr $r1 = MOVCCi32imm killed $r1, 500500500, 0, killed $cpsr
$r0 = MOVr killed $r1, 14, $noreg, $noreg $r0 = MOVr killed $r1, 14, $noreg, $noreg
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test3 name: test3
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$r0', virtual-reg: '' } - { reg: '$r0', virtual-reg: '' }
- { reg: '$r1', virtual-reg: '' } - { reg: '$r1', virtual-reg: '' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test3
; CHECK: liveins: $r0, $r1
; CHECK: CMPri $r1, 500, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: $r0 = MOVr killed $r1, 12 /* CC::gt */, killed $cpsr, $noreg, implicit killed $r0
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
CMPri $r1, 500, 14, $noreg, implicit-def $cpsr CMPri $r1, 500, 14, $noreg, implicit-def $cpsr
$r0 = MOVCCr killed $r0, killed $r1, 12, killed $cpsr $r0 = MOVCCr killed $r0, killed $r1, 12, killed $cpsr
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
# CHECK-LABEL: name: test1
# CHECK: $r1 = MOVi16 500, 0, killed $cpsr, implicit killed $r1
# CHECK-LABEL: name: test2
# CHECK: $r1 = MOVi16 2068, 0, $cpsr, implicit killed $r1
# CHECK: $r1 = MOVTi16 $r1, 7637, 0, $cpsr
# CHECK-LABEL: name: test3
# CHECK: $r0 = MOVr killed $r1, 12, killed $cpsr, $noreg, implicit killed $r0

llvm/test/CodeGen/ARM/fpoffset_overflow.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - %s -mtriple=thumbv7-- -run-pass=stack-protector -run-pass=prologepilog | FileCheck %s # RUN: llc -o - %s -mtriple=thumbv7-- -run-pass=stack-protector -run-pass=prologepilog | FileCheck %s
--- ---
# This should trigger an emergency spill in the register scavenger because the # This should trigger an emergency spill in the register scavenger because the
# frame offset into the large argument is too large. # frame offset into the large argument is too large.
# CHECK-LABEL: name: func0
# CHECK: t2STRi12 killed [[SPILLED:\$r[0-9]+]], $sp, 0, 14, $noreg :: (store 4 into %stack.0)
# CHECK: [[SPILLED]] = t2ADDri killed $sp, 4096, 14, $noreg, $noreg
# CHECK: $sp = t2LDRi12 killed [[SPILLED]], 40, 14, $noreg :: (load 4)
# CHECK: [[SPILLED]] = t2LDRi12 $sp, 0, 14, $noreg :: (load 4 from %stack.0)
name: func0 name: func0
tracksRegLiveness: true tracksRegLiveness: true
fixedStack: fixedStack:
- { id: 0, offset: 4084, size: 4, alignment: 4, isImmutable: true, - { id: 0, offset: 4084, size: 4, alignment: 4, isImmutable: true,
isAliased: false } isAliased: false }
- { id: 1, offset: -12, size: 4096, alignment: 4, isImmutable: false, - { id: 1, offset: -12, size: 4096, alignment: 4, isImmutable: false,
isAliased: false } isAliased: false }
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: func0
; CHECK: liveins: $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr
; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -16
; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -20
; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -24
; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -28
; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -32
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -36
; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -40
; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -44
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -48
; CHECK: $sp = frame-setup tSUBspi $sp, 4, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 52
; CHECK: $r0 = IMPLICIT_DEF
; CHECK: $r1 = IMPLICIT_DEF
; CHECK: $r2 = IMPLICIT_DEF
; CHECK: $r3 = IMPLICIT_DEF
; CHECK: $r4 = IMPLICIT_DEF
; CHECK: $r5 = IMPLICIT_DEF
; CHECK: $r6 = IMPLICIT_DEF
; CHECK: $r7 = IMPLICIT_DEF
; CHECK: $r8 = IMPLICIT_DEF
; CHECK: $r9 = IMPLICIT_DEF
; CHECK: $r10 = IMPLICIT_DEF
; CHECK: $r11 = IMPLICIT_DEF
; CHECK: $r12 = IMPLICIT_DEF
; CHECK: $lr = IMPLICIT_DEF
; CHECK: t2STRi12 killed $r0, $sp, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.0)
; CHECK: $r0 = t2ADDri killed $sp, 4096, 14 /* CC::al */, $noreg, $noreg
; CHECK: $sp = t2LDRi12 killed $r0, 40, 14 /* CC::al */, $noreg :: (load 4)
; CHECK: $r0 = t2LDRi12 $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.0)
; CHECK: KILL $r0
; CHECK: KILL $r1
; CHECK: KILL $r2
; CHECK: KILL $r3
; CHECK: KILL $r4
; CHECK: KILL $r5
; CHECK: KILL $r6
; CHECK: KILL $r7
; CHECK: KILL $r8
; CHECK: KILL $r9
; CHECK: KILL $r10
; CHECK: KILL $r11
; CHECK: KILL $r12
; CHECK: KILL $lr
$r0 = IMPLICIT_DEF $r0 = IMPLICIT_DEF
$r1 = IMPLICIT_DEF $r1 = IMPLICIT_DEF
$r2 = IMPLICIT_DEF $r2 = IMPLICIT_DEF
$r3 = IMPLICIT_DEF $r3 = IMPLICIT_DEF
$r4 = IMPLICIT_DEF $r4 = IMPLICIT_DEF
$r5 = IMPLICIT_DEF $r5 = IMPLICIT_DEF
$r6 = IMPLICIT_DEF $r6 = IMPLICIT_DEF
$r7 = IMPLICIT_DEF $r7 = IMPLICIT_DEF
Show All 18 Lines bb.0:
KILL $r9 KILL $r9
KILL $r10 KILL $r10
KILL $r11 KILL $r11
KILL $r12 KILL $r12
KILL $lr KILL $lr
... ...
--- ---
# This should not trigger an emergency spill yet. # This should not trigger an emergency spill yet.
# CHECK-LABEL: name: func1
# CHECK-NOT: t2STRi12
# CHECK-NOT: t2ADDri
# CHECK: $r11 = t2LDRi12 $sp, 4092, 14, $noreg :: (load 4)
# CHECK-NOT: t2LDRi12
name: func1 name: func1
tracksRegLiveness: true tracksRegLiveness: true
fixedStack: fixedStack:
- { id: 0, offset: 4044, size: 4, alignment: 4, isImmutable: true, - { id: 0, offset: 4044, size: 4, alignment: 4, isImmutable: true,
isAliased: false } isAliased: false }
- { id: 1, offset: -12, size: 4056, alignment: 4, isImmutable: false, - { id: 1, offset: -12, size: 4056, alignment: 4, isImmutable: false,
isAliased: false } isAliased: false }
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: func1
; CHECK: liveins: $r4, $r5, $r6, $r8, $r9, $r10, $r11, $lr
; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 32
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -16
; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -20
; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -24
; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -28
; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -32
; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -36
; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -40
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -44
; CHECK: $sp = frame-setup tSUBspi $sp, 4, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 48
; CHECK: $r0 = IMPLICIT_DEF
; CHECK: $r1 = IMPLICIT_DEF
; CHECK: $r2 = IMPLICIT_DEF
; CHECK: $r3 = IMPLICIT_DEF
; CHECK: $r4 = IMPLICIT_DEF
; CHECK: $r5 = IMPLICIT_DEF
; CHECK: $r6 = IMPLICIT_DEF
; CHECK: $r8 = IMPLICIT_DEF
; CHECK: $r9 = IMPLICIT_DEF
; CHECK: $r10 = IMPLICIT_DEF
; CHECK: $r11 = IMPLICIT_DEF
; CHECK: $r12 = IMPLICIT_DEF
; CHECK: $lr = IMPLICIT_DEF
; CHECK: $r11 = t2LDRi12 $sp, 4092, 14 /* CC::al */, $noreg :: (load 4)
; CHECK: KILL $r0
; CHECK: KILL $r1
; CHECK: KILL $r2
; CHECK: KILL $r3
; CHECK: KILL $r4
; CHECK: KILL $r5
; CHECK: KILL $r6
; CHECK: KILL $r8
; CHECK: KILL $r9
; CHECK: KILL $r10
; CHECK: KILL $r11
; CHECK: KILL $r12
; CHECK: KILL $lr
$r0 = IMPLICIT_DEF $r0 = IMPLICIT_DEF
$r1 = IMPLICIT_DEF $r1 = IMPLICIT_DEF
$r2 = IMPLICIT_DEF $r2 = IMPLICIT_DEF
$r3 = IMPLICIT_DEF $r3 = IMPLICIT_DEF
$r4 = IMPLICIT_DEF $r4 = IMPLICIT_DEF
$r5 = IMPLICIT_DEF $r5 = IMPLICIT_DEF
$r6 = IMPLICIT_DEF $r6 = IMPLICIT_DEF
$r8 = IMPLICIT_DEF $r8 = IMPLICIT_DEF
Show All 22 Lines

llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc %s -o - -run-pass=if-converter -verify-machineinstrs | FileCheck %s # RUN: llc %s -o - -run-pass=if-converter -verify-machineinstrs | FileCheck %s
# Make sure we correctly if-convert blocks containing an INLINEASM_BR. # Make sure we correctly if-convert blocks containing an INLINEASM_BR.
# CHECK: t2CMPri killed renamable $r2, 34
# CHECK-NEXT: $r0 = t2MOVi 2, 1, $cpsr, $noreg
# CHECK-NEXT: $r0 = t2MOVi 3, 0, killed $cpsr, $noreg, implicit killed $r0
# CHECK-NEXT: tBL 14, $noreg, @fn2
# CHECK-NEXT: INLINEASM_BR &"", 9, 13, 0, 13, blockaddress(@fn1, %ir-block.l_yes)
# CHECK-NEXT: t2B %bb.1, 14, $noreg
--- | --- |
target triple = "thumbv7-unknown-linux-gnueabi" target triple = "thumbv7-unknown-linux-gnueabi"
define dso_local void @fn1() { define dso_local void @fn1() {
l_yes: l_yes:
ret void ret void
} }
declare dso_local i32 @fn2(...) declare dso_local i32 @fn2(...)
... ...
--- ---
name: fn1 name: fn1
alignment: 2 alignment: 2
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
; CHECK-LABEL: name: fn1
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK: liveins: $r0, $r1, $r2, $r4, $lr
; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $lr
; CHECK: t2CMPri killed renamable $r2, 34, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: $r0 = t2MOVi 2, 1 /* CC::ne */, $cpsr, $noreg
; CHECK: $r0 = t2MOVi 3, 0 /* CC::eq */, killed $cpsr, $noreg, implicit killed $r0
; CHECK: tBL 14 /* CC::al */, $noreg, @fn2, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit killed $r1, implicit-def $sp, implicit-def dead $r0
; CHECK: INLINEASM_BR &"", 9, 13, 0, 13, blockaddress(@fn1, %ir-block.l_yes)
; CHECK: t2B %bb.1, 14 /* CC::al */, $noreg
; CHECK: bb.1:
; CHECK: INLINEASM &"", 1
; CHECK: $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $pc
; CHECK: bb.2.l_yes (address-taken):
; CHECK: $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $pc
bb.0: bb.0:
successors: %bb.1(0x40000000), %bb.2(0x40000000) successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $r0, $r1, $r2, $r4, $lr liveins: $r0, $r1, $r2, $r4, $lr
$sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $lr $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $lr
t2CMPri killed renamable $r2, 34, 14, $noreg, implicit-def $cpsr t2CMPri killed renamable $r2, 34, 14, $noreg, implicit-def $cpsr
t2Bcc %bb.2, 1, killed $cpsr t2Bcc %bb.2, 1, killed $cpsr
bb.1: bb.1:
successors: %bb.3(0x40000000), %bb.4(0x40000000) successors: %bb.3(0x40000000), %bb.4(0x40000000)
liveins: $r1 liveins: $r1
$r0 = t2MOVi 3, 14, $noreg, $noreg $r0 = t2MOVi 3, 14, $noreg, $noreg
tBL 14, $noreg, @fn2, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $sp, implicit-def dead $r0 tBL 14, $noreg, @fn2, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $sp, implicit-def dead $r0
INLINEASM_BR &"", 9, 13, 0, 13, blockaddress(@fn1, %ir-block.l_yes) INLINEASM_BR &"", 9, 13, 0, 13, blockaddress(@fn1, %ir-block.l_yes)
t2B %bb.3, 14, $noreg t2B %bb.3, 14, $noreg
bb.2: bb.2:
successors: %bb.3(0x40000000), %bb.4(0x40000000) successors: %bb.3(0x40000000), %bb.4(0x40000000)
liveins: $r1 liveins: $r1
$r0 = t2MOVi 2, 14, $noreg, $noreg $r0 = t2MOVi 2, 14, $noreg, $noreg
tBL 14, $noreg, @fn2, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $sp, implicit-def dead $r0 tBL 14, $noreg, @fn2, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $sp, implicit-def dead $r0
INLINEASM_BR &"", 9, 13, 0, 13, blockaddress(@fn1, %ir-block.l_yes) INLINEASM_BR &"", 9, 13, 0, 13, blockaddress(@fn1, %ir-block.l_yes)
t2B %bb.3, 14, $noreg t2B %bb.3, 14, $noreg
bb.3: bb.3:
INLINEASM &"", 1 INLINEASM &"", 1
$sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $pc $sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $pc
bb.4.l_yes (address-taken): bb.4.l_yes (address-taken):
$sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $pc $sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $pc
... ...

llvm/test/CodeGen/ARM/ifcvt_diamond_unanalyzable.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumbv7-apple-ios -run-pass=if-converter %s -o - | FileCheck %s # RUN: llc -mtriple=thumbv7-apple-ios -run-pass=if-converter %s -o - | FileCheck %s
# Diamond testcase with unanalyzable instruction in the BB following the
# diamond.
--- ---
name: foo name: foo
body: | body: |
; CHECK-LABEL: name: foo
; CHECK: bb.0:
; CHECK: $sp = tADDspi $sp, 2, 1 /* CC::ne */, $cpsr
; CHECK: $sp = tADDspi $sp, 1, 0 /* CC::eq */, $cpsr, implicit $sp
; CHECK: $sp = tADDspi $sp, 3, 14 /* CC::al */, $noreg
; CHECK: tBX_RET 14 /* CC::al */, $noreg
bb.0: bb.0:
tBcc %bb.2, 1, $cpsr tBcc %bb.2, 1, $cpsr
bb.1: bb.1:
$sp = tADDspi $sp, 1, 14, _ $sp = tADDspi $sp, 1, 14, _
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.2: bb.2:
$sp = tADDspi $sp, 2, 14, _ $sp = tADDspi $sp, 2, 14, _
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3: bb.3:
successors: successors:
$sp = tADDspi $sp, 3, 14, _ $sp = tADDspi $sp, 3, 14, _
tBX_RET 14, _ tBX_RET 14, _
... ...
# Diamond testcase with unanalyzable instruction in the BB following the
# diamond.
# CHECK: body: |
# CHECK: bb.0:
# CHECK: $sp = tADDspi $sp, 2, 1, $cpsr
# CHECK: $sp = tADDspi $sp, 1, 0, $cpsr, implicit $sp
# CHECK: $sp = tADDspi $sp, 3, 14, $noreg
# CHECK: tBX_RET 14, $noreg

llvm/test/CodeGen/ARM/ifcvt_forked_diamond_unanalyzable.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumbv7-apple-ios -run-pass=if-converter %s -o - | FileCheck %s # RUN: llc -mtriple=thumbv7-apple-ios -run-pass=if-converter %s -o - | FileCheck %s
# Forked-diamond testcase with unanalyzable instructions in both the True and
# False BBs following the forked diamond.
--- ---
name: foo name: foo
body: | body: |
; CHECK-LABEL: name: foo
; CHECK: bb.0:
; CHECK: successors: %bb.2(0x20000000), %bb.1(0x60000000)
; CHECK: $sp = tADDspi $sp, 2, 1 /* CC::ne */, $cpsr
; CHECK: $sp = tADDspi $sp, 1, 0 /* CC::eq */, $cpsr, implicit $sp
; CHECK: t2Bcc %bb.2, 1 /* CC::ne */, $cpsr
; CHECK: bb.1:
; CHECK: $sp = tADDspi $sp, 4, 14 /* CC::al */, $noreg
; CHECK: tBX_RET 14 /* CC::al */, $noreg
; CHECK: bb.2:
; CHECK: $sp = tADDspi $sp, 3, 14 /* CC::al */, $noreg
; CHECK: tBX_RET 14 /* CC::al */, $noreg
bb.0: bb.0:
tBcc %bb.2, 1, $cpsr tBcc %bb.2, 1, $cpsr
bb.1: bb.1:
successors: %bb.3(0x20000000), %bb.4(0x60000000) successors: %bb.3(0x20000000), %bb.4(0x60000000)
$sp = tADDspi $sp, 1, 14, _ $sp = tADDspi $sp, 1, 14, _
tBcc %bb.3, 1, $cpsr tBcc %bb.3, 1, $cpsr
tB %bb.4, 14, $noreg tB %bb.4, 14, $noreg
Show All 9 Lines successors:
$sp = tADDspi $sp, 3, 14, _ $sp = tADDspi $sp, 3, 14, _
tBX_RET 14, _ tBX_RET 14, _
bb.4: bb.4:
successors: successors:
$sp = tADDspi $sp, 4, 14, _ $sp = tADDspi $sp, 4, 14, _
tBX_RET 14, _ tBX_RET 14, _
... ...
# Forked-diamond testcase with unanalyzable instructions in both the True and
# False BBs following the forked diamond.
# CHECK: body: |
# CHECK: bb.0:
# CHECK: successors: %bb.2(0x20000000), %bb.1(0x60000000)
# CHECK: $sp = tADDspi $sp, 2, 1, $cpsr
# CHECK: $sp = tADDspi $sp, 1, 0, $cpsr, implicit $sp
# CHECK: t2Bcc %bb.2, 1, $cpsr
# CHECK: bb.1:
# CHECK: $sp = tADDspi $sp, 4, 14, $noreg
# CHECK: tBX_RET 14, $noreg
# CHECK: bb.2:
# CHECK: $sp = tADDspi $sp, 3, 14, $noreg
# CHECK: tBX_RET 14, $noreg

llvm/test/CodeGen/ARM/ifcvt_simple_bad_zero_prob_succ.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumbv7-apple-ios -run-pass=if-converter %s -o - | FileCheck %s # RUN: llc -mtriple=thumbv7-apple-ios -run-pass=if-converter %s -o - | FileCheck %s
# We should only get bb.1 as successor to bb.1. No zero percent probability
# edge from bb.1 to bb.2. There shouldn't even be a bb.2 at all.
--- ---
name: f1 name: f1
body: | body: |
; CHECK-LABEL: name: f1
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: bb.1:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: tBRIND $r1, 1 /* CC::ne */, $cpsr
; CHECK: t2B %bb.1, 14 /* CC::al */, $noreg
; CHECK-NOT: bb.2:
bb.0: bb.0:
bb.1: bb.1:
tBcc %bb.3, 0, $cpsr tBcc %bb.3, 0, $cpsr
bb.2: bb.2:
bb.3: bb.3:
tBcc %bb.1, 0, $cpsr tBcc %bb.1, 0, $cpsr
bb.4: bb.4:
successors: %bb.1 successors: %bb.1
tBRIND $r1, 14, _ tBRIND $r1, 14, _
... ...
# We should only get bb.1 as successor to bb.1. No zero percent probability
# edge from bb.1 to bb.2. There shouldn't even be a bb.2 at all.
# CHECK: body: |
# CHECK: bb.0:
# CHECK: successors: %bb.1(0x80000000)
# CHECK: bb.1:
# CHECK: successors: %bb.1(0x80000000)
# CHECK-NOT: %bb.2(0x00000000)
# CHECK: tBRIND $r1, 1, $cpsr
# CHECK: t2B %bb.1
#CHECK-NOT: bb.2:

llvm/test/CodeGen/ARM/ifcvt_simple_unanalyzable.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumbv7-apple-ios -run-pass=if-converter %s -o - | FileCheck %s # RUN: llc -mtriple=thumbv7-apple-ios -run-pass=if-converter %s -o - | FileCheck %s
# Simple testcase with unanalyzable instructions in both TBB and FBB.
--- ---
name: foo name: foo
body: | body: |
; CHECK-LABEL: name: foo
; CHECK: bb.0:
; CHECK: $sp = tADDspi $sp, 2, 0 /* CC::eq */, $cpsr
; CHECK: tBX_RET 0 /* CC::eq */, $cpsr
; CHECK: tBX_RET 14 /* CC::al */, $noreg
bb.0: bb.0:
tBcc %bb.2, 0, $cpsr tBcc %bb.2, 0, $cpsr
bb.1: bb.1:
successors: successors:
tBX_RET 14, _ tBX_RET 14, _
bb.2: bb.2:
successors: successors:
$sp = tADDspi $sp, 2, 14, _ $sp = tADDspi $sp, 2, 14, _
tBX_RET 14, _ tBX_RET 14, _
... ...
# Simple testcase with unanalyzable instructions in both TBB and FBB.
# CHECK: body: |
# CHECK: bb.0:
# CHECK: $sp = tADDspi $sp, 2, 0, $cpsr
# CHECK: tBX_RET 0, $cpsr
# CHECK: tBX_RET 14, $noreg

llvm/test/CodeGen/ARM/ifcvt_triangleSameCvtNext.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumbv7-apple-ios -run-pass=if-converter -verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -mtriple=thumbv7-apple-ios -run-pass=if-converter -verify-machineinstrs %s -o - | FileCheck %s
# Both branches in bb.3 jump to bb.1. IfConversion shouldn't treat this as a
# tringle and insert the tADDspi in bb3, but leave it as it is.
... ...
--- ---
name: foo name: foo
body: | body: |
; CHECK-LABEL: name: foo
; CHECK: bb.0:
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK: tBcc %bb.2, 1 /* CC::ne */, $cpsr
; CHECK: bb.1:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: $sp = tADDspi $sp, 2, 14 /* CC::al */, $noreg
; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
; CHECK: bb.2:
; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK: tBcc %bb.3, 0 /* CC::eq */, $cpsr
; CHECK: tB %bb.2, 14 /* CC::al */, $noreg
; CHECK: bb.3:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: tBcc %bb.1, 1 /* CC::ne */, $cpsr
; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
bb.0: bb.0:
tBcc %bb.2, 1, $cpsr tBcc %bb.2, 1, $cpsr
bb.1: bb.1:
$sp = tADDspi $sp, 2, 14, _ $sp = tADDspi $sp, 2, 14, _
tB %bb.1, 14, $noreg tB %bb.1, 14, $noreg
bb.2: bb.2:
tBcc %bb.3, 0, $cpsr tBcc %bb.3, 0, $cpsr
tB %bb.2, 14, $noreg tB %bb.2, 14, $noreg
bb.3: bb.3:
tBcc %bb.1, 1, $cpsr tBcc %bb.1, 1, $cpsr
tB %bb.1, 14, $noreg tB %bb.1, 14, $noreg
... ...
# Both branches in bb.3 jump to bb.1. IfConversion shouldn't treat this as a
# tringle and insert the tADDspi in bb3, but leave it as it is.
# CHECK: bb.3:
# CHECK: successors: %bb.1
# CHECK-NOT: tADDspi
# CHECK: Bcc %bb.1, 1, $cpsr
# CHECK: B %bb.1

llvm/test/CodeGen/ARM/ifcvt_triangleWoCvtToNextEdge.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumb-apple-ios -run-pass=if-converter %s -o - | FileCheck %s # RUN: llc -mtriple=thumb-apple-ios -run-pass=if-converter %s -o - | FileCheck %s
# bb.2 has no successors, presumably because __stack_chk_fail doesn't return,
# so there should be no edge from bb.2 to bb.3.
# Nevertheless, IfConversion treats bb.1, bb.2, bb.3 as a triangle and
# inserts a predicated copy of bb.2 in bb.1.
# This caused r302876 to die with a failed assertion.
--- | --- |
declare void @__stack_chk_fail() declare void @__stack_chk_fail()
declare void @bar() declare void @bar()
define void @foo() { define void @foo() {
ret void ret void
} }
... ...
--- ---
name: foo name: foo
body: | body: |
; CHECK-LABEL: name: foo
; CHECK: bb.0:
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK: tBcc %bb.2, 1 /* CC::ne */, $cpsr
; CHECK: bb.1:
; CHECK: successors:
; CHECK: tBL 14 /* CC::al */, $cpsr, @__stack_chk_fail
; CHECK: bb.2:
; CHECK: tBL 1 /* CC::ne */, $cpsr, @__stack_chk_fail
; CHECK: $sp = tADDspi $sp, 2, 14 /* CC::al */, $noreg
; CHECK: $sp = tADDspi $sp, 2, 14 /* CC::al */, $noreg
; CHECK: tTAILJMPdND @bar, 14 /* CC::al */, $cpsr
bb.0: bb.0:
tBcc %bb.1, 1, $cpsr tBcc %bb.1, 1, $cpsr
tB %bb.2, 14, $noreg tB %bb.2, 14, $noreg
bb.1: bb.1:
tBcc %bb.3, 0, $cpsr tBcc %bb.3, 0, $cpsr
bb.2: bb.2:
successors: successors:
tBL 14, $cpsr, @__stack_chk_fail tBL 14, $cpsr, @__stack_chk_fail
bb.3: bb.3:
successors: successors:
$sp = tADDspi $sp, 2, 14, _ $sp = tADDspi $sp, 2, 14, _
$sp = tADDspi $sp, 2, 14, _ $sp = tADDspi $sp, 2, 14, _
tTAILJMPdND @bar, 14, $cpsr tTAILJMPdND @bar, 14, $cpsr
... ...
# bb.2 has no successors, presumably because __stack_chk_fail doesn't return,
# so there should be no edge from bb.2 to bb.3.
# Nevertheless, IfConversion treats bb.1, bb.2, bb.3 as a triangle and
# inserts a predicated copy of bb.2 in bb.1.
# This caused r302876 to die with a failed assertion.
# CHECK: bb.0:
# CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
# CHECK: tBcc %bb.2, 1, $cpsr
# CHECK: bb.1:
# CHECK-NOT: successors: %bb
# CHECK: tBL 14, $cpsr, @__stack_chk_fail
# CHECK: bb.2:
# CHECK-NOT: successors: %bb
# CHECK: tBL 1, $cpsr, @__stack_chk_fail
# CHECK: $sp = tADDspi $sp, 2, 14, $noreg
# CHECK: $sp = tADDspi $sp, 2, 14, $noreg
# CHECK: tTAILJMPdND @bar, 14, $cpsr

llvm/test/CodeGen/ARM/load_store_opt_clobber_cpsr.mir

# RUN: llc -mtriple=thumbv6m--eabi -verify-machineinstrs -run-pass=arm-ldst-opt %s -o - | FileCheck %s # RUN: llc -mtriple=thumbv6m--eabi -verify-machineinstrs -run-pass=arm-ldst-opt %s -o - | FileCheck %s
# Make sure bb.0 isn't transformed: it would incorrectly clobber CPSR. # Make sure bb.0 isn't transformed: it would incorrectly clobber CPSR.
# #
# Make sure bb.1 is transformed, so the test doesn't accidentally break. # Make sure bb.1 is transformed, so the test doesn't accidentally break.
# CHECK-LABEL: bb.0: # CHECK-LABEL: bb.0:
# CHECK: renamable $r0 = tLDRi renamable $r4, 0, 14, $noreg :: (load 4) # CHECK: renamable $r0 = tLDRi renamable $r4, 0, 14 /* CC::al */, $noreg :: (load 4)
# CHECK: renamable $r1 = tLDRi renamable $r4, 1, 14, $noreg :: (load 4) # CHECK: renamable $r1 = tLDRi renamable $r4, 1, 14 /* CC::al */, $noreg :: (load 4)
# CHECK-LABEL: bb.1: # CHECK-LABEL: bb.1:
# CHECK: $r4 = tLDMIA_UPD $r4, 14, $noreg, def $r0, def $r1 # CHECK: $r4 = tLDMIA_UPD $r4, 14 /* CC::al */, $noreg, def $r0, def $r1
# CHECK: $r4, dead $cpsr = tSUBi8 $r4, 8, 14, $noreg # CHECK: $r4, dead $cpsr = tSUBi8 $r4, 8, 14 /* CC::al */, $noreg
name: foo name: foo
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $r2, $r4 liveins: $r2, $r4
renamable $r0 = tLDRi renamable $r2, 4, 14, $noreg :: (load 4) renamable $r0 = tLDRi renamable $r2, 4, 14, $noreg :: (load 4)
dead renamable $r0, $cpsr = tADDi3 killed renamable $r0, 1, 14, $noreg dead renamable $r0, $cpsr = tADDi3 killed renamable $r0, 1, 14, $noreg
Show All 12 Lines

llvm/test/CodeGen/ARM/load_store_opt_kill.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=armv7-none-eabi -verify-machineinstrs -run-pass arm-ldst-opt %s -o - | FileCheck %s # RUN: llc -mtriple=armv7-none-eabi -verify-machineinstrs -run-pass arm-ldst-opt %s -o - | FileCheck %s
--- ---
# CHECK-LABEL: name: f
name: f name: f
# Make sure the load into $r0 doesn't clobber the base register before the second load uses it. # Make sure the load into $r0 doesn't clobber the base register before the second load uses it.
# CHECK: $r3 = LDRi12 $r0, 12, 14, $noreg
# CHECK-NEXT: $r0 = LDRi12 $r0, 8, 14, $noreg
body: | body: |
bb.0: bb.0:
liveins: $r0, $r3 liveins: $r0, $r3
; CHECK-LABEL: name: f
; CHECK: $r3 = LDRi12 $r0, 12, 14 /* CC::al */, $noreg
; CHECK: $r0 = LDRi12 $r0, 8, 14 /* CC::al */, $noreg
$r0, $r3 = LDRD $r0, $noreg, 8, 14, $noreg $r0, $r3 = LDRD $r0, $noreg, 8, 14, $noreg
... ...

llvm/test/CodeGen/ARM/load_store_opt_reg_limit.mir

# RUN: llc -mtriple=thumbv7--linux-android -verify-machineinstrs -run-pass=arm-ldst-opt %s -o - | FileCheck %s --check-prefix=CHECK-MERGE # RUN: llc -mtriple=thumbv7--linux-android -verify-machineinstrs -run-pass=arm-ldst-opt %s -o - | FileCheck %s --check-prefix=CHECK-MERGE
#CHECK-MERGE: foo #CHECK-MERGE: foo
name: foo name: foo
# CHECK-MERGE: VSTMDIA $r4, 14, $noreg, $d15, $d16, $d17, $d18, $d19, $d20, $d21, $d22, $d23, $d24, $d25, $d26, $d27, $d28, $d29, $d30 # CHECK-MERGE: VSTMDIA $r4, 14 /* CC::al */, $noreg, $d15, $d16, $d17, $d18, $d19, $d20, $d21, $d22, $d23, $d24, $d25, $d26, $d27, $d28, $d29, $d30
# CHECK-MERGE-NEXT: VSTRD $d31, $r4, 32, 14, $noreg :: (store 8) # CHECK-MERGE-NEXT: VSTRD $d31, $r4, 32, 14 /* CC::al */, $noreg :: (store 8)
# CHECK-MERGE: VSTMDIA killed $r0, 14, $noreg, $d4, $d5, $d6, $d7, $d8, $d9, $d10, $d11, $d12, $d13, $d14 # CHECK-MERGE: VSTMDIA killed $r0, 14 /* CC::al */, $noreg, $d4, $d5, $d6, $d7, $d8, $d9, $d10, $d11, $d12, $d13, $d14
body: | body: |
bb.0: bb.0:
VSTRD $d15, $r4, 0, 14, $noreg :: (store 8) VSTRD $d15, $r4, 0, 14, $noreg :: (store 8)
VSTRD $d16, $r4, 2, 14, $noreg :: (store 8) VSTRD $d16, $r4, 2, 14, $noreg :: (store 8)
VSTRD $d17, $r4, 4, 14, $noreg :: (store 8) VSTRD $d17, $r4, 4, 14, $noreg :: (store 8)
VSTRD $d18, $r4, 6, 14, $noreg :: (store 8) VSTRD $d18, $r4, 6, 14, $noreg :: (store 8)
VSTRD $d19, $r4, 8, 14, $noreg :: (store 8) VSTRD $d19, $r4, 8, 14, $noreg :: (store 8)
VSTRD $d20, $r4, 10, 14, $noreg :: (store 8) VSTRD $d20, $r4, 10, 14, $noreg :: (store 8)
Show All 26 Lines

llvm/test/CodeGen/ARM/machine-copyprop.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - %s -mtriple=armv7s-- -run-pass=machine-cp | FileCheck %s # RUN: llc -o - %s -mtriple=armv7s-- -run-pass=machine-cp | FileCheck %s
--- ---
# Test that machine copy prop recognizes the implicit-def operands on a COPY # Test that machine copy prop recognizes the implicit-def operands on a COPY
# as clobbering the register. # as clobbering the register.
# CHECK-LABEL: name: func
# CHECK: $d2 = VMOVv2i32 2, 14, $noreg
# CHECK: $s5 = COPY $s0, implicit $q1, implicit-def $q1
# CHECK: VST1q32 $r0, 0, $q1, 14, $noreg
# The following two COPYs must not be removed # The following two COPYs must not be removed
# CHECK: $s4 = COPY $s20, implicit-def $q1
# CHECK: $s5 = COPY $s0, implicit killed $d0, implicit $q1, implicit-def $q1
# CHECK: VST1q32 $r2, 0, $q1, 14, $noreg
name: func name: func
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: func
; CHECK: $d2 = VMOVv2i32 2, 14 /* CC::al */, $noreg
; CHECK: $s5 = COPY $s0, implicit $q1, implicit-def $q1
; CHECK: VST1q32 $r0, 0, $q1, 14 /* CC::al */, $noreg
; CHECK: $s4 = COPY $s20, implicit-def $q1
; CHECK: $s5 = COPY $s0, implicit killed $d0, implicit $q1, implicit-def $q1
; CHECK: VST1q32 $r2, 0, $q1, 14 /* CC::al */, $noreg
$d2 = VMOVv2i32 2, 14, $noreg $d2 = VMOVv2i32 2, 14, $noreg
$s5 = COPY $s0, implicit $q1, implicit-def $q1 $s5 = COPY $s0, implicit $q1, implicit-def $q1
VST1q32 $r0, 0, $q1, 14, $noreg VST1q32 $r0, 0, $q1, 14, $noreg
$s4 = COPY $s20, implicit-def $q1 $s4 = COPY $s20, implicit-def $q1
$s5 = COPY $s0, implicit killed $d0, implicit $q1, implicit-def $q1 $s5 = COPY $s0, implicit killed $d0, implicit $q1, implicit-def $q1
VST1q32 $r2, 0, $q1, 14, $noreg VST1q32 $r2, 0, $q1, 14, $noreg
... ...

llvm/test/CodeGen/ARM/peephole-phi.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - %s -mtriple=armv7-- -verify-machineinstrs -run-pass=peephole-opt | FileCheck %s # RUN: llc -o - %s -mtriple=armv7-- -verify-machineinstrs -run-pass=peephole-opt | FileCheck %s
# #
# Make sure we do not crash on this input. # Make sure we do not crash on this input.
# Note that this input could in principle be optimized, but right now we don't # Note that this input could in principle be optimized, but right now we don't
# have this case implemented so the output should simply be unchanged. # have this case implemented so the output should simply be unchanged.
#
# CHECK-LABEL: name: func
# CHECK: body: |
# CHECK: bb.0:
# CHECK: Bcc %bb.2, 1, undef $cpsr
#
# CHECK: bb.1:
# CHECK: %0:dpr = IMPLICIT_DEF
# CHECK: %1:gpr, %2:gpr = VMOVRRD %0, 14, $noreg
# CHECK: B %bb.3
#
# CHECK: bb.2:
# CHECK: %3:spr = IMPLICIT_DEF
# CHECK: %4:gpr = VMOVRS %3, 14, $noreg
#
# CHECK: bb.3:
# CHECK: %5:gpr = PHI %1, %bb.1, %4, %bb.2
# CHECK: %6:spr = VMOVSR %5, 14, $noreg
--- ---
name: func0 name: func0
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
; CHECK-LABEL: name: func0
; CHECK: bb.0:
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK: Bcc %bb.2, 1 /* CC::ne */, undef $cpsr
; CHECK: bb.1:
; CHECK: successors: %bb.3(0x80000000)
; CHECK: [[DEF:%[0-9]+]]:dpr = IMPLICIT_DEF
; CHECK: [[VMOVRRD:%[0-9]+]]:gpr, [[VMOVRRD1:%[0-9]+]]:gpr = VMOVRRD [[DEF]], 14 /* CC::al */, $noreg
; CHECK: B %bb.3
; CHECK: bb.2:
; CHECK: successors: %bb.3(0x80000000)
; CHECK: [[DEF1:%[0-9]+]]:spr = IMPLICIT_DEF
; CHECK: [[VMOVRS:%[0-9]+]]:gpr = VMOVRS [[DEF1]], 14 /* CC::al */, $noreg
; CHECK: bb.3:
; CHECK: [[PHI:%[0-9]+]]:gpr = PHI [[VMOVRRD]], %bb.1, [[VMOVRS]], %bb.2
; CHECK: [[VMOVSR:%[0-9]+]]:spr = VMOVSR [[PHI]], 14 /* CC::al */, $noreg
bb.0: bb.0:
Bcc %bb.2, 1, undef $cpsr Bcc %bb.2, 1, undef $cpsr
bb.1: bb.1:
%0:dpr = IMPLICIT_DEF %0:dpr = IMPLICIT_DEF
%1:gpr, %2:gpr = VMOVRRD %0:dpr, 14, $noreg %1:gpr, %2:gpr = VMOVRRD %0:dpr, 14, $noreg
B %bb.3 B %bb.3
bb.2: bb.2:
%3:spr = IMPLICIT_DEF %3:spr = IMPLICIT_DEF
%4:gpr = VMOVRS %3:spr, 14, $noreg %4:gpr = VMOVRS %3:spr, 14, $noreg
bb.3: bb.3:
%5:gpr = PHI %1, %bb.1, %4, %bb.2 %5:gpr = PHI %1, %bb.1, %4, %bb.2
%6:spr = VMOVSR %5, 14, $noreg %6:spr = VMOVSR %5, 14, $noreg
... ...
# CHECK-LABEL: name: func1
# CHECK: %6:spr = PHI %0, %bb.1, %2, %bb.2
# CHECK: %7:spr = COPY %6
--- ---
name: func1 name: func1
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
; CHECK-LABEL: name: func1
; CHECK: bb.0:
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK: Bcc %bb.2, 1 /* CC::ne */, undef $cpsr
; CHECK: bb.1:
; CHECK: successors: %bb.3(0x80000000)
; CHECK: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF
; CHECK: [[VMOVRS:%[0-9]+]]:gpr = VMOVRS [[DEF]], 14 /* CC::al */, $noreg
; CHECK: B %bb.3
; CHECK: bb.2:
; CHECK: successors: %bb.3(0x80000000)
; CHECK: [[DEF1:%[0-9]+]]:spr = IMPLICIT_DEF
; CHECK: [[VMOVRS1:%[0-9]+]]:gpr = VMOVRS [[DEF1]], 14 /* CC::al */, $noreg
; CHECK: bb.3:
; CHECK: [[PHI:%[0-9]+]]:spr = PHI [[DEF]], %bb.1, [[DEF1]], %bb.2
; CHECK: [[PHI1:%[0-9]+]]:gpr = PHI [[VMOVRS]], %bb.1, [[VMOVRS1]], %bb.2
; CHECK: [[COPY:%[0-9]+]]:spr = COPY [[PHI]]
bb.0: bb.0:
Bcc %bb.2, 1, undef $cpsr Bcc %bb.2, 1, undef $cpsr
bb.1: bb.1:
%1:spr = IMPLICIT_DEF %1:spr = IMPLICIT_DEF
%0:gpr = VMOVRS %1, 14, $noreg %0:gpr = VMOVRS %1, 14, $noreg
B %bb.3 B %bb.3
bb.2: bb.2:
%3:spr = IMPLICIT_DEF %3:spr = IMPLICIT_DEF
%2:gpr = VMOVRS %3:spr, 14, $noreg %2:gpr = VMOVRS %3:spr, 14, $noreg
bb.3: bb.3:
%4:gpr = PHI %0, %bb.1, %2, %bb.2 %4:gpr = PHI %0, %bb.1, %2, %bb.2
%5:spr = VMOVSR %4, 14, $noreg %5:spr = VMOVSR %4, 14, $noreg
... ...
# The current implementation doesn't perform any transformations if undef # The current implementation doesn't perform any transformations if undef
# operands are involved. # operands are involved.
# CHECK-LABEL: name: func-undefops
# CHECK: body: |
# CHECK: bb.0:
# CHECK: Bcc %bb.2, 1, undef $cpsr
#
# CHECK: bb.1:
# CHECK: %0:gpr = VMOVRS undef %1:spr, 14, $noreg
# CHECK: B %bb.3
#
# CHECK: bb.2:
# CHECK: %2:gpr = VMOVRS undef %3:spr, 14, $noreg
#
# CHECK: bb.3:
# CHECK: %4:gpr = PHI %0, %bb.1, %2, %bb.2
# CHECK: %5:spr = VMOVSR %4, 14, $noreg
--- ---
name: func-undefops name: func-undefops
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
; CHECK-LABEL: name: func-undefops
; CHECK: bb.0:
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK: Bcc %bb.2, 1 /* CC::ne */, undef $cpsr
; CHECK: bb.1:
; CHECK: successors: %bb.3(0x80000000)
; CHECK: [[VMOVRS:%[0-9]+]]:gpr = VMOVRS undef %1:spr, 14 /* CC::al */, $noreg
; CHECK: B %bb.3
; CHECK: bb.2:
; CHECK: successors: %bb.3(0x80000000)
; CHECK: [[VMOVRS1:%[0-9]+]]:gpr = VMOVRS undef %3:spr, 14 /* CC::al */, $noreg
; CHECK: bb.3:
; CHECK: [[PHI:%[0-9]+]]:gpr = PHI [[VMOVRS]], %bb.1, [[VMOVRS1]], %bb.2
; CHECK: [[VMOVSR:%[0-9]+]]:spr = VMOVSR [[PHI]], 14 /* CC::al */, $noreg
bb.0: bb.0:
Bcc %bb.2, 1, undef $cpsr Bcc %bb.2, 1, undef $cpsr
bb.1: bb.1:
%0:gpr = VMOVRS undef %1:spr, 14, $noreg %0:gpr = VMOVRS undef %1:spr, 14, $noreg
B %bb.3 B %bb.3
bb.2: bb.2:
%2:gpr = VMOVRS undef %3:spr, 14, $noreg %2:gpr = VMOVRS undef %3:spr, 14, $noreg
bb.3: bb.3:
%4:gpr = PHI %0, %bb.1, %2, %bb.2 %4:gpr = PHI %0, %bb.1, %2, %bb.2
%5:spr = VMOVSR %4, 14, $noreg %5:spr = VMOVSR %4, 14, $noreg
... ...

llvm/test/CodeGen/ARM/regcoal-invalid-subrange-update.mir

Show First 20 Lines • Show All 59 Lines • ▼ Show 20 Lines bb.0:
; CHECK-LABEL: name: main ; CHECK-LABEL: name: main
; CHECK: liveins: $d2, $s1, $d4 ; CHECK: liveins: $d2, $s1, $d4
; CHECK: undef %4.dsub_0:qqqqpr_with_ssub_4 = COPY $d4 ; CHECK: undef %4.dsub_0:qqqqpr_with_ssub_4 = COPY $d4
; CHECK: %4.ssub_4:qqqqpr_with_ssub_4 = COPY $s1 ; CHECK: %4.ssub_4:qqqqpr_with_ssub_4 = COPY $s1
; CHECK: %4.dsub_1:qqqqpr_with_ssub_4 = COPY $d2 ; CHECK: %4.dsub_1:qqqqpr_with_ssub_4 = COPY $d2
; CHECK: %4.dsub_3:qqqqpr_with_ssub_4 = COPY %4.dsub_1 ; CHECK: %4.dsub_3:qqqqpr_with_ssub_4 = COPY %4.dsub_1
; CHECK: KILL implicit-def %4.dsub_2, implicit %4.qqsub_0 ; CHECK: KILL implicit-def %4.dsub_2, implicit %4.qqsub_0
; CHECK: %4.dsub_4:qqqqpr_with_ssub_4 = COPY %4.dsub_1 ; CHECK: %4.dsub_4:qqqqpr_with_ssub_4 = COPY %4.dsub_1
; CHECK: tBX_RET 14, $noreg, implicit %4.ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %4.ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
%3:dpr_vfp2 = COPY $d4 %3:dpr_vfp2 = COPY $d4
undef %0.ssub_0:dpr_vfp2 = COPY $s1 undef %0.ssub_0:dpr_vfp2 = COPY $s1
%1:dpr_vfp2 = COPY $d2 %1:dpr_vfp2 = COPY $d2
undef %4.dsub_0:dquad = COPY %3 undef %4.dsub_0:dquad = COPY %3
%4.dsub_1:dquad = COPY %1 %4.dsub_1:dquad = COPY %1
%4.dsub_2:dquad = COPY %0 %4.dsub_2:dquad = COPY %0
%4.dsub_3:dquad = COPY %1 %4.dsub_3:dquad = COPY %1
KILL implicit-def undef %5.dsub_0:dtriple, implicit %4 KILL implicit-def undef %5.dsub_0:dtriple, implicit %4
%5.dsub_1:dtriple = COPY %4.dsub_3 %5.dsub_1:dtriple = COPY %4.dsub_3
%5.dsub_2:dtriple = COPY %1 %5.dsub_2:dtriple = COPY %1
tBX_RET 14, $noreg, implicit %5 tBX_RET 14, $noreg, implicit %5
... ...

llvm/test/CodeGen/ARM/register-scavenger-exceptions.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - %s -run-pass=prologepilog | FileCheck %s # RUN: llc -o - %s -run-pass=prologepilog | FileCheck %s
--- | --- |
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "armv7--none-eabi" target triple = "armv7--none-eabi"
define hidden void @_Z3foov(i32 %P0, ...) { define hidden void @_Z3foov(i32 %P0, ...) {
entry: entry:
%V1 = alloca [4075 x i8], align 8 %V1 = alloca [4075 x i8], align 8
%tmp3 = alloca i8, i32 undef, align 8 %tmp3 = alloca i8, i32 undef, align 8
unreachable unreachable
} }
declare dso_local void @_Z3barv() noreturn declare dso_local void @_Z3barv() noreturn
... ...
--- ---
# Check that the register scavenger does pick r5 (not preserved in prolog) for # Check that the register scavenger does pick r5 (not preserved in prolog) for
# materialising a stack frame address when the function ends in throwing an # materialising a stack frame address when the function ends in throwing an
# exception. # exception.
# CHECK: $sp = frame-setup STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r10, killed $r11, killed $lr
# CHECK-NOT: $r5
name: _Z3foov name: _Z3foov
stack: stack:
- { id: 0, name: V1, type: default, offset: 0, size: 5000, alignment: 8, - { id: 0, name: V1, type: default, offset: 0, size: 5000, alignment: 8,
stack-id: default, callee-saved-register: '', callee-saved-restored: true, stack-id: default, callee-saved-register: '', callee-saved-restored: true,
local-offset: -4080, debug-info-variable: '', debug-info-expression: '', local-offset: -4080, debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' } debug-info-location: '' }
- { id: 1, name: tmp3, type: variable-sized, offset: 0, alignment: 1, - { id: 1, name: tmp3, type: variable-sized, offset: 0, alignment: 1,
stack-id: default, callee-saved-register: '', callee-saved-restored: true, stack-id: default, callee-saved-register: '', callee-saved-restored: true,
local-offset: -4112, debug-info-variable: '', debug-info-expression: '', local-offset: -4112, debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' } debug-info-location: '' }
- { id: 2, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4, - { id: 2, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '', callee-saved-restored: true, stack-id: default, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: _Z3foov
; CHECK: $sp = frame-setup STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r10, killed $r11, killed $lr
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8
; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16
; CHECK: $r11 = frame-setup ADDri killed $sp, 8, 14 /* CC::al */, $noreg, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r11, 8
; CHECK: $sp = frame-setup SUBri killed $sp, 912, 14 /* CC::al */, $noreg, $noreg
; CHECK: $sp = frame-setup SUBri killed $sp, 4096, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r1 = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r2 = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r3 = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r4 = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r10 = SUBri killed $r11, 4096, 14 /* CC::al */, $noreg, $noreg
; CHECK: STRi12 killed $lr, killed $r10, -916, 14 /* CC::al */, $noreg :: (store 4 into %stack.2)
; CHECK: BL @_Z3barv, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3, implicit killed $r4, implicit-def $sp
$r0 = MOVi 0, 14, $noreg, $noreg $r0 = MOVi 0, 14, $noreg, $noreg
$r1 = MOVi 0, 14, $noreg, $noreg $r1 = MOVi 0, 14, $noreg, $noreg
$r2 = MOVi 0, 14, $noreg, $noreg $r2 = MOVi 0, 14, $noreg, $noreg
$r3 = MOVi 0, 14, $noreg, $noreg $r3 = MOVi 0, 14, $noreg, $noreg
$r4 = MOVi 0, 14, $noreg, $noreg $r4 = MOVi 0, 14, $noreg, $noreg
STRi12 killed $lr, %stack.2, 0, 14, $noreg :: (store 4 into %stack.2) STRi12 killed $lr, %stack.2, 0, 14, $noreg :: (store 4 into %stack.2)
BL @_Z3barv, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3, implicit killed $r4, implicit-def $sp BL @_Z3barv, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3, implicit killed $r4, implicit-def $sp
... ...

llvm/test/CodeGen/ARM/tail-dup-bundle.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - %s -run-pass=block-placement -mtriple=thumbv7k-apple-ios8.0.0 -verify-machineinstrs -O3 | FileCheck %s # RUN: llc -o - %s -run-pass=block-placement -mtriple=thumbv7k-apple-ios8.0.0 -verify-machineinstrs -O3 | FileCheck %s
--- ---
# CHECK-LABEL: name: func
# Make sure the bundle gets duplicated correctly # Make sure the bundle gets duplicated correctly
# CHECK: BUNDLE implicit-def dead $itstate, implicit-def $cpsr, implicit killed $r0, implicit killed $cpsr {
# CHECK: t2IT 1, 24, implicit-def $itstate
# CHECK: t2CMPri killed $r0, 9, 1, killed $cpsr, implicit-def $cpsr, implicit internal killed $itstate
# CHECK: }
# CHECK: BUNDLE implicit-def dead $itstate, implicit-def $cpsr, implicit killed $r0, implicit killed $cpsr {
# CHECK: t2IT 1, 24, implicit-def $itstate
# CHECK: t2CMPri killed $r0, 9, 1, killed $cpsr, implicit-def $cpsr, implicit internal killed $itstate
# CHECK: }
name: func name: func
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
; CHECK-LABEL: name: func
; CHECK: bb.0:
; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK: liveins: $r0, $lr, $r7
; CHECK: t2CMPri $r0, 32, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: BUNDLE implicit-def dead $itstate, implicit-def $cpsr, implicit killed $r0, implicit killed $cpsr {
; CHECK: t2IT 1, 24, implicit-def $itstate
; CHECK: t2CMPri killed $r0, 9, 1 /* CC::ne */, killed $cpsr, implicit-def $cpsr, implicit internal killed $itstate
; CHECK: }
; CHECK: t2Bcc %bb.3, 1 /* CC::ne */, killed $cpsr
; CHECK: bb.2:
; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK: $r0 = IMPLICIT_DEF
; CHECK: t2CMPri $r0, 32, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: BUNDLE implicit-def dead $itstate, implicit-def $cpsr, implicit killed $r0, implicit killed $cpsr {
; CHECK: t2IT 1, 24, implicit-def $itstate
; CHECK: t2CMPri killed $r0, 9, 1 /* CC::ne */, killed $cpsr, implicit-def $cpsr, implicit internal killed $itstate
; CHECK: }
; CHECK: t2Bcc %bb.2, 0 /* CC::eq */, killed $cpsr
; CHECK: bb.3:
; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK: $r0 = IMPLICIT_DEF
; CHECK: t2CMPri $r0, 32, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: BUNDLE implicit-def dead $itstate, implicit-def $cpsr, implicit killed $r0, implicit killed $cpsr {
; CHECK: t2IT 1, 24, implicit-def $itstate
; CHECK: t2CMPri killed $r0, 9, 1 /* CC::ne */, killed $cpsr, implicit-def $cpsr, implicit internal killed $itstate
; CHECK: }
; CHECK: t2Bcc %bb.3, 1 /* CC::ne */, killed $cpsr
; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg
bb.0: bb.0:
liveins: $r0, $lr, $r7 liveins: $r0, $lr, $r7
bb.1: bb.1:
liveins: $r0 liveins: $r0
t2CMPri $r0, 32, 14, $noreg, implicit-def $cpsr t2CMPri $r0, 32, 14, $noreg, implicit-def $cpsr
BUNDLE implicit-def dead $itstate, implicit-def $cpsr, implicit killed $r0, implicit killed $cpsr { BUNDLE implicit-def dead $itstate, implicit-def $cpsr, implicit killed $r0, implicit killed $cpsr {
Show All 13 Lines

llvm/test/CodeGen/ARM/tst-peephole.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=peephole-opt %s -o - -verify-machineinstrs | FileCheck %s # RUN: llc -run-pass=peephole-opt %s -o - -verify-machineinstrs | FileCheck %s
# The and -> ands transform is sensitive to scheduling; make sure we don't # The and -> ands transform is sensitive to scheduling; make sure we don't
# transform cases which aren't legal. # transform cases which aren't legal.
# CHECK-LABEL: name: foo_transform
# CHECK: %2:gpr = ANDri %0, 1, 14, $noreg, def $cpsr
# CHECK-NEXT: %3:gpr = MOVCCi16 %1, 5, 0, $cpsr
# CHECK-LABEL: name: foo_notransform
# CHECK: TSTri %0, 1, 14, $noreg, implicit-def $cpsr
# CHECK-NEXT: %2:gpr = MOVCCi16 %1, 5, 0, $cpsr
--- | --- |
target triple = "armv7-unknown-unknown" target triple = "armv7-unknown-unknown"
define i32 @foo_transform(i32 %in) { define i32 @foo_transform(i32 %in) {
ret i32 undef ret i32 undef
} }
define i32 @foo_notransform(i32 %in) { define i32 @foo_notransform(i32 %in) {
ret i32 undef ret i32 undef
} }
... ...
--- ---
name: foo_transform name: foo_transform
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: foo_transform
; CHECK: liveins: $r0
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[COPY]], 1, 14 /* CC::al */, $noreg, def $cpsr
; CHECK: [[MOVCCi16_:%[0-9]+]]:gpr = MOVCCi16 [[MOVi]], 5, 0 /* CC::eq */, $cpsr
; CHECK: $r0 = COPY killed [[MOVCCi16_]]
; CHECK: $r1 = COPY killed [[ANDri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
%1:gpr = COPY $r0 %1:gpr = COPY $r0
%2:gpr = MOVi 4, 14, $noreg, $noreg %2:gpr = MOVi 4, 14, $noreg, $noreg
%4:gpr = ANDri %1:gpr, 1, 14, $noreg, $noreg %4:gpr = ANDri %1:gpr, 1, 14, $noreg, $noreg
TSTri %1:gpr, 1, 14, $noreg, implicit-def $cpsr TSTri %1:gpr, 1, 14, $noreg, implicit-def $cpsr
%3:gpr = MOVCCi16 %2, 5, 0, $cpsr %3:gpr = MOVCCi16 %2, 5, 0, $cpsr
$r0 = COPY killed %3 $r0 = COPY killed %3
$r1 = COPY killed %4 $r1 = COPY killed %4
BX_RET 14, $noreg, implicit $r0, implicit $r1 BX_RET 14, $noreg, implicit $r0, implicit $r1
Show All 16 Lines

llvm/test/CodeGen/ARM/vldm-liveness.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass arm-ldst-opt -verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -run-pass arm-ldst-opt -verify-machineinstrs %s -o - | FileCheck %s
# ARM load store optimizer was dealing with a sequence like: # ARM load store optimizer was dealing with a sequence like:
# s1 = VLDRS [r0, 1], implicit-def Q0 # s1 = VLDRS [r0, 1], implicit-def Q0
# s3 = VLDRS [r0, 2], implicit killed Q0, implicit-def Q0 # s3 = VLDRS [r0, 2], implicit killed Q0, implicit-def Q0
# s0 = VLDRS [r0, 0], implicit killed Q0, implicit-def Q0 # s0 = VLDRS [r0, 0], implicit killed Q0, implicit-def Q0
# s2 = VLDRS [r0, 4], implicit killed Q0, implicit-def Q0 # s2 = VLDRS [r0, 4], implicit killed Q0, implicit-def Q0
# #
# It decided to combine the {s0, s1} loads into a single instruction in the # It decided to combine the {s0, s1} loads into a single instruction in the
Show All 12 Lines
name: foo name: foo
alignment: 2 alignment: 2
liveins: liveins:
- { reg: '$r0' } - { reg: '$r0' }
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: foo
; CHECK: $s3 = VLDRS $r0, 2, 14 /* CC::al */, $noreg, implicit killed undef $q0, implicit-def $q0 :: (load 4)
; CHECK: VLDMSIA $r0, 14 /* CC::al */, $noreg, def $s0, def $s1, implicit-def $noreg :: (load 4)
; CHECK: $s2 = VLDRS killed $r0, 4, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load 4)
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
$s1 = VLDRS $r0, 1, 14, $noreg, implicit-def $q0 :: (load 4) $s1 = VLDRS $r0, 1, 14, $noreg, implicit-def $q0 :: (load 4)
$s3 = VLDRS $r0, 2, 14, $noreg, implicit killed $q0, implicit-def $q0 :: (load 4) $s3 = VLDRS $r0, 2, 14, $noreg, implicit killed $q0, implicit-def $q0 :: (load 4)
; CHECK: $s3 = VLDRS $r0, 2, 14, $noreg, implicit killed undef $q0, implicit-def $q0 :: (load 4)
$s0 = VLDRS $r0, 0, 14, $noreg, implicit killed $q0, implicit-def $q0 :: (load 4) $s0 = VLDRS $r0, 0, 14, $noreg, implicit killed $q0, implicit-def $q0 :: (load 4)
; CHECK: VLDMSIA $r0, 14, $noreg, def $s0, def $s1, implicit-def $noreg
$s2 = VLDRS killed $r0, 4, 14, $noreg, implicit killed $q0, implicit-def $q0 :: (load 4) $s2 = VLDRS killed $r0, 4, 14, $noreg, implicit killed $q0, implicit-def $q0 :: (load 4)
; CHECK: $s2 = VLDRS killed $r0, 4, 14, $noreg, implicit killed $q0, implicit-def $q0 :: (load 4)
tBX_RET 14, $noreg, implicit $q0 tBX_RET 14, $noreg, implicit $q0
... ...

llvm/test/CodeGen/MIR/ARM/bundled-instructions.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple thumbv7-apple-ios -run-pass none -o - %s | FileCheck %s # RUN: llc -mtriple thumbv7-apple-ios -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses the bundled machine instructions # This test ensures that the MIR parser parses the bundled machine instructions
# and 'internal' register flags correctly. # and 'internal' register flags correctly.
--- | --- |
define i32 @test1(i32 %a) { define i32 @test1(i32 %a) {
entry: entry:
Show All 14 Lines
name: test1 name: test1
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$r0' } - { reg: '$r0' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $r0 liveins: $r0
; CHECK-LABEL: name: test1 ; CHECK-LABEL: name: test1
; CHECK: $r1 = t2MOVi 0, 14, $noreg, $noreg ; CHECK: liveins: $r0
; CHECK-NEXT: t2CMNri killed $r0, 78, 14, $noreg, implicit-def $cpsr ; CHECK: $r1 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $cpsr { ; CHECK: t2CMNri killed $r0, 78, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK-NEXT: t2IT 12, 8, implicit-def $itstate ; CHECK: BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $cpsr {
; CHECK-NEXT: $r1 = t2MOVi 1, 12, killed $cpsr, $noreg, implicit internal killed $itstate ; CHECK: t2IT 12, 8, implicit-def $itstate
; CHECK-NEXT: } ; CHECK: $r1 = t2MOVi 1, 12 /* CC::gt */, killed $cpsr, $noreg, implicit internal killed $itstate
; CHECK-NEXT: $r0 = tMOVr killed $r1, 14, $noreg ; CHECK: }
; CHECK-NEXT: tBX_RET 14, $noreg, implicit killed $r0 ; CHECK: $r0 = tMOVr killed $r1, 14 /* CC::al */, $noreg
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0
$r1 = t2MOVi 0, 14, _, _ $r1 = t2MOVi 0, 14, _, _
t2CMNri killed $r0, 78, 14, _, implicit-def $cpsr t2CMNri killed $r0, 78, 14, _, implicit-def $cpsr
BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $cpsr { BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $cpsr {
t2IT 12, 8, implicit-def $itstate t2IT 12, 8, implicit-def $itstate
$r1 = t2MOVi 1, 12, killed $cpsr, _, implicit internal killed $itstate $r1 = t2MOVi 1, 12, killed $cpsr, _, implicit internal killed $itstate
} }
$r0 = tMOVr killed $r1, 14, _ $r0 = tMOVr killed $r1, 14, _
tBX_RET 14, _, implicit killed $r0 tBX_RET 14, _, implicit killed $r0
... ...
--- ---
name: test2 name: test2
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$r0' } - { reg: '$r0' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $r0 liveins: $r0
; Verify that the next machine instruction can be on the same line as ; Verify that the next machine instruction can be on the same line as
; '{' or '}'. ; '{' or '}'.
; CHECK-LABEL: name: test2 ; CHECK-LABEL: name: test2
; CHECK: $r1 = t2MOVi 0, 14, $noreg, $noreg ; CHECK: liveins: $r0
; CHECK-NEXT: t2CMNri killed $r0, 78, 14, $noreg, implicit-def $cpsr ; CHECK: $r1 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $cpsr { ; CHECK: t2CMNri killed $r0, 78, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK-NEXT: t2IT 12, 8, implicit-def $itstate ; CHECK: BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $cpsr {
; CHECK-NEXT: $r1 = t2MOVi 1, 12, killed $cpsr, $noreg, implicit internal killed $itstate ; CHECK: t2IT 12, 8, implicit-def $itstate
; CHECK-NEXT: } ; CHECK: $r1 = t2MOVi 1, 12 /* CC::gt */, killed $cpsr, $noreg, implicit internal killed $itstate
; CHECK-NEXT: $r0 = tMOVr killed $r1, 14, $noreg ; CHECK: }
; CHECK-NEXT: tBX_RET 14, $noreg, implicit killed $r0 ; CHECK: $r0 = tMOVr killed $r1, 14 /* CC::al */, $noreg
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0
$r1 = t2MOVi 0, 14, _, _ $r1 = t2MOVi 0, 14, _, _
t2CMNri killed $r0, 78, 14, _, implicit-def $cpsr t2CMNri killed $r0, 78, 14, _, implicit-def $cpsr
BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $cpsr { t2IT 12, 8, implicit-def $itstate BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $cpsr { t2IT 12, 8, implicit-def $itstate
$r1 = t2MOVi 1, 12, killed $cpsr, _, internal implicit killed $itstate $r1 = t2MOVi 1, 12, killed $cpsr, _, internal implicit killed $itstate
} $r0 = tMOVr killed $r1, 14, _ } $r0 = tMOVr killed $r1, 14, _
tBX_RET 14, _, implicit killed $r0 tBX_RET 14, _, implicit killed $r0
... ...

llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
--- | --- |
; RUN: llc --run-pass=prologepilog -o - %s | FileCheck %s ; RUN: llc --run-pass=prologepilog -o - %s | FileCheck %s
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
; CHECK-NEXT: $sp = frame-setup t2SUBspImm12 killed $sp, 4008, 14, $noreg
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv7-none-none-eabi" target triple = "thumbv7-none-none-eabi"
define void @foo() #0 { define void @foo() #0 {
entry: entry:
%v = alloca [4000 x i8], align 1 %v = alloca [4000 x i8], align 1
%s = alloca i8*, align 4 %s = alloca i8*, align 4
%0 = bitcast [4000 x i8]* %v to i8* %0 = bitcast [4000 x i8]* %v to i8*
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines - { id: 1, name: s, type: default, offset: 0, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '', callee-saved-restored: true, stack-id: default, callee-saved-register: '', callee-saved-restored: true,
local-offset: -4004, debug-info-variable: '', debug-info-expression: '', local-offset: -4004, debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' } debug-info-location: '' }
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: foo
; CHECK: liveins: $lr
; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r7, killed $lr
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: $r7 = frame-setup tMOVr killed $sp, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
; CHECK: $sp = frame-setup t2SUBspImm12 killed $sp, 4008, 14 /* CC::al */, $noreg
; CHECK: renamable $r0 = t2ADDri $sp, 8, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2STRi12 killed renamable $r0, $sp, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.s)
; CHECK: renamable $r0 = t2LDRi12 $sp, 4, 14 /* CC::al */, $noreg :: (dereferenceable load 4 from %ir.s)
; CHECK: tBL 14 /* CC::al */, $noreg, @bar, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit-def $sp
; CHECK: $sp = t2ADDspImm12 killed $sp, 4008, 14 /* CC::al */, $noreg
; CHECK: $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r7, def $pc
renamable $r0 = t2ADDri %stack.0.v, 0, 14, $noreg, $noreg renamable $r0 = t2ADDri %stack.0.v, 0, 14, $noreg, $noreg
t2STRi12 killed renamable $r0, %stack.1.s, 0, 14, $noreg :: (store 4 into %ir.s) t2STRi12 killed renamable $r0, %stack.1.s, 0, 14, $noreg :: (store 4 into %ir.s)
renamable $r0 = t2LDRi12 %stack.1.s, 0, 14, $noreg :: (dereferenceable load 4 from %ir.s) renamable $r0 = t2LDRi12 %stack.1.s, 0, 14, $noreg :: (dereferenceable load 4 from %ir.s)
ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
tBL 14, $noreg, @bar, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit-def $sp tBL 14, $noreg, @bar, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit-def $sp
ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
tBX_RET 14, $noreg tBX_RET 14, $noreg
... ...

llvm/test/CodeGen/Thumb/peephole-cmp.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple thumbv8m.base-none-eabi -run-pass=peephole-opt -verify-machineinstrs -o - %s | FileCheck %s # RUN: llc -mtriple thumbv8m.base-none-eabi -run-pass=peephole-opt -verify-machineinstrs -o - %s | FileCheck %s
--- | --- |
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv8m.base-none-none-eabi" target triple = "thumbv8m.base-none-none-eabi"
define i32 @test_subrr(i32 %a, i32 %b) { ret i32 %a } define i32 @test_subrr(i32 %a, i32 %b) { ret i32 %a }
define i32 @test_subrr_c(i32 %a, i32 %b) { ret i32 %a } define i32 @test_subrr_c(i32 %a, i32 %b) { ret i32 %a }
define i32 @test_subri3(i32 %a) { ret i32 %a } define i32 @test_subri3(i32 %a) { ret i32 %a }
define i32 @test_subri8(i32 %a) { ret i32 %a } define i32 @test_subri8(i32 %a) { ret i32 %a }
define i32 @test_addrr(i32 %a) { ret i32 %a } define i32 @test_addrr(i32 %a) { ret i32 %a }
define i32 @test_addri3(i32 %a) { ret i32 %a } define i32 @test_addri3(i32 %a) { ret i32 %a }
define i32 @test_addri8(i32 %a) { ret i32 %a } define i32 @test_addri8(i32 %a) { ret i32 %a }
... ...
--- ---
name: test_subrr name: test_subrr
liveins: liveins:
- { reg: '$r0', virtual-reg: '%1' } - { reg: '$r0', virtual-reg: '%1' }
- { reg: '$r1', virtual-reg: '%2' } - { reg: '$r1', virtual-reg: '%2' }
body: | body: |
; CHECK-LABEL: name: test_subrr
; CHECK: bb.0:
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
; CHECK: %2:tgpr, $cpsr = tSUBrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
; CHECK: tBcc %bb.2, 8 /* CC::hi */, $cpsr
; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
; CHECK: bb.1:
; CHECK: $r0 = COPY %2
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
; CHECK: bb.2:
; CHECK: %3:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY %3
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
bb.0: bb.0:
successors: %bb.2(0x40000000), %bb.1(0x40000000) successors: %bb.2(0x40000000), %bb.1(0x40000000)
liveins: $r0, $r1 liveins: $r0, $r1
%2:tgpr = COPY $r1 %2:tgpr = COPY $r1
%1:tgpr = COPY $r0 %1:tgpr = COPY $r0
%0:tgpr, $cpsr = tSUBrr %2, %1, 14, $noreg %0:tgpr, $cpsr = tSUBrr %2, %1, 14, $noreg
tCMPr %1, %2, 14, $noreg, implicit-def $cpsr tCMPr %1, %2, 14, $noreg, implicit-def $cpsr
tBcc %bb.2, 3, $cpsr tBcc %bb.2, 3, $cpsr
tB %bb.1, 14, $noreg tB %bb.1, 14, $noreg
bb.1: bb.1:
$r0 = COPY %0 $r0 = COPY %0
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
bb.2: bb.2:
%3:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg %3:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
$r0 = COPY %3 $r0 = COPY %3
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
# CHECK-LABEL: name: test_subrr
# CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r1
# CHECK-NEXT: [[COPY0:%[0-9]+]]:tgpr = COPY $r0
# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tSUBrr [[COPY1]], [[COPY0]], 14, $noreg
# CHECK-NEXT: tBcc %bb.2, 8, $cpsr
... ...
--- ---
name: test_subrr_c name: test_subrr_c
liveins: liveins:
- { reg: '$r0', virtual-reg: '%1' } - { reg: '$r0', virtual-reg: '%1' }
- { reg: '$r1', virtual-reg: '%2' } - { reg: '$r1', virtual-reg: '%2' }
body: | body: |
; CHECK-LABEL: name: test_subrr_c
; CHECK: bb.0:
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
; CHECK: %2:tgpr, $cpsr = tSUBrr [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg
; CHECK: tBcc %bb.2, 3 /* CC::lo */, $cpsr
; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
; CHECK: bb.1:
; CHECK: $r0 = COPY %2
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
; CHECK: bb.2:
; CHECK: %3:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY %3
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
bb.0: bb.0:
successors: %bb.2(0x40000000), %bb.1(0x40000000) successors: %bb.2(0x40000000), %bb.1(0x40000000)
liveins: $r0, $r1 liveins: $r0, $r1
%2:tgpr = COPY $r1 %2:tgpr = COPY $r1
%1:tgpr = COPY $r0 %1:tgpr = COPY $r0
%0:tgpr, $cpsr = tSUBrr %1, %2, 14, $noreg %0:tgpr, $cpsr = tSUBrr %1, %2, 14, $noreg
tCMPr %1, %2, 14, $noreg, implicit-def $cpsr tCMPr %1, %2, 14, $noreg, implicit-def $cpsr
tBcc %bb.2, 3, $cpsr tBcc %bb.2, 3, $cpsr
tB %bb.1, 14, $noreg tB %bb.1, 14, $noreg
bb.1: bb.1:
$r0 = COPY %0 $r0 = COPY %0
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
bb.2: bb.2:
%3:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg %3:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
$r0 = COPY %3 $r0 = COPY %3
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
# CHECK-LABEL: name: test_subrr_c
# CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r1
# CHECK-NEXT: [[COPY0:%[0-9]+]]:tgpr = COPY $r0
# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tSUBrr [[COPY0]], [[COPY1]], 14, $noreg
# CHECK-NEXT: tBcc %bb.2, 3, $cpsr
... ...
--- ---
name: test_subri3 name: test_subri3
liveins: liveins:
- { reg: '$r0', virtual-reg: '%1' } - { reg: '$r0', virtual-reg: '%1' }
body: | body: |
; CHECK-LABEL: name: test_subri3
; CHECK: bb.0:
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
; CHECK: %1:tgpr, $cpsr = tSUBi3 [[COPY]], 1, 14 /* CC::al */, $noreg
; CHECK: tBcc %bb.2, 3 /* CC::lo */, $cpsr
; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
; CHECK: bb.1:
; CHECK: $r0 = COPY %1
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
; CHECK: bb.2:
; CHECK: %2:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY %2
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
bb.0: bb.0:
successors: %bb.2(0x40000000), %bb.1(0x40000000) successors: %bb.2(0x40000000), %bb.1(0x40000000)
liveins: $r0 liveins: $r0
%1:tgpr = COPY $r0 %1:tgpr = COPY $r0
%0:tgpr, $cpsr = tSUBi3 %1, 1, 14, $noreg %0:tgpr, $cpsr = tSUBi3 %1, 1, 14, $noreg
tCMPi8 %1, 1, 14, $noreg, implicit-def $cpsr tCMPi8 %1, 1, 14, $noreg, implicit-def $cpsr
tBcc %bb.2, 3, $cpsr tBcc %bb.2, 3, $cpsr
tB %bb.1, 14, $noreg tB %bb.1, 14, $noreg
bb.1: bb.1:
$r0 = COPY %0 $r0 = COPY %0
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
bb.2: bb.2:
%2:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg %2:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
# CHECK-LABEL: name: test_subri3
# CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tSUBi3 [[COPY]], 1, 14, $noreg
# CHECK-NEXT: tBcc %bb.2, 3, $cpsr
... ...
--- ---
name: test_subri8 name: test_subri8
liveins: liveins:
- { reg: '$r0', virtual-reg: '%1' } - { reg: '$r0', virtual-reg: '%1' }
body: | body: |
; CHECK-LABEL: name: test_subri8
; CHECK: bb.0:
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
; CHECK: %1:tgpr, $cpsr = tSUBi8 [[COPY]], 1, 14 /* CC::al */, $noreg
; CHECK: tBcc %bb.2, 3 /* CC::lo */, $cpsr
; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
; CHECK: bb.1:
; CHECK: $r0 = COPY %1
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
; CHECK: bb.2:
; CHECK: %2:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY %2
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
bb.0: bb.0:
successors: %bb.2(0x40000000), %bb.1(0x40000000) successors: %bb.2(0x40000000), %bb.1(0x40000000)
liveins: $r0 liveins: $r0
%1:tgpr = COPY $r0 %1:tgpr = COPY $r0
%0:tgpr, $cpsr = tSUBi8 %1, 1, 14, $noreg %0:tgpr, $cpsr = tSUBi8 %1, 1, 14, $noreg
tCMPi8 %1, 1, 14, $noreg, implicit-def $cpsr tCMPi8 %1, 1, 14, $noreg, implicit-def $cpsr
tBcc %bb.2, 3, $cpsr tBcc %bb.2, 3, $cpsr
tB %bb.1, 14, $noreg tB %bb.1, 14, $noreg
bb.1: bb.1:
$r0 = COPY %0 $r0 = COPY %0
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
bb.2: bb.2:
%2:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg %2:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
# CHECK-LABEL: name: test_subri8
# CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tSUBi8 [[COPY]], 1, 14, $noreg
# CHECK-NEXT: tBcc %bb.2, 3, $cpsr
... ...
--- ---
name: test_addrr name: test_addrr
liveins: liveins:
- { reg: '$r0', virtual-reg: '%1' } - { reg: '$r0', virtual-reg: '%1' }
- { reg: '$r1', virtual-reg: '%2' } - { reg: '$r1', virtual-reg: '%2' }
body: | body: |
; CHECK-LABEL: name: test_addrr
; CHECK: bb.0:
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
; CHECK: %2:tgpr, $cpsr = tADDrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
; CHECK: tBcc %bb.2, 2 /* CC::hs */, $cpsr
; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
; CHECK: bb.1:
; CHECK: $r0 = COPY %2
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
; CHECK: bb.2:
; CHECK: %3:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY %3
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
bb.0: bb.0:
successors: %bb.2(0x40000000), %bb.1(0x40000000) successors: %bb.2(0x40000000), %bb.1(0x40000000)
liveins: $r0, $r1 liveins: $r0, $r1
%2:tgpr = COPY $r1 %2:tgpr = COPY $r1
%1:tgpr = COPY $r0 %1:tgpr = COPY $r0
%0:tgpr, $cpsr = tADDrr %2, %1, 14, $noreg %0:tgpr, $cpsr = tADDrr %2, %1, 14, $noreg
tCMPr %0, %2, 14, $noreg, implicit-def $cpsr tCMPr %0, %2, 14, $noreg, implicit-def $cpsr
tBcc %bb.2, 3, $cpsr tBcc %bb.2, 3, $cpsr
tB %bb.1, 14, $noreg tB %bb.1, 14, $noreg
bb.1: bb.1:
$r0 = COPY %0 $r0 = COPY %0
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
bb.2: bb.2:
%3:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg %3:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
$r0 = COPY %3 $r0 = COPY %3
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
# CHECK-LABEL: name: test_addrr
# CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r1
# CHECK-NEXT: [[COPY0:%[0-9]+]]:tgpr = COPY $r0
# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tADDrr [[COPY1]], [[COPY0]], 14, $noreg
# CHECK-NEXT: tBcc %bb.2, 2, $cpsr
... ...
--- ---
name: test_addri3 name: test_addri3
liveins: liveins:
- { reg: '$r0', virtual-reg: '%1' } - { reg: '$r0', virtual-reg: '%1' }
body: | body: |
; CHECK-LABEL: name: test_addri3
; CHECK: bb.0:
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
; CHECK: %0:tgpr, $cpsr = tADDi3 [[COPY]], 1, 14 /* CC::al */, $noreg
; CHECK: tBcc %bb.2, 2 /* CC::hs */, $cpsr
; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
; CHECK: bb.1:
; CHECK: $r0 = COPY [[COPY]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
; CHECK: bb.2:
; CHECK: %2:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY %2
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
bb.0: bb.0:
successors: %bb.2(0x40000000), %bb.1(0x40000000) successors: %bb.2(0x40000000), %bb.1(0x40000000)
liveins: $r0 liveins: $r0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%1:tgpr, $cpsr = tADDi3 %0, 1, 14, $noreg %1:tgpr, $cpsr = tADDi3 %0, 1, 14, $noreg
tCMPr %1, %0, 14, $noreg, implicit-def $cpsr tCMPr %1, %0, 14, $noreg, implicit-def $cpsr
tBcc %bb.2, 3, $cpsr tBcc %bb.2, 3, $cpsr
tB %bb.1, 14, $noreg tB %bb.1, 14, $noreg
bb.1: bb.1:
$r0 = COPY %0 $r0 = COPY %0
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
bb.2: bb.2:
%2:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg %2:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
# CHECK-LABEL: name: test_addri3
# CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tADDi3 [[COPY]], 1, 14, $noreg
# CHECK-NEXT: tBcc %bb.2, 2, $cpsr
... ...
--- ---
name: test_addri8 name: test_addri8
liveins: liveins:
- { reg: '$r0', virtual-reg: '%1' } - { reg: '$r0', virtual-reg: '%1' }
body: | body: |
; CHECK-LABEL: name: test_addri8
; CHECK: bb.0:
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
; CHECK: %0:tgpr, $cpsr = tADDi8 [[COPY]], 10, 14 /* CC::al */, $noreg
; CHECK: tBcc %bb.2, 2 /* CC::hs */, $cpsr
; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
; CHECK: bb.1:
; CHECK: $r0 = COPY [[COPY]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
; CHECK: bb.2:
; CHECK: %2:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY %2
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
bb.0: bb.0:
successors: %bb.2(0x40000000), %bb.1(0x40000000) successors: %bb.2(0x40000000), %bb.1(0x40000000)
liveins: $r0 liveins: $r0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%1:tgpr, $cpsr = tADDi8 %0, 10, 14, $noreg %1:tgpr, $cpsr = tADDi8 %0, 10, 14, $noreg
tCMPr %1, %0, 14, $noreg, implicit-def $cpsr tCMPr %1, %0, 14, $noreg, implicit-def $cpsr
tBcc %bb.2, 3, $cpsr tBcc %bb.2, 3, $cpsr
tB %bb.1, 14, $noreg tB %bb.1, 14, $noreg
bb.1: bb.1:
$r0 = COPY %0 $r0 = COPY %0
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
bb.2: bb.2:
%2:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg %2:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
# CHECK-LABEL: name: test_addri8
# CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tADDi8 [[COPY]], 10, 14, $noreg
# CHECK-NEXT: tBcc %bb.2, 2, $cpsr
... ...

llvm/test/CodeGen/Thumb/peephole-mi.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple thumbv8m.base-none-eabi -run-pass=peephole-opt -verify-machineinstrs -o - %s | FileCheck %s # RUN: llc -mtriple thumbv8m.base-none-eabi -run-pass=peephole-opt -verify-machineinstrs -o - %s | FileCheck %s
--- | --- |
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv8m.base-none-none-eabi" target triple = "thumbv8m.base-none-none-eabi"
define i32 @test_adc(i32 %a, i32 %b) { ret i32 %a } define i32 @test_adc(i32 %a, i32 %b) { ret i32 %a }
define i32 @test_adc_mov(i32 %a, i32 %b) { ret i32 %a } define i32 @test_adc_mov(i32 %a, i32 %b) { ret i32 %a }
define i32 @test_sbc(i32 %a, i32 %b) { ret i32 %a } define i32 @test_sbc(i32 %a, i32 %b) { ret i32 %a }
Show All 10 Lines
... ...
--- ---
name: test_adc name: test_adc
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$r1', virtual-reg: '%1' } - { reg: '$r1', virtual-reg: '%1' }
body: | body: |
; CHECK-LABEL: name: test_adc ; CHECK-LABEL: name: test_adc
; CHECK: bb.0:
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[tADDrr:%[0-9]+]]:tgpr, $cpsr = tADDrr [[COPY1]], [[COPY]], 14, $noreg ; CHECK: %2:tgpr, $cpsr = tADDrr [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg
; CHECK: [[tADC:%[0-9]+]]:tgpr, $cpsr = tADC [[COPY1]], [[COPY]], 14, $noreg, implicit $cpsr ; CHECK: %3:tgpr, $cpsr = tADC [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg, implicit $cpsr
; CHECK: tBcc %bb.2, 1, $cpsr ; CHECK: tBcc %bb.2, 1 /* CC::ne */, $cpsr
; CHECK: tB %bb.1, 14, $noreg ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
; CHECK: bb.1:
; CHECK: $r0 = COPY [[COPY1]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
; CHECK: bb.2:
; CHECK: %4:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY %3
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
bb.0: bb.0:
successors: %bb.2(0x40000000), %bb.1(0x40000000) successors: %bb.2(0x40000000), %bb.1(0x40000000)
liveins: $r0, $r1 liveins: $r0, $r1
%1:tgpr = COPY $r1 %1:tgpr = COPY $r1
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%3:tgpr, $cpsr = tADDrr %0, %1, 14, $noreg %3:tgpr, $cpsr = tADDrr %0, %1, 14, $noreg
%2:tgpr, dead $cpsr = tADC %0, %1, 14, $noreg, implicit $cpsr %2:tgpr, dead $cpsr = tADC %0, %1, 14, $noreg, implicit $cpsr
Show All 12 Lines
... ...
--- ---
name: test_adc_mov name: test_adc_mov
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$r1', virtual-reg: '%1' } - { reg: '$r1', virtual-reg: '%1' }
body: | body: |
; CHECK-LABEL: name: test_adc_mov ; CHECK-LABEL: name: test_adc_mov
; CHECK: bb.0:
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[tADDrr:%[0-9]+]]:tgpr, $cpsr = tADDrr [[COPY1]], [[COPY]], 14, $noreg ; CHECK: %2:tgpr, $cpsr = tADDrr [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg
; CHECK: [[tADC:%[0-9]+]]:tgpr, dead $cpsr = tADC [[COPY1]], [[COPY]], 14, $noreg, implicit $cpsr ; CHECK: %3:tgpr, dead $cpsr = tADC [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg, implicit $cpsr
; CHECK: [[tMOVi8_:%[0-9]+]]:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: %4:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: tCMPi8 [[tADC]], 0, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 %3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.2, 1, $cpsr ; CHECK: tBcc %bb.2, 1 /* CC::ne */, $cpsr
; CHECK: tB %bb.1, 14, $noreg ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
; CHECK: bb.1:
; CHECK: $r0 = COPY [[COPY1]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
; CHECK: bb.2:
; CHECK: %5:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY %3
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
bb.0: bb.0:
successors: %bb.2(0x40000000), %bb.1(0x40000000) successors: %bb.2(0x40000000), %bb.1(0x40000000)
liveins: $r0, $r1 liveins: $r0, $r1
%1:tgpr = COPY $r1 %1:tgpr = COPY $r1
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%3:tgpr, $cpsr = tADDrr %0, %1, 14, $noreg %3:tgpr, $cpsr = tADDrr %0, %1, 14, $noreg
%2:tgpr, dead $cpsr = tADC %0, %1, 14, $noreg, implicit $cpsr %2:tgpr, dead $cpsr = tADC %0, %1, 14, $noreg, implicit $cpsr
Show All 13 Lines
... ...
--- ---
name: test_sbc name: test_sbc
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$r1', virtual-reg: '%1' } - { reg: '$r1', virtual-reg: '%1' }
body: | body: |
; CHECK-LABEL: name: test_sbc ; CHECK-LABEL: name: test_sbc
; CHECK: bb.0:
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[tADDrr:%[0-9]+]]:tgpr, $cpsr = tADDrr [[COPY1]], [[COPY]], 14, $noreg ; CHECK: %2:tgpr, $cpsr = tADDrr [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg
; CHECK: [[tSBC:%[0-9]+]]:tgpr, $cpsr = tSBC [[COPY1]], [[COPY]], 14, $noreg, implicit $cpsr ; CHECK: %3:tgpr, $cpsr = tSBC [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg, implicit $cpsr
; CHECK: tBcc %bb.2, 1, $cpsr ; CHECK: tBcc %bb.2, 1 /* CC::ne */, $cpsr
; CHECK: tB %bb.1, 14, $noreg ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
; CHECK: bb.1:
; CHECK: $r0 = COPY [[COPY1]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
; CHECK: bb.2:
; CHECK: %4:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY %3
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
bb.0: bb.0:
successors: %bb.2(0x40000000), %bb.1(0x40000000) successors: %bb.2(0x40000000), %bb.1(0x40000000)
liveins: $r0, $r1 liveins: $r0, $r1
%1:tgpr = COPY $r1 %1:tgpr = COPY $r1
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%3:tgpr, $cpsr = tADDrr %0, %1, 14, $noreg %3:tgpr, $cpsr = tADDrr %0, %1, 14, $noreg
%2:tgpr, dead $cpsr = tSBC %0, %1, 14, $noreg, implicit $cpsr %2:tgpr, dead $cpsr = tSBC %0, %1, 14, $noreg, implicit $cpsr
Show All 11 Lines bb.2:
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_rsb name: test_rsb
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
body: | body: |
; CHECK-LABEL: name: test_rsb ; CHECK-LABEL: name: test_rsb
; CHECK: bb.0:
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[tRSB:%[0-9]+]]:tgpr, $cpsr = tRSB [[COPY]], 14, $noreg ; CHECK: %1:tgpr, $cpsr = tRSB [[COPY]], 14 /* CC::al */, $noreg
; CHECK: tBcc %bb.2, 1, $cpsr ; CHECK: tBcc %bb.2, 1 /* CC::ne */, $cpsr
; CHECK: tB %bb.1, 14, $noreg ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
; CHECK: bb.1:
; CHECK: $r0 = COPY [[COPY]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
; CHECK: bb.2:
; CHECK: %2:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY %1
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
bb.0: bb.0:
successors: %bb.2(0x40000000), %bb.1(0x40000000) successors: %bb.2(0x40000000), %bb.1(0x40000000)
liveins: $r0, $r1 liveins: $r0, $r1
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%1:tgpr, dead $cpsr = tRSB %0, 14, $noreg %1:tgpr, dead $cpsr = tRSB %0, 14, $noreg
tCMPi8 %1, 0, 14, $noreg, implicit-def $cpsr tCMPi8 %1, 0, 14, $noreg, implicit-def $cpsr
tBcc %bb.2, 1, $cpsr tBcc %bb.2, 1, $cpsr
Show All 10 Lines
... ...
--- ---
name: test_and name: test_and
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$r1', virtual-reg: '%1' } - { reg: '$r1', virtual-reg: '%1' }
body: | body: |
; CHECK-LABEL: name: test_and ; CHECK-LABEL: name: test_and
; CHECK: bb.0:
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[tAND:%[0-9]+]]:tgpr, $cpsr = tAND [[COPY1]], [[COPY]], 14, $noreg ; CHECK: %2:tgpr, $cpsr = tAND [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg
; CHECK: tBcc %bb.2, 1, $cpsr ; CHECK: tBcc %bb.2, 1 /* CC::ne */, $cpsr
; CHECK: tB %bb.1, 14, $noreg ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
; CHECK: bb.1:
; CHECK: $r0 = COPY [[COPY1]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
; CHECK: bb.2:
; CHECK: %3:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY %2
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
bb.0: bb.0:
successors: %bb.2(0x40000000), %bb.1(0x40000000) successors: %bb.2(0x40000000), %bb.1(0x40000000)
liveins: $r0, $r1 liveins: $r0, $r1
%1:tgpr = COPY $r1 %1:tgpr = COPY $r1
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%2:tgpr, dead $cpsr = tAND %0, %1, 14, $noreg %2:tgpr, dead $cpsr = tAND %0, %1, 14, $noreg
tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
Show All 11 Lines
... ...
--- ---
name: test_orr name: test_orr
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$r1', virtual-reg: '%1' } - { reg: '$r1', virtual-reg: '%1' }
body: | body: |
; CHECK-LABEL: name: test_orr ; CHECK-LABEL: name: test_orr
; CHECK: bb.0:
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[tORR:%[0-9]+]]:tgpr, $cpsr = tORR [[COPY1]], [[COPY]], 14, $noreg ; CHECK: %2:tgpr, $cpsr = tORR [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg
; CHECK: tBcc %bb.2, 1, $cpsr ; CHECK: tBcc %bb.2, 1 /* CC::ne */, $cpsr
; CHECK: tB %bb.1, 14, $noreg ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
; CHECK: bb.1:
; CHECK: $r0 = COPY [[COPY1]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
; CHECK: bb.2:
; CHECK: %3:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY %2
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
bb.0: bb.0:
successors: %bb.2(0x40000000), %bb.1(0x40000000) successors: %bb.2(0x40000000), %bb.1(0x40000000)
liveins: $r0, $r1 liveins: $r0, $r1
%1:tgpr = COPY $r1 %1:tgpr = COPY $r1
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%2:tgpr, dead $cpsr = tORR %0, %1, 14, $noreg %2:tgpr, dead $cpsr = tORR %0, %1, 14, $noreg
tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
Show All 11 Lines
... ...
--- ---
name: test_eor name: test_eor
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$r1', virtual-reg: '%1' } - { reg: '$r1', virtual-reg: '%1' }
body: | body: |
; CHECK-LABEL: name: test_eor ; CHECK-LABEL: name: test_eor
; CHECK: bb.0:
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[tEOR:%[0-9]+]]:tgpr, $cpsr = tEOR [[COPY1]], [[COPY]], 14, $noreg ; CHECK: %2:tgpr, $cpsr = tEOR [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg
; CHECK: tBcc %bb.2, 1, $cpsr ; CHECK: tBcc %bb.2, 1 /* CC::ne */, $cpsr
; CHECK: tB %bb.1, 14, $noreg ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
; CHECK: bb.1:
; CHECK: $r0 = COPY [[COPY1]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
; CHECK: bb.2:
; CHECK: %3:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY %2
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
bb.0: bb.0:
successors: %bb.2(0x40000000), %bb.1(0x40000000) successors: %bb.2(0x40000000), %bb.1(0x40000000)
liveins: $r0, $r1 liveins: $r0, $r1
%1:tgpr = COPY $r1 %1:tgpr = COPY $r1
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%2:tgpr, dead $cpsr = tEOR %0, %1, 14, $noreg %2:tgpr, dead $cpsr = tEOR %0, %1, 14, $noreg
tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
Show All 11 Lines
... ...
--- ---
name: test_bic name: test_bic
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$r1', virtual-reg: '%1' } - { reg: '$r1', virtual-reg: '%1' }
body: | body: |
; CHECK-LABEL: name: test_bic ; CHECK-LABEL: name: test_bic
; CHECK: bb.0:
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[tBIC:%[0-9]+]]:tgpr, $cpsr = tBIC [[COPY1]], [[COPY]], 14, $noreg ; CHECK: %2:tgpr, $cpsr = tBIC [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg
; CHECK: tBcc %bb.2, 1, $cpsr ; CHECK: tBcc %bb.2, 1 /* CC::ne */, $cpsr
; CHECK: tB %bb.1, 14, $noreg ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
; CHECK: bb.1:
; CHECK: $r0 = COPY [[COPY1]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
; CHECK: bb.2:
; CHECK: %3:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY %2
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
bb.0: bb.0:
successors: %bb.2(0x40000000), %bb.1(0x40000000) successors: %bb.2(0x40000000), %bb.1(0x40000000)
liveins: $r0, $r1 liveins: $r0, $r1
%1:tgpr = COPY $r1 %1:tgpr = COPY $r1
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%2:tgpr, dead $cpsr = tBIC %0, %1, 14, $noreg %2:tgpr, dead $cpsr = tBIC %0, %1, 14, $noreg
tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
Show All 10 Lines bb.2:
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_mvn name: test_mvn
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
body: | body: |
; CHECK-LABEL: name: test_mvn ; CHECK-LABEL: name: test_mvn
; CHECK: bb.0:
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[tMVN:%[0-9]+]]:tgpr, $cpsr = tMVN [[COPY]], 14, $noreg ; CHECK: %1:tgpr, $cpsr = tMVN [[COPY]], 14 /* CC::al */, $noreg
; CHECK: tBcc %bb.2, 1, $cpsr ; CHECK: tBcc %bb.2, 1 /* CC::ne */, $cpsr
; CHECK: tB %bb.1, 14, $noreg ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
; CHECK: bb.1:
; CHECK: $r0 = COPY [[COPY]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
; CHECK: bb.2:
; CHECK: %2:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY %1
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
bb.0: bb.0:
successors: %bb.2(0x40000000), %bb.1(0x40000000) successors: %bb.2(0x40000000), %bb.1(0x40000000)
liveins: $r0, $r1 liveins: $r0, $r1
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%1:tgpr, dead $cpsr = tMVN %0, 14, $noreg %1:tgpr, dead $cpsr = tMVN %0, 14, $noreg
tCMPi8 %1, 0, 14, $noreg, implicit-def $cpsr tCMPi8 %1, 0, 14, $noreg, implicit-def $cpsr
tBcc %bb.2, 1, $cpsr tBcc %bb.2, 1, $cpsr
Show All 10 Lines
... ...
--- ---
name: test_asrrr name: test_asrrr
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$r1', virtual-reg: '%1' } - { reg: '$r1', virtual-reg: '%1' }
body: | body: |
; CHECK-LABEL: name: test_asrrr ; CHECK-LABEL: name: test_asrrr
; CHECK: bb.0:
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[tASRrr:%[0-9]+]]:tgpr, $cpsr = tASRrr [[COPY1]], [[COPY]], 14, $noreg ; CHECK: %2:tgpr, $cpsr = tASRrr [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg
; CHECK: tBcc %bb.2, 1, $cpsr ; CHECK: tBcc %bb.2, 1 /* CC::ne */, $cpsr
; CHECK: tB %bb.1, 14, $noreg ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
; CHECK: bb.1:
; CHECK: $r0 = COPY [[COPY1]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
; CHECK: bb.2:
; CHECK: %3:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY %2
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
bb.0: bb.0:
successors: %bb.2(0x40000000), %bb.1(0x40000000) successors: %bb.2(0x40000000), %bb.1(0x40000000)
liveins: $r0, $r1 liveins: $r0, $r1
%1:tgpr = COPY $r1 %1:tgpr = COPY $r1
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%2:tgpr, dead $cpsr = tASRrr %0, %1, 14, $noreg %2:tgpr, dead $cpsr = tASRrr %0, %1, 14, $noreg
tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
Show All 10 Lines bb.2:
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: test_asrri name: test_asrri
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
body: | body: |
; CHECK-LABEL: name: test_asrri ; CHECK-LABEL: name: test_asrri
; CHECK: bb.0:
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[tASRri:%[0-9]+]]:tgpr, $cpsr = tASRri [[COPY]], 1, 14, $noreg ; CHECK: %1:tgpr, $cpsr = tASRri [[COPY]], 1, 14 /* CC::al */, $noreg
; CHECK: tBcc %bb.2, 1, $cpsr ; CHECK: tBcc %bb.2, 1 /* CC::ne */, $cpsr
; CHECK: tB %bb.1, 14, $noreg ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
; CHECK: bb.1:
; CHECK: $r0 = COPY [[COPY]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
; CHECK: bb.2:
; CHECK: %2:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY %1
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
bb.0: bb.0:
successors: %bb.2(0x40000000), %bb.1(0x40000000) successors: %bb.2(0x40000000), %bb.1(0x40000000)
liveins: $r0, $r1 liveins: $r0, $r1
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%2:tgpr, dead $cpsr = tASRri %0, 1, 14, $noreg %2:tgpr, dead $cpsr = tASRri %0, 1, 14, $noreg
tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
tBcc %bb.2, 1, $cpsr tBcc %bb.2, 1, $cpsr
Show All 10 Lines
... ...
--- ---
name: test_ror name: test_ror
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$r1', virtual-reg: '%1' } - { reg: '$r1', virtual-reg: '%1' }
body: | body: |
; CHECK-LABEL: name: test_ror ; CHECK-LABEL: name: test_ror
; CHECK: bb.0:
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[tROR:%[0-9]+]]:tgpr, $cpsr = tROR [[COPY1]], [[COPY]], 14, $noreg ; CHECK: %2:tgpr, $cpsr = tROR [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg
; CHECK: tBcc %bb.2, 1, $cpsr ; CHECK: tBcc %bb.2, 1 /* CC::ne */, $cpsr
; CHECK: tB %bb.1, 14, $noreg ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
; CHECK: bb.1:
; CHECK: $r0 = COPY [[COPY1]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
; CHECK: bb.2:
; CHECK: %3:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY %2
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
bb.0: bb.0:
successors: %bb.2(0x40000000), %bb.1(0x40000000) successors: %bb.2(0x40000000), %bb.1(0x40000000)
liveins: $r0, $r1 liveins: $r0, $r1
%1:tgpr = COPY $r1 %1:tgpr = COPY $r1
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%2:tgpr, dead $cpsr = tROR %0, %1, 14, $noreg %2:tgpr, dead $cpsr = tROR %0, %1, 14, $noreg
tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
Show All 12 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/add_reduce.mir

Show First 20 Lines • Show All 143 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: max_min_add_reduce ; CHECK-LABEL: name: max_min_add_reduce
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000) ; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8
; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $lr ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $lr
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 24 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 24
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -8
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -12
; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -16 ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -16
; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -20 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -20
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -24 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -24
; CHECK: renamable $r12 = t2LDRi12 $sp, 48, 14, $noreg :: (load 4 from %fixed-stack.6, align 8) ; CHECK: renamable $r12 = t2LDRi12 $sp, 48, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.6, align 8)
; CHECK: renamable $r5 = t2ADDri renamable $r12, 3, 14, $noreg, $noreg ; CHECK: renamable $r5 = t2ADDri renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r7, dead $cpsr = tLSRri killed renamable $r5, 2, 14, $noreg ; CHECK: renamable $r7, dead $cpsr = tLSRri killed renamable $r5, 2, 14 /* CC::al */, $noreg
; CHECK: dead $lr = t2WLS renamable $r7, %bb.3 ; CHECK: dead $lr = t2WLS renamable $r7, %bb.3
; CHECK: bb.1.for.body.lr.ph: ; CHECK: bb.1.for.body.lr.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3, $r7, $r12 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r7, $r12
; CHECK: $r6, $r5 = t2LDRDi8 $sp, 40, 14, $noreg :: (load 4 from %fixed-stack.4, align 8), (load 4 from %fixed-stack.5) ; CHECK: $r6, $r5 = t2LDRDi8 $sp, 40, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.4, align 8), (load 4 from %fixed-stack.5)
; CHECK: $r4 = tMOVr killed $r7, 14, $noreg ; CHECK: $r4 = tMOVr killed $r7, 14 /* CC::al */, $noreg
; CHECK: $r7, $r8 = t2LDRDi8 $sp, 24, 14, $noreg :: (load 4 from %fixed-stack.0, align 8), (load 4 from %fixed-stack.1) ; CHECK: $r7, $r8 = t2LDRDi8 $sp, 24, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.0, align 8), (load 4 from %fixed-stack.1)
; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, undef renamable $q0
; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r6, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r6, 0, $noreg, undef renamable $q1
; CHECK: renamable $r5, dead $cpsr = tSUBi3 killed renamable $r7, 4, 14, $noreg ; CHECK: renamable $r5, dead $cpsr = tSUBi3 killed renamable $r7, 4, 14 /* CC::al */, $noreg
; CHECK: bb.2.for.body: ; CHECK: bb.2.for.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r8, $r12 ; CHECK: liveins: $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r8, $r12
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 1, renamable $vpr :: (load 16 from %ir.input_2_cast, align 4) ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 1, renamable $vpr :: (load 16 from %ir.input_2_cast, align 4)
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 1, renamable $vpr :: (load 16 from %ir.input_1_cast, align 4) ; CHECK: renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 1, renamable $vpr :: (load 16 from %ir.input_1_cast, align 4)
; CHECK: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, undef renamable $q2
; CHECK: renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, undef renamable $q3 ; CHECK: renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, undef renamable $q3
; CHECK: $lr = tMOVr $r4, 14, $noreg ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg
; CHECK: renamable $q2 = MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2
; CHECK: renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14, $noreg ; CHECK: renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r8, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r8, 0, $noreg, undef renamable $q2
; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $q2 = MVE_VMAXu32 killed renamable $q2, renamable $q1, 1, renamable $vpr, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VMAXu32 killed renamable $q2, renamable $q1, 1, renamable $vpr, undef renamable $q2
; CHECK: renamable $q2 = MVE_VMINu32 killed renamable $q2, renamable $q0, 1, killed renamable $vpr, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VMINu32 killed renamable $q2, renamable $q0, 1, killed renamable $vpr, undef renamable $q2
; CHECK: renamable $r6 = MVE_VADDVu32no_acc killed renamable $q2, 0, $noreg ; CHECK: renamable $r6 = MVE_VADDVu32no_acc killed renamable $q2, 0, $noreg
; CHECK: early-clobber renamable $r5 = t2STR_PRE killed renamable $r6, killed renamable $r5, 4, 14, $noreg :: (store 4 into %ir.scevgep2) ; CHECK: early-clobber renamable $r5 = t2STR_PRE killed renamable $r6, killed renamable $r5, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep2)
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: $sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $pc, implicit killed $r0 ; CHECK: $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x40000000), %bb.3(0x40000000) successors: %bb.1(0x40000000), %bb.3(0x40000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $lr liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $lr
$sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $lr $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $lr
frame-setup CFI_INSTRUCTION def_cfa_offset 24 frame-setup CFI_INSTRUCTION def_cfa_offset 24
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r8, -8 frame-setup CFI_INSTRUCTION offset $r8, -8
▲ Show 20 Lines • Show All 51 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir

Show First 20 Lines • Show All 81 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: do_copy ; CHECK-LABEL: name: do_copy
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: $lr = t2DLS killed $r0 ; CHECK: $lr = t2DLS killed $r0
; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg ; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: bb.1.while.body: ; CHECK: bb.1.while.body:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $r0, $r1 ; CHECK: liveins: $lr, $r0, $r1
; CHECK: renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6) ; CHECK: renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep6)
; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2) ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep2)
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1
; CHECK: bb.2.while.end: ; CHECK: bb.2.while.end:
; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
Show All 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir

Show First 20 Lines • Show All 116 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: test ; CHECK-LABEL: name: test
; CHECK: bb.0.bb: ; CHECK: bb.0.bb:
; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7
; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16
; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14, $noreg ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20
; CHECK: tCBZ $r2, %bb.3 ; CHECK: tCBZ $r2, %bb.3
; CHECK: bb.1.bb3: ; CHECK: bb.1.bb3:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: $r12 = t2MOVi16 target-flags(arm-lo16) @mask, 14, $noreg ; CHECK: $r12 = t2MOVi16 target-flags(arm-lo16) @mask, 14 /* CC::al */, $noreg
; CHECK: renamable $r4, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg ; CHECK: renamable $r4, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
; CHECK: $r12 = t2MOVTi16 killed $r12, target-flags(arm-hi16) @mask, 14, $noreg ; CHECK: $r12 = t2MOVTi16 killed $r12, target-flags(arm-hi16) @mask, 14 /* CC::al */, $noreg
; CHECK: renamable $r4 = t2BICri killed renamable $r4, 3, 14, $noreg, $noreg ; CHECK: renamable $r4 = t2BICri killed renamable $r4, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r5 = t2LDRHi12 killed renamable $r12, 0, 14, $noreg :: (dereferenceable load 2 from %ir.mask.gep9) ; CHECK: renamable $r5 = t2LDRHi12 killed renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load 2 from %ir.mask.gep9)
; CHECK: renamable $r12 = t2SUBri killed renamable $r4, 4, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r4, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: $vpr = VMSR_P0 $r5, 14, $noreg ; CHECK: $vpr = VMSR_P0 $r5, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r12, 19, 14, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 16, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 16, 14 /* CC::al */, $noreg, $noreg
; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store 4 into %stack.0) ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.0)
; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, undef renamable $q0
; CHECK: $r3 = tMOVr $r0, 14, $noreg ; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: $lr = t2DLS killed renamable $lr
; CHECK: bb.2.bb9: ; CHECK: bb.2.bb9:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r12 ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r12
; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load 4 from %stack.0) ; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.0)
; CHECK: MVE_VPST 2, implicit $vpr ; CHECK: MVE_VPST 2, implicit $vpr
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr
; CHECK: renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv24, align 4) ; CHECK: renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv24, align 4)
; CHECK: renamable $r3, renamable $q2 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv1, align 4) ; CHECK: renamable $r3, renamable $q2 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv1, align 4)
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
; CHECK: renamable $r12, renamable $q2 = MVE_VLDRWU32_pre killed renamable $r12, 16, 0, $noreg :: (load 16 from %ir.scevgep2, align 8) ; CHECK: renamable $r12, renamable $q2 = MVE_VLDRWU32_pre killed renamable $r12, 16, 0, $noreg :: (load 16 from %ir.scevgep2, align 8)
; CHECK: MVE_VPTv4u32 8, renamable $q0, killed renamable $q2, 2, implicit-def $vpr ; CHECK: MVE_VPTv4u32 8, renamable $q0, killed renamable $q2, 2, implicit-def $vpr
; CHECK: MVE_VSTRWU32 killed renamable $q1, killed renamable $r0, 0, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4) ; CHECK: MVE_VSTRWU32 killed renamable $q1, killed renamable $r0, 0, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4)
; CHECK: $r0 = tMOVr $r3, 14, $noreg ; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.bb27: ; CHECK: bb.3.bb27:
; CHECK: $sp = tADDspi $sp, 1, 14, $noreg ; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc
bb.0.bb: bb.0.bb:
successors: %bb.3(0x30000000), %bb.1(0x50000000) successors: %bb.3(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 16 frame-setup CFI_INSTRUCTION def_cfa_offset 16
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
▲ Show 20 Lines • Show All 49 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-ignore-vctp.mir

Show First 20 Lines • Show All 90 Lines • ▼ Show 20 Lines - id: 0
alignment: 16 alignment: 16
isTargetSpecific: false isTargetSpecific: false
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: dont_ignore_vctp ; CHECK-LABEL: name: dont_ignore_vctp
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r3, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r3, $r7
; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: tCMPi8 renamable $r3, 4, 14, $noreg, implicit-def dead $cpsr ; CHECK: tCMPi8 renamable $r3, 4, 14 /* CC::al */, $noreg, implicit-def dead $cpsr
; CHECK: renamable $r2 = tLEApcrel %const.0, 14, $noreg ; CHECK: renamable $r2 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load 16 from constant-pool) ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load 16 from constant-pool)
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
; CHECK: bb.1.do.body (align 4): ; CHECK: bb.1.do.body (align 4):
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1 ; CHECK: liveins: $lr, $q0, $r0, $r1
; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg ; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg
; CHECK: renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1
; CHECK: MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg ; CHECK: MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg
; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg ; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
; CHECK: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14, $noreg ; CHECK: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK: bb.2.do.end: ; CHECK: bb.2.do.end:
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
; CHECK: bb.3 (align 16): ; CHECK: bb.3 (align 16):
; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16 ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
Show All 38 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir

Show First 20 Lines • Show All 99 Lines • ▼ Show 20 Lines - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: use_before_def ; CHECK-LABEL: name: use_before_def
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7
; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: dead $r7 = frame-setup tMOVr $sp, 14, $noreg ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
; CHECK: tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: t2IT 11, 8, implicit-def $itstate
; CHECK: tPOP_RET 11, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $lr = t2MOVi 1, 14, $noreg, $noreg ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: $lr = t2DLS killed renamable $lr
; CHECK: bb.1.vector.body: ; CHECK: bb.1.vector.body:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv13, align 4) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv13, align 4)
; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1416, align 4) ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1416, align 4)
; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1719, align 4) ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1719, align 4)
; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1
; CHECK: bb.2.for.cond.cleanup: ; CHECK: bb.2.for.cond.cleanup:
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
Show All 33 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update2.mir

Show First 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: CPSR_not_dead ; CHECK-LABEL: name: CPSR_not_dead
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4
; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8
; CHECK: tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: t2IT 11, 8, implicit-def $itstate
; CHECK: tPOP_RET 11, killed $cpsr, def $r4, def $pc, implicit killed $itstate ; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate
; CHECK: $lr = MVE_DLSTP_32 renamable $r3 ; CHECK: $lr = MVE_DLSTP_32 renamable $r3
; CHECK: bb.1.vector.body: ; CHECK: bb.1.vector.body:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
; CHECK: renamable $r3, $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg ; CHECK: renamable $r3, $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: t2IT 11, 8, implicit-def $itstate
; CHECK: tPOP_RET 11, killed $cpsr, def $r4, def $pc, implicit killed $itstate ; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load 16 from %ir.lsr.iv13, align 4) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load 16 from %ir.lsr.iv13, align 4)
; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg :: (load 16 from %ir.lsr.iv1416, align 4) ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg :: (load 16 from %ir.lsr.iv1416, align 4)
; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv1719, align 4) ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv1719, align 4)
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK: bb.2.for.cond.cleanup: ; CHECK: bb.2.for.cond.cleanup:
; CHECK: t2IT 11, 8, implicit-def dead $itstate ; CHECK: t2IT 11, 8, implicit-def dead $itstate
; CHECK: tPOP_RET 14, $noreg, def $r4, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r4, $lr liveins: $r0, $r1, $r2, $r3, $r4, $lr
frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r4, -8 frame-setup CFI_INSTRUCTION offset $r4, -8
Show All 36 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir

Show First 20 Lines • Show All 121 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: size_limit ; CHECK-LABEL: name: size_limit
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.3(0x80000000) ; CHECK: successors: %bb.3(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7
; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: $sp = frame-setup tSUBspi $sp, 8, 14, $noreg ; CHECK: $sp = frame-setup tSUBspi $sp, 8, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 40 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 40
; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14, $noreg ; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14, $noreg ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
; CHECK: tSTRspi killed $r1, $sp, 7, 14, $noreg :: (store 4 into %stack.0) ; CHECK: tSTRspi killed $r1, $sp, 7, 14 /* CC::al */, $noreg :: (store 4 into %stack.0)
; CHECK: tSTRspi killed $r2, $sp, 6, 14, $noreg :: (store 4 into %stack.1) ; CHECK: tSTRspi killed $r2, $sp, 6, 14 /* CC::al */, $noreg :: (store 4 into %stack.1)
; CHECK: tSTRspi killed $r0, $sp, 5, 14, $noreg :: (store 4 into %stack.2) ; CHECK: tSTRspi killed $r0, $sp, 5, 14 /* CC::al */, $noreg :: (store 4 into %stack.2)
; CHECK: tSTRspi killed $r3, $sp, 4, 14, $noreg :: (store 4 into %stack.3) ; CHECK: tSTRspi killed $r3, $sp, 4, 14 /* CC::al */, $noreg :: (store 4 into %stack.3)
; CHECK: tB %bb.3, 14, $noreg ; CHECK: tB %bb.3, 14 /* CC::al */, $noreg
; CHECK: bb.1.for.body: ; CHECK: bb.1.for.body:
; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000) ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK: $r0 = tLDRspi $sp, 3, 14, $noreg :: (load 4 from %stack.4) ; CHECK: $r0 = tLDRspi $sp, 3, 14 /* CC::al */, $noreg :: (load 4 from %stack.4)
; CHECK: renamable $r1, renamable $r0 = t2LDR_PRE killed renamable $r0, 4, 14, $noreg :: (load 4 from %ir.scevgep11) ; CHECK: renamable $r1, renamable $r0 = t2LDR_PRE killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep11)
; CHECK: $r2 = tLDRspi $sp, 2, 14, $noreg :: (load 4 from %stack.5) ; CHECK: $r2 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load 4 from %stack.5)
; CHECK: renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14, $noreg :: (load 4 from %ir.scevgep7) ; CHECK: renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep7)
; CHECK: renamable $r1, dead $cpsr = nsw tMUL killed renamable $r3, killed renamable $r1, 14, $noreg ; CHECK: renamable $r1, dead $cpsr = nsw tMUL killed renamable $r3, killed renamable $r1, 14 /* CC::al */, $noreg
; CHECK: $r3 = tLDRspi $sp, 1, 14, $noreg :: (load 4 from %stack.6) ; CHECK: $r3 = tLDRspi $sp, 1, 14 /* CC::al */, $noreg :: (load 4 from %stack.6)
; CHECK: early-clobber renamable $r3 = t2STR_PRE killed renamable $r1, killed renamable $r3, 4, 14, $noreg :: (store 4 into %ir.scevgep3) ; CHECK: early-clobber renamable $r3 = t2STR_PRE killed renamable $r1, killed renamable $r3, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep3)
; CHECK: $r1 = tLDRspi $sp, 0, 14, $noreg :: (load 4 from %stack.7) ; CHECK: $r1 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.7)
; CHECK: $lr = tMOVr killed $r1, 14, $noreg ; CHECK: $lr = tMOVr killed $r1, 14 /* CC::al */, $noreg
; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14, $noreg, def $cpsr ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
; CHECK: $r12 = tMOVr killed $lr, 14, $noreg ; CHECK: $r12 = tMOVr killed $lr, 14 /* CC::al */, $noreg
; CHECK: tSTRspi killed $r0, $sp, 7, 14, $noreg :: (store 4 into %stack.0) ; CHECK: tSTRspi killed $r0, $sp, 7, 14 /* CC::al */, $noreg :: (store 4 into %stack.0)
; CHECK: tSTRspi killed $r2, $sp, 6, 14, $noreg :: (store 4 into %stack.1) ; CHECK: tSTRspi killed $r2, $sp, 6, 14 /* CC::al */, $noreg :: (store 4 into %stack.1)
; CHECK: tSTRspi killed $r3, $sp, 5, 14, $noreg :: (store 4 into %stack.2) ; CHECK: tSTRspi killed $r3, $sp, 5, 14 /* CC::al */, $noreg :: (store 4 into %stack.2)
; CHECK: t2STRi12 killed $r12, $sp, 16, 14, $noreg :: (store 4 into %stack.3) ; CHECK: t2STRi12 killed $r12, $sp, 16, 14 /* CC::al */, $noreg :: (store 4 into %stack.3)
; CHECK: tBcc %bb.3, 1, killed $cpsr ; CHECK: tBcc %bb.3, 1 /* CC::ne */, killed $cpsr
; CHECK: tB %bb.2, 14, $noreg ; CHECK: tB %bb.2, 14 /* CC::al */, $noreg
; CHECK: bb.2.for.cond.cleanup: ; CHECK: bb.2.for.cond.cleanup:
; CHECK: $sp = tADDspi $sp, 8, 14, $noreg ; CHECK: $sp = tADDspi $sp, 8, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
; CHECK: bb.3.for.header: ; CHECK: bb.3.for.header:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: $r0 = tLDRspi $sp, 4, 14, $noreg :: (load 4 from %stack.3) ; CHECK: $r0 = tLDRspi $sp, 4, 14 /* CC::al */, $noreg :: (load 4 from %stack.3)
; CHECK: $r1 = tLDRspi $sp, 5, 14, $noreg :: (load 4 from %stack.2) ; CHECK: $r1 = tLDRspi $sp, 5, 14 /* CC::al */, $noreg :: (load 4 from %stack.2)
; CHECK: $r2 = tLDRspi $sp, 6, 14, $noreg :: (load 4 from %stack.1) ; CHECK: $r2 = tLDRspi $sp, 6, 14 /* CC::al */, $noreg :: (load 4 from %stack.1)
; CHECK: $r3 = tLDRspi $sp, 7, 14, $noreg :: (load 4 from %stack.0) ; CHECK: $r3 = tLDRspi $sp, 7, 14 /* CC::al */, $noreg :: (load 4 from %stack.0)
; CHECK: tSTRspi killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.7) ; CHECK: tSTRspi killed $r0, $sp, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.7)
; CHECK: tSTRspi killed $r1, $sp, 1, 14, $noreg :: (store 4 into %stack.6) ; CHECK: tSTRspi killed $r1, $sp, 1, 14 /* CC::al */, $noreg :: (store 4 into %stack.6)
; CHECK: tSTRspi killed $r2, $sp, 2, 14, $noreg :: (store 4 into %stack.5) ; CHECK: tSTRspi killed $r2, $sp, 2, 14 /* CC::al */, $noreg :: (store 4 into %stack.5)
; CHECK: tSTRspi killed $r3, $sp, 3, 14, $noreg :: (store 4 into %stack.4) ; CHECK: tSTRspi killed $r3, $sp, 3, 14 /* CC::al */, $noreg :: (store 4 into %stack.4)
; CHECK: tB %bb.1, 14, $noreg ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
bb.0.entry: bb.0.entry:
successors: %bb.3(0x80000000) successors: %bb.3(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
▲ Show 20 Lines • Show All 51 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/extract-element.mir

Show First 20 Lines • Show All 101 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: no_vpsel_liveout ; CHECK-LABEL: name: no_vpsel_liveout
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
; CHECK: tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 0, 4, implicit-def $itstate ; CHECK: t2IT 0, 4, implicit-def $itstate
; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
; CHECK: tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: dead $lr = t2DLS renamable $r12 ; CHECK: dead $lr = t2DLS renamable $r12
; CHECK: $r3 = tMOVr killed $r12, 14, $noreg ; CHECK: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg
; CHECK: bb.1.vector.body: ; CHECK: bb.1.vector.body:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $q0, $r0, $r1, $r2, $r3 ; CHECK: liveins: $q0, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2)
; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2) ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2)
; CHECK: $lr = tMOVr $r3, 14, $noreg ; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.1 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.1
; CHECK: bb.2.middle.block: ; CHECK: bb.2.middle.block:
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK: $r0 = VMOVRS killed $s3, 14, $noreg, implicit killed $q0 ; CHECK: $r0 = VMOVRS killed $s3, 14 /* CC::al */, $noreg, implicit killed $q0
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $lr, $r7 liveins: $r0, $r1, $r2, $lr, $r7
tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr
t2IT 0, 4, implicit-def $itstate t2IT 0, 4, implicit-def $itstate
renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate
tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate
Show All 37 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-16.mir

Show First 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: incorrect_sub_16 ; CHECK-LABEL: name: incorrect_sub_16
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7
; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: t2IT 11, 8, implicit-def $itstate
; CHECK: tPOP_RET 11, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $lr = t2MOVi 1, 14, $noreg, $noreg ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: $lr = t2DLS killed renamable $lr
; CHECK: bb.1.vector.body: ; CHECK: bb.1.vector.body:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv13, align 4) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv13, align 4)
; CHECK: renamable $r2, renamable $q1 = MVE_VLDRHU16_post killed renamable $r2, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1416, align 4) ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRHU16_post killed renamable $r2, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1416, align 4)
; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 7, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 7, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = nsw MVE_VADDi16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VADDi16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r0 = MVE_VSTRHU16_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1719, align 4) ; CHECK: renamable $r0 = MVE_VSTRHU16_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1719, align 4)
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1
; CHECK: bb.2.for.cond.cleanup: ; CHECK: bb.2.for.cond.cleanup:
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
Show All 30 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-32.mir

Show First 20 Lines • Show All 100 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: incorrect_sub_32 ; CHECK-LABEL: name: incorrect_sub_32
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7
; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: t2IT 11, 8, implicit-def $itstate
; CHECK: tPOP_RET 11, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $lr = t2MOVi 1, 14, $noreg, $noreg ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: $lr = t2DLS killed renamable $lr
; CHECK: bb.1.vector.body: ; CHECK: bb.1.vector.body:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv13, align 4) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv13, align 4)
; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1416, align 4) ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1416, align 4)
; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 5, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 5, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1719, align 4) ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1719, align 4)
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1
; CHECK: bb.2.for.cond.cleanup: ; CHECK: bb.2.for.cond.cleanup:
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
Show All 30 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-8.mir

Show First 20 Lines • Show All 93 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: incorrect_sub_8 ; CHECK-LABEL: name: incorrect_sub_8
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7
; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: t2IT 11, 8, implicit-def $itstate
; CHECK: tPOP_RET 11, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $lr = t2MOVi 1, 14, $noreg, $noreg ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: $lr = t2DLS killed renamable $lr
; CHECK: bb.1.vector.body: ; CHECK: bb.1.vector.body:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv13, align 4) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv13, align 4)
; CHECK: renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1416, align 4) ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1416, align 4)
; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 15, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 15, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = nsw MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1719, align 4) ; CHECK: renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1719, align 4)
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1
; CHECK: bb.2.for.cond.cleanup: ; CHECK: bb.2.for.cond.cleanup:
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
Show All 30 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-1.mir

Show First 20 Lines • Show All 126 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: inloop_vpnot ; CHECK-LABEL: name: inloop_vpnot
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7
; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16
; CHECK: renamable $r12 = t2LDRi12 $sp, 20, 14, $noreg :: (load 4 from %fixed-stack.1) ; CHECK: renamable $r12 = t2LDRi12 $sp, 20, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.1)
; CHECK: t2CMPri renamable $r12, 0, 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPri renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.3, 0, killed $cpsr ; CHECK: tBcc %bb.3, 0 /* CC::eq */, killed $cpsr
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12
; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14, $noreg, $noreg ; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14, $noreg, $noreg ; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r5 = tLDRspi $sp, 4, 14, $noreg :: (load 4 from %fixed-stack.0, align 8) ; CHECK: renamable $r5 = tLDRspi $sp, 4, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.0, align 8)
; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14, $noreg, $noreg ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: $lr = t2DLS killed renamable $lr
; CHECK: $r4 = tMOVr killed $lr, 14, $noreg ; CHECK: $r4 = tMOVr killed $lr, 14 /* CC::al */, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r12 ; CHECK: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r12
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17.d, align 2) ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17.d, align 2)
; CHECK: renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1820.c, align 2) ; CHECK: renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1820.c, align 2)
; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2)
; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2) ; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2)
; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2
; CHECK: $lr = tMOVr $r4, 14, $noreg ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14, $noreg ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg ; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r5 = MVE_VSTRWU32_post renamable $q0, killed renamable $r5, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.cast.e, align 4) ; CHECK: renamable $r5 = MVE_VSTRWU32_post renamable $q0, killed renamable $r5, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.cast.e, align 4)
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.3(0x30000000), %bb.1(0x50000000) successors: %bb.3(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 16 frame-setup CFI_INSTRUCTION def_cfa_offset 16
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
▲ Show 20 Lines • Show All 49 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-2.mir

Show First 20 Lines • Show All 126 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: inloop_vpnot ; CHECK-LABEL: name: inloop_vpnot
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7
; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16
; CHECK: renamable $r12 = t2LDRi12 $sp, 20, 14, $noreg :: (load 4 from %fixed-stack.1) ; CHECK: renamable $r12 = t2LDRi12 $sp, 20, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.1)
; CHECK: t2CMPri renamable $r12, 0, 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPri renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.3, 0, killed $cpsr ; CHECK: tBcc %bb.3, 0 /* CC::eq */, killed $cpsr
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12
; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14, $noreg, $noreg ; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14, $noreg, $noreg ; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r5 = tLDRspi $sp, 4, 14, $noreg :: (load 4 from %fixed-stack.0, align 8) ; CHECK: renamable $r5 = tLDRspi $sp, 4, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.0, align 8)
; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14, $noreg, $noreg ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: $lr = t2DLS killed renamable $lr
; CHECK: $r4 = tMOVr killed $lr, 14, $noreg ; CHECK: $r4 = tMOVr killed $lr, 14 /* CC::al */, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r12 ; CHECK: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r12
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17.d, align 2) ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17.d, align 2)
; CHECK: renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1820.c, align 2) ; CHECK: renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1820.c, align 2)
; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2)
; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2) ; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2)
; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2
; CHECK: $lr = tMOVr $r4, 14, $noreg ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14, $noreg ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, killed renamable $vpr ; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, killed renamable $vpr
; CHECK: renamable $r5 = MVE_VSTRWU32_post renamable $q0, killed renamable $r5, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.cast.e, align 4) ; CHECK: renamable $r5 = MVE_VSTRWU32_post renamable $q0, killed renamable $r5, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.cast.e, align 4)
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.3(0x30000000), %bb.1(0x50000000) successors: %bb.3(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 16 frame-setup CFI_INSTRUCTION def_cfa_offset 16
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
▲ Show 20 Lines • Show All 49 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-3.mir

Show First 20 Lines • Show All 126 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: inloop_vpnot ; CHECK-LABEL: name: inloop_vpnot
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7
; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16
; CHECK: renamable $r12 = t2LDRi12 $sp, 20, 14, $noreg :: (load 4 from %fixed-stack.1) ; CHECK: renamable $r12 = t2LDRi12 $sp, 20, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.1)
; CHECK: t2CMPri renamable $r12, 0, 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPri renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.3, 0, killed $cpsr ; CHECK: tBcc %bb.3, 0 /* CC::eq */, killed $cpsr
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12
; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14, $noreg, $noreg ; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14, $noreg, $noreg ; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r5 = tLDRspi $sp, 4, 14, $noreg :: (load 4 from %fixed-stack.0, align 8) ; CHECK: renamable $r5 = tLDRspi $sp, 4, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.0, align 8)
; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14, $noreg, $noreg ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: $lr = t2DLS killed renamable $lr
; CHECK: $r4 = tMOVr killed $lr, 14, $noreg ; CHECK: $r4 = tMOVr killed $lr, 14 /* CC::al */, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r12 ; CHECK: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r12
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17.d, align 2) ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17.d, align 2)
; CHECK: renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1820.c, align 2) ; CHECK: renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1820.c, align 2)
; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2)
; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2) ; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2)
; CHECK: $lr = tMOVr $r4, 14, $noreg ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg
; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14, $noreg ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: MVE_VPST 2, implicit $vpr ; CHECK: MVE_VPST 2, implicit $vpr
; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2
; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, renamable $vpr, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, renamable $vpr, undef renamable $q1
; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, renamable $vpr, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, renamable $vpr, undef renamable $q0
; CHECK: renamable $r5 = MVE_VSTRWU32_post renamable $q0, killed renamable $r5, 16, 1, renamable $vpr :: (store 16 into %ir.lsr.cast.e, align 4) ; CHECK: renamable $r5 = MVE_VSTRWU32_post renamable $q0, killed renamable $r5, 16, 1, renamable $vpr :: (store 16 into %ir.lsr.cast.e, align 4)
; CHECK: dead renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg ; CHECK: dead renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.3(0x30000000), %bb.1(0x50000000) successors: %bb.3(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 16 frame-setup CFI_INSTRUCTION def_cfa_offset 16
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
▲ Show 20 Lines • Show All 49 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-1.mir

Show First 20 Lines • Show All 124 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: vpsel_after_vpt ; CHECK-LABEL: name: vpsel_after_vpt
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000) ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7
; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16
; CHECK: renamable $r12 = t2LDRi12 $sp, 16, 14, $noreg :: (load 4 from %fixed-stack.0, align 8) ; CHECK: renamable $r12 = t2LDRi12 $sp, 16, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.0, align 8)
; CHECK: t2CMPri renamable $r12, 0, 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPri renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.4, 0, killed $cpsr ; CHECK: tBcc %bb.4, 0 /* CC::eq */, killed $cpsr
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12
; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14, $noreg, $noreg ; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14, $noreg, $noreg ; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14, $noreg, $noreg ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r5 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14, $noreg, $noreg ; CHECK: renamable $r5 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: dead $lr = t2DLS renamable $r5 ; CHECK: dead $lr = t2DLS renamable $r5
; CHECK: $r4 = tMOVr killed $r5, 14, $noreg ; CHECK: $r4 = tMOVr killed $r5, 14 /* CC::al */, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r12 ; CHECK: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r12
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17.d, align 2) ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17.d, align 2)
; CHECK: renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1820.c, align 2) ; CHECK: renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1820.c, align 2)
; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2)
; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2) ; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2)
; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2
; CHECK: $lr = tMOVr $r4, 14, $noreg ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14, $noreg ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1
; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.middle.block: ; CHECK: bb.3.middle.block:
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
; CHECK: bb.4: ; CHECK: bb.4:
; CHECK: renamable $r0, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: renamable $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.4(0x30000000), %bb.1(0x50000000) successors: %bb.4(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 16 frame-setup CFI_INSTRUCTION def_cfa_offset 16
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
▲ Show 20 Lines • Show All 53 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-2.mir

Show First 20 Lines • Show All 126 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: vpsel_after_vpt ; CHECK-LABEL: name: vpsel_after_vpt
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000) ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7
; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16
; CHECK: renamable $r12 = t2LDRi12 $sp, 16, 14, $noreg :: (load 4 from %fixed-stack.0, align 8) ; CHECK: renamable $r12 = t2LDRi12 $sp, 16, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.0, align 8)
; CHECK: t2CMPri renamable $r12, 0, 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPri renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.4, 0, killed $cpsr ; CHECK: tBcc %bb.4, 0 /* CC::eq */, killed $cpsr
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12
; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14, $noreg, $noreg ; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14, $noreg, $noreg ; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14, $noreg, $noreg ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r5 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14, $noreg, $noreg ; CHECK: renamable $r5 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: dead $lr = t2DLS renamable $r5 ; CHECK: dead $lr = t2DLS renamable $r5
; CHECK: $r4 = tMOVr killed $r5, 14, $noreg ; CHECK: $r4 = tMOVr killed $r5, 14 /* CC::al */, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r12 ; CHECK: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r12
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg
; CHECK: MVE_VPST 2, implicit $vpr ; CHECK: MVE_VPST 2, implicit $vpr
; CHECK: renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17.d, align 2) ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17.d, align 2)
; CHECK: renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1820.c, align 2) ; CHECK: renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1820.c, align 2)
; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2) ; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2)
; CHECK: renamable $r0, renamable $q4 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q4 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2)
; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q4, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q4, 0, $noreg, undef renamable $q2
; CHECK: $lr = tMOVr $r4, 14, $noreg ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14, $noreg ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1
; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.middle.block: ; CHECK: bb.3.middle.block:
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
; CHECK: bb.4: ; CHECK: bb.4:
; CHECK: renamable $r0, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: renamable $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.4(0x30000000), %bb.1(0x50000000) successors: %bb.4(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 16 frame-setup CFI_INSTRUCTION def_cfa_offset 16
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
▲ Show 20 Lines • Show All 52 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain.mir

Show First 20 Lines • Show All 92 Lines • ▼ Show 20 Lines - id: 0
alignment: 16 alignment: 16
isTargetSpecific: false isTargetSpecific: false
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: it_block_2_stmts ; CHECK-LABEL: name: it_block_2_stmts
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r0, $r2, $r7 ; CHECK: liveins: $lr, $r0, $r2, $r7
; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = t2MOVi 4, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2MOVi 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: tCMPi8 killed renamable $r3, 4, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: t2IT 11, 8, implicit-def $itstate
; CHECK: $r1 = t2ADDri renamable $r0, 3, 11, $noreg, $noreg, implicit $itstate ; CHECK: $r1 = t2ADDri renamable $r0, 3, 11 /* CC::lt */, $noreg, $noreg, implicit $itstate
; CHECK: $r3 = t2LSLri renamable $r2, 1, 11, $cpsr, $noreg, implicit renamable $r12, implicit $itstate ; CHECK: $r3 = t2LSLri renamable $r2, 1, 11 /* CC::lt */, $cpsr, $noreg, implicit renamable $r12, implicit $itstate
; CHECK: $r12 = t2LSLri renamable $r3, 1, 11, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate ; CHECK: $r12 = t2LSLri renamable $r3, 1, 11 /* CC::lt */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
; CHECK: renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14, $noreg, $noreg ; CHECK: renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14 /* CC::al */, $noreg, $noreg
; CHECK: dead renamable $r12 = t2ADDri killed renamable $r2, 3, 14, $noreg, $noreg ; CHECK: dead renamable $r12 = t2ADDri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: dead renamable $r2, dead $cpsr = tMOVi8 1, 14, $noreg ; CHECK: dead renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = tLEApcrel %const.0, 14, $noreg ; CHECK: renamable $r2 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load 16 from constant-pool) ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load 16 from constant-pool)
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
; CHECK: bb.1.do.body (align 4): ; CHECK: bb.1.do.body (align 4):
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1 ; CHECK: liveins: $lr, $q0, $r0, $r1
; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg ; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg
; CHECK: renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1
; CHECK: MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg ; CHECK: MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg
; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg ; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
; CHECK: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14, $noreg ; CHECK: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK: bb.2.do.end: ; CHECK: bb.2.do.end:
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
; CHECK: bb.3 (align 16): ; CHECK: bb.3 (align 16):
; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16 ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
Show All 40 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-itercount.mir

Show First 20 Lines • Show All 93 Lines • ▼ Show 20 Lines - id: 0
alignment: 16 alignment: 16
isTargetSpecific: false isTargetSpecific: false
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: it_block_2_stmts ; CHECK-LABEL: name: it_block_2_stmts
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: renamable $r3, dead $cpsr = tLSLri killed renamable $r2, 1, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tLSLri killed renamable $r2, 1, 14 /* CC::al */, $noreg
; CHECK: dead renamable $r12 = t2MOVi 4, 14, $noreg, $noreg ; CHECK: dead renamable $r12 = t2MOVi 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: tCMPi8 renamable $r3, 4, 14, $noreg, implicit-def dead $cpsr ; CHECK: tCMPi8 renamable $r3, 4, 14 /* CC::al */, $noreg, implicit-def dead $cpsr
; CHECK: renamable $r2 = tLEApcrel %const.0, 14, $noreg ; CHECK: renamable $r2 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load 16 from constant-pool) ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load 16 from constant-pool)
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
; CHECK: bb.1.do.body (align 4): ; CHECK: bb.1.do.body (align 4):
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1 ; CHECK: liveins: $lr, $q0, $r0, $r1
; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg ; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg
; CHECK: renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1
; CHECK: MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg ; CHECK: MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg
; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg ; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
; CHECK: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14, $noreg ; CHECK: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK: bb.2.do.end: ; CHECK: bb.2.do.end:
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
; CHECK: bb.3 (align 16): ; CHECK: bb.3 (align 16):
; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16 ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
Show All 39 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir

Show All 35 Lines - id: 0
alignment: 4 alignment: 4
isTargetSpecific: false isTargetSpecific: false
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: cond_trip_count ; CHECK-LABEL: name: cond_trip_count
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r4 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4
; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8
; CHECK: tCMPi8 renamable $r1, 4, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r1, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: renamable $r3 = t2MOVi 4, 14, $noreg, $noreg ; CHECK: renamable $r3 = t2MOVi 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: t2IT 11, 8, implicit-def $itstate
; CHECK: dead $r3 = tMOVr renamable $r1, 11, killed $cpsr, implicit killed renamable $r3, implicit killed $itstate ; CHECK: dead $r3 = tMOVr renamable $r1, 11 /* CC::lt */, killed $cpsr, implicit killed renamable $r3, implicit killed $itstate
; CHECK: tCMPi8 renamable $r1, 2, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r1, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: renamable $r12 = t2MOVi 4, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2MOVi 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: tBcc %bb.2, 2, killed $cpsr ; CHECK: tBcc %bb.2, 2 /* CC::hs */, killed $cpsr
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: liveins: $r2 ; CHECK: liveins: $r2
; CHECK: renamable $s0 = VLDRS %const.0, 0, 14, $noreg ; CHECK: renamable $s0 = VLDRS %const.0, 0, 14 /* CC::al */, $noreg
; CHECK: VSTRS killed renamable $s0, killed renamable $r2, 0, 14, $noreg ; CHECK: VSTRS killed renamable $s0, killed renamable $r2, 0, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14, $noreg, def $r4, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: successors: %bb.3(0x80000000) ; CHECK: successors: %bb.3(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r12 ; CHECK: liveins: $r0, $r1, $r2, $r12
; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: tCMPi8 renamable $r1, 4, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r1, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: t2IT 11, 8, implicit-def $itstate
; CHECK: $r12 = tMOVr renamable $r1, 11, killed $cpsr, implicit killed renamable $r12, implicit killed $itstate ; CHECK: $r12 = tMOVr renamable $r1, 11 /* CC::lt */, killed $cpsr, implicit killed renamable $r12, implicit killed $itstate
; CHECK: renamable $r3 = t2SUBrr renamable $r1, killed renamable $r12, 14, $noreg, $noreg ; CHECK: renamable $r3 = t2SUBrr renamable $r1, killed renamable $r12, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 3, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 3, 14 /* CC::al */, $noreg
; CHECK: $r12 = tMOVr $r1, 14, $noreg ; CHECK: $r12 = tMOVr $r1, 14 /* CC::al */, $noreg
; CHECK: dead renamable $r4 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r3, 19, 14, $noreg, $noreg ; CHECK: dead renamable $r4 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
; CHECK: $r3 = tMOVr $r0, 14, $noreg ; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r12 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r12
; CHECK: bb.3: ; CHECK: bb.3:
; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000) ; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3
; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r3, 0, 0, $noreg ; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r3, 0, 0, $noreg
; CHECK: renamable $q0 = nnan ninf nsz MVE_VADDf32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, killed renamable $q0 ; CHECK: renamable $q0 = nnan ninf nsz MVE_VADDf32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, killed renamable $q0
; CHECK: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 16, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.3 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.3
; CHECK: bb.4: ; CHECK: bb.4:
; CHECK: successors: %bb.5(0x80000000) ; CHECK: successors: %bb.5(0x80000000)
; CHECK: liveins: $q0, $r0, $r1, $r2 ; CHECK: liveins: $q0, $r0, $r1, $r2
; CHECK: renamable $s4 = nnan ninf nsz VADDS renamable $s0, renamable $s1, 14, $noreg ; CHECK: renamable $s4 = nnan ninf nsz VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg
; CHECK: $r3 = tMOVr $r1, 14, $noreg ; CHECK: $r3 = tMOVr $r1, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
; CHECK: renamable $s4 = nnan ninf nsz VADDS renamable $s2, killed renamable $s4, 14, $noreg ; CHECK: renamable $s4 = nnan ninf nsz VADDS renamable $s2, killed renamable $s4, 14 /* CC::al */, $noreg
; CHECK: renamable $s0 = nnan ninf nsz VADDS killed renamable $s3, killed renamable $s4, 14, $noreg, implicit killed $q0 ; CHECK: renamable $s0 = nnan ninf nsz VADDS killed renamable $s3, killed renamable $s4, 14 /* CC::al */, $noreg, implicit killed $q0
; CHECK: $s2 = VMOVSR $r1, 14, $noreg ; CHECK: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
; CHECK: renamable $s2 = VUITOS killed renamable $s2, 14, $noreg ; CHECK: renamable $s2 = VUITOS killed renamable $s2, 14 /* CC::al */, $noreg
; CHECK: renamable $s4 = nnan ninf nsz VDIVS killed renamable $s0, killed renamable $s2, 14, $noreg ; CHECK: renamable $s4 = nnan ninf nsz VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
; CHECK: bb.5: ; CHECK: bb.5:
; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000) ; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $s4 ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $s4
; CHECK: $r4 = VMOVRS $s4, 14, $noreg ; CHECK: $r4 = VMOVRS $s4, 14 /* CC::al */, $noreg
; CHECK: renamable $q2 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg ; CHECK: renamable $q2 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg
; CHECK: renamable $q2 = nnan ninf nsz MVE_VSUB_qr_f32 killed renamable $q2, killed renamable $r4, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = nnan ninf nsz MVE_VSUB_qr_f32 killed renamable $q2, killed renamable $r4, 0, $noreg, undef renamable $q2
; CHECK: renamable $q0 = nnan ninf nsz MVE_VFMAf32 killed renamable $q0, killed renamable $q2, killed renamable $q2, 0, killed $noreg ; CHECK: renamable $q0 = nnan ninf nsz MVE_VFMAf32 killed renamable $q0, killed renamable $q2, killed renamable $q2, 0, killed $noreg
; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg ; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5
; CHECK: bb.6: ; CHECK: bb.6:
; CHECK: liveins: $q0, $r1, $r2 ; CHECK: liveins: $q0, $r1, $r2
; CHECK: renamable $s4 = nnan ninf nsz VADDS renamable $s0, renamable $s1, 14, $noreg ; CHECK: renamable $s4 = nnan ninf nsz VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg
; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 1, 14, $noreg ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $s4 = nnan ninf nsz VADDS renamable $s2, killed renamable $s4, 14, $noreg ; CHECK: renamable $s4 = nnan ninf nsz VADDS renamable $s2, killed renamable $s4, 14 /* CC::al */, $noreg
; CHECK: renamable $s0 = nnan ninf nsz VADDS killed renamable $s3, killed renamable $s4, 14, $noreg, implicit killed $q0 ; CHECK: renamable $s0 = nnan ninf nsz VADDS killed renamable $s3, killed renamable $s4, 14 /* CC::al */, $noreg, implicit killed $q0
; CHECK: $s2 = VMOVSR killed $r0, 14, $noreg ; CHECK: $s2 = VMOVSR killed $r0, 14 /* CC::al */, $noreg
; CHECK: renamable $s2 = VUITOS killed renamable $s2, 14, $noreg ; CHECK: renamable $s2 = VUITOS killed renamable $s2, 14 /* CC::al */, $noreg
; CHECK: renamable $s0 = nnan ninf nsz VDIVS killed renamable $s0, killed renamable $s2, 14, $noreg ; CHECK: renamable $s0 = nnan ninf nsz VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg
; CHECK: VSTRS killed renamable $s0, killed renamable $r2, 0, 14, $noreg ; CHECK: VSTRS killed renamable $s0, killed renamable $r2, 0, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14, $noreg, def $r4, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
; CHECK: bb.7 (align 4): ; CHECK: bb.7 (align 4):
; CHECK: CONSTPOOL_ENTRY 0, %const.0, 4 ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 4
bb.0: bb.0:
successors: %bb.1(0x40000000), %bb.2(0x40000000) successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $r0, $r1, $r2, $r4, $lr liveins: $r0, $r1, $r2, $r4, $lr
frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
▲ Show 20 Lines • Show All 98 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-random.mir

Show First 20 Lines • Show All 94 Lines • ▼ Show 20 Lines - id: 0
alignment: 16 alignment: 16
isTargetSpecific: false isTargetSpecific: false
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: it_block_2_stmts ; CHECK-LABEL: name: it_block_2_stmts
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = t2MOVi 4, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2MOVi 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: tCMPi8 renamable $r3, 4, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r3, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: t2IT 11, 8, implicit-def $itstate
; CHECK: $r12 = t2LSLri renamable $r2, 1, 11, $cpsr, $noreg, implicit killed renamable $r12, implicit $itstate ; CHECK: $r12 = t2LSLri renamable $r2, 1, 11 /* CC::lt */, $cpsr, $noreg, implicit killed renamable $r12, implicit $itstate
; CHECK: $r0 = t2ADDri killed renamable $r0, 42, 11, killed $cpsr, $noreg, implicit killed renamable $r0, implicit killed $itstate ; CHECK: $r0 = t2ADDri killed renamable $r0, 42, 11 /* CC::lt */, killed $cpsr, $noreg, implicit killed renamable $r0, implicit killed $itstate
; CHECK: renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14, $noreg, $noreg ; CHECK: renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14 /* CC::al */, $noreg, $noreg
; CHECK: dead renamable $r12 = t2ADDri killed renamable $r2, 3, 14, $noreg, $noreg ; CHECK: dead renamable $r12 = t2ADDri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: dead renamable $r2, dead $cpsr = tMOVi8 1, 14, $noreg ; CHECK: dead renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = tLEApcrel %const.0, 14, $noreg ; CHECK: renamable $r2 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load 16 from constant-pool) ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load 16 from constant-pool)
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
; CHECK: bb.1.do.body (align 4): ; CHECK: bb.1.do.body (align 4):
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1 ; CHECK: liveins: $lr, $q0, $r0, $r1
; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg ; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg
; CHECK: renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1
; CHECK: MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg ; CHECK: MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg
; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg ; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
; CHECK: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14, $noreg ; CHECK: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK: bb.2.do.end: ; CHECK: bb.2.do.end:
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
; CHECK: bb.3 (align 16): ; CHECK: bb.3 (align 16):
; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16 ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
Show All 39 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/livereg-no-loop-def.mir

Show First 20 Lines • Show All 82 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: exit_liveout ; CHECK-LABEL: name: exit_liveout
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4
; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8
; CHECK: renamable $r12 = t2ADDri $sp, 8, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2ADDri $sp, 8, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg :: (load 16 from %fixed-stack.0, align 8) ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg :: (load 16 from %fixed-stack.0, align 8)
; CHECK: tCBZ $r3, %bb.3 ; CHECK: tCBZ $r3, %bb.3
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $q0, $r0, $r1, $r2, $r3 ; CHECK: liveins: $q0, $r0, $r1, $r2, $r3
; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $q1, $r0, $r1, $r2 ; CHECK: liveins: $lr, $q0, $q1, $r0, $r1, $r2
; CHECK: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg :: (load 8 from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg :: (load 8 from %ir.lsr.iv17, align 2)
; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, $noreg :: (load 8 from %ir.lsr.iv1820, align 2) ; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, $noreg :: (load 8 from %ir.lsr.iv1820, align 2)
; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2
; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
; CHECK: renamable $r2 = MVE_VSTRWU32_post renamable $q1, killed renamable $r2, 16, 0, killed $noreg :: (store 16 into %ir.lsr.store, align 4) ; CHECK: renamable $r2 = MVE_VSTRWU32_post renamable $q1, killed renamable $r2, 16, 0, killed $noreg :: (store 16 into %ir.lsr.store, align 4)
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.exit: ; CHECK: bb.3.exit:
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK: renamable $r0, renamable $r1 = VMOVRRD renamable $d0, 14, $noreg ; CHECK: renamable $r0, renamable $r1 = VMOVRRD renamable $d0, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, renamable $r3 = VMOVRRD killed renamable $d1, 14, $noreg, implicit killed $q0 ; CHECK: renamable $r2, renamable $r3 = VMOVRRD killed renamable $d1, 14 /* CC::al */, $noreg, implicit killed $q0
; CHECK: tPOP_RET 14, $noreg, def $r4, def $pc, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3
bb.0.entry: bb.0.entry:
successors: %bb.3(0x30000000), %bb.1(0x50000000) successors: %bb.3(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r4, $lr liveins: $r0, $r1, $r2, $r3, $r4, $lr
frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r4, -8 frame-setup CFI_INSTRUCTION offset $r4, -8
▲ Show 20 Lines • Show All 44 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-chain.mir

Show First 20 Lines • Show All 218 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: test1 ; CHECK-LABEL: name: test1
; CHECK: bb.0.bb: ; CHECK: bb.0.bb:
; CHECK: successors: %bb.8(0x30000000), %bb.1(0x50000000) ; CHECK: successors: %bb.8(0x30000000), %bb.1(0x50000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11
; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8
; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12
; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16 ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16
; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20 ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24
; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28 ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28
; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36
; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14, $noreg ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 40 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 40
; CHECK: tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.8, 0, killed $cpsr ; CHECK: tBcc %bb.8, 0 /* CC::eq */, killed $cpsr
; CHECK: bb.1.bb4: ; CHECK: bb.1.bb4:
; CHECK: successors: %bb.2(0x40000000), %bb.3(0x40000000) ; CHECK: successors: %bb.2(0x40000000), %bb.3(0x40000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: renamable $r4, dead $cpsr = tSUBi3 renamable $r3, 1, 14, $noreg ; CHECK: renamable $r4, dead $cpsr = tSUBi3 renamable $r3, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r7 = t2ANDri renamable $r3, 3, 14, $noreg, $noreg ; CHECK: renamable $r7 = t2ANDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: tCMPi8 killed renamable $r4, 3, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 killed renamable $r4, 3, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tSTRspi killed renamable $r7, $sp, 0, 14, $noreg :: (store 4 into %stack.0) ; CHECK: tSTRspi killed renamable $r7, $sp, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.0)
; CHECK: tBcc %bb.3, 2, killed $cpsr ; CHECK: tBcc %bb.3, 2 /* CC::hs */, killed $cpsr
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: successors: %bb.5(0x80000000) ; CHECK: successors: %bb.5(0x80000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: renamable $r8 = t2MOVi 0, 14, $noreg, $noreg ; CHECK: renamable $r8 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: tB %bb.5, 14, $noreg ; CHECK: tB %bb.5, 14 /* CC::al */, $noreg
; CHECK: bb.3.bb12: ; CHECK: bb.3.bb12:
; CHECK: successors: %bb.4(0x80000000) ; CHECK: successors: %bb.4(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r8 = t2MOVi 0, 14, $noreg, $noreg ; CHECK: renamable $r8 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r3, 19, 14, $noreg, $noreg ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r12 = tMOVr killed $r3, 14, $noreg ; CHECK: $r12 = tMOVr killed $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: bb.4.bb28: ; CHECK: bb.4.bb28:
; CHECK: successors: %bb.4(0x7c000000), %bb.5(0x04000000) ; CHECK: successors: %bb.4(0x7c000000), %bb.5(0x04000000)
; CHECK: liveins: $r0, $r1, $r2, $r3, $r8, $r12 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r8, $r12
; CHECK: renamable $r5 = tLDRr renamable $r1, $r3, 14, $noreg :: (load 4 from %ir.scevgep617) ; CHECK: renamable $r5 = tLDRr renamable $r1, $r3, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep617)
; CHECK: renamable $r7, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg ; CHECK: renamable $r7, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $r6 = tLDRr renamable $r2, $r3, 14, $noreg :: (load 4 from %ir.scevgep418) ; CHECK: renamable $r6 = tLDRr renamable $r2, $r3, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep418)
; CHECK: $lr = tMOVr killed $r12, 14, $noreg ; CHECK: $lr = tMOVr killed $r12, 14 /* CC::al */, $noreg
; CHECK: renamable $r8 = nuw t2ADDri killed renamable $r8, 4, 14, $noreg, $noreg ; CHECK: renamable $r8 = nuw t2ADDri killed renamable $r8, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r5, dead $cpsr = tEOR killed renamable $r5, killed renamable $r6, 14, $noreg ; CHECK: renamable $r5, dead $cpsr = tEOR killed renamable $r5, killed renamable $r6, 14 /* CC::al */, $noreg
; CHECK: renamable $r6 = tLDRr renamable $r0, $r3, 14, $noreg :: (load 4 from %ir.scevgep219) ; CHECK: renamable $r6 = tLDRr renamable $r0, $r3, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep219)
; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14, $noreg, $noreg ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r12 = tMOVr $lr, 14, $noreg ; CHECK: $r12 = tMOVr $lr, 14 /* CC::al */, $noreg
; CHECK: renamable $r5 = nsw tADDhirr killed renamable $r5, killed renamable $r6, 14, $noreg ; CHECK: renamable $r5 = nsw tADDhirr killed renamable $r5, killed renamable $r6, 14 /* CC::al */, $noreg
; CHECK: tSTRr killed renamable $r5, renamable $r0, $r3, 14, $noreg :: (store 4 into %ir.scevgep219) ; CHECK: tSTRr killed renamable $r5, renamable $r0, $r3, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep219)
; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14, $noreg ; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $r4 = tLDRi renamable $r7, 1, 14, $noreg :: (load 4 from %ir.scevgep11) ; CHECK: renamable $r4 = tLDRi renamable $r7, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep11)
; CHECK: renamable $r6 = tLDRi renamable $r5, 1, 14, $noreg :: (load 4 from %ir.scevgep14) ; CHECK: renamable $r6 = tLDRi renamable $r5, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep14)
; CHECK: renamable $r9 = t2EORrr killed renamable $r4, killed renamable $r6, 14, $noreg, $noreg ; CHECK: renamable $r9 = t2EORrr killed renamable $r4, killed renamable $r6, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r6, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14, $noreg ; CHECK: renamable $r6, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: $r11 = t2ADDri $r6, 4, 14, $noreg, $noreg ; CHECK: $r11 = t2ADDri $r6, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 16, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg
; CHECK: t2LDMIA killed $r11, 14, $noreg, def $r4, def $r10, def $r11 :: (load 4 from %ir.scevgep9), (load 4 from %ir.scevgep8), (load 4 from %ir.scevgep1) ; CHECK: t2LDMIA killed $r11, 14 /* CC::al */, $noreg, def $r4, def $r10, def $r11 :: (load 4 from %ir.scevgep9), (load 4 from %ir.scevgep8), (load 4 from %ir.scevgep1)
; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r9, 14, $noreg ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r9, 14 /* CC::al */, $noreg
; CHECK: tSTRi killed renamable $r4, renamable $r6, 1, 14, $noreg :: (store 4 into %ir.scevgep9) ; CHECK: tSTRi killed renamable $r4, renamable $r6, 1, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep9)
; CHECK: renamable $r9 = t2LDRi12 renamable $r5, 8, 14, $noreg :: (load 4 from %ir.scevgep12) ; CHECK: renamable $r9 = t2LDRi12 renamable $r5, 8, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep12)
; CHECK: renamable $r4 = tLDRi renamable $r7, 2, 14, $noreg :: (load 4 from %ir.scevgep10) ; CHECK: renamable $r4 = tLDRi renamable $r7, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep10)
; CHECK: renamable $r4 = t2EORrr killed renamable $r4, killed renamable $r9, 14, $noreg, $noreg ; CHECK: renamable $r4 = t2EORrr killed renamable $r4, killed renamable $r9, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r10, 14, $noreg ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r10, 14 /* CC::al */, $noreg
; CHECK: tSTRi killed renamable $r4, renamable $r6, 2, 14, $noreg :: (store 4 into %ir.scevgep8) ; CHECK: tSTRi killed renamable $r4, renamable $r6, 2, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep8)
; CHECK: renamable $r4 = tLDRi killed renamable $r5, 3, 14, $noreg :: (load 4 from %ir.scevgep5) ; CHECK: renamable $r4 = tLDRi killed renamable $r5, 3, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep5)
; CHECK: renamable $r5 = tLDRi killed renamable $r7, 3, 14, $noreg :: (load 4 from %ir.scevgep3) ; CHECK: renamable $r5 = tLDRi killed renamable $r7, 3, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep3)
; CHECK: renamable $r4, dead $cpsr = tEOR killed renamable $r4, killed renamable $r5, 14, $noreg ; CHECK: renamable $r4, dead $cpsr = tEOR killed renamable $r4, killed renamable $r5, 14 /* CC::al */, $noreg
; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r11, 14, $noreg ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r11, 14 /* CC::al */, $noreg
; CHECK: tSTRi killed renamable $r4, killed renamable $r6, 3, 14, $noreg :: (store 4 into %ir.scevgep1) ; CHECK: tSTRi killed renamable $r4, killed renamable $r6, 3, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep1)
; CHECK: t2CMPri killed $lr, 0, 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPri killed $lr, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.4, 1, killed $cpsr ; CHECK: tBcc %bb.4, 1 /* CC::ne */, killed $cpsr
; CHECK: tB %bb.5, 14, $noreg ; CHECK: tB %bb.5, 14 /* CC::al */, $noreg
; CHECK: bb.5.bb13: ; CHECK: bb.5.bb13:
; CHECK: successors: %bb.8(0x30000000), %bb.6(0x50000000) ; CHECK: successors: %bb.8(0x30000000), %bb.6(0x50000000)
; CHECK: liveins: $r0, $r1, $r2, $r8 ; CHECK: liveins: $r0, $r1, $r2, $r8
; CHECK: renamable $r5 = tLDRspi $sp, 0, 14, $noreg :: (load 4 from %stack.0) ; CHECK: renamable $r5 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.0)
; CHECK: tCBZ $r5, %bb.8 ; CHECK: tCBZ $r5, %bb.8
; CHECK: bb.6.bb16: ; CHECK: bb.6.bb16:
; CHECK: successors: %bb.8(0x40000000), %bb.7(0x40000000) ; CHECK: successors: %bb.8(0x40000000), %bb.7(0x40000000)
; CHECK: liveins: $r0, $r1, $r2, $r5, $r8 ; CHECK: liveins: $r0, $r1, $r2, $r5, $r8
; CHECK: renamable $lr = t2LDRs renamable $r1, renamable $r8, 2, 14, $noreg :: (load 4 from %ir.tmp17) ; CHECK: renamable $lr = t2LDRs renamable $r1, renamable $r8, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.tmp17)
; CHECK: tCMPi8 renamable $r5, 1, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r5, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: renamable $r3 = t2LDRs renamable $r2, renamable $r8, 2, 14, $noreg :: (load 4 from %ir.tmp19) ; CHECK: renamable $r3 = t2LDRs renamable $r2, renamable $r8, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.tmp19)
; CHECK: renamable $lr = t2EORrr killed renamable $lr, killed renamable $r3, 14, $noreg, $noreg ; CHECK: renamable $lr = t2EORrr killed renamable $lr, killed renamable $r3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3 = t2LDRs renamable $r0, renamable $r8, 2, 14, $noreg :: (load 4 from %ir.tmp22) ; CHECK: renamable $r3 = t2LDRs renamable $r0, renamable $r8, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.tmp22)
; CHECK: renamable $r3 = nsw tADDhirr killed renamable $r3, killed renamable $lr, 14, $noreg ; CHECK: renamable $r3 = nsw tADDhirr killed renamable $r3, killed renamable $lr, 14 /* CC::al */, $noreg
; CHECK: t2STRs killed renamable $r3, renamable $r0, renamable $r8, 2, 14, $noreg :: (store 4 into %ir.tmp22) ; CHECK: t2STRs killed renamable $r3, renamable $r0, renamable $r8, 2, 14 /* CC::al */, $noreg :: (store 4 into %ir.tmp22)
; CHECK: tBcc %bb.8, 0, killed $cpsr ; CHECK: tBcc %bb.8, 0 /* CC::eq */, killed $cpsr
; CHECK: bb.7.bb57: ; CHECK: bb.7.bb57:
; CHECK: successors: %bb.8(0x40000000), %bb.9(0x40000000) ; CHECK: successors: %bb.8(0x40000000), %bb.9(0x40000000)
; CHECK: liveins: $r0, $r1, $r2, $r5, $r8 ; CHECK: liveins: $r0, $r1, $r2, $r5, $r8
; CHECK: renamable $r3 = nuw t2ADDri renamable $r8, 1, 14, $noreg, $noreg ; CHECK: renamable $r3 = nuw t2ADDri renamable $r8, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: tCMPi8 killed renamable $r5, 2, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 killed renamable $r5, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: renamable $r7 = t2LDRs renamable $r1, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp58) ; CHECK: renamable $r7 = t2LDRs renamable $r1, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.tmp58)
; CHECK: renamable $r6 = t2LDRs renamable $r2, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp60) ; CHECK: renamable $r6 = t2LDRs renamable $r2, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.tmp60)
; CHECK: renamable $r7 = t2EORrr killed renamable $r7, killed renamable $r6, 14, $noreg, $noreg ; CHECK: renamable $r7 = t2EORrr killed renamable $r7, killed renamable $r6, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r6 = t2LDRs renamable $r0, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp63) ; CHECK: renamable $r6 = t2LDRs renamable $r0, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.tmp63)
; CHECK: renamable $r7 = nsw tADDhirr killed renamable $r7, killed renamable $r6, 14, $noreg ; CHECK: renamable $r7 = nsw tADDhirr killed renamable $r7, killed renamable $r6, 14 /* CC::al */, $noreg
; CHECK: t2STRs killed renamable $r7, renamable $r0, killed renamable $r3, 2, 14, $noreg :: (store 4 into %ir.tmp63) ; CHECK: t2STRs killed renamable $r7, renamable $r0, killed renamable $r3, 2, 14 /* CC::al */, $noreg :: (store 4 into %ir.tmp63)
; CHECK: tBcc %bb.9, 1, killed $cpsr ; CHECK: tBcc %bb.9, 1 /* CC::ne */, killed $cpsr
; CHECK: bb.8.bb27: ; CHECK: bb.8.bb27:
; CHECK: $sp = tADDspi $sp, 1, 14, $noreg ; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK: $sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc ; CHECK: $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc
; CHECK: bb.9.bb68: ; CHECK: bb.9.bb68:
; CHECK: liveins: $r0, $r1, $r2, $r8 ; CHECK: liveins: $r0, $r1, $r2, $r8
; CHECK: renamable $r3 = nuw t2ADDri killed renamable $r8, 2, 14, $noreg, $noreg ; CHECK: renamable $r3 = nuw t2ADDri killed renamable $r8, 2, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r1 = t2LDRs killed renamable $r1, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp69) ; CHECK: renamable $r1 = t2LDRs killed renamable $r1, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.tmp69)
; CHECK: renamable $r2 = t2LDRs killed renamable $r2, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp71) ; CHECK: renamable $r2 = t2LDRs killed renamable $r2, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.tmp71)
; CHECK: renamable $r1, dead $cpsr = tEOR killed renamable $r1, killed renamable $r2, 14, $noreg ; CHECK: renamable $r1, dead $cpsr = tEOR killed renamable $r1, killed renamable $r2, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = t2LDRs renamable $r0, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp74) ; CHECK: renamable $r2 = t2LDRs renamable $r0, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.tmp74)
; CHECK: renamable $r1 = nsw tADDhirr killed renamable $r1, killed renamable $r2, 14, $noreg ; CHECK: renamable $r1 = nsw tADDhirr killed renamable $r1, killed renamable $r2, 14 /* CC::al */, $noreg
; CHECK: t2STRs killed renamable $r1, killed renamable $r0, killed renamable $r3, 2, 14, $noreg :: (store 4 into %ir.tmp74) ; CHECK: t2STRs killed renamable $r1, killed renamable $r0, killed renamable $r3, 2, 14 /* CC::al */, $noreg :: (store 4 into %ir.tmp74)
; CHECK: $sp = tADDspi $sp, 1, 14, $noreg ; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK: $sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc ; CHECK: $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc
bb.0.bb: bb.0.bb:
successors: %bb.8(0x30000000), %bb.1(0x50000000) successors: %bb.8(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr
$sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
frame-setup CFI_INSTRUCTION def_cfa_offset 36 frame-setup CFI_INSTRUCTION def_cfa_offset 36
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r11, -8 frame-setup CFI_INSTRUCTION offset $r11, -8
▲ Show 20 Lines • Show All 132 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-prev-iteration.mir

Show First 20 Lines • Show All 219 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: test1 ; CHECK-LABEL: name: test1
; CHECK: bb.0.bb: ; CHECK: bb.0.bb:
; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11
; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8
; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12
; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16 ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16
; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20 ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24
; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28 ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28
; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36
; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14, $noreg ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 40 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 40
; CHECK: tCBZ $r3, %bb.3 ; CHECK: tCBZ $r3, %bb.3
; CHECK: bb.1.bb4: ; CHECK: bb.1.bb4:
; CHECK: successors: %bb.2(0x40000000), %bb.4(0x40000000) ; CHECK: successors: %bb.2(0x40000000), %bb.4(0x40000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: renamable $r4, dead $cpsr = tSUBi3 renamable $r3, 1, 14, $noreg ; CHECK: renamable $r4, dead $cpsr = tSUBi3 renamable $r3, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r7 = t2ANDri renamable $r3, 3, 14, $noreg, $noreg ; CHECK: renamable $r7 = t2ANDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: tCMPi8 killed renamable $r4, 3, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 killed renamable $r4, 3, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tSTRspi killed renamable $r7, $sp, 0, 14, $noreg :: (store 4 into %stack.0) ; CHECK: tSTRspi killed renamable $r7, $sp, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.0)
; CHECK: tBcc %bb.4, 2, killed $cpsr ; CHECK: tBcc %bb.4, 2 /* CC::hs */, killed $cpsr
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: successors: %bb.6(0x80000000) ; CHECK: successors: %bb.6(0x80000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: renamable $r8 = t2MOVi 0, 14, $noreg, $noreg ; CHECK: renamable $r8 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $lr = t2MOVi 0, 14, $noreg, $noreg ; CHECK: renamable $lr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: tB %bb.6, 14, $noreg ; CHECK: tB %bb.6, 14 /* CC::al */, $noreg
; CHECK: bb.3: ; CHECK: bb.3:
; CHECK: successors: %bb.12(0x80000000) ; CHECK: successors: %bb.12(0x80000000)
; CHECK: renamable $lr = t2MOVi 0, 14, $noreg, $noreg ; CHECK: renamable $lr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: tB %bb.12, 14, $noreg ; CHECK: tB %bb.12, 14 /* CC::al */, $noreg
; CHECK: bb.4.bb12: ; CHECK: bb.4.bb12:
; CHECK: successors: %bb.5(0x80000000) ; CHECK: successors: %bb.5(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r8 = t2MOVi 0, 14, $noreg, $noreg ; CHECK: renamable $r8 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r3, 19, 14, $noreg, $noreg ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: $lr = t2DLS killed renamable $r3 ; CHECK: $lr = t2DLS killed renamable $r3
; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: bb.5.bb28: ; CHECK: bb.5.bb28:
; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000) ; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r8 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r8
; CHECK: renamable $r5 = tLDRr renamable $r1, $r3, 14, $noreg :: (load 4 from %ir.scevgep617) ; CHECK: renamable $r5 = tLDRr renamable $r1, $r3, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep617)
; CHECK: renamable $r7, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg ; CHECK: renamable $r7, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $r6 = tLDRr renamable $r2, $r3, 14, $noreg :: (load 4 from %ir.scevgep418) ; CHECK: renamable $r6 = tLDRr renamable $r2, $r3, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep418)
; CHECK: dead $r12 = tMOVr $lr, 14, $noreg ; CHECK: dead $r12 = tMOVr $lr, 14 /* CC::al */, $noreg
; CHECK: renamable $r8 = nuw t2ADDri killed renamable $r8, 4, 14, $noreg, $noreg ; CHECK: renamable $r8 = nuw t2ADDri killed renamable $r8, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r5, dead $cpsr = tEOR killed renamable $r5, killed renamable $r6, 14, $noreg ; CHECK: renamable $r5, dead $cpsr = tEOR killed renamable $r5, killed renamable $r6, 14 /* CC::al */, $noreg
; CHECK: renamable $r6 = tLDRr renamable $r0, $r3, 14, $noreg :: (load 4 from %ir.scevgep219) ; CHECK: renamable $r6 = tLDRr renamable $r0, $r3, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep219)
; CHECK: renamable $r5 = nsw tADDhirr killed renamable $r5, killed renamable $r6, 14, $noreg ; CHECK: renamable $r5 = nsw tADDhirr killed renamable $r5, killed renamable $r6, 14 /* CC::al */, $noreg
; CHECK: tSTRr killed renamable $r5, renamable $r0, $r3, 14, $noreg :: (store 4 into %ir.scevgep219) ; CHECK: tSTRr killed renamable $r5, renamable $r0, $r3, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep219)
; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14, $noreg ; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $r4 = tLDRi renamable $r7, 1, 14, $noreg :: (load 4 from %ir.scevgep11) ; CHECK: renamable $r4 = tLDRi renamable $r7, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep11)
; CHECK: renamable $r6 = tLDRi renamable $r5, 1, 14, $noreg :: (load 4 from %ir.scevgep14) ; CHECK: renamable $r6 = tLDRi renamable $r5, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep14)
; CHECK: renamable $r9 = t2EORrr killed renamable $r4, killed renamable $r6, 14, $noreg, $noreg ; CHECK: renamable $r9 = t2EORrr killed renamable $r4, killed renamable $r6, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r6, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14, $noreg ; CHECK: renamable $r6, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: $r11 = t2ADDri $r6, 4, 14, $noreg, $noreg ; CHECK: $r11 = t2ADDri $r6, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 16, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg
; CHECK: t2LDMIA killed $r11, 14, $noreg, def $r4, def $r10, def $r11 :: (load 4 from %ir.scevgep9), (load 4 from %ir.scevgep8), (load 4 from %ir.scevgep1) ; CHECK: t2LDMIA killed $r11, 14 /* CC::al */, $noreg, def $r4, def $r10, def $r11 :: (load 4 from %ir.scevgep9), (load 4 from %ir.scevgep8), (load 4 from %ir.scevgep1)
; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r9, 14, $noreg ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r9, 14 /* CC::al */, $noreg
; CHECK: tSTRi killed renamable $r4, renamable $r6, 1, 14, $noreg :: (store 4 into %ir.scevgep9) ; CHECK: tSTRi killed renamable $r4, renamable $r6, 1, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep9)
; CHECK: renamable $r9 = t2LDRi12 renamable $r5, 8, 14, $noreg :: (load 4 from %ir.scevgep12) ; CHECK: renamable $r9 = t2LDRi12 renamable $r5, 8, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep12)
; CHECK: renamable $r4 = tLDRi renamable $r7, 2, 14, $noreg :: (load 4 from %ir.scevgep10) ; CHECK: renamable $r4 = tLDRi renamable $r7, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep10)
; CHECK: renamable $r4 = t2EORrr killed renamable $r4, killed renamable $r9, 14, $noreg, $noreg ; CHECK: renamable $r4 = t2EORrr killed renamable $r4, killed renamable $r9, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r10, 14, $noreg ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r10, 14 /* CC::al */, $noreg
; CHECK: tSTRi killed renamable $r4, renamable $r6, 2, 14, $noreg :: (store 4 into %ir.scevgep8) ; CHECK: tSTRi killed renamable $r4, renamable $r6, 2, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep8)
; CHECK: renamable $r4 = tLDRi killed renamable $r5, 3, 14, $noreg :: (load 4 from %ir.scevgep5) ; CHECK: renamable $r4 = tLDRi killed renamable $r5, 3, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep5)
; CHECK: renamable $r5 = tLDRi killed renamable $r7, 3, 14, $noreg :: (load 4 from %ir.scevgep3) ; CHECK: renamable $r5 = tLDRi killed renamable $r7, 3, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep3)
; CHECK: renamable $r4, dead $cpsr = tEOR killed renamable $r4, killed renamable $r5, 14, $noreg ; CHECK: renamable $r4, dead $cpsr = tEOR killed renamable $r4, killed renamable $r5, 14 /* CC::al */, $noreg
; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r11, 14, $noreg ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r11, 14 /* CC::al */, $noreg
; CHECK: tSTRi killed renamable $r4, killed renamable $r6, 3, 14, $noreg :: (store 4 into %ir.scevgep1) ; CHECK: tSTRi killed renamable $r4, killed renamable $r6, 3, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep1)
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.5 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.5
; CHECK: bb.6.bb13: ; CHECK: bb.6.bb13:
; CHECK: successors: %bb.12(0x30000000), %bb.7(0x50000000) ; CHECK: successors: %bb.12(0x30000000), %bb.7(0x50000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r8 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r8
; CHECK: renamable $r5 = tLDRspi $sp, 0, 14, $noreg :: (load 4 from %stack.0) ; CHECK: renamable $r5 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.0)
; CHECK: tCBZ $r5, %bb.12 ; CHECK: tCBZ $r5, %bb.12
; CHECK: bb.7.bb16: ; CHECK: bb.7.bb16:
; CHECK: successors: %bb.8(0x40000000), %bb.9(0x40000000) ; CHECK: successors: %bb.8(0x40000000), %bb.9(0x40000000)
; CHECK: liveins: $r0, $r1, $r2, $r5, $r8 ; CHECK: liveins: $r0, $r1, $r2, $r5, $r8
; CHECK: renamable $lr = t2LDRs renamable $r1, renamable $r8, 2, 14, $noreg :: (load 4 from %ir.tmp17) ; CHECK: renamable $lr = t2LDRs renamable $r1, renamable $r8, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.tmp17)
; CHECK: tCMPi8 renamable $r5, 1, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r5, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: renamable $r3 = t2LDRs renamable $r2, renamable $r8, 2, 14, $noreg :: (load 4 from %ir.tmp19) ; CHECK: renamable $r3 = t2LDRs renamable $r2, renamable $r8, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.tmp19)
; CHECK: renamable $lr = t2EORrr killed renamable $lr, killed renamable $r3, 14, $noreg, $noreg ; CHECK: renamable $lr = t2EORrr killed renamable $lr, killed renamable $r3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3 = t2LDRs renamable $r0, renamable $r8, 2, 14, $noreg :: (load 4 from %ir.tmp22) ; CHECK: renamable $r3 = t2LDRs renamable $r0, renamable $r8, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.tmp22)
; CHECK: renamable $r3 = nsw tADDhirr killed renamable $r3, killed renamable $lr, 14, $noreg ; CHECK: renamable $r3 = nsw tADDhirr killed renamable $r3, killed renamable $lr, 14 /* CC::al */, $noreg
; CHECK: t2STRs killed renamable $r3, renamable $r0, renamable $r8, 2, 14, $noreg :: (store 4 into %ir.tmp22) ; CHECK: t2STRs killed renamable $r3, renamable $r0, renamable $r8, 2, 14 /* CC::al */, $noreg :: (store 4 into %ir.tmp22)
; CHECK: tBcc %bb.9, 1, killed $cpsr ; CHECK: tBcc %bb.9, 1 /* CC::ne */, killed $cpsr
; CHECK: bb.8: ; CHECK: bb.8:
; CHECK: successors: %bb.12(0x80000000) ; CHECK: successors: %bb.12(0x80000000)
; CHECK: renamable $lr = t2MOVi 1, 14, $noreg, $noreg ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: tB %bb.12, 14, $noreg ; CHECK: tB %bb.12, 14 /* CC::al */, $noreg
; CHECK: bb.9.bb57: ; CHECK: bb.9.bb57:
; CHECK: successors: %bb.10(0x40000000), %bb.11(0x40000000) ; CHECK: successors: %bb.10(0x40000000), %bb.11(0x40000000)
; CHECK: liveins: $r0, $r1, $r2, $r5, $r8 ; CHECK: liveins: $r0, $r1, $r2, $r5, $r8
; CHECK: renamable $r3 = nuw t2ADDri renamable $r8, 1, 14, $noreg, $noreg ; CHECK: renamable $r3 = nuw t2ADDri renamable $r8, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: tCMPi8 killed renamable $r5, 2, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 killed renamable $r5, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: renamable $r7 = t2LDRs renamable $r1, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp58) ; CHECK: renamable $r7 = t2LDRs renamable $r1, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.tmp58)
; CHECK: renamable $r6 = t2LDRs renamable $r2, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp60) ; CHECK: renamable $r6 = t2LDRs renamable $r2, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.tmp60)
; CHECK: renamable $r7 = t2EORrr killed renamable $r7, killed renamable $r6, 14, $noreg, $noreg ; CHECK: renamable $r7 = t2EORrr killed renamable $r7, killed renamable $r6, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r6 = t2LDRs renamable $r0, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp63) ; CHECK: renamable $r6 = t2LDRs renamable $r0, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.tmp63)
; CHECK: renamable $r7 = nsw tADDhirr killed renamable $r7, killed renamable $r6, 14, $noreg ; CHECK: renamable $r7 = nsw tADDhirr killed renamable $r7, killed renamable $r6, 14 /* CC::al */, $noreg
; CHECK: t2STRs killed renamable $r7, renamable $r0, killed renamable $r3, 2, 14, $noreg :: (store 4 into %ir.tmp63) ; CHECK: t2STRs killed renamable $r7, renamable $r0, killed renamable $r3, 2, 14 /* CC::al */, $noreg :: (store 4 into %ir.tmp63)
; CHECK: tBcc %bb.11, 1, killed $cpsr ; CHECK: tBcc %bb.11, 1 /* CC::ne */, killed $cpsr
; CHECK: bb.10: ; CHECK: bb.10:
; CHECK: successors: %bb.12(0x80000000) ; CHECK: successors: %bb.12(0x80000000)
; CHECK: renamable $lr = t2MOVi 2, 14, $noreg, $noreg ; CHECK: renamable $lr = t2MOVi 2, 14 /* CC::al */, $noreg, $noreg
; CHECK: tB %bb.12, 14, $noreg ; CHECK: tB %bb.12, 14 /* CC::al */, $noreg
; CHECK: bb.11.bb68: ; CHECK: bb.11.bb68:
; CHECK: successors: %bb.12(0x80000000) ; CHECK: successors: %bb.12(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r8 ; CHECK: liveins: $r0, $r1, $r2, $r8
; CHECK: renamable $r3 = nuw t2ADDri killed renamable $r8, 2, 14, $noreg, $noreg ; CHECK: renamable $r3 = nuw t2ADDri killed renamable $r8, 2, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $lr = t2MOVi 3, 14, $noreg, $noreg ; CHECK: renamable $lr = t2MOVi 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r1 = t2LDRs killed renamable $r1, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp69) ; CHECK: renamable $r1 = t2LDRs killed renamable $r1, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.tmp69)
; CHECK: renamable $r2 = t2LDRs killed renamable $r2, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp71) ; CHECK: renamable $r2 = t2LDRs killed renamable $r2, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.tmp71)
; CHECK: renamable $r1, dead $cpsr = tEOR killed renamable $r1, killed renamable $r2, 14, $noreg ; CHECK: renamable $r1, dead $cpsr = tEOR killed renamable $r1, killed renamable $r2, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = t2LDRs renamable $r0, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp74) ; CHECK: renamable $r2 = t2LDRs renamable $r0, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.tmp74)
; CHECK: renamable $r1 = nsw tADDhirr killed renamable $r1, killed renamable $r2, 14, $noreg ; CHECK: renamable $r1 = nsw tADDhirr killed renamable $r1, killed renamable $r2, 14 /* CC::al */, $noreg
; CHECK: t2STRs killed renamable $r1, killed renamable $r0, killed renamable $r3, 2, 14, $noreg :: (store 4 into %ir.tmp74) ; CHECK: t2STRs killed renamable $r1, killed renamable $r0, killed renamable $r3, 2, 14 /* CC::al */, $noreg :: (store 4 into %ir.tmp74)
; CHECK: bb.12.bb27: ; CHECK: bb.12.bb27:
; CHECK: liveins: $lr ; CHECK: liveins: $lr
; CHECK: $r0 = tMOVr killed $lr, 14, $noreg ; CHECK: $r0 = tMOVr killed $lr, 14 /* CC::al */, $noreg
; CHECK: $sp = tADDspi $sp, 1, 14, $noreg ; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK: $sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc, implicit killed $r0 ; CHECK: $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc, implicit killed $r0
bb.0.bb: bb.0.bb:
successors: %bb.3(0x30000000), %bb.1(0x50000000) successors: %bb.3(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr
$sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
frame-setup CFI_INSTRUCTION def_cfa_offset 36 frame-setup CFI_INSTRUCTION def_cfa_offset 36
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r11, -8 frame-setup CFI_INSTRUCTION offset $r11, -8
▲ Show 20 Lines • Show All 152 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-liveout.mir

Show First 20 Lines • Show All 219 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: test1 ; CHECK-LABEL: name: test1
; CHECK: bb.0.bb: ; CHECK: bb.0.bb:
; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11
; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8
; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12
; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16 ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16
; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20 ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24
; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28 ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28
; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36
; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14, $noreg ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 40 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 40
; CHECK: tCBZ $r3, %bb.3 ; CHECK: tCBZ $r3, %bb.3
; CHECK: bb.1.bb4: ; CHECK: bb.1.bb4:
; CHECK: successors: %bb.2(0x40000000), %bb.4(0x40000000) ; CHECK: successors: %bb.2(0x40000000), %bb.4(0x40000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: renamable $r4, dead $cpsr = tSUBi3 renamable $r3, 1, 14, $noreg ; CHECK: renamable $r4, dead $cpsr = tSUBi3 renamable $r3, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r7 = t2ANDri renamable $r3, 3, 14, $noreg, $noreg ; CHECK: renamable $r7 = t2ANDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: tCMPi8 killed renamable $r4, 3, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 killed renamable $r4, 3, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tSTRspi killed renamable $r7, $sp, 0, 14, $noreg :: (store 4 into %stack.0) ; CHECK: tSTRspi killed renamable $r7, $sp, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.0)
; CHECK: tBcc %bb.4, 2, killed $cpsr ; CHECK: tBcc %bb.4, 2 /* CC::hs */, killed $cpsr
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: successors: %bb.6(0x80000000) ; CHECK: successors: %bb.6(0x80000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: renamable $r8 = t2MOVi 0, 14, $noreg, $noreg ; CHECK: renamable $r8 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $lr = t2MOVi 0, 14, $noreg, $noreg ; CHECK: renamable $lr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: tB %bb.6, 14, $noreg ; CHECK: tB %bb.6, 14 /* CC::al */, $noreg
; CHECK: bb.3: ; CHECK: bb.3:
; CHECK: successors: %bb.12(0x80000000) ; CHECK: successors: %bb.12(0x80000000)
; CHECK: renamable $lr = t2MOVi 0, 14, $noreg, $noreg ; CHECK: renamable $lr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: tB %bb.12, 14, $noreg ; CHECK: tB %bb.12, 14 /* CC::al */, $noreg
; CHECK: bb.4.bb12: ; CHECK: bb.4.bb12:
; CHECK: successors: %bb.5(0x80000000) ; CHECK: successors: %bb.5(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r8 = t2MOVi 0, 14, $noreg, $noreg ; CHECK: renamable $r8 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r3, 19, 14, $noreg, $noreg ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: $lr = t2DLS killed renamable $r3 ; CHECK: $lr = t2DLS killed renamable $r3
; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: bb.5.bb28: ; CHECK: bb.5.bb28:
; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000) ; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r8 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r8
; CHECK: renamable $r5 = tLDRr renamable $r1, $r3, 14, $noreg :: (load 4 from %ir.scevgep617) ; CHECK: renamable $r5 = tLDRr renamable $r1, $r3, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep617)
; CHECK: renamable $r7, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg ; CHECK: renamable $r7, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $r6 = tLDRr renamable $r2, $r3, 14, $noreg :: (load 4 from %ir.scevgep418) ; CHECK: renamable $r6 = tLDRr renamable $r2, $r3, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep418)
; CHECK: renamable $r8 = nuw t2ADDri killed renamable $r8, 4, 14, $noreg, $noreg ; CHECK: renamable $r8 = nuw t2ADDri killed renamable $r8, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r5, dead $cpsr = tEOR killed renamable $r5, killed renamable $r6, 14, $noreg ; CHECK: renamable $r5, dead $cpsr = tEOR killed renamable $r5, killed renamable $r6, 14 /* CC::al */, $noreg
; CHECK: renamable $r6 = tLDRr renamable $r0, $r3, 14, $noreg :: (load 4 from %ir.scevgep219) ; CHECK: renamable $r6 = tLDRr renamable $r0, $r3, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep219)
; CHECK: renamable $r5 = nsw tADDhirr killed renamable $r5, killed renamable $r6, 14, $noreg ; CHECK: renamable $r5 = nsw tADDhirr killed renamable $r5, killed renamable $r6, 14 /* CC::al */, $noreg
; CHECK: tSTRr killed renamable $r5, renamable $r0, $r3, 14, $noreg :: (store 4 into %ir.scevgep219) ; CHECK: tSTRr killed renamable $r5, renamable $r0, $r3, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep219)
; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14, $noreg ; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $r4 = tLDRi renamable $r7, 1, 14, $noreg :: (load 4 from %ir.scevgep11) ; CHECK: renamable $r4 = tLDRi renamable $r7, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep11)
; CHECK: renamable $r6 = tLDRi renamable $r5, 1, 14, $noreg :: (load 4 from %ir.scevgep14) ; CHECK: renamable $r6 = tLDRi renamable $r5, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep14)
; CHECK: renamable $r9 = t2EORrr killed renamable $r4, killed renamable $r6, 14, $noreg, $noreg ; CHECK: renamable $r9 = t2EORrr killed renamable $r4, killed renamable $r6, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r6, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14, $noreg ; CHECK: renamable $r6, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: $r11 = t2ADDri $r6, 4, 14, $noreg, $noreg ; CHECK: $r11 = t2ADDri $r6, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 16, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg
; CHECK: t2LDMIA killed $r11, 14, $noreg, def $r4, def $r10, def $r11 :: (load 4 from %ir.scevgep9), (load 4 from %ir.scevgep8), (load 4 from %ir.scevgep1) ; CHECK: t2LDMIA killed $r11, 14 /* CC::al */, $noreg, def $r4, def $r10, def $r11 :: (load 4 from %ir.scevgep9), (load 4 from %ir.scevgep8), (load 4 from %ir.scevgep1)
; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r9, 14, $noreg ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r9, 14 /* CC::al */, $noreg
; CHECK: tSTRi killed renamable $r4, renamable $r6, 1, 14, $noreg :: (store 4 into %ir.scevgep9) ; CHECK: tSTRi killed renamable $r4, renamable $r6, 1, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep9)
; CHECK: renamable $r9 = t2LDRi12 renamable $r5, 8, 14, $noreg :: (load 4 from %ir.scevgep12) ; CHECK: renamable $r9 = t2LDRi12 renamable $r5, 8, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep12)
; CHECK: renamable $r4 = tLDRi renamable $r7, 2, 14, $noreg :: (load 4 from %ir.scevgep10) ; CHECK: renamable $r4 = tLDRi renamable $r7, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep10)
; CHECK: renamable $r4 = t2EORrr killed renamable $r4, killed renamable $r9, 14, $noreg, $noreg ; CHECK: renamable $r4 = t2EORrr killed renamable $r4, killed renamable $r9, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r10, 14, $noreg ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r10, 14 /* CC::al */, $noreg
; CHECK: tSTRi killed renamable $r4, renamable $r6, 2, 14, $noreg :: (store 4 into %ir.scevgep8) ; CHECK: tSTRi killed renamable $r4, renamable $r6, 2, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep8)
; CHECK: renamable $r4 = tLDRi killed renamable $r5, 3, 14, $noreg :: (load 4 from %ir.scevgep5) ; CHECK: renamable $r4 = tLDRi killed renamable $r5, 3, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep5)
; CHECK: renamable $r5 = tLDRi killed renamable $r7, 3, 14, $noreg :: (load 4 from %ir.scevgep3) ; CHECK: renamable $r5 = tLDRi killed renamable $r7, 3, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep3)
; CHECK: renamable $r4, dead $cpsr = tEOR killed renamable $r4, killed renamable $r5, 14, $noreg ; CHECK: renamable $r4, dead $cpsr = tEOR killed renamable $r4, killed renamable $r5, 14 /* CC::al */, $noreg
; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r11, 14, $noreg ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r11, 14 /* CC::al */, $noreg
; CHECK: tSTRi killed renamable $r4, killed renamable $r6, 3, 14, $noreg :: (store 4 into %ir.scevgep1) ; CHECK: tSTRi killed renamable $r4, killed renamable $r6, 3, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep1)
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.5 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.5
; CHECK: bb.6.bb13: ; CHECK: bb.6.bb13:
; CHECK: successors: %bb.12(0x30000000), %bb.7(0x50000000) ; CHECK: successors: %bb.12(0x30000000), %bb.7(0x50000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r8 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r8
; CHECK: renamable $r5 = tLDRspi $sp, 0, 14, $noreg :: (load 4 from %stack.0) ; CHECK: renamable $r5 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.0)
; CHECK: tCBZ $r5, %bb.12 ; CHECK: tCBZ $r5, %bb.12
; CHECK: bb.7.bb16: ; CHECK: bb.7.bb16:
; CHECK: successors: %bb.8(0x40000000), %bb.9(0x40000000) ; CHECK: successors: %bb.8(0x40000000), %bb.9(0x40000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r5, $r8 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r5, $r8
; CHECK: renamable $lr = t2LDRs renamable $r1, renamable $r8, 2, 14, $noreg :: (load 4 from %ir.tmp17) ; CHECK: renamable $lr = t2LDRs renamable $r1, renamable $r8, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.tmp17)
; CHECK: tCMPi8 renamable $r5, 1, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r5, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: renamable $r3 = t2LDRs renamable $r2, renamable $r8, 2, 14, $noreg :: (load 4 from %ir.tmp19) ; CHECK: renamable $r3 = t2LDRs renamable $r2, renamable $r8, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.tmp19)
; CHECK: renamable $lr = t2EORrr killed renamable $lr, killed renamable $r3, 14, $noreg, $noreg ; CHECK: renamable $lr = t2EORrr killed renamable $lr, killed renamable $r3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3 = t2LDRs renamable $r0, renamable $r8, 2, 14, $noreg :: (load 4 from %ir.tmp22) ; CHECK: renamable $r3 = t2LDRs renamable $r0, renamable $r8, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.tmp22)
; CHECK: renamable $r3 = nsw tADDhirr killed renamable $r3, killed renamable $lr, 14, $noreg ; CHECK: renamable $r3 = nsw tADDhirr killed renamable $r3, killed renamable $lr, 14 /* CC::al */, $noreg
; CHECK: t2STRs killed renamable $r3, renamable $r0, renamable $r8, 2, 14, $noreg :: (store 4 into %ir.tmp22) ; CHECK: t2STRs killed renamable $r3, renamable $r0, renamable $r8, 2, 14 /* CC::al */, $noreg :: (store 4 into %ir.tmp22)
; CHECK: tBcc %bb.9, 1, killed $cpsr ; CHECK: tBcc %bb.9, 1 /* CC::ne */, killed $cpsr
; CHECK: bb.8: ; CHECK: bb.8:
; CHECK: successors: %bb.12(0x80000000) ; CHECK: successors: %bb.12(0x80000000)
; CHECK: renamable $lr = t2MOVi 1, 14, $noreg, $noreg ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: tB %bb.12, 14, $noreg ; CHECK: tB %bb.12, 14 /* CC::al */, $noreg
; CHECK: bb.9.bb57: ; CHECK: bb.9.bb57:
; CHECK: successors: %bb.10(0x40000000), %bb.11(0x40000000) ; CHECK: successors: %bb.10(0x40000000), %bb.11(0x40000000)
; CHECK: liveins: $r0, $r1, $r2, $r5, $r8 ; CHECK: liveins: $r0, $r1, $r2, $r5, $r8
; CHECK: renamable $r3 = nuw t2ADDri renamable $r8, 1, 14, $noreg, $noreg ; CHECK: renamable $r3 = nuw t2ADDri renamable $r8, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: tCMPi8 killed renamable $r5, 2, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 killed renamable $r5, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: renamable $r7 = t2LDRs renamable $r1, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp58) ; CHECK: renamable $r7 = t2LDRs renamable $r1, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.tmp58)
; CHECK: renamable $r6 = t2LDRs renamable $r2, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp60) ; CHECK: renamable $r6 = t2LDRs renamable $r2, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.tmp60)
; CHECK: renamable $r7 = t2EORrr killed renamable $r7, killed renamable $r6, 14, $noreg, $noreg ; CHECK: renamable $r7 = t2EORrr killed renamable $r7, killed renamable $r6, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r6 = t2LDRs renamable $r0, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp63) ; CHECK: renamable $r6 = t2LDRs renamable $r0, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.tmp63)
; CHECK: renamable $r7 = nsw tADDhirr killed renamable $r7, killed renamable $r6, 14, $noreg ; CHECK: renamable $r7 = nsw tADDhirr killed renamable $r7, killed renamable $r6, 14 /* CC::al */, $noreg
; CHECK: t2STRs killed renamable $r7, renamable $r0, killed renamable $r3, 2, 14, $noreg :: (store 4 into %ir.tmp63) ; CHECK: t2STRs killed renamable $r7, renamable $r0, killed renamable $r3, 2, 14 /* CC::al */, $noreg :: (store 4 into %ir.tmp63)
; CHECK: tBcc %bb.11, 1, killed $cpsr ; CHECK: tBcc %bb.11, 1 /* CC::ne */, killed $cpsr
; CHECK: bb.10: ; CHECK: bb.10:
; CHECK: successors: %bb.12(0x80000000) ; CHECK: successors: %bb.12(0x80000000)
; CHECK: renamable $lr = t2MOVi 2, 14, $noreg, $noreg ; CHECK: renamable $lr = t2MOVi 2, 14 /* CC::al */, $noreg, $noreg
; CHECK: tB %bb.12, 14, $noreg ; CHECK: tB %bb.12, 14 /* CC::al */, $noreg
; CHECK: bb.11.bb68: ; CHECK: bb.11.bb68:
; CHECK: successors: %bb.12(0x80000000) ; CHECK: successors: %bb.12(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r8 ; CHECK: liveins: $r0, $r1, $r2, $r8
; CHECK: renamable $r3 = nuw t2ADDri killed renamable $r8, 2, 14, $noreg, $noreg ; CHECK: renamable $r3 = nuw t2ADDri killed renamable $r8, 2, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $lr = t2MOVi 3, 14, $noreg, $noreg ; CHECK: renamable $lr = t2MOVi 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r1 = t2LDRs killed renamable $r1, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp69) ; CHECK: renamable $r1 = t2LDRs killed renamable $r1, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.tmp69)
; CHECK: renamable $r2 = t2LDRs killed renamable $r2, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp71) ; CHECK: renamable $r2 = t2LDRs killed renamable $r2, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.tmp71)
; CHECK: renamable $r1, dead $cpsr = tEOR killed renamable $r1, killed renamable $r2, 14, $noreg ; CHECK: renamable $r1, dead $cpsr = tEOR killed renamable $r1, killed renamable $r2, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = t2LDRs renamable $r0, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp74) ; CHECK: renamable $r2 = t2LDRs renamable $r0, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.tmp74)
; CHECK: renamable $r1 = nsw tADDhirr killed renamable $r1, killed renamable $r2, 14, $noreg ; CHECK: renamable $r1 = nsw tADDhirr killed renamable $r1, killed renamable $r2, 14 /* CC::al */, $noreg
; CHECK: t2STRs killed renamable $r1, killed renamable $r0, killed renamable $r3, 2, 14, $noreg :: (store 4 into %ir.tmp74) ; CHECK: t2STRs killed renamable $r1, killed renamable $r0, killed renamable $r3, 2, 14 /* CC::al */, $noreg :: (store 4 into %ir.tmp74)
; CHECK: bb.12.bb27: ; CHECK: bb.12.bb27:
; CHECK: liveins: $lr ; CHECK: liveins: $lr
; CHECK: $r0 = tMOVr killed $lr, 14, $noreg ; CHECK: $r0 = tMOVr killed $lr, 14 /* CC::al */, $noreg
; CHECK: $sp = tADDspi $sp, 1, 14, $noreg ; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK: $sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc, implicit killed $r0 ; CHECK: $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc, implicit killed $r0
bb.0.bb: bb.0.bb:
successors: %bb.3(0x30000000), %bb.1(0x50000000) successors: %bb.3(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr
$sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
frame-setup CFI_INSTRUCTION def_cfa_offset 36 frame-setup CFI_INSTRUCTION def_cfa_offset 36
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r11, -8 frame-setup CFI_INSTRUCTION offset $r11, -8
▲ Show 20 Lines • Show All 151 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix-debug.mir

Show First 20 Lines • Show All 202 Lines • ▼ Show 20 Linesbody: |
; CHECK-LABEL: name: test_debug ; CHECK-LABEL: name: test_debug
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x50000000), %bb.5(0x30000000) ; CHECK: successors: %bb.1(0x50000000), %bb.5(0x30000000)
; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8, $r9, $r10 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8, $r9, $r10
; CHECK: DBG_VALUE $r0, $noreg, !23, !DIExpression(), debug-location !32 ; CHECK: DBG_VALUE $r0, $noreg, !23, !DIExpression(), debug-location !32
; CHECK: DBG_VALUE $r1, $noreg, !24, !DIExpression(), debug-location !32 ; CHECK: DBG_VALUE $r1, $noreg, !24, !DIExpression(), debug-location !32
; CHECK: DBG_VALUE $r2, $noreg, !25, !DIExpression(), debug-location !32 ; CHECK: DBG_VALUE $r2, $noreg, !25, !DIExpression(), debug-location !32
; CHECK: DBG_VALUE $r3, $noreg, !26, !DIExpression(), debug-location !32 ; CHECK: DBG_VALUE $r3, $noreg, !26, !DIExpression(), debug-location !32
; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12
; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20
; CHECK: $r7 = frame-setup tADDrSPi $sp, 3, 14, $noreg ; CHECK: $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8
; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r8, killed $r9, killed $r10 ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r8, killed $r9, killed $r10
; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -24 ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -24
; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -28 ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -28
; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -32 ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -32
; CHECK: $r5 = tMOVr killed $r2, 14, $noreg ; CHECK: $r5 = tMOVr killed $r2, 14 /* CC::al */, $noreg
; CHECK: DBG_VALUE $r5, $noreg, !25, !DIExpression(), debug-location !32 ; CHECK: DBG_VALUE $r5, $noreg, !25, !DIExpression(), debug-location !32
; CHECK: $r2, dead $cpsr = tMOVi8 0, 14, $noreg, debug-location !33 ; CHECK: $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg, debug-location !33
; CHECK: $r8 = tMOVr killed $r3, 14, $noreg ; CHECK: $r8 = tMOVr killed $r3, 14 /* CC::al */, $noreg
; CHECK: DBG_VALUE $r8, $noreg, !26, !DIExpression(), debug-location !32 ; CHECK: DBG_VALUE $r8, $noreg, !26, !DIExpression(), debug-location !32
; CHECK: $r9 = tMOVr $r1, 14, $noreg ; CHECK: $r9 = tMOVr $r1, 14 /* CC::al */, $noreg
; CHECK: DBG_VALUE $r9, $noreg, !24, !DIExpression(), debug-location !32 ; CHECK: DBG_VALUE $r9, $noreg, !24, !DIExpression(), debug-location !32
; CHECK: $r10 = tMOVr $r0, 14, $noreg ; CHECK: $r10 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: DBG_VALUE 0, $noreg, !29, !DIExpression(), debug-location !32 ; CHECK: DBG_VALUE 0, $noreg, !29, !DIExpression(), debug-location !32
; CHECK: DBG_VALUE $r10, $noreg, !23, !DIExpression(), debug-location !32 ; CHECK: DBG_VALUE $r10, $noreg, !23, !DIExpression(), debug-location !32
; CHECK: tBL 14, $noreg, @get_input, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit-def $sp, implicit-def dead $r0, debug-location !33 ; CHECK: tBL 14 /* CC::al */, $noreg, @get_input, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit-def $sp, implicit-def dead $r0, debug-location !33
; CHECK: DBG_VALUE 0, $noreg, !30, !DIExpression(), debug-location !32 ; CHECK: DBG_VALUE 0, $noreg, !30, !DIExpression(), debug-location !32
; CHECK: DBG_VALUE $noreg, $noreg, !28, !DIExpression(), debug-location !32 ; CHECK: DBG_VALUE $noreg, $noreg, !28, !DIExpression(), debug-location !32
; CHECK: t2CMPri renamable $r10, 1, 14, $noreg, implicit-def $cpsr, debug-location !37 ; CHECK: t2CMPri renamable $r10, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr, debug-location !37
; CHECK: tBcc %bb.5, 11, killed $cpsr, debug-location !37 ; CHECK: tBcc %bb.5, 11 /* CC::lt */, killed $cpsr, debug-location !37
; CHECK: bb.1.for.cond1.preheader.us.preheader: ; CHECK: bb.1.for.cond1.preheader.us.preheader:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r5, $r8, $r9, $r10 ; CHECK: liveins: $r5, $r8, $r9, $r10
; CHECK: renamable $r12 = t2LSLri renamable $r10, 1, 14, $noreg, $noreg, debug-location !37 ; CHECK: renamable $r12 = t2LSLri renamable $r10, 1, 14 /* CC::al */, $noreg, $noreg, debug-location !37
; CHECK: renamable $r1, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: renamable $r1, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: bb.2.for.cond1.preheader.us: ; CHECK: bb.2.for.cond1.preheader.us:
; CHECK: successors: %bb.3(0x80000000) ; CHECK: successors: %bb.3(0x80000000)
; CHECK: liveins: $r1, $r5, $r8, $r9, $r10, $r12 ; CHECK: liveins: $r1, $r5, $r8, $r9, $r10, $r12
; CHECK: DBG_VALUE $r1, $noreg, !30, !DIExpression(), debug-location !32 ; CHECK: DBG_VALUE $r1, $noreg, !30, !DIExpression(), debug-location !32
; CHECK: DBG_VALUE 0, $noreg, !31, !DIExpression(), debug-location !32 ; CHECK: DBG_VALUE 0, $noreg, !31, !DIExpression(), debug-location !32
; CHECK: renamable $r2 = t2LDRs renamable $r9, renamable $r1, 2, 14, $noreg, debug-location !41 :: (load 4 from %ir.arrayidx7.us) ; CHECK: renamable $r2 = t2LDRs renamable $r9, renamable $r1, 2, 14 /* CC::al */, $noreg, debug-location !41 :: (load 4 from %ir.arrayidx7.us)
; CHECK: $r3 = tMOVr $r5, 14, $noreg, debug-location !32 ; CHECK: $r3 = tMOVr $r5, 14 /* CC::al */, $noreg, debug-location !32
; CHECK: $r0 = tMOVr $r8, 14, $noreg, debug-location !32 ; CHECK: $r0 = tMOVr $r8, 14 /* CC::al */, $noreg, debug-location !32
; CHECK: $lr = t2DLS renamable $r10, debug-location !32 ; CHECK: $lr = t2DLS renamable $r10, debug-location !32
; CHECK: bb.3.for.body3.us: ; CHECK: bb.3.for.body3.us:
; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000) ; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r8, $r9, $r10, $r12 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r8, $r9, $r10, $r12
; CHECK: DBG_VALUE $noreg, $noreg, !31, !DIExpression(), debug-location !32 ; CHECK: DBG_VALUE $noreg, $noreg, !31, !DIExpression(), debug-location !32
; CHECK: renamable $r6, renamable $r3 = t2LDRSH_POST killed renamable $r3, 2, 14, $noreg, debug-location !43 :: (load 2 from %ir.lsr.iv5) ; CHECK: renamable $r6, renamable $r3 = t2LDRSH_POST killed renamable $r3, 2, 14 /* CC::al */, $noreg, debug-location !43 :: (load 2 from %ir.lsr.iv5)
; CHECK: renamable $r4, renamable $r0 = t2LDRSH_POST killed renamable $r0, 2, 14, $noreg, debug-location !44 :: (load 2 from %ir.lsr.iv1) ; CHECK: renamable $r4, renamable $r0 = t2LDRSH_POST killed renamable $r0, 2, 14 /* CC::al */, $noreg, debug-location !44 :: (load 2 from %ir.lsr.iv1)
; CHECK: renamable $r2 = nsw t2SMLABB killed renamable $r4, killed renamable $r6, killed renamable $r2, 14, $noreg, debug-location !41 ; CHECK: renamable $r2 = nsw t2SMLABB killed renamable $r4, killed renamable $r6, killed renamable $r2, 14 /* CC::al */, $noreg, debug-location !41
; CHECK: DBG_VALUE $noreg, $noreg, !31, !DIExpression(DW_OP_plus_uconst, 1, DW_OP_stack_value), debug-location !32 ; CHECK: DBG_VALUE $noreg, $noreg, !31, !DIExpression(DW_OP_plus_uconst, 1, DW_OP_stack_value), debug-location !32
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.3, debug-location !42 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.3, debug-location !42
; CHECK: bb.4.for.cond1.for.inc9_crit_edge.us: ; CHECK: bb.4.for.cond1.for.inc9_crit_edge.us:
; CHECK: successors: %bb.5(0x04000000), %bb.2(0x7c000000) ; CHECK: successors: %bb.5(0x04000000), %bb.2(0x7c000000)
; CHECK: liveins: $r1, $r2, $r5, $r8, $r9, $r10, $r12 ; CHECK: liveins: $r1, $r2, $r5, $r8, $r9, $r10, $r12
; CHECK: t2STRs killed renamable $r2, renamable $r9, renamable $r1, 2, 14, $noreg, debug-location !41 :: (store 4 into %ir.8) ; CHECK: t2STRs killed renamable $r2, renamable $r9, renamable $r1, 2, 14 /* CC::al */, $noreg, debug-location !41 :: (store 4 into %ir.8)
; CHECK: renamable $r1, dead $cpsr = nuw nsw tADDi8 killed renamable $r1, 1, 14, $noreg, debug-location !49 ; CHECK: renamable $r1, dead $cpsr = nuw nsw tADDi8 killed renamable $r1, 1, 14 /* CC::al */, $noreg, debug-location !49
; CHECK: DBG_VALUE $r1, $noreg, !30, !DIExpression(), debug-location !32 ; CHECK: DBG_VALUE $r1, $noreg, !30, !DIExpression(), debug-location !32
; CHECK: renamable $r5 = tADDhirr killed renamable $r5, renamable $r12, 14, $noreg, debug-location !37 ; CHECK: renamable $r5 = tADDhirr killed renamable $r5, renamable $r12, 14 /* CC::al */, $noreg, debug-location !37
; CHECK: tCMPhir renamable $r1, renamable $r10, 14, $noreg, implicit-def $cpsr, debug-location !37 ; CHECK: tCMPhir renamable $r1, renamable $r10, 14 /* CC::al */, $noreg, implicit-def $cpsr, debug-location !37
; CHECK: tBcc %bb.2, 1, killed $cpsr, debug-location !37 ; CHECK: tBcc %bb.2, 1 /* CC::ne */, killed $cpsr, debug-location !37
; CHECK: bb.5.for.end11: ; CHECK: bb.5.for.end11:
; CHECK: $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r8, def $r9, def $r10, debug-location !52 ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r10, debug-location !52
; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc, debug-location !52 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc, debug-location !52
bb.0.entry: bb.0.entry:
successors: %bb.1(0x50000000), %bb.5(0x30000000) successors: %bb.1(0x50000000), %bb.5(0x30000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8, $r9, $r10 liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8, $r9, $r10
DBG_VALUE $r0, $noreg, !23, !DIExpression(), debug-location !32 DBG_VALUE $r0, $noreg, !23, !DIExpression(), debug-location !32
DBG_VALUE $r1, $noreg, !24, !DIExpression(), debug-location !32 DBG_VALUE $r1, $noreg, !24, !DIExpression(), debug-location !32
DBG_VALUE $r2, $noreg, !25, !DIExpression(), debug-location !32 DBG_VALUE $r2, $noreg, !25, !DIExpression(), debug-location !32
DBG_VALUE $r3, $noreg, !26, !DIExpression(), debug-location !32 DBG_VALUE $r3, $noreg, !26, !DIExpression(), debug-location !32
▲ Show 20 Lines • Show All 77 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir

Show First 20 Lines • Show All 210 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: matrix_test ; CHECK-LABEL: name: matrix_test
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x50000000), %bb.12(0x30000000) ; CHECK: successors: %bb.1(0x50000000), %bb.12(0x30000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10
; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $lr ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $lr
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 32 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 32
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -8
; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -12
; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -16 ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -16
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -20 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -20
; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -24 ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -24
; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -28 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -28
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -32 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -32
; CHECK: tCMPi8 renamable $r0, 1, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r0, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2Bcc %bb.12, 11, killed $cpsr ; CHECK: t2Bcc %bb.12, 11 /* CC::lt */, killed $cpsr
; CHECK: bb.1.for.body.i.preheader: ; CHECK: bb.1.for.body.i.preheader:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: $r5 = tMOVr killed $r2, 14, $noreg ; CHECK: $r5 = tMOVr killed $r2, 14 /* CC::al */, $noreg
; CHECK: $r8 = tMOVr killed $r3, 14, $noreg ; CHECK: $r8 = tMOVr killed $r3, 14 /* CC::al */, $noreg
; CHECK: $r4 = tMOVr $r1, 14, $noreg ; CHECK: $r4 = tMOVr $r1, 14 /* CC::al */, $noreg
; CHECK: renamable $r6, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: renamable $r6, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = IMPLICIT_DEF ; CHECK: renamable $r2 = IMPLICIT_DEF
; CHECK: $r10 = tMOVr $r0, 14, $noreg ; CHECK: $r10 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: $lr = t2DLS killed renamable $r0 ; CHECK: $lr = t2DLS killed renamable $r0
; CHECK: bb.2.for.body.i: ; CHECK: bb.2.for.body.i:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r1, $r2, $r4, $r5, $r6, $r8, $r10 ; CHECK: liveins: $lr, $r1, $r2, $r4, $r5, $r6, $r8, $r10
; CHECK: renamable $r3, renamable $r1 = t2LDR_POST killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.lsr.iv15) ; CHECK: renamable $r3, renamable $r1 = t2LDR_POST killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.lsr.iv15)
; CHECK: renamable $r2 = nsw tADDhirr killed renamable $r2, renamable $r3, 14, $noreg ; CHECK: renamable $r2 = nsw tADDhirr killed renamable $r2, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: renamable $r7 = t2CSINC $zr, $zr, 13, implicit killed $cpsr ; CHECK: renamable $r7 = t2CSINC $zr, $zr, 13, implicit killed $cpsr
; CHECK: tCMPi8 killed renamable $r3, 0, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 killed renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: renamable $r3 = t2CSINC $zr, $zr, 13, implicit killed $cpsr ; CHECK: renamable $r3 = t2CSINC $zr, $zr, 13, implicit killed $cpsr
; CHECK: tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: renamable $r3 = t2ANDrr killed renamable $r3, killed renamable $r7, 14, $noreg, $noreg ; CHECK: renamable $r3 = t2ANDrr killed renamable $r3, killed renamable $r7, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2IT 12, 8, implicit-def $itstate ; CHECK: t2IT 12, 8, implicit-def $itstate
; CHECK: $r2 = tMOVi8 $noreg, 0, 12, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate ; CHECK: $r2 = tMOVi8 $noreg, 0, 12 /* CC::gt */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate
; CHECK: renamable $r6 = tADDhirr killed renamable $r6, killed renamable $r3, 14, $noreg ; CHECK: renamable $r6 = tADDhirr killed renamable $r6, killed renamable $r3, 14 /* CC::al */, $noreg
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.c.exit: ; CHECK: bb.3.c.exit:
; CHECK: successors: %bb.4(0x50000000), %bb.14(0x30000000) ; CHECK: successors: %bb.4(0x50000000), %bb.14(0x30000000)
; CHECK: liveins: $r4, $r5, $r6, $r8, $r10 ; CHECK: liveins: $r4, $r5, $r6, $r8, $r10
; CHECK: renamable $r0 = tSXTH killed renamable $r6, 14, $noreg ; CHECK: renamable $r0 = tSXTH killed renamable $r6, 14 /* CC::al */, $noreg
; CHECK: tBL 14, $noreg, @crc16, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0 ; CHECK: tBL 14 /* CC::al */, $noreg, @crc16, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0
; CHECK: $r12 = tMOVr killed $r0, 14, $noreg ; CHECK: $r12 = tMOVr killed $r0, 14 /* CC::al */, $noreg
; CHECK: renamable $r7, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: renamable $r7, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: t2CMPri $r10, 1, 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPri $r10, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.14, 11, killed $cpsr ; CHECK: tBcc %bb.14, 11 /* CC::lt */, killed $cpsr
; CHECK: bb.4.for.cond4.preheader.us.preheader: ; CHECK: bb.4.for.cond4.preheader.us.preheader:
; CHECK: successors: %bb.5(0x80000000) ; CHECK: successors: %bb.5(0x80000000)
; CHECK: liveins: $r4, $r5, $r7, $r8, $r10, $r12 ; CHECK: liveins: $r4, $r5, $r7, $r8, $r10, $r12
; CHECK: renamable $r0 = t2ADDri $r10, 3, 14, $noreg, $noreg ; CHECK: renamable $r0 = t2ADDri $r10, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: $lr = tMOVr $r10, 14, $noreg ; CHECK: $lr = tMOVr $r10, 14 /* CC::al */, $noreg
; CHECK: renamable $r0 = t2BICri killed renamable $r0, 3, 14, $noreg, $noreg ; CHECK: renamable $r0 = t2BICri killed renamable $r0, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3 = t2LSLri $r10, 1, 14, $noreg, $noreg ; CHECK: renamable $r3 = t2LSLri $r10, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r0, 4, 14, $noreg ; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r0, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r0, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VDUP32 renamable $r7, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VDUP32 renamable $r7, 0, $noreg, undef renamable $q0
; CHECK: renamable $r1, dead $cpsr = tLSRri killed renamable $r1, 2, 14, $noreg ; CHECK: renamable $r0 = nuw nsw t2ADDrs killed renamable $r0, renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r9 = t2SUBrs $r10, killed renamable $r1, 18, 14, $noreg, $noreg ; CHECK: renamable $r1, dead $cpsr = tLSRri killed renamable $r1, 2, 14 /* CC::al */, $noreg
; CHECK: renamable $r9 = t2SUBrs $r10, killed renamable $r1, 18, 14 /* CC::al */, $noreg, $noreg
; CHECK: bb.5.for.cond4.preheader.us: ; CHECK: bb.5.for.cond4.preheader.us:
; CHECK: successors: %bb.6(0x80000000) ; CHECK: successors: %bb.6(0x80000000)
; CHECK: liveins: $lr, $q0, $r0, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r12 ; CHECK: liveins: $lr, $q0, $r0, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r12
; CHECK: renamable $r1 = t2LDRs renamable $r4, renamable $r7, 2, 14, $noreg :: (load 4 from %ir.arrayidx12.us) ; CHECK: renamable $r1 = t2LDRs renamable $r4, renamable $r7, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.arrayidx12.us)
; CHECK: $q1 = MVE_VORR $q0, $q0, 0, $noreg, undef $q1 ; CHECK: $q1 = MVE_VORR $q0, $q0, 0, $noreg, undef $q1
; CHECK: $r2 = tMOVr killed $lr, 14, $noreg ; CHECK: $r2 = tMOVr killed $lr, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VMOV_to_lane_32 killed renamable $q1, killed renamable $r1, 0, 14, $noreg ; CHECK: renamable $q1 = MVE_VMOV_to_lane_32 killed renamable $q1, killed renamable $r1, 0, 14 /* CC::al */, $noreg
; CHECK: $r6 = tMOVr $r5, 14, $noreg ; CHECK: $r6 = tMOVr $r5, 14 /* CC::al */, $noreg
; CHECK: $r1 = tMOVr $r8, 14, $noreg ; CHECK: $r1 = tMOVr $r8, 14 /* CC::al */, $noreg
; CHECK: $lr = t2DLS renamable $r0 ; CHECK: $lr = t2DLS renamable $r0
; CHECK: bb.6.vector.body: ; CHECK: bb.6.vector.body:
; CHECK: successors: %bb.6(0x7c000000), %bb.7(0x04000000) ; CHECK: successors: %bb.6(0x7c000000), %bb.7(0x04000000)
; CHECK: liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r12 ; CHECK: liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r12
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
; CHECK: $q2 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q2 ; CHECK: $q2 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q2
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r6, renamable $q1 = MVE_VLDRHS32_post killed renamable $r6, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1012, align 2) ; CHECK: renamable $r6, renamable $q1 = MVE_VLDRHS32_post killed renamable $r6, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1012, align 2)
; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv46, align 2) ; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv46, align 2)
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q1, 0, $noreg, undef renamable $q1
; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q2, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q2, 0, $noreg, undef renamable $q1
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.6 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.6
; CHECK: bb.7.middle.block: ; CHECK: bb.7.middle.block:
; CHECK: successors: %bb.8(0x04000000), %bb.5(0x7c000000) ; CHECK: successors: %bb.8(0x04000000), %bb.5(0x7c000000)
; CHECK: liveins: $q0, $q1, $q2, $r0, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r12 ; CHECK: liveins: $q0, $q1, $q2, $r0, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r12
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r9, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r9, 0, $noreg
; CHECK: renamable $r5 = tADDhirr killed renamable $r5, renamable $r3, 14, $noreg ; CHECK: renamable $r5 = tADDhirr killed renamable $r5, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VPSEL killed renamable $q1, killed renamable $q2, 0, killed renamable $vpr ; CHECK: renamable $q1 = MVE_VPSEL killed renamable $q1, killed renamable $q2, 0, killed renamable $vpr
; CHECK: $lr = tMOVr $r10, 14, $noreg ; CHECK: $lr = tMOVr $r10, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = MVE_VADDVu32no_acc killed renamable $q1, 0, $noreg ; CHECK: renamable $r2 = MVE_VADDVu32no_acc killed renamable $q1, 0, $noreg
; CHECK: t2STRs killed renamable $r2, renamable $r4, renamable $r7, 2, 14, $noreg :: (store 4 into %ir.27) ; CHECK: t2STRs killed renamable $r2, renamable $r4, renamable $r7, 2, 14 /* CC::al */, $noreg :: (store 4 into %ir.27)
; CHECK: renamable $r7, dead $cpsr = nuw nsw tADDi8 killed renamable $r7, 1, 14, $noreg ; CHECK: renamable $r7, dead $cpsr = nuw nsw tADDi8 killed renamable $r7, 1, 14 /* CC::al */, $noreg
; CHECK: tCMPhir renamable $r7, $r10, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPhir renamable $r7, $r10, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.5, 1, killed $cpsr ; CHECK: tBcc %bb.5, 1 /* CC::ne */, killed $cpsr
; CHECK: bb.8.for.end16: ; CHECK: bb.8.for.end16:
; CHECK: successors: %bb.9(0x50000000), %bb.13(0x30000000) ; CHECK: successors: %bb.9(0x50000000), %bb.13(0x30000000)
; CHECK: liveins: $lr, $r4, $r12 ; CHECK: liveins: $lr, $r4, $r12
; CHECK: t2CMPri renamable $lr, 1, 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPri renamable $lr, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.13, 11, killed $cpsr ; CHECK: tBcc %bb.13, 11 /* CC::lt */, killed $cpsr
; CHECK: bb.9.for.body.i57.preheader: ; CHECK: bb.9.for.body.i57.preheader:
; CHECK: successors: %bb.10(0x80000000) ; CHECK: successors: %bb.10(0x80000000)
; CHECK: liveins: $lr, $r4, $r12 ; CHECK: liveins: $lr, $r4, $r12
; CHECK: renamable $r0, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: renamable $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: renamable $r1 = IMPLICIT_DEF ; CHECK: renamable $r1 = IMPLICIT_DEF
; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: $lr = t2DLS killed renamable $lr
; CHECK: bb.10.for.body.i57: ; CHECK: bb.10.for.body.i57:
; CHECK: successors: %bb.10(0x7c000000), %bb.11(0x04000000) ; CHECK: successors: %bb.10(0x7c000000), %bb.11(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r4, $r12 ; CHECK: liveins: $lr, $r0, $r1, $r4, $r12
; CHECK: renamable $r2, renamable $r4 = t2LDR_POST killed renamable $r4, 4, 14, $noreg :: (load 4 from %ir.lsr.iv1) ; CHECK: renamable $r2, renamable $r4 = t2LDR_POST killed renamable $r4, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.lsr.iv1)
; CHECK: renamable $r1 = nsw tADDhirr killed renamable $r1, renamable $r2, 14, $noreg ; CHECK: renamable $r1 = nsw tADDhirr killed renamable $r1, renamable $r2, 14 /* CC::al */, $noreg
; CHECK: tCMPi8 renamable $r1, 0, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r1, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: renamable $r3 = t2CSINC $zr, $zr, 13, implicit killed $cpsr ; CHECK: renamable $r3 = t2CSINC $zr, $zr, 13, implicit killed $cpsr
; CHECK: tCMPi8 killed renamable $r2, 0, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 killed renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: renamable $r2 = t2CSINC $zr, $zr, 13, implicit killed $cpsr ; CHECK: renamable $r2 = t2CSINC $zr, $zr, 13, implicit killed $cpsr
; CHECK: tCMPi8 renamable $r1, 0, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r1, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: renamable $r2 = t2ANDrr killed renamable $r2, killed renamable $r3, 14, $noreg, $noreg ; CHECK: renamable $r2 = t2ANDrr killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2IT 12, 8, implicit-def $itstate ; CHECK: t2IT 12, 8, implicit-def $itstate
; CHECK: $r1 = tMOVi8 $noreg, 0, 12, killed $cpsr, implicit killed renamable $r1, implicit killed $itstate ; CHECK: $r1 = tMOVi8 $noreg, 0, 12 /* CC::gt */, killed $cpsr, implicit killed renamable $r1, implicit killed $itstate
; CHECK: renamable $r0 = tADDhirr killed renamable $r0, killed renamable $r2, 14, $noreg ; CHECK: renamable $r0 = tADDhirr killed renamable $r0, killed renamable $r2, 14 /* CC::al */, $noreg
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.10 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.10
; CHECK: bb.11.c.exit59.loopexit: ; CHECK: bb.11.c.exit59.loopexit:
; CHECK: successors: %bb.14(0x80000000) ; CHECK: successors: %bb.14(0x80000000)
; CHECK: liveins: $r0, $r12 ; CHECK: liveins: $r0, $r12
; CHECK: renamable $r7 = tSXTH killed renamable $r0, 14, $noreg ; CHECK: renamable $r7 = tSXTH killed renamable $r0, 14 /* CC::al */, $noreg
; CHECK: tB %bb.14, 14, $noreg ; CHECK: tB %bb.14, 14 /* CC::al */, $noreg
; CHECK: bb.12.c.exit.thread: ; CHECK: bb.12.c.exit.thread:
; CHECK: successors: %bb.14(0x80000000) ; CHECK: successors: %bb.14(0x80000000)
; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: renamable $r7, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: renamable $r7, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: tBL 14, $noreg, @crc16, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0 ; CHECK: tBL 14 /* CC::al */, $noreg, @crc16, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0
; CHECK: $r12 = tMOVr killed $r0, 14, $noreg ; CHECK: $r12 = tMOVr killed $r0, 14 /* CC::al */, $noreg
; CHECK: tB %bb.14, 14, $noreg ; CHECK: tB %bb.14, 14 /* CC::al */, $noreg
; CHECK: bb.13: ; CHECK: bb.13:
; CHECK: successors: %bb.14(0x80000000) ; CHECK: successors: %bb.14(0x80000000)
; CHECK: liveins: $r12 ; CHECK: liveins: $r12
; CHECK: renamable $r7, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: renamable $r7, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: bb.14.c.exit59: ; CHECK: bb.14.c.exit59:
; CHECK: liveins: $r7, $r12 ; CHECK: liveins: $r7, $r12
; CHECK: $r0 = tMOVr killed $r7, 14, $noreg ; CHECK: $r0 = tMOVr killed $r7, 14 /* CC::al */, $noreg
; CHECK: $r1 = tMOVr killed $r12, 14, $noreg ; CHECK: $r1 = tMOVr killed $r12, 14 /* CC::al */, $noreg
; CHECK: $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $lr ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $lr
; CHECK: tTAILJMPdND @crc16, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0, implicit killed $r1 ; CHECK: tTAILJMPdND @crc16, 14 /* CC::al */, $noreg, implicit $sp, implicit $sp, implicit killed $r0, implicit killed $r1
bb.0.entry: bb.0.entry:
successors: %bb.1(0x50000000), %bb.12(0x30000000) successors: %bb.1(0x50000000), %bb.12(0x30000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $lr liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $lr
$sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $lr $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $lr
frame-setup CFI_INSTRUCTION def_cfa_offset 32 frame-setup CFI_INSTRUCTION def_cfa_offset 32
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r10, -8 frame-setup CFI_INSTRUCTION offset $r10, -8
▲ Show 20 Lines • Show All 175 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dls.mir

Show First 20 Lines • Show All 81 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: do_copy ; CHECK-LABEL: name: do_copy
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: $lr = t2DLS killed $r0 ; CHECK: $lr = t2DLS killed $r0
; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg ; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: bb.1.while.body: ; CHECK: bb.1.while.body:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $r0, $r1 ; CHECK: liveins: $lr, $r0, $r1
; CHECK: renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6) ; CHECK: renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep6)
; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2) ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep2)
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1
; CHECK: bb.2.while.end: ; CHECK: bb.2.while.end:
; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
Show All 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir

Show First 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: start_before_elems ; CHECK-LABEL: name: start_before_elems
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4
; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8
; CHECK: renamable $r12 = t2MOVi 0, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2CMPrs killed renamable $r12, renamable $r3, 11, 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPrs killed renamable $r12, renamable $r3, 11, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 0, 8, implicit-def $itstate ; CHECK: t2IT 0, 8, implicit-def $itstate
; CHECK: tPOP_RET 0, killed $cpsr, def $r4, def $pc, implicit killed $itstate ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate
; CHECK: renamable $r12 = t2LSRri killed renamable $r3, 1, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2LSRri killed renamable $r3, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r12 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r12
; CHECK: bb.1.vector.body: ; CHECK: bb.1.vector.body:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14, $noreg ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep45, align 1) ; CHECK: renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep45, align 1)
; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep23, align 1) ; CHECK: renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep23, align 1)
; CHECK: renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv1, align 4) ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv1, align 4)
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK: bb.2.for.cond.cleanup: ; CHECK: bb.2.for.cond.cleanup:
; CHECK: tPOP_RET 14, $noreg, def $r4, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r4, $lr liveins: $r0, $r1, $r2, $r3, $r4, $lr
frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r4, -8 frame-setup CFI_INSTRUCTION offset $r4, -8
Show All 39 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir

Show First 20 Lines • Show All 100 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: start_before_elems ; CHECK-LABEL: name: start_before_elems
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4
; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8
; CHECK: renamable $r12 = t2MOVi 0, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2CMPrs killed renamable $r12, renamable $r3, 11, 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPrs killed renamable $r12, renamable $r3, 11, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 0, 8, implicit-def $itstate ; CHECK: t2IT 0, 8, implicit-def $itstate
; CHECK: tPOP_RET 0, killed $cpsr, def $r4, def $pc, implicit killed $itstate ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate
; CHECK: $r12 = t2MOVr killed $r3, 14, $noreg, $noreg ; CHECK: $r12 = t2MOVr killed $r3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 1, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r12 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r12
; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: bb.1.vector.body: ; CHECK: bb.1.vector.body:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14, $noreg ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep45, align 1) ; CHECK: renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep45, align 1)
; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep23, align 1) ; CHECK: renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep23, align 1)
; CHECK: renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv1, align 4) ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv1, align 4)
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK: bb.2.for.cond.cleanup: ; CHECK: bb.2.for.cond.cleanup:
; CHECK: tPOP_RET 14, $noreg, def $r4, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r4, $lr liveins: $r0, $r1, $r2, $r3, $r4, $lr
frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r4, -8 frame-setup CFI_INSTRUCTION offset $r4, -8
Show All 39 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir

Show First 20 Lines • Show All 100 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: start_before_elems ; CHECK-LABEL: name: start_before_elems
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4
; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8
; CHECK: renamable $r12 = t2MOVi 0, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2CMPrs killed renamable $r12, renamable $r3, 11, 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPrs killed renamable $r12, renamable $r3, 11, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 0, 8, implicit-def $itstate ; CHECK: t2IT 0, 8, implicit-def $itstate
; CHECK: tPOP_RET 0, killed $cpsr, def $r4, def $pc, implicit killed $itstate ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate
; CHECK: $r12 = t2MOVr killed $r3, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2MOVi 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: renamable $r12 = nuw t2ADDrs killed renamable $r12, renamable $r3, 11, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 1, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: dead renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r12 = t2MOVr killed $r3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r12 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r12
; CHECK: bb.1.vector.body: ; CHECK: bb.1.vector.body:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14, $noreg ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep45, align 1) ; CHECK: renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep45, align 1)
; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep23, align 1) ; CHECK: renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep23, align 1)
; CHECK: renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv1, align 4) ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv1, align 4)
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK: bb.2.for.cond.cleanup: ; CHECK: bb.2.for.cond.cleanup:
; CHECK: tPOP_RET 14, $noreg, def $r4, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r4, $lr liveins: $r0, $r1, $r2, $r3, $r4, $lr
frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r4, -8 frame-setup CFI_INSTRUCTION offset $r4, -8
Show All 39 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiple-do-loops.mir

Show First 20 Lines • Show All 342 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: test1 ; CHECK-LABEL: name: test1
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.6(0x30000000), %bb.1(0x50000000) ; CHECK: successors: %bb.6(0x30000000), %bb.1(0x50000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8
; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12
; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20
; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 3, 14, $noreg ; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8
; CHECK: early-clobber $sp = frame-setup t2STR_PRE killed $r8, $sp, -4, 14, $noreg ; CHECK: early-clobber $sp = frame-setup t2STR_PRE killed $r8, $sp, -4, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -24 ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -24
; CHECK: tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.6, 0, killed $cpsr ; CHECK: tBcc %bb.6, 0 /* CC::eq */, killed $cpsr
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: $r8 = tMOVr $r0, 14, $noreg ; CHECK: $r8 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: $r5 = tMOVr $r2, 14, $noreg ; CHECK: $r5 = tMOVr $r2, 14 /* CC::al */, $noreg
; CHECK: $r4 = tMOVr $r3, 14, $noreg ; CHECK: $r4 = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK: $r6 = tMOVr $r1, 14, $noreg ; CHECK: $r6 = tMOVr $r1, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r4 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r4
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r6, $r8 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r6, $r8
; CHECK: renamable $r6, renamable $q0 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg :: (load 16 from %ir.lsr.iv6264, align 4) ; CHECK: renamable $r6, renamable $q0 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg :: (load 16 from %ir.lsr.iv6264, align 4)
; CHECK: renamable $r5, renamable $q1 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg :: (load 16 from %ir.lsr.iv6567, align 4) ; CHECK: renamable $r5, renamable $q1 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg :: (load 16 from %ir.lsr.iv6567, align 4)
; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv6870, align 4) ; CHECK: renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv6870, align 4)
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond4.preheader: ; CHECK: bb.3.for.cond4.preheader:
; CHECK: successors: %bb.6(0x30000000), %bb.4(0x50000000) ; CHECK: successors: %bb.6(0x30000000), %bb.4(0x50000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: tCBZ $r3, %bb.6 ; CHECK: tCBZ $r3, %bb.6
; CHECK: bb.4.vector.ph39: ; CHECK: bb.4.vector.ph39:
; CHECK: successors: %bb.5(0x80000000) ; CHECK: successors: %bb.5(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: $r12 = tMOVr $r0, 14, $noreg ; CHECK: $r12 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
; CHECK: bb.5.vector.body38: ; CHECK: bb.5.vector.body38:
; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000) ; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r12 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r12
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load 16 from %ir.lsr.iv55, align 4) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load 16 from %ir.lsr.iv55, align 4)
; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg :: (load 16 from %ir.lsr.iv5658, align 4) ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg :: (load 16 from %ir.lsr.iv5658, align 4)
; CHECK: renamable $r12, renamable $q2 = MVE_VLDRWU32_post killed renamable $r12, 16, 0, $noreg :: (load 16 from %ir.lsr.iv5961, align 4) ; CHECK: renamable $r12, renamable $q2 = MVE_VLDRWU32_post killed renamable $r12, 16, 0, $noreg :: (load 16 from %ir.lsr.iv5961, align 4)
; CHECK: renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg :: (store 16 into %ir.lsr.iv5961, align 4) ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg :: (store 16 into %ir.lsr.iv5961, align 4)
; CHECK: $r0 = tMOVr $r12, 14, $noreg ; CHECK: $r0 = tMOVr $r12, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5
; CHECK: bb.6.for.cond.cleanup6: ; CHECK: bb.6.for.cond.cleanup6:
; CHECK: $r8, $sp = t2LDR_POST $sp, 4, 14, $noreg ; CHECK: $r8, $sp = t2LDR_POST $sp, 4, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.6(0x30000000), %bb.1(0x50000000) successors: %bb.6(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8 liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8
frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 20 frame-setup CFI_INSTRUCTION def_cfa_offset 20
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
▲ Show 20 Lines • Show All 135 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: test2 ; CHECK-LABEL: name: test2
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8
; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12
; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20
; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 3, 14, $noreg ; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8
; CHECK: early-clobber $sp = frame-setup t2STR_PRE killed $r8, $sp, -4, 14, $noreg ; CHECK: early-clobber $sp = frame-setup t2STR_PRE killed $r8, $sp, -4, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -24 ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -24
; CHECK: renamable $r6, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: renamable $r6, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: t2CMPrs killed renamable $r6, renamable $r3, 11, 14, $noreg, implicit-def $cpsr ; CHECK: dead renamable $r12 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: tBcc %bb.3, 0, killed $cpsr ; CHECK: t2CMPrs killed renamable $r6, renamable $r3, 11, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.3, 0 /* CC::eq */, killed $cpsr
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: renamable $r4, dead $cpsr = tLSRri renamable $r3, 1, 14, $noreg ; CHECK: renamable $r4, dead $cpsr = tLSRri renamable $r3, 1, 14 /* CC::al */, $noreg
; CHECK: $r8 = tMOVr $r0, 14, $noreg ; CHECK: $r8 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: $r5 = tMOVr $r1, 14, $noreg ; CHECK: $r5 = tMOVr $r1, 14 /* CC::al */, $noreg
; CHECK: $r6 = tMOVr $r2, 14, $noreg ; CHECK: $r6 = tMOVr $r2, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r4 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r4
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r6, $r8 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r6, $r8
; CHECK: renamable $r5, renamable $q0 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg :: (load 16 from %ir.lsr.iv6264, align 4) ; CHECK: renamable $r5, renamable $q0 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg :: (load 16 from %ir.lsr.iv6264, align 4)
; CHECK: renamable $r6, renamable $q1 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg :: (load 16 from %ir.lsr.iv6567, align 4) ; CHECK: renamable $r6, renamable $q1 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg :: (load 16 from %ir.lsr.iv6567, align 4)
; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv6870, align 4) ; CHECK: renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv6870, align 4)
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond4.preheader: ; CHECK: bb.3.for.cond4.preheader:
; CHECK: successors: %bb.6(0x30000000), %bb.4(0x50000000) ; CHECK: successors: %bb.6(0x30000000), %bb.4(0x50000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: tCBZ $r3, %bb.6 ; CHECK: tCBZ $r3, %bb.6
; CHECK: bb.4.vector.ph39: ; CHECK: bb.4.vector.ph39:
; CHECK: successors: %bb.5(0x80000000) ; CHECK: successors: %bb.5(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: $r4 = tMOVr $r0, 14, $noreg ; CHECK: $r4 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
; CHECK: bb.5.vector.body38: ; CHECK: bb.5.vector.body38:
; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000) ; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r4 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load 16 from %ir.lsr.iv55, align 4) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load 16 from %ir.lsr.iv55, align 4)
; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg :: (load 16 from %ir.lsr.iv5658, align 4) ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg :: (load 16 from %ir.lsr.iv5658, align 4)
; CHECK: renamable $r4, renamable $q2 = MVE_VLDRWU32_post killed renamable $r4, 16, 0, $noreg :: (load 16 from %ir.lsr.iv5961, align 4) ; CHECK: renamable $r4, renamable $q2 = MVE_VLDRWU32_post killed renamable $r4, 16, 0, $noreg :: (load 16 from %ir.lsr.iv5961, align 4)
; CHECK: renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg :: (store 16 into %ir.lsr.iv5961, align 4) ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg :: (store 16 into %ir.lsr.iv5961, align 4)
; CHECK: $r0 = tMOVr $r4, 14, $noreg ; CHECK: $r0 = tMOVr $r4, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5
; CHECK: bb.6.for.cond.cleanup6: ; CHECK: bb.6.for.cond.cleanup6:
; CHECK: $r8, $sp = t2LDR_POST $sp, 4, 14, $noreg ; CHECK: $r8, $sp = t2LDR_POST $sp, 4, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.3(0x30000000), %bb.1(0x50000000) successors: %bb.3(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8 liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8
frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 20 frame-setup CFI_INSTRUCTION def_cfa_offset 20
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
▲ Show 20 Lines • Show All 145 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: test3 ; CHECK-LABEL: name: test3
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.9(0x30000000), %bb.1(0x50000000) ; CHECK: successors: %bb.9(0x30000000), %bb.1(0x50000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r9, $r10 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r9, $r10
; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12
; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20
; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 3, 14, $noreg ; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8
; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r8, killed $r9, killed $r10 ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r8, killed $r9, killed $r10
; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -24 ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -24
; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -28 ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -28
; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -32 ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -32
; CHECK: tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.9, 0, killed $cpsr ; CHECK: tBcc %bb.9, 0 /* CC::eq */, killed $cpsr
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: $r8 = tMOVr $r0, 14, $noreg ; CHECK: $r8 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: $r5 = tMOVr $r2, 14, $noreg ; CHECK: $r5 = tMOVr $r2, 14 /* CC::al */, $noreg
; CHECK: $r4 = tMOVr $r3, 14, $noreg ; CHECK: $r4 = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK: $r6 = tMOVr $r1, 14, $noreg ; CHECK: $r6 = tMOVr $r1, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r4 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r4
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r6, $r8 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r6, $r8
; CHECK: renamable $r6, renamable $q0 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg :: (load 16 from %ir.lsr.iv117119, align 4) ; CHECK: renamable $r6, renamable $q0 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg :: (load 16 from %ir.lsr.iv117119, align 4)
; CHECK: renamable $r5, renamable $q1 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg :: (load 16 from %ir.lsr.iv120122, align 4) ; CHECK: renamable $r5, renamable $q1 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg :: (load 16 from %ir.lsr.iv120122, align 4)
; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv123125, align 4) ; CHECK: renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv123125, align 4)
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond4.preheader: ; CHECK: bb.3.for.cond4.preheader:
; CHECK: successors: %bb.6(0x30000000), %bb.4(0x50000000) ; CHECK: successors: %bb.6(0x30000000), %bb.4(0x50000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: renamable $r6, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: renamable $r6, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: t2CMPrs killed renamable $r6, renamable $r3, 11, 14, $noreg, implicit-def $cpsr ; CHECK: dead renamable $r8 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: tBcc %bb.6, 0, killed $cpsr ; CHECK: t2CMPrs killed renamable $r6, renamable $r3, 11, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.6, 0 /* CC::eq */, killed $cpsr
; CHECK: bb.4.vector.ph66: ; CHECK: bb.4.vector.ph66:
; CHECK: successors: %bb.5(0x80000000) ; CHECK: successors: %bb.5(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: renamable $r5, dead $cpsr = tLSRri renamable $r3, 1, 14, $noreg ; CHECK: renamable $r5, dead $cpsr = tLSRri renamable $r3, 1, 14 /* CC::al */, $noreg
; CHECK: $r10 = tMOVr $r0, 14, $noreg ; CHECK: $r10 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: $r9 = tMOVr $r2, 14, $noreg ; CHECK: $r9 = tMOVr $r2, 14 /* CC::al */, $noreg
; CHECK: $r4 = tMOVr $r1, 14, $noreg ; CHECK: $r4 = tMOVr $r1, 14 /* CC::al */, $noreg
; CHECK: $r6 = tMOVr $r0, 14, $noreg ; CHECK: $r6 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r5 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r5
; CHECK: bb.5.vector.body65: ; CHECK: bb.5.vector.body65:
; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000) ; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r6, $r9, $r10 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r6, $r9, $r10
; CHECK: renamable $r4, renamable $q0 = MVE_VLDRWU32_post killed renamable $r4, 16, 0, $noreg :: (load 16 from %ir.lsr.iv108110, align 4) ; CHECK: renamable $r4, renamable $q0 = MVE_VLDRWU32_post killed renamable $r4, 16, 0, $noreg :: (load 16 from %ir.lsr.iv108110, align 4)
; CHECK: renamable $r9, renamable $q1 = MVE_VLDRWU32_post killed renamable $r9, 16, 0, $noreg :: (load 16 from %ir.lsr.iv111113, align 4) ; CHECK: renamable $r9, renamable $q1 = MVE_VLDRWU32_post killed renamable $r9, 16, 0, $noreg :: (load 16 from %ir.lsr.iv111113, align 4)
; CHECK: renamable $r6, renamable $q2 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg :: (load 16 from %ir.lsr.iv114116, align 4) ; CHECK: renamable $r6, renamable $q2 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg :: (load 16 from %ir.lsr.iv114116, align 4)
; CHECK: renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r10, 0, 0, killed $noreg :: (store 16 into %ir.lsr.iv114116, align 4) ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r10, 0, 0, killed $noreg :: (store 16 into %ir.lsr.iv114116, align 4)
; CHECK: $r10 = tMOVr $r6, 14, $noreg ; CHECK: $r10 = tMOVr $r6, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5
; CHECK: bb.6.for.cond15.preheader: ; CHECK: bb.6.for.cond15.preheader:
; CHECK: successors: %bb.9(0x30000000), %bb.7(0x50000000) ; CHECK: successors: %bb.9(0x30000000), %bb.7(0x50000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: tCBZ $r3, %bb.9 ; CHECK: tCBZ $r3, %bb.9
; CHECK: bb.7.vector.ph85: ; CHECK: bb.7.vector.ph85:
; CHECK: successors: %bb.8(0x80000000) ; CHECK: successors: %bb.8(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: $r5 = tMOVr $r0, 14, $noreg ; CHECK: $r5 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
; CHECK: bb.8.vector.body84: ; CHECK: bb.8.vector.body84:
; CHECK: successors: %bb.8(0x7c000000), %bb.9(0x04000000) ; CHECK: successors: %bb.8(0x7c000000), %bb.9(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r5 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r5
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load 16 from %ir.lsr.iv101, align 4) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load 16 from %ir.lsr.iv101, align 4)
; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg :: (load 16 from %ir.lsr.iv102104, align 4) ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg :: (load 16 from %ir.lsr.iv102104, align 4)
; CHECK: renamable $r5, renamable $q2 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg :: (load 16 from %ir.lsr.iv105107, align 4) ; CHECK: renamable $r5, renamable $q2 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg :: (load 16 from %ir.lsr.iv105107, align 4)
; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: renamable $q0 = MVE_VSUBi32 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VSUBi32 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg :: (store 16 into %ir.lsr.iv105107, align 4) ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg :: (store 16 into %ir.lsr.iv105107, align 4)
; CHECK: $r0 = tMOVr $r5, 14, $noreg ; CHECK: $r0 = tMOVr $r5, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.8 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.8
; CHECK: bb.9.for.cond.cleanup17: ; CHECK: bb.9.for.cond.cleanup17:
; CHECK: $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r8, def $r9, def $r10 ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r10
; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.9(0x30000000), %bb.1(0x50000000) successors: %bb.9(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8, $r9, $r10 liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8, $r9, $r10
frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 20 frame-setup CFI_INSTRUCTION def_cfa_offset 20
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
▲ Show 20 Lines • Show All 125 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-cbnz.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumbv8.1m.main %s -run-pass=arm-cp-islands --verify-machineinstrs -o - | FileCheck %s --check-prefix=CHECK-LOB # RUN: llc -mtriple=thumbv8.1m.main %s -run-pass=arm-cp-islands --verify-machineinstrs -o - | FileCheck %s --check-prefix=CHECK-LOB
# RUN: llc -mtriple=thumbv8.1m.main -mattr=-lob %s -run-pass=arm-cp-islands --verify-machineinstrs -o - | FileCheck %s --check-prefix=CHECK-NOLOB # RUN: llc -mtriple=thumbv8.1m.main -mattr=-lob %s -run-pass=arm-cp-islands --verify-machineinstrs -o - | FileCheck %s --check-prefix=CHECK-NOLOB
# CHECK-NOLOB-NOT: t2LE
# CHECK-LOB: bb.3.land.rhs:
# CHECK-LOB: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg
# CHECK-LOB: tCBNZ $r0, %bb.8
# CHECK-LOB: t2LE %bb.3
# CHECK-LOB: bb.7.while.body19:
# CHECK-LOB: tCBZ $r0, %bb.8
# CHECK-LOB: t2LE %bb.6
# CHECK-LOB: bb.8:
--- | --- |
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv8.1m.main" target triple = "thumbv8.1m.main"
%struct.head_s = type { %struct.head_s*, %struct.data_s* } %struct.head_s = type { %struct.head_s*, %struct.data_s* }
%struct.data_s = type { i16, i16 } %struct.data_s = type { i16, i16 }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define dso_local arm_aapcscc %struct.head_s* @search(%struct.head_s* readonly %list, %struct.data_s* nocapture readonly %info) local_unnamed_addr #0 { define dso_local arm_aapcscc %struct.head_s* @search(%struct.head_s* readonly %list, %struct.data_s* nocapture readonly %info) local_unnamed_addr #0 {
entry: entry:
%idx = getelementptr inbounds %struct.data_s, %struct.data_s* %info, i32 0, i32 1 %idx = getelementptr inbounds %struct.data_s, %struct.data_s* %info, i32 0, i32 1
%0 = load i16, i16* %idx, align 2 %0 = load i16, i16* %idx, align 2
%cmp = icmp sgt i16 %0, -1 %cmp = icmp sgt i16 %0, -1
br i1 %cmp, label %while.cond.preheader, label %while.cond9.preheader br i1 %cmp, label %while.cond.preheader, label %while.cond9.preheader
while.cond9.preheader: ; preds = %entry while.cond9.preheader: ; preds = %entry
%1 = icmp eq %struct.head_s* %list, null %1 = icmp eq %struct.head_s* %list, null
br i1 %1, label %return, label %land.rhs11.lr.ph br i1 %1, label %return, label %land.rhs11.lr.ph
land.rhs11.lr.ph: ; preds = %while.cond9.preheader land.rhs11.lr.ph: ; preds = %while.cond9.preheader
%data16143 = bitcast %struct.data_s* %info to i16* %data16143 = bitcast %struct.data_s* %info to i16*
%2 = load i16, i16* %data16143, align 2 %2 = load i16, i16* %data16143, align 2
%conv15 = sext i16 %2 to i32 %conv15 = sext i16 %2 to i32
br label %land.rhs11 br label %land.rhs11
while.cond.preheader: ; preds = %entry while.cond.preheader: ; preds = %entry
%3 = icmp eq %struct.head_s* %list, null %3 = icmp eq %struct.head_s* %list, null
br i1 %3, label %return, label %land.rhs.preheader br i1 %3, label %return, label %land.rhs.preheader
land.rhs.preheader: ; preds = %while.cond.preheader land.rhs.preheader: ; preds = %while.cond.preheader
br label %land.rhs br label %land.rhs
land.rhs: ; preds = %land.rhs.preheader, %while.body land.rhs: ; preds = %land.rhs.preheader, %while.body
%list.addr.033 = phi %struct.head_s* [ %6, %while.body ], [ %list, %land.rhs.preheader ] %list.addr.033 = phi %struct.head_s* [ %6, %while.body ], [ %list, %land.rhs.preheader ]
%info2 = getelementptr inbounds %struct.head_s, %struct.head_s* %list.addr.033, i32 0, i32 1 %info2 = getelementptr inbounds %struct.head_s, %struct.head_s* %list.addr.033, i32 0, i32 1
%4 = load %struct.data_s*, %struct.data_s** %info2, align 4 %4 = load %struct.data_s*, %struct.data_s** %info2, align 4
%idx3 = getelementptr inbounds %struct.data_s, %struct.data_s* %4, i32 0, i32 1 %idx3 = getelementptr inbounds %struct.data_s, %struct.data_s* %4, i32 0, i32 1
%5 = load i16, i16* %idx3, align 2 %5 = load i16, i16* %idx3, align 2
%cmp7 = icmp eq i16 %5, %0 %cmp7 = icmp eq i16 %5, %0
br i1 %cmp7, label %return, label %while.body br i1 %cmp7, label %return, label %while.body
while.body: ; preds = %land.rhs while.body: ; preds = %land.rhs
%next4 = bitcast %struct.head_s* %list.addr.033 to %struct.head_s** %next4 = bitcast %struct.head_s* %list.addr.033 to %struct.head_s**
%6 = load %struct.head_s*, %struct.head_s** %next4, align 4 %6 = load %struct.head_s*, %struct.head_s** %next4, align 4
%tobool = icmp ne %struct.head_s* %6, null %tobool = icmp ne %struct.head_s* %6, null
br i1 %tobool, label %return, label %land.rhs br i1 %tobool, label %return, label %land.rhs
land.rhs11: ; preds = %while.body19, %land.rhs11.lr.ph land.rhs11: ; preds = %while.body19, %land.rhs11.lr.ph
%list.addr.136 = phi %struct.head_s* [ %list, %land.rhs11.lr.ph ], [ %10, %while.body19 ] %list.addr.136 = phi %struct.head_s* [ %list, %land.rhs11.lr.ph ], [ %10, %while.body19 ]
%info12 = getelementptr inbounds %struct.head_s, %struct.head_s* %list.addr.136, i32 0, i32 1 %info12 = getelementptr inbounds %struct.head_s, %struct.head_s* %list.addr.136, i32 0, i32 1
%7 = load %struct.data_s*, %struct.data_s** %info12, align 4 %7 = load %struct.data_s*, %struct.data_s** %info12, align 4
%data165 = bitcast %struct.data_s* %7 to i16* %data165 = bitcast %struct.data_s* %7 to i16*
%8 = load i16, i16* %data165, align 2 %8 = load i16, i16* %data165, align 2
%9 = and i16 %8, 255 %9 = and i16 %8, 255
%and = zext i16 %9 to i32 %and = zext i16 %9 to i32
%cmp16 = icmp eq i32 %and, %conv15 %cmp16 = icmp eq i32 %and, %conv15
br i1 %cmp16, label %return, label %while.body19 br i1 %cmp16, label %return, label %while.body19
while.body19: ; preds = %land.rhs11 while.body19: ; preds = %land.rhs11
%next206 = bitcast %struct.head_s* %list.addr.136 to %struct.head_s** %next206 = bitcast %struct.head_s* %list.addr.136 to %struct.head_s**
%10 = load %struct.head_s*, %struct.head_s** %next206, align 4 %10 = load %struct.head_s*, %struct.head_s** %next206, align 4
%tobool10 = icmp eq %struct.head_s* %10, null %tobool10 = icmp eq %struct.head_s* %10, null
br i1 %tobool10, label %return, label %land.rhs11 br i1 %tobool10, label %return, label %land.rhs11
return: ; preds = %while.body19, %land.rhs11, %while.body, %land.rhs, %while.cond.preheader, %while.cond9.preheader return: ; preds = %while.body19, %land.rhs11, %while.body, %land.rhs, %while.cond.preheader, %while.cond9.preheader
%retval.0 = phi %struct.head_s* [ null, %while.cond.preheader ], [ null, %while.cond9.preheader ], [ %list.addr.033, %land.rhs ], [ null, %while.body ], [ %list.addr.136, %land.rhs11 ], [ null, %while.body19 ] %retval.0 = phi %struct.head_s* [ null, %while.cond.preheader ], [ null, %while.cond9.preheader ], [ %list.addr.033, %land.rhs ], [ null, %while.body ], [ %list.addr.136, %land.rhs11 ], [ null, %while.body19 ]
ret %struct.head_s* %retval.0 ret %struct.head_s* %retval.0
} }
attributes #0 = { norecurse nounwind readonly "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+hwdiv,+lob,+ras,+soft-float,+strict-align,+thumb-mode,-crypto,-d32,-dotprod,-fp-armv8,-fp-armv8d16,-fp-armv8d16sp,-fp-armv8sp,-fp16,-fp16fml,-fp64,-fpregs,-fullfp16,-neon,-vfp2,-vfp2d16,-vfp2d16sp,-vfp2sp,-vfp3,-vfp3d16,-vfp3d16sp,-vfp3sp,-vfp4,-vfp4d16,-vfp4d16sp,-vfp4sp" "unsafe-fp-math"="false" "use-soft-float"="true" } attributes #0 = { norecurse nounwind readonly "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+hwdiv,+lob,+ras,+soft-float,+strict-align,+thumb-mode,-crypto,-d32,-dotprod,-fp-armv8,-fp-armv8d16,-fp-armv8d16sp,-fp-armv8sp,-fp16,-fp16fml,-fp64,-fpregs,-fullfp16,-neon,-vfp2,-vfp2d16,-vfp2d16sp,-vfp2sp,-vfp3,-vfp3d16,-vfp3d16sp,-vfp3sp,-vfp4,-vfp4d16,-vfp4d16sp,-vfp4sp" "unsafe-fp-math"="false" "use-soft-float"="true" }
... ...
--- ---
name: search name: search
alignment: 1 alignment: 1
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 24 LinesframeInfo:
savePoint: '' savePoint: ''
restorePoint: '' restorePoint: ''
fixedStack: [] fixedStack: []
stack: [] stack: []
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LOB-LABEL: name: search
; CHECK-LOB: bb.0.entry:
; CHECK-LOB: successors: %bb.1(0x50000000), %bb.4(0x30000000)
; CHECK-LOB: liveins: $r0, $r1
; CHECK-LOB: renamable $r2 = t2LDRSHi12 renamable $r1, 2, 14 /* CC::al */, $noreg :: (load 2 from %ir.idx)
; CHECK-LOB: t2CMPri renamable $r2, -1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK-LOB: tBcc %bb.4, 13 /* CC::le */, killed $cpsr
; CHECK-LOB: bb.1.while.cond.preheader:
; CHECK-LOB: successors: %bb.8(0x30000000), %bb.2(0x50000000)
; CHECK-LOB: liveins: $r0, $r2
; CHECK-LOB: tCBZ $r0, %bb.8
; CHECK-LOB: bb.2.land.rhs.preheader:
; CHECK-LOB: successors: %bb.3(0x80000000)
; CHECK-LOB: liveins: $r0, $r2
; CHECK-LOB: renamable $r1 = tUXTH killed renamable $r2, 14 /* CC::al */, $noreg
; CHECK-LOB: bb.3.land.rhs:
; CHECK-LOB: successors: %bb.8(0x04000000), %bb.3(0x7c000000)
; CHECK-LOB: liveins: $r0, $r1
; CHECK-LOB: renamable $r2 = tLDRi renamable $r0, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.info2)
; CHECK-LOB: renamable $r2 = tLDRHi killed renamable $r2, 1, 14 /* CC::al */, $noreg :: (load 2 from %ir.idx3)
; CHECK-LOB: tCMPr killed renamable $r2, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK-LOB: t2IT 0, 8, implicit-def $itstate
; CHECK-LOB: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
; CHECK-LOB: renamable $r0 = tLDRi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.next4)
; CHECK-LOB: tCBNZ $r0, %bb.8
; CHECK-LOB: t2LE %bb.3
; CHECK-LOB: bb.4.while.cond9.preheader:
; CHECK-LOB: successors: %bb.8(0x30000000), %bb.5(0x50000000)
; CHECK-LOB: liveins: $r0, $r1
; CHECK-LOB: tCBZ $r0, %bb.8
; CHECK-LOB: bb.5.land.rhs11.lr.ph:
; CHECK-LOB: successors: %bb.6(0x80000000)
; CHECK-LOB: liveins: $r0, $r1
; CHECK-LOB: renamable $r1 = t2LDRSHi12 killed renamable $r1, 0, 14 /* CC::al */, $noreg :: (load 2 from %ir.data16143)
; CHECK-LOB: bb.6.land.rhs11:
; CHECK-LOB: successors: %bb.9(0x04000000), %bb.7(0x7c000000)
; CHECK-LOB: liveins: $r0, $r1
; CHECK-LOB: renamable $r2 = tLDRi renamable $r0, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.info12)
; CHECK-LOB: renamable $r2 = tLDRBi killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (load 1 from %ir.data165, align 2)
; CHECK-LOB: tCMPr killed renamable $r2, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK-LOB: tBcc %bb.9, 0 /* CC::eq */, killed $cpsr
; CHECK-LOB: bb.7.while.body19:
; CHECK-LOB: successors: %bb.8(0x04000000), %bb.6(0x7c000000)
; CHECK-LOB: liveins: $r0, $r1
; CHECK-LOB: renamable $r0 = tLDRi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.next206)
; CHECK-LOB: tCBZ $r0, %bb.8
; CHECK-LOB: t2LE %bb.6
; CHECK-LOB: bb.8:
; CHECK-LOB: successors: %bb.9(0x80000000)
; CHECK-LOB: renamable $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK-LOB: bb.9.return:
; CHECK-LOB: liveins: $r0
; CHECK-LOB: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0
; CHECK-NOLOB-LABEL: name: search
; CHECK-NOLOB: bb.0.entry:
; CHECK-NOLOB: successors: %bb.1(0x50000000), %bb.4(0x30000000)
; CHECK-NOLOB: liveins: $r0, $r1
; CHECK-NOLOB: renamable $r2 = t2LDRSHi12 renamable $r1, 2, 14 /* CC::al */, $noreg :: (load 2 from %ir.idx)
; CHECK-NOLOB: t2CMPri renamable $r2, -1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK-NOLOB: tBcc %bb.4, 13 /* CC::le */, killed $cpsr
; CHECK-NOLOB: bb.1.while.cond.preheader:
; CHECK-NOLOB: successors: %bb.8(0x30000000), %bb.2(0x50000000)
; CHECK-NOLOB: liveins: $r0, $r2
; CHECK-NOLOB: tCBZ $r0, %bb.8
; CHECK-NOLOB: bb.2.land.rhs.preheader:
; CHECK-NOLOB: successors: %bb.3(0x80000000)
; CHECK-NOLOB: liveins: $r0, $r2
; CHECK-NOLOB: renamable $r1 = tUXTH killed renamable $r2, 14 /* CC::al */, $noreg
; CHECK-NOLOB: bb.3.land.rhs:
; CHECK-NOLOB: successors: %bb.8(0x04000000), %bb.3(0x7c000000)
; CHECK-NOLOB: liveins: $r0, $r1
; CHECK-NOLOB: renamable $r2 = tLDRi renamable $r0, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.info2)
; CHECK-NOLOB: renamable $r2 = tLDRHi killed renamable $r2, 1, 14 /* CC::al */, $noreg :: (load 2 from %ir.idx3)
; CHECK-NOLOB: tCMPr killed renamable $r2, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK-NOLOB: t2IT 0, 8, implicit-def $itstate
; CHECK-NOLOB: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
; CHECK-NOLOB: renamable $r0 = tLDRi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.next4)
; CHECK-NOLOB: tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK-NOLOB: tBcc %bb.3, 0 /* CC::eq */, killed $cpsr
; CHECK-NOLOB: tB %bb.8, 14 /* CC::al */, $noreg
; CHECK-NOLOB: bb.4.while.cond9.preheader:
; CHECK-NOLOB: successors: %bb.8(0x30000000), %bb.5(0x50000000)
; CHECK-NOLOB: liveins: $r0, $r1
; CHECK-NOLOB: tCBZ $r0, %bb.8
; CHECK-NOLOB: bb.5.land.rhs11.lr.ph:
; CHECK-NOLOB: successors: %bb.6(0x80000000)
; CHECK-NOLOB: liveins: $r0, $r1
; CHECK-NOLOB: renamable $r1 = t2LDRSHi12 killed renamable $r1, 0, 14 /* CC::al */, $noreg :: (load 2 from %ir.data16143)
; CHECK-NOLOB: bb.6.land.rhs11:
; CHECK-NOLOB: successors: %bb.9(0x04000000), %bb.7(0x7c000000)
; CHECK-NOLOB: liveins: $r0, $r1
; CHECK-NOLOB: renamable $r2 = tLDRi renamable $r0, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.info12)
; CHECK-NOLOB: renamable $r2 = tLDRBi killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (load 1 from %ir.data165, align 2)
; CHECK-NOLOB: tCMPr killed renamable $r2, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK-NOLOB: tBcc %bb.9, 0 /* CC::eq */, killed $cpsr
; CHECK-NOLOB: bb.7.while.body19:
; CHECK-NOLOB: successors: %bb.8(0x04000000), %bb.6(0x7c000000)
; CHECK-NOLOB: liveins: $r0, $r1
; CHECK-NOLOB: renamable $r0 = tLDRi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.next206)
; CHECK-NOLOB: tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK-NOLOB: tBcc %bb.6, 1 /* CC::ne */, killed $cpsr
; CHECK-NOLOB: bb.8:
; CHECK-NOLOB: successors: %bb.9(0x80000000)
; CHECK-NOLOB: renamable $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK-NOLOB: bb.9.return:
; CHECK-NOLOB: liveins: $r0
; CHECK-NOLOB: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.5(0x50000000), %bb.1(0x30000000) successors: %bb.5(0x50000000), %bb.1(0x30000000)
liveins: $r0, $r1 liveins: $r0, $r1
renamable $r2 = t2LDRSHi12 renamable $r1, 2, 14, $noreg :: (load 2 from %ir.idx) renamable $r2 = t2LDRSHi12 renamable $r1, 2, 14, $noreg :: (load 2 from %ir.idx)
t2CMPri renamable $r2, -1, 14, $noreg, implicit-def $cpsr t2CMPri renamable $r2, -1, 14, $noreg, implicit-def $cpsr
t2Bcc %bb.1, 13, killed $cpsr t2Bcc %bb.1, 13, killed $cpsr
bb.5.while.cond.preheader: bb.5.while.cond.preheader:
successors: %bb.8(0x30000000), %bb.6(0x50000000) successors: %bb.8(0x30000000), %bb.6(0x50000000)
liveins: $r0, $r2 liveins: $r0, $r2
tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr
t2Bcc %bb.8, 0, killed $cpsr t2Bcc %bb.8, 0, killed $cpsr
bb.6.land.rhs.preheader: bb.6.land.rhs.preheader:
successors: %bb.7(0x80000000) successors: %bb.7(0x80000000)
liveins: $r0, $r2 liveins: $r0, $r2
renamable $r1 = tUXTH killed renamable $r2, 14, $noreg renamable $r1 = tUXTH killed renamable $r2, 14, $noreg
bb.7.land.rhs: bb.7.land.rhs:
successors: %bb.8(0x04000000), %bb.7(0x7c000000) successors: %bb.8(0x04000000), %bb.7(0x7c000000)
liveins: $r0, $r1 liveins: $r0, $r1
renamable $r2 = tLDRi renamable $r0, 1, 14, $noreg :: (load 4 from %ir.info2) renamable $r2 = tLDRi renamable $r0, 1, 14, $noreg :: (load 4 from %ir.info2)
renamable $r2 = tLDRHi killed renamable $r2, 1, 14, $noreg :: (load 2 from %ir.idx3) renamable $r2 = tLDRHi killed renamable $r2, 1, 14, $noreg :: (load 2 from %ir.idx3)
tCMPr killed renamable $r2, renamable $r1, 14, $noreg, implicit-def $cpsr tCMPr killed renamable $r2, renamable $r1, 14, $noreg, implicit-def $cpsr
t2IT 0, 8, implicit-def $itstate t2IT 0, 8, implicit-def $itstate
tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate
renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.next4) renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.next4)
tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr
t2Bcc %bb.7, 0, killed $cpsr t2Bcc %bb.7, 0, killed $cpsr
t2B %bb.8, 14, $noreg t2B %bb.8, 14, $noreg
bb.1.while.cond9.preheader: bb.1.while.cond9.preheader:
successors: %bb.8(0x30000000), %bb.2(0x50000000) successors: %bb.8(0x30000000), %bb.2(0x50000000)
liveins: $r0, $r1 liveins: $r0, $r1
tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr
t2Bcc %bb.8, 0, killed $cpsr t2Bcc %bb.8, 0, killed $cpsr
bb.2.land.rhs11.lr.ph: bb.2.land.rhs11.lr.ph:
successors: %bb.3(0x80000000) successors: %bb.3(0x80000000)
liveins: $r0, $r1 liveins: $r0, $r1
renamable $r1 = t2LDRSHi12 killed renamable $r1, 0, 14, $noreg :: (load 2 from %ir.data16143) renamable $r1 = t2LDRSHi12 killed renamable $r1, 0, 14, $noreg :: (load 2 from %ir.data16143)
bb.3.land.rhs11: bb.3.land.rhs11:
successors: %bb.9(0x04000000), %bb.4(0x7c000000) successors: %bb.9(0x04000000), %bb.4(0x7c000000)
liveins: $r0, $r1 liveins: $r0, $r1
renamable $r2 = tLDRi renamable $r0, 1, 14, $noreg :: (load 4 from %ir.info12) renamable $r2 = tLDRi renamable $r0, 1, 14, $noreg :: (load 4 from %ir.info12)
renamable $r2 = tLDRBi killed renamable $r2, 0, 14, $noreg :: (load 1 from %ir.data165, align 2) renamable $r2 = tLDRBi killed renamable $r2, 0, 14, $noreg :: (load 1 from %ir.data165, align 2)
tCMPr killed renamable $r2, renamable $r1, 14, $noreg, implicit-def $cpsr tCMPr killed renamable $r2, renamable $r1, 14, $noreg, implicit-def $cpsr
t2Bcc %bb.9, 0, killed $cpsr t2Bcc %bb.9, 0, killed $cpsr
bb.4.while.body19: bb.4.while.body19:
successors: %bb.8(0x04000000), %bb.3(0x7c000000) successors: %bb.8(0x04000000), %bb.3(0x7c000000)
liveins: $r0, $r1 liveins: $r0, $r1
renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.next206) renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.next206)
tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr
t2Bcc %bb.3, 1, killed $cpsr t2Bcc %bb.3, 1, killed $cpsr
bb.8: bb.8:
successors: %bb.9(0x80000000) successors: %bb.9(0x80000000)
renamable $r0, dead $cpsr = tMOVi8 0, 14, $noreg renamable $r0, dead $cpsr = tMOVi8 0, 14, $noreg
bb.9.return: bb.9.return:
liveins: $r0 liveins: $r0
tBX_RET 14, $noreg, implicit killed $r0 tBX_RET 14, $noreg, implicit killed $r0
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-vpsel-liveout.mir

Show First 20 Lines • Show All 98 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: no_vpsel_liveout ; CHECK-LABEL: name: no_vpsel_liveout
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
; CHECK: tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 0, 4, implicit-def $itstate ; CHECK: t2IT 0, 4, implicit-def $itstate
; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
; CHECK: tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: dead $lr = t2DLS renamable $r12 ; CHECK: dead $lr = t2DLS renamable $r12
; CHECK: $r3 = tMOVr killed $r12, 14, $noreg ; CHECK: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg
; CHECK: bb.1.vector.body: ; CHECK: bb.1.vector.body:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $q0, $r0, $r1, $r2, $r3 ; CHECK: liveins: $q0, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2)
; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2) ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2)
; CHECK: $lr = tMOVr $r3, 14, $noreg ; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.1 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.1
; CHECK: bb.2.middle.block: ; CHECK: bb.2.middle.block:
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $lr, $r7 liveins: $r0, $r1, $r2, $lr, $r7
tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr
t2IT 0, 4, implicit-def $itstate t2IT 0, 4, implicit-def $itstate
renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate
tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate
Show All 37 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-load.mir

Show First 20 Lines • Show All 103 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: non_masked_load ; CHECK-LABEL: name: non_masked_load
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: liveins: $lr, $r0, $r1, $r2
; CHECK: tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 0, 2, implicit-def $itstate ; CHECK: t2IT 0, 2, implicit-def $itstate
; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
; CHECK: renamable $r0 = tUXTB killed renamable $r0, 0, $cpsr, implicit killed $r0, implicit $itstate ; CHECK: renamable $r0 = tUXTB killed renamable $r0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
; CHECK: tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
; CHECK: frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: dead $r7 = frame-setup tMOVr $sp, 14, $noreg ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
; CHECK: renamable $r3 = t2ADDri renamable $r2, 15, 14, $noreg, $noreg ; CHECK: renamable $r3 = t2ADDri renamable $r2, 15, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 15, 14, $noreg, $noreg ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 15, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 16, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 16, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, renamable $r12, 35, 14, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, renamable $r12, 35, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3 = t2LSRri killed renamable $r12, 4, 14, $noreg, $noreg ; CHECK: renamable $r3 = t2LSRri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r3, 34, 14, $noreg, $noreg ; CHECK: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r3, 34, 14 /* CC::al */, $noreg, $noreg
; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: $lr = t2DLS killed renamable $lr
; CHECK: bb.1.vector.body: ; CHECK: bb.1.vector.body:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg
; CHECK: $q1 = MVE_VORR killed $q0, killed $q0, 0, $noreg, undef $q1 ; CHECK: $q1 = MVE_VORR killed $q0, killed $q0, 0, $noreg, undef $q1
; CHECK: MVE_VPST 2, implicit $vpr ; CHECK: MVE_VPST 2, implicit $vpr
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv2022, align 1) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv2022, align 1)
; CHECK: renamable $r0, renamable $q2 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, $noreg :: (load 16 from %ir.lsr.iv19, align 1) ; CHECK: renamable $r0, renamable $q2 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, $noreg :: (load 16 from %ir.lsr.iv19, align 1)
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
; CHECK: renamable $q2 = MVE_VADDi8 killed renamable $q2, renamable $q1, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VADDi8 killed renamable $q2, renamable $q1, 0, $noreg, undef renamable $q2
; CHECK: renamable $q0 = MVE_VADDi8 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VADDi8 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1
; CHECK: bb.2.middle.block: ; CHECK: bb.2.middle.block:
; CHECK: liveins: $q0, $q1, $r3 ; CHECK: liveins: $q0, $q1, $r3
; CHECK: renamable $vpr = MVE_VCTP8 killed renamable $r3, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP8 killed renamable $r3, 0, $noreg
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr
; CHECK: renamable $r0 = MVE_VADDVu8no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r0 = MVE_VADDVu8no_acc killed renamable $q0, 0, $noreg
; CHECK: $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r7, def $lr ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr
; CHECK: renamable $r0 = tUXTB killed renamable $r0, 14, $noreg ; CHECK: renamable $r0 = tUXTB killed renamable $r0, 14 /* CC::al */, $noreg
; CHECK: tBX_RET 14, $noreg, implicit killed $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $lr liveins: $r0, $r1, $r2, $lr
tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr
t2IT 0, 2, implicit-def $itstate t2IT 0, 2, implicit-def $itstate
renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate
renamable $r0 = tUXTB killed renamable $r0, 0, $cpsr, implicit killed $r0, implicit $itstate renamable $r0 = tUXTB killed renamable $r0, 0, $cpsr, implicit killed $r0, implicit $itstate
▲ Show 20 Lines • Show All 44 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-store.mir

Show First 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: non_masked_store ; CHECK-LABEL: name: non_masked_store
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
; CHECK: frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: dead $r7 = frame-setup tMOVr $sp, 14, $noreg ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
; CHECK: tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 0, 8, implicit-def $itstate ; CHECK: t2IT 0, 8, implicit-def $itstate
; CHECK: tPOP_RET 0, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
; CHECK: renamable $r12 = t2ADDri renamable $r3, 15, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2ADDri renamable $r3, 15, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $lr = t2MOVi 1, 14, $noreg, $noreg ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2BICri killed renamable $r12, 15, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 15, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 16, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 16, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 35, 14, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 35, 14 /* CC::al */, $noreg, $noreg
; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: $lr = t2DLS killed renamable $lr
; CHECK: bb.1.vector.body: ; CHECK: bb.1.vector.body:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg
; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv15, align 1) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv15, align 1)
; CHECK: renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv1618, align 1) ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv1618, align 1)
; CHECK: renamable $q0 = MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, $noreg :: (store 16 into %ir.lsr.iv1921, align 1) ; CHECK: renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, $noreg :: (store 16 into %ir.lsr.iv1921, align 1)
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1
; CHECK: bb.2.for.cond.cleanup: ; CHECK: bb.2.for.cond.cleanup:
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $lr liveins: $r0, $r1, $r2, $r3, $lr
frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
Show All 31 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/out-of-range-cbz.mir

Show First 20 Lines • Show All 156 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: f ; CHECK-LABEL: name: f
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.5(0x30000000), %bb.1(0x50000000) ; CHECK: successors: %bb.5(0x30000000), %bb.1(0x50000000)
; CHECK: liveins: $r0, $r1, $r7, $lr ; CHECK: liveins: $r0, $r1, $r7, $lr
; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: dead renamable $r1, $cpsr = tORR killed renamable $r1, renamable $r0, 14, $noreg ; CHECK: dead renamable $r1, $cpsr = tORR killed renamable $r1, renamable $r0, 14 /* CC::al */, $noreg
; CHECK: tBcc %bb.5, 0, killed $cpsr ; CHECK: tBcc %bb.5, 0 /* CC::eq */, killed $cpsr
; CHECK: bb.1.entry.split: ; CHECK: bb.1.entry.split:
; CHECK: successors: %bb.15(0x30000000), %bb.2(0x50000000) ; CHECK: successors: %bb.15(0x30000000), %bb.2(0x50000000)
; CHECK: liveins: $r0 ; CHECK: liveins: $r0
; CHECK: tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.15, 0, killed $cpsr ; CHECK: tBcc %bb.15, 0 /* CC::eq */, killed $cpsr
; CHECK: bb.2.j.preheader: ; CHECK: bb.2.j.preheader:
; CHECK: successors: %bb.3(0x80000000) ; CHECK: successors: %bb.3(0x80000000)
; CHECK: liveins: $r0 ; CHECK: liveins: $r0
; CHECK: $r1 = t2MOVi16 target-flags(arm-lo16) @a, 14, $noreg ; CHECK: $r1 = t2MOVi16 target-flags(arm-lo16) @a, 14 /* CC::al */, $noreg
; CHECK: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @a, 14, $noreg ; CHECK: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @a, 14 /* CC::al */, $noreg
; CHECK: tCMPr killed renamable $r0, killed renamable $r1, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPr killed renamable $r0, killed renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: $r1 = t2MOVi16 target-flags(arm-lo16) @d, 14, $noreg ; CHECK: $r1 = t2MOVi16 target-flags(arm-lo16) @d, 14 /* CC::al */, $noreg
; CHECK: renamable $r0 = t2CSINC $zr, $zr, 10, implicit killed $cpsr ; CHECK: renamable $r0 = t2CSINC $zr, $zr, 10, implicit killed $cpsr
; CHECK: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @d, 14, $noreg ; CHECK: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @d, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = tLDRi killed renamable $r1, 0, 14, $noreg :: (dereferenceable load 4 from @d) ; CHECK: renamable $r2 = tLDRi killed renamable $r1, 0, 14 /* CC::al */, $noreg :: (dereferenceable load 4 from @d)
; CHECK: $r1 = t2MOVi16 target-flags(arm-lo16) @e, 14, $noreg ; CHECK: $r1 = t2MOVi16 target-flags(arm-lo16) @e, 14 /* CC::al */, $noreg
; CHECK: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @e, 14, $noreg ; CHECK: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @e, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = tLDRi renamable $r1, 0, 14, $noreg :: (dereferenceable load 4 from @e) ; CHECK: renamable $r3 = tLDRi renamable $r1, 0, 14 /* CC::al */, $noreg :: (dereferenceable load 4 from @e)
; CHECK: bb.3.j (align 4): ; CHECK: bb.3.j (align 4):
; CHECK: successors: %bb.4(0x04000000), %bb.3(0x7c000000) ; CHECK: successors: %bb.4(0x04000000), %bb.3(0x7c000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: renamable $r3, dead $cpsr = tAND killed renamable $r3, renamable $r0, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tAND killed renamable $r3, renamable $r0, 14 /* CC::al */, $noreg
; CHECK: tCBZ $r2, %bb.4 ; CHECK: tCBZ $r2, %bb.4
; CHECK: t2LE %bb.3
; CHECK: bb.4.if.end: ; CHECK: bb.4.if.end:
; CHECK: liveins: $r1, $r3 ; CHECK: liveins: $r1, $r3
; CHECK: tSTRi killed renamable $r3, killed renamable $r1, 0, 14, $noreg :: (store 4 into @e) ; CHECK: tSTRi killed renamable $r3, killed renamable $r1, 0, 14 /* CC::al */, $noreg :: (store 4 into @e)
; CHECK: INLINEASM &"", 1 ; CHECK: INLINEASM &"", 1
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
; CHECK: bb.5.j.us.us.preheader: ; CHECK: bb.5.j.us.us.preheader:
; CHECK: successors: %bb.6(0x80000000) ; CHECK: successors: %bb.6(0x80000000)
; CHECK: $r12 = t2MOVi16 target-flags(arm-lo16) @d, 14, $noreg ; CHECK: $r12 = t2MOVi16 target-flags(arm-lo16) @d, 14 /* CC::al */, $noreg
; CHECK: $lr = t2MOVi16 target-flags(arm-lo16) @a, 14, $noreg ; CHECK: $lr = t2MOVi16 target-flags(arm-lo16) @a, 14 /* CC::al */, $noreg
; CHECK: $r12 = t2MOVTi16 killed $r12, target-flags(arm-hi16) @d, 14, $noreg ; CHECK: $r12 = t2MOVTi16 killed $r12, target-flags(arm-hi16) @d, 14 /* CC::al */, $noreg
; CHECK: $r2 = t2MOVi16 target-flags(arm-lo16) @e, 14, $noreg ; CHECK: $r2 = t2MOVi16 target-flags(arm-lo16) @e, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load 4 from @d) ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load 4 from @d)
; CHECK: $lr = t2MOVTi16 killed $lr, target-flags(arm-hi16) @a, 14, $noreg ; CHECK: $lr = t2MOVTi16 killed $lr, target-flags(arm-hi16) @a, 14 /* CC::al */, $noreg
; CHECK: $r2 = t2MOVTi16 killed $r2, target-flags(arm-hi16) @e, 14, $noreg ; CHECK: $r2 = t2MOVTi16 killed $r2, target-flags(arm-hi16) @e, 14 /* CC::al */, $noreg
; CHECK: bb.6.j.us.us (align 4): ; CHECK: bb.6.j.us.us (align 4):
; CHECK: successors: %bb.7(0x40000000), %bb.6(0x40000000) ; CHECK: successors: %bb.7(0x40000000), %bb.6(0x40000000)
; CHECK: liveins: $lr, $r2, $r3, $r12 ; CHECK: liveins: $lr, $r2, $r3, $r12
; CHECK: tCMPhir renamable $r3, renamable $lr, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPhir renamable $r3, renamable $lr, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: renamable $r1 = tLDRi renamable $r2, 0, 14, $noreg :: (dereferenceable load 4 from @e) ; CHECK: renamable $r1 = tLDRi renamable $r2, 0, 14 /* CC::al */, $noreg :: (dereferenceable load 4 from @e)
; CHECK: renamable $r0 = t2CSINC $zr, $zr, 10, implicit killed $cpsr ; CHECK: renamable $r0 = t2CSINC $zr, $zr, 10, implicit killed $cpsr
; CHECK: renamable $r0 = t2ANDrr killed renamable $r0, killed renamable $r1, 14, $noreg, $noreg ; CHECK: renamable $r0 = t2ANDrr killed renamable $r0, killed renamable $r1, 14 /* CC::al */, $noreg, $noreg
; CHECK: tSTRi killed renamable $r0, renamable $r2, 0, 14, $noreg :: (store 4 into @e) ; CHECK: tSTRi killed renamable $r0, renamable $r2, 0, 14 /* CC::al */, $noreg :: (store 4 into @e)
; CHECK: tCBZ $r3, %bb.7 ; CHECK: tCBZ $r3, %bb.7
; CHECK: t2LE %bb.6
; CHECK: bb.7.if.end.us.us.us: ; CHECK: bb.7.if.end.us.us.us:
; CHECK: successors: %bb.8(0x40000000), %bb.6(0x40000000) ; CHECK: successors: %bb.8(0x40000000), %bb.6(0x40000000)
; CHECK: liveins: $lr, $r2, $r12 ; CHECK: liveins: $lr, $r2, $r12
; CHECK: INLINEASM &"", 1 ; CHECK: INLINEASM &"", 1
; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load 4 from @d) ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load 4 from @d)
; CHECK: tCBZ $r3, %bb.8 ; CHECK: tCBZ $r3, %bb.8
; CHECK: t2LE %bb.6
; CHECK: bb.8.if.end.us.us.us.1: ; CHECK: bb.8.if.end.us.us.us.1:
; CHECK: successors: %bb.9(0x40000000), %bb.6(0x40000000) ; CHECK: successors: %bb.9(0x40000000), %bb.6(0x40000000)
; CHECK: liveins: $lr, $r2, $r12 ; CHECK: liveins: $lr, $r2, $r12
; CHECK: INLINEASM &"", 1 ; CHECK: INLINEASM &"", 1
; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load 4 from @d) ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load 4 from @d)
; CHECK: tCBZ $r3, %bb.9 ; CHECK: tCBZ $r3, %bb.9
; CHECK: t2LE %bb.6
; CHECK: bb.9.if.end.us.us.us.2: ; CHECK: bb.9.if.end.us.us.us.2:
; CHECK: successors: %bb.10(0x40000000), %bb.6(0x40000000) ; CHECK: successors: %bb.10(0x40000000), %bb.6(0x40000000)
; CHECK: liveins: $lr, $r2, $r12 ; CHECK: liveins: $lr, $r2, $r12
; CHECK: INLINEASM &"", 1 ; CHECK: INLINEASM &"", 1
; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load 4 from @d) ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load 4 from @d)
; CHECK: tCBZ $r3, %bb.10 ; CHECK: tCBZ $r3, %bb.10
; CHECK: t2LE %bb.6
; CHECK: bb.10.if.end.us.us.us.3: ; CHECK: bb.10.if.end.us.us.us.3:
; CHECK: successors: %bb.11(0x40000000), %bb.6(0x40000000) ; CHECK: successors: %bb.11(0x40000000), %bb.6(0x40000000)
; CHECK: liveins: $lr, $r2, $r12 ; CHECK: liveins: $lr, $r2, $r12
; CHECK: INLINEASM &"", 1 ; CHECK: INLINEASM &"", 1
; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load 4 from @d) ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load 4 from @d)
; CHECK: tCBZ $r3, %bb.11 ; CHECK: tCBZ $r3, %bb.11
; CHECK: t2LE %bb.6
; CHECK: bb.11.if.end.us.us.us.4: ; CHECK: bb.11.if.end.us.us.us.4:
; CHECK: successors: %bb.12(0x40000000), %bb.6(0x40000000) ; CHECK: successors: %bb.12(0x40000000), %bb.6(0x40000000)
; CHECK: liveins: $lr, $r2, $r12 ; CHECK: liveins: $lr, $r2, $r12
; CHECK: INLINEASM &"", 1 ; CHECK: INLINEASM &"", 1
; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load 4 from @d) ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load 4 from @d)
; CHECK: tCBZ $r3, %bb.12 ; CHECK: tCBZ $r3, %bb.12
; CHECK: t2LE %bb.6
; CHECK: bb.12.if.end.us.us.us.5: ; CHECK: bb.12.if.end.us.us.us.5:
; CHECK: successors: %bb.13(0x40000000), %bb.6(0x40000000) ; CHECK: successors: %bb.13(0x40000000), %bb.6(0x40000000)
; CHECK: liveins: $lr, $r2, $r12 ; CHECK: liveins: $lr, $r2, $r12
; CHECK: INLINEASM &"", 1 ; CHECK: INLINEASM &"", 1
; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load 4 from @d) ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load 4 from @d)
; CHECK: tCBZ $r3, %bb.13 ; CHECK: tCBZ $r3, %bb.13
; CHECK: t2LE %bb.6
; CHECK: bb.13.if.end.us.us.us.6: ; CHECK: bb.13.if.end.us.us.us.6:
; CHECK: successors: %bb.14(0x04000000), %bb.6(0x7c000000) ; CHECK: successors: %bb.14(0x04000000), %bb.6(0x7c000000)
; CHECK: liveins: $lr, $r2, $r12 ; CHECK: liveins: $lr, $r2, $r12
; CHECK: INLINEASM &"", 1 ; CHECK: INLINEASM &"", 1
; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load 4 from @d) ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load 4 from @d)
; CHECK: tCBZ $r3, %bb.14 ; CHECK: tCBZ $r3, %bb.14
; CHECK: t2LE %bb.6
; CHECK: bb.14.if.end.us.us.us.7: ; CHECK: bb.14.if.end.us.us.us.7:
; CHECK: INLINEASM &"", 1 ; CHECK: INLINEASM &"", 1
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
; CHECK: bb.15.j.us27.preheader: ; CHECK: bb.15.j.us27.preheader:
; CHECK: successors: %bb.16(0x80000000) ; CHECK: successors: %bb.16(0x80000000)
; CHECK: $r0 = t2MOVi16 target-flags(arm-lo16) @d, 14, $noreg ; CHECK: $r0 = t2MOVi16 target-flags(arm-lo16) @d, 14 /* CC::al */, $noreg
; CHECK: $r1 = t2MOVi16 target-flags(arm-lo16) @a, 14, $noreg ; CHECK: $r1 = t2MOVi16 target-flags(arm-lo16) @a, 14 /* CC::al */, $noreg
; CHECK: $r0 = t2MOVTi16 killed $r0, target-flags(arm-hi16) @d, 14, $noreg ; CHECK: $r0 = t2MOVTi16 killed $r0, target-flags(arm-hi16) @d, 14 /* CC::al */, $noreg
; CHECK: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @a, 14, $noreg ; CHECK: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @a, 14 /* CC::al */, $noreg
; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (dereferenceable load 4 from @d) ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (dereferenceable load 4 from @d)
; CHECK: tCMPr renamable $r0, killed renamable $r1, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPr renamable $r0, killed renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: $r1 = t2MOVi16 target-flags(arm-lo16) @e, 14, $noreg ; CHECK: $r1 = t2MOVi16 target-flags(arm-lo16) @e, 14 /* CC::al */, $noreg
; CHECK: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @e, 14, $noreg ; CHECK: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @e, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = t2CSINC $zr, $zr, 10, implicit killed $cpsr ; CHECK: renamable $r2 = t2CSINC $zr, $zr, 10, implicit killed $cpsr
; CHECK: renamable $r3 = tLDRi renamable $r1, 0, 14, $noreg :: (dereferenceable load 4 from @e) ; CHECK: renamable $r3 = tLDRi renamable $r1, 0, 14 /* CC::al */, $noreg :: (dereferenceable load 4 from @e)
; CHECK: bb.16.j.us27 (align 4): ; CHECK: bb.16.j.us27 (align 4):
; CHECK: successors: %bb.17(0x04000000), %bb.16(0x7c000000) ; CHECK: successors: %bb.17(0x04000000), %bb.16(0x7c000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: renamable $r3, dead $cpsr = tAND killed renamable $r3, renamable $r2, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tAND killed renamable $r3, renamable $r2, 14 /* CC::al */, $noreg
; CHECK: tCBZ $r0, %bb.17 ; CHECK: tCBZ $r0, %bb.17
; CHECK: t2LE %bb.16
; CHECK: bb.17.if.end.us38: ; CHECK: bb.17.if.end.us38:
; CHECK: liveins: $r1, $r3 ; CHECK: liveins: $r1, $r3
; CHECK: tSTRi killed renamable $r3, killed renamable $r1, 0, 14, $noreg :: (store 4 into @e) ; CHECK: tSTRi killed renamable $r3, killed renamable $r1, 0, 14 /* CC::al */, $noreg :: (store 4 into @e)
; CHECK: INLINEASM &"", 1 ; CHECK: INLINEASM &"", 1
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x30000000), %bb.11(0x50000000) successors: %bb.1(0x30000000), %bb.11(0x50000000)
liveins: $r0, $r1, $r7, $lr liveins: $r0, $r1, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
▲ Show 20 Lines • Show All 160 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-liveout.mir

Show First 20 Lines • Show All 74 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: predicated_livout ; CHECK-LABEL: name: predicated_livout
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x40000000), %bb.4(0x40000000) ; CHECK: successors: %bb.1(0x40000000), %bb.4(0x40000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
; CHECK: frame-setup tPUSH 14, $noreg, $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: $lr = MVE_WLSTP_16 killed renamable $r2, %bb.4 ; CHECK: $lr = MVE_WLSTP_16 killed renamable $r2, %bb.4
; CHECK: bb.1.for.body.preheader: ; CHECK: bb.1.for.body.preheader:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $lr, $r0, $r1 ; CHECK: liveins: $lr, $r0, $r1
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: bb.2.for.body: ; CHECK: bb.2.for.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1, $r3 ; CHECK: liveins: $lr, $q0, $r0, $r1, $r3
; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed $r3, 1, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r1, renamable $q1 = MVE_VLDRBU16_post killed renamable $r1, 8, 0, $noreg :: (load 8 from %ir.input_2_cast, align 1) ; CHECK: renamable $r1, renamable $q1 = MVE_VLDRBU16_post killed renamable $r1, 8, 0, $noreg :: (load 8 from %ir.input_2_cast, align 1)
; CHECK: renamable $r0, renamable $q2 = MVE_VLDRBU16_post killed renamable $r0, 8, 0, $noreg :: (load 8 from %ir.input_1_cast, align 1) ; CHECK: renamable $r0, renamable $q2 = MVE_VLDRBU16_post killed renamable $r0, 8, 0, $noreg :: (load 8 from %ir.input_1_cast, align 1)
; CHECK: renamable $q1 = MVE_VADDi16 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VADDi16 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
; CHECK: renamable $q0 = MVE_VADDi16 killed renamable $q1, killed renamable $q0, 0, killed $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VADDi16 killed renamable $q1, killed renamable $q0, 0, killed $noreg, undef renamable $q0
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.middle.block: ; CHECK: bb.3.middle.block:
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK: renamable $r0 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r0 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
; CHECK: bb.4.for.cond.cleanup: ; CHECK: bb.4.for.cond.cleanup:
; CHECK: liveins: $lr, $r7 ; CHECK: liveins: $lr, $r7
; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: tBX_RET 14, $noreg, implicit killed $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x40000000), %bb.4(0x40000000) successors: %bb.1(0x40000000), %bb.4(0x40000000)
liveins: $r0, $r1, $r2, $lr, $r7 liveins: $r0, $r1, $r2, $lr, $r7
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
▲ Show 20 Lines • Show All 41 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir

Show First 20 Lines • Show All 138 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: remove_mov_lr_chain ; CHECK-LABEL: name: remove_mov_lr_chain
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.9(0x30000000), %bb.1(0x50000000) ; CHECK: successors: %bb.9(0x30000000), %bb.1(0x50000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r4, $r5, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4, $r5, $r7
; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16
; CHECK: tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.9, 0, killed $cpsr ; CHECK: tBcc %bb.9, 0 /* CC::eq */, killed $cpsr
; CHECK: bb.1.while.body.preheader: ; CHECK: bb.1.while.body.preheader:
; CHECK: successors: %bb.6(0x40000000), %bb.2(0x40000000) ; CHECK: successors: %bb.6(0x40000000), %bb.2(0x40000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: tCMPi8 renamable $r2, 4, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r2, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.6, 3, killed $cpsr ; CHECK: tBcc %bb.6, 3 /* CC::lo */, killed $cpsr
; CHECK: bb.2.vector.memcheck: ; CHECK: bb.2.vector.memcheck:
; CHECK: successors: %bb.3(0x40000000), %bb.6(0x40000000) ; CHECK: successors: %bb.3(0x40000000), %bb.6(0x40000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: renamable $r3 = t2ADDrs renamable $r0, renamable $r2, 18, 14, $noreg, $noreg ; CHECK: renamable $r3 = t2ADDrs renamable $r0, renamable $r2, 18, 14 /* CC::al */, $noreg, $noreg
; CHECK: tCMPr killed renamable $r3, renamable $r1, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPr killed renamable $r3, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 8, 4, implicit-def $itstate ; CHECK: t2IT 8, 4, implicit-def $itstate
; CHECK: renamable $r3 = t2ADDrs renamable $r1, renamable $r2, 18, 8, $cpsr, $noreg, implicit $itstate ; CHECK: renamable $r3 = t2ADDrs renamable $r1, renamable $r2, 18, 8 /* CC::hi */, $cpsr, $noreg, implicit $itstate
; CHECK: tCMPr killed renamable $r3, renamable $r0, 8, killed $cpsr, implicit-def $cpsr, implicit killed $itstate ; CHECK: tCMPr killed renamable $r3, renamable $r0, 8 /* CC::hi */, killed $cpsr, implicit-def $cpsr, implicit killed $itstate
; CHECK: tBcc %bb.6, 8, killed $cpsr ; CHECK: tBcc %bb.6, 8 /* CC::hi */, killed $cpsr
; CHECK: bb.3.vector.ph: ; CHECK: bb.3.vector.ph:
; CHECK: successors: %bb.4(0x80000000) ; CHECK: successors: %bb.4(0x80000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: renamable $r4 = t2BICri renamable $r2, 3, 14, $noreg, $noreg ; CHECK: renamable $r4 = t2BICri renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = t2SUBri renamable $r4, 4, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri renamable $r4, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r7, dead $cpsr = tSUBrr renamable $r2, renamable $r4, 14, $noreg ; CHECK: renamable $r7, dead $cpsr = tSUBrr renamable $r2, renamable $r4, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2ADDrs renamable $r0, renamable $r4, 18, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2ADDrs renamable $r0, renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 16, 14, $noreg ; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
; CHECK: $r5 = tMOVr killed $r3, 14, $noreg ; CHECK: $r5 = tMOVr killed $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = t2ADDrs renamable $r1, renamable $r4, 18, 14, $noreg, $noreg ; CHECK: renamable $r3 = t2ADDrs renamable $r1, renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14, $noreg ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg
; CHECK: bb.4.vector.body: ; CHECK: bb.4.vector.body:
; CHECK: successors: %bb.4(0x7c000000), %bb.5(0x04000000) ; CHECK: successors: %bb.4(0x7c000000), %bb.5(0x04000000)
; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $r12 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $r12
; CHECK: renamable $r0, renamable $q0 = MVE_VLDRWU32_pre killed renamable $r0, 16, 0, $noreg :: (load 16 from %ir.scevgep18, align 4) ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRWU32_pre killed renamable $r0, 16, 0, $noreg :: (load 16 from %ir.scevgep18, align 4)
; CHECK: $lr = tMOVr killed $r5, 14, $noreg ; CHECK: $lr = tMOVr killed $r5, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VABSf32 killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VABSf32 killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: renamable $r1 = MVE_VSTRBU8_pre killed renamable $q0, killed renamable $r1, 16, 0, $noreg :: (store 16 into %ir.scevgep13, align 4) ; CHECK: renamable $r1 = MVE_VSTRBU8_pre killed renamable $q0, killed renamable $r1, 16, 0, $noreg :: (store 16 into %ir.scevgep13, align 4)
; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14, $noreg, def $cpsr ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
; CHECK: $r5 = tMOVr killed $lr, 14, $noreg ; CHECK: $r5 = tMOVr killed $lr, 14 /* CC::al */, $noreg
; CHECK: tBcc %bb.4, 1, killed $cpsr ; CHECK: tBcc %bb.4, 1 /* CC::ne */, killed $cpsr
; CHECK: tB %bb.5, 14, $noreg ; CHECK: tB %bb.5, 14 /* CC::al */, $noreg
; CHECK: bb.5.middle.block: ; CHECK: bb.5.middle.block:
; CHECK: successors: %bb.7(0x80000000) ; CHECK: successors: %bb.7(0x80000000)
; CHECK: liveins: $r2, $r3, $r4, $r7, $r12 ; CHECK: liveins: $r2, $r3, $r4, $r7, $r12
; CHECK: tCMPr killed renamable $r4, killed renamable $r2, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPr killed renamable $r4, killed renamable $r2, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: $lr = tMOVr killed $r7, 14, $noreg ; CHECK: $lr = tMOVr killed $r7, 14 /* CC::al */, $noreg
; CHECK: t2IT 0, 8, implicit-def $itstate ; CHECK: t2IT 0, 8, implicit-def $itstate
; CHECK: tPOP_RET 0, killed $cpsr, def $r4, def $r5, def $r7, def $pc, implicit killed $itstate ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $r5, def $r7, def $pc, implicit killed $itstate
; CHECK: tB %bb.7, 14, $noreg ; CHECK: tB %bb.7, 14 /* CC::al */, $noreg
; CHECK: bb.6: ; CHECK: bb.6:
; CHECK: successors: %bb.7(0x80000000) ; CHECK: successors: %bb.7(0x80000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: $lr = tMOVr killed $r2, 14, $noreg ; CHECK: $lr = tMOVr killed $r2, 14 /* CC::al */, $noreg
; CHECK: $r12 = tMOVr killed $r0, 14, $noreg ; CHECK: $r12 = tMOVr killed $r0, 14 /* CC::al */, $noreg
; CHECK: $r3 = tMOVr killed $r1, 14, $noreg ; CHECK: $r3 = tMOVr killed $r1, 14 /* CC::al */, $noreg
; CHECK: bb.7.while.body.preheader19: ; CHECK: bb.7.while.body.preheader19:
; CHECK: successors: %bb.8(0x80000000) ; CHECK: successors: %bb.8(0x80000000)
; CHECK: liveins: $lr, $r3, $r12 ; CHECK: liveins: $lr, $r3, $r12
; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r3, 4, 14, $noreg ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r3, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r1 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg ; CHECK: renamable $r1 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: $lr = t2DLS killed renamable $lr
; CHECK: bb.8.while.body: ; CHECK: bb.8.while.body:
; CHECK: successors: %bb.8(0x7c000000), %bb.9(0x04000000) ; CHECK: successors: %bb.8(0x7c000000), %bb.9(0x04000000)
; CHECK: liveins: $lr, $r0, $r1 ; CHECK: liveins: $lr, $r0, $r1
; CHECK: renamable $s0 = VLDRS renamable $r1, 1, 14, $noreg :: (load 4 from %ir.scevgep3) ; CHECK: renamable $s0 = VLDRS renamable $r1, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep3)
; CHECK: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 4, 14, $noreg ; CHECK: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VABSS killed renamable $s0, 14, $noreg ; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VABSS killed renamable $s0, 14 /* CC::al */, $noreg
; CHECK: VSTRS killed renamable $s0, renamable $r0, 1, 14, $noreg :: (store 4 into %ir.scevgep7) ; CHECK: VSTRS killed renamable $s0, renamable $r0, 1, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep7)
; CHECK: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14, $noreg ; CHECK: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.8 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.8
; CHECK: bb.9.while.end: ; CHECK: bb.9.while.end:
; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.9(0x30000000), %bb.1(0x50000000) successors: %bb.9(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r4, $r5, $r7, $lr liveins: $r0, $r1, $r2, $r4, $r5, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 16 frame-setup CFI_INSTRUCTION def_cfa_offset 16
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
▲ Show 20 Lines • Show All 95 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir

# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s
# CHECK-NOT: t2DLS # CHECK-NOT: t2DLS
# CHECK: bb.5.for.inc16: # CHECK: bb.5.for.inc16:
# CHECK: $lr = t2SUBri killed renamable $lr, 1, 14, $noreg, def $cpsr # CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
# CHECK-NOT: t2CMPri $lr # CHECK-NOT: t2CMPri $lr
# CHECK: tBcc %bb.6, 1 # CHECK: tBcc %bb.6, 1 /* CC::ne */
# CHECK: tB %bb.2 # CHECK: tB %bb.2
# CHECK: bb.6.for.cond4.preheader: # CHECK: bb.6.for.cond4.preheader:
--- | --- |
; ModuleID = 'revert-non-header.ll' ; ModuleID = 'revert-non-header.ll'
source_filename = "revert-non-header.ll" source_filename = "revert-non-header.ll"
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv8.1m.main" target triple = "thumbv8.1m.main"
▲ Show 20 Lines • Show All 255 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir

Show First 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: ne_trip_count ; CHECK-LABEL: name: ne_trip_count
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000) ; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000)
; CHECK: liveins: $lr, $r1, $r2, $r3, $r7 ; CHECK: liveins: $lr, $r1, $r2, $r3, $r7
; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: t2CMPri $r3, 0, 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPri $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2Bcc %bb.3, 0, killed $cpsr ; CHECK: t2Bcc %bb.3, 0 /* CC::eq */, killed $cpsr
; CHECK: tB %bb.1, 14, $noreg ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
; CHECK: bb.1.do.body.preheader: ; CHECK: bb.1.do.body.preheader:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r1, $r2, $r3 ; CHECK: liveins: $r1, $r2, $r3
; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14, $noreg ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
; CHECK: $lr = tMOVr killed $r3, 14, $noreg ; CHECK: $lr = tMOVr killed $r3, 14 /* CC::al */, $noreg
; CHECK: bb.2.do.body: ; CHECK: bb.2.do.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1 ; CHECK: liveins: $lr, $r0, $r1
; CHECK: dead renamable $r2 = SPACE 4096, undef renamable $r0 ; CHECK: dead renamable $r2 = SPACE 4096, undef renamable $r0
; CHECK: renamable $r2, renamable $r0 = t2LDR_PRE killed renamable $r0, 4, 14, $noreg :: (load 4 from %ir.scevgep) ; CHECK: renamable $r2, renamable $r0 = t2LDR_PRE killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep)
; CHECK: early-clobber renamable $r1 = t2STR_PRE killed renamable $r2, killed renamable $r1, 4, 14, $noreg :: (store 4 into %ir.scevgep1) ; CHECK: early-clobber renamable $r1 = t2STR_PRE killed renamable $r2, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep1)
; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14, $noreg, def $cpsr ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
; CHECK: t2Bcc %bb.2, 1, killed $cpsr ; CHECK: t2Bcc %bb.2, 1 /* CC::ne */, killed $cpsr
; CHECK: tB %bb.3, 14, $noreg ; CHECK: tB %bb.3, 14 /* CC::al */, $noreg
; CHECK: bb.3.if.end: ; CHECK: bb.3.if.end:
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x40000000), %bb.3(0x40000000) successors: %bb.1(0x40000000), %bb.3(0x40000000)
liveins: $r1, $r2, $r3, $r7, $lr liveins: $r1, $r2, $r3, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
Show All 26 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir

Show First 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: do_copy ; CHECK-LABEL: name: do_copy
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: dead $lr = t2DLS killed $r0 ; CHECK: dead $lr = t2DLS killed $r0
; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg ; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: bb.1.preheader: ; CHECK: bb.1.preheader:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1 ; CHECK: liveins: $r0, $r1
; CHECK: $lr = tMOVr $r0, 14, $noreg ; CHECK: $lr = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: bb.2.while.body: ; CHECK: bb.2.while.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1 ; CHECK: liveins: $lr, $r0, $r1
; CHECK: renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6) ; CHECK: renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep6)
; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2) ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep2)
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.while.end: ; CHECK: bb.3.while.end:
; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
Show All 24 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir

Show First 20 Lines • Show All 104 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: size_limit ; CHECK-LABEL: name: size_limit
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7
; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: tCMPi8 $r3, 0, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 0, 8, implicit-def $itstate ; CHECK: t2IT 0, 8, implicit-def $itstate
; CHECK: tPOP_RET 0, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14, $noreg ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14, $noreg ; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg
; CHECK: $lr = t2DLS killed $r3 ; CHECK: $lr = t2DLS killed $r3
; CHECK: bb.1.for.body: ; CHECK: bb.1.for.body:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: liveins: $lr, $r0, $r1, $r2
; CHECK: dead renamable $r3 = SPACE 4070, undef renamable $r0 ; CHECK: dead renamable $r3 = SPACE 4070, undef renamable $r0
; CHECK: renamable $r12, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep3) ; CHECK: renamable $r12, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep3)
; CHECK: renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14, $noreg :: (load 4 from %ir.scevgep7) ; CHECK: renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep7)
; CHECK: renamable $r3 = nsw t2MUL killed renamable $r3, killed renamable $r12, 14, $noreg ; CHECK: renamable $r3 = nsw t2MUL killed renamable $r3, killed renamable $r12, 14 /* CC::al */, $noreg
; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep11) ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep11)
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1
; CHECK: bb.2.for.cond.cleanup: ; CHECK: bb.2.for.cond.cleanup:
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
Show All 26 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-debug.mir

Show First 20 Lines • Show All 169 Lines • ▼ Show 20 Linesbody: |
; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000) ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r4, $r6 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4, $r6
; CHECK: DBG_VALUE $r0, $noreg, !17, !DIExpression(), debug-location !23 ; CHECK: DBG_VALUE $r0, $noreg, !17, !DIExpression(), debug-location !23
; CHECK: DBG_VALUE $r0, $noreg, !17, !DIExpression(), debug-location !23 ; CHECK: DBG_VALUE $r0, $noreg, !17, !DIExpression(), debug-location !23
; CHECK: DBG_VALUE $r1, $noreg, !18, !DIExpression(), debug-location !23 ; CHECK: DBG_VALUE $r1, $noreg, !18, !DIExpression(), debug-location !23
; CHECK: DBG_VALUE $r1, $noreg, !18, !DIExpression(), debug-location !23 ; CHECK: DBG_VALUE $r1, $noreg, !18, !DIExpression(), debug-location !23
; CHECK: DBG_VALUE $r2, $noreg, !19, !DIExpression(), debug-location !23 ; CHECK: DBG_VALUE $r2, $noreg, !19, !DIExpression(), debug-location !23
; CHECK: DBG_VALUE $r2, $noreg, !19, !DIExpression(), debug-location !23 ; CHECK: DBG_VALUE $r2, $noreg, !19, !DIExpression(), debug-location !23
; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r6, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r6, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16
; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 2, 14, $noreg ; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 2, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8
; CHECK: renamable $r12 = t2LDRi12 renamable $r0, 0, 14, $noreg, debug-location !24 :: (load 4 from %ir.a) ; CHECK: renamable $r12 = t2LDRi12 renamable $r0, 0, 14 /* CC::al */, $noreg, debug-location !24 :: (load 4 from %ir.a)
; CHECK: DBG_VALUE 0, $noreg, !21, !DIExpression(), debug-location !25 ; CHECK: DBG_VALUE 0, $noreg, !21, !DIExpression(), debug-location !25
; CHECK: DBG_VALUE $r12, $noreg, !20, !DIExpression(), debug-location !23 ; CHECK: DBG_VALUE $r12, $noreg, !20, !DIExpression(), debug-location !23
; CHECK: tCBZ $r2, %bb.4, debug-location !28 ; CHECK: tCBZ $r2, %bb.4, debug-location !28
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r12 ; CHECK: liveins: $r0, $r1, $r2, $r12
; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg, debug-location !28 ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg, debug-location !28
; CHECK: renamable $lr = t2MOVi 1, 14, $noreg, $noreg ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg, debug-location !28 ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg, debug-location !28
; CHECK: renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: renamable $r4, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg, debug-location !28 ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg, debug-location !28
; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r4, 0, $noreg, undef renamable $q0, debug-location !28 ; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r4, 0, $noreg, undef renamable $q0, debug-location !28
; CHECK: renamable $q0 = MVE_VMOV_to_lane_32 killed renamable $q0, killed renamable $r12, 0, 14, $noreg, debug-location !28 ; CHECK: renamable $q0 = MVE_VMOV_to_lane_32 killed renamable $q0, killed renamable $r12, 0, 14 /* CC::al */, $noreg, debug-location !28
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, renamable $r3, 19, 14, $noreg, $noreg, debug-location !28 ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg, debug-location !28
; CHECK: renamable $r3, dead $cpsr = tLSRri killed renamable $r3, 2, 14, $noreg, debug-location !28 ; CHECK: renamable $r3, dead $cpsr = tLSRri killed renamable $r3, 2, 14 /* CC::al */, $noreg, debug-location !28
; CHECK: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r3, 18, 14, $noreg, $noreg, debug-location !28 ; CHECK: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r3, 18, 14 /* CC::al */, $noreg, $noreg, debug-location !28
; CHECK: $lr = t2DLS killed renamable $lr, debug-location !28 ; CHECK: $lr = t2DLS killed renamable $lr, debug-location !28
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, debug-location !30 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, debug-location !30
; CHECK: DBG_VALUE $vpr, $noreg, !17, !DIExpression(), debug-location !30 ; CHECK: DBG_VALUE $vpr, $noreg, !17, !DIExpression(), debug-location !30
; CHECK: $q1 = MVE_VORR killed $q0, killed $q0, 0, $noreg, undef $q1 ; CHECK: $q1 = MVE_VORR killed $q0, killed $q0, 0, $noreg, undef $q1
; CHECK: MVE_VPST 8, implicit $vpr, debug-location !30 ; CHECK: MVE_VPST 8, implicit $vpr, debug-location !30
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 8, 1, killed renamable $vpr, debug-location !30 :: (load 8 from %ir.lsr.iv14, align 2) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 8, 1, killed renamable $vpr, debug-location !30 :: (load 8 from %ir.lsr.iv14, align 2)
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg, debug-location !30 ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg, debug-location !30
; CHECK: renamable $q0 = MVE_VMOVLs16bh killed renamable $q0, 0, $noreg, undef renamable $q0, debug-location !30 ; CHECK: renamable $q0 = MVE_VMOVLs16bh killed renamable $q0, 0, $noreg, undef renamable $q0, debug-location !30
; CHECK: renamable $q0 = MVE_VSUBi32 renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0, debug-location !32 ; CHECK: renamable $q0 = MVE_VSUBi32 renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0, debug-location !32
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2, debug-location !29 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2, debug-location !29
; CHECK: bb.3.middle.block: ; CHECK: bb.3.middle.block:
; CHECK: successors: %bb.4(0x80000000) ; CHECK: successors: %bb.4(0x80000000)
; CHECK: liveins: $q0, $q1, $r0, $r3 ; CHECK: liveins: $q0, $q1, $r0, $r3
; CHECK: renamable $vpr = MVE_VCTP32 killed renamable $r3, 0, $noreg, debug-location !30 ; CHECK: renamable $vpr = MVE_VCTP32 killed renamable $r3, 0, $noreg, debug-location !30
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, debug-location !32 ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, debug-location !32
; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, debug-location !28 ; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, debug-location !28
; CHECK: bb.4.for.cond.cleanup: ; CHECK: bb.4.for.cond.cleanup:
; CHECK: liveins: $r0, $r12 ; CHECK: liveins: $r0, $r12
; CHECK: DBG_VALUE $r12, $noreg, !20, !DIExpression(), debug-location !23 ; CHECK: DBG_VALUE $r12, $noreg, !20, !DIExpression(), debug-location !23
; CHECK: t2STRi12 killed renamable $r12, killed renamable $r0, 0, 14, $noreg, debug-location !33 :: (store 4 into %ir.a) ; CHECK: t2STRi12 killed renamable $r12, killed renamable $r0, 0, 14 /* CC::al */, $noreg, debug-location !33 :: (store 4 into %ir.a)
; CHECK: tPOP_RET 14, $noreg, def $r4, def $r6, def $r7, def $pc, debug-location !34 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r6, def $r7, def $pc, debug-location !34
bb.0.entry: bb.0.entry:
successors: %bb.4(0x30000000), %bb.1(0x50000000) successors: %bb.4(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r4, $r6, $lr liveins: $r0, $r1, $r2, $r4, $r6, $lr
DBG_VALUE $r0, $noreg, !17, !DIExpression(), debug-location !23 DBG_VALUE $r0, $noreg, !17, !DIExpression(), debug-location !23
DBG_VALUE $r0, $noreg, !17, !DIExpression(), debug-location !23 DBG_VALUE $r0, $noreg, !17, !DIExpression(), debug-location !23
DBG_VALUE $r1, $noreg, !18, !DIExpression(), debug-location !23 DBG_VALUE $r1, $noreg, !18, !DIExpression(), debug-location !23
DBG_VALUE $r1, $noreg, !18, !DIExpression(), debug-location !23 DBG_VALUE $r1, $noreg, !18, !DIExpression(), debug-location !23
▲ Show 20 Lines • Show All 63 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/unrolled-and-vector.mir

Show First 20 Lines • Show All 227 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: unrolled_and_vector ; CHECK-LABEL: name: unrolled_and_vector
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.11(0x30000000), %bb.1(0x50000000) ; CHECK: successors: %bb.11(0x30000000), %bb.1(0x50000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r9, $r11 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r9, $r11
; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12
; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20
; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 3, 14, $noreg ; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8
; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r8, killed $r9, killed $r11 ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r8, killed $r9, killed $r11
; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -24 ; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -24
; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -28 ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -28
; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -32 ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -32
; CHECK: tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.11, 0, killed $cpsr ; CHECK: tBcc %bb.11, 0 /* CC::eq */, killed $cpsr
; CHECK: bb.1.vector.memcheck: ; CHECK: bb.1.vector.memcheck:
; CHECK: successors: %bb.2(0x40000000), %bb.4(0x40000000) ; CHECK: successors: %bb.2(0x40000000), %bb.4(0x40000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14, $noreg ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg ; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: tCMPr renamable $r4, renamable $r2, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPr renamable $r4, renamable $r2, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: renamable $lr = t2MOVi 1, 14, $noreg, $noreg ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2CSINC $zr, $zr, 9, implicit killed $cpsr ; CHECK: renamable $r12 = t2CSINC $zr, $zr, 9, implicit killed $cpsr
; CHECK: tCMPr killed renamable $r5, renamable $r0, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPr killed renamable $r5, renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: renamable $r6 = t2CSINC $zr, $zr, 9, implicit killed $cpsr ; CHECK: renamable $r6 = t2CSINC $zr, $zr, 9, implicit killed $cpsr
; CHECK: tCMPr killed renamable $r4, renamable $r1, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPr killed renamable $r4, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: renamable $r5 = t2ADDrr renamable $r1, renamable $r3, 14, $noreg, $noreg ; CHECK: renamable $r5 = t2ADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r4 = t2CSINC $zr, $zr, 9, implicit killed $cpsr ; CHECK: renamable $r4 = t2CSINC $zr, $zr, 9, implicit killed $cpsr
; CHECK: tCMPr killed renamable $r5, renamable $r0, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPr killed renamable $r5, renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: renamable $r5 = t2CSINC $zr, $zr, 9, implicit killed $cpsr ; CHECK: renamable $r5 = t2CSINC $zr, $zr, 9, implicit killed $cpsr
; CHECK: renamable $r5, dead $cpsr = tAND killed renamable $r5, killed renamable $r4, 14, $noreg ; CHECK: renamable $r5, dead $cpsr = tAND killed renamable $r5, killed renamable $r4, 14 /* CC::al */, $noreg
; CHECK: dead renamable $r5, $cpsr = tLSLri killed renamable $r5, 31, 14, $noreg ; CHECK: dead renamable $r5, $cpsr = tLSLri killed renamable $r5, 31, 14 /* CC::al */, $noreg
; CHECK: t2IT 0, 4, implicit-def $itstate ; CHECK: t2IT 0, 4, implicit-def $itstate
; CHECK: renamable $r6 = t2ANDrr killed renamable $r6, killed renamable $r12, 0, $cpsr, $noreg, implicit killed $r6, implicit $itstate ; CHECK: renamable $r6 = t2ANDrr killed renamable $r6, killed renamable $r12, 0 /* CC::eq */, $cpsr, $noreg, implicit killed $r6, implicit $itstate
; CHECK: dead renamable $r6 = t2LSLri killed renamable $r6, 31, 0, killed $cpsr, def $cpsr, implicit killed $r6, implicit killed $itstate ; CHECK: dead renamable $r6 = t2LSLri killed renamable $r6, 31, 0 /* CC::eq */, killed $cpsr, def $cpsr, implicit killed $r6, implicit killed $itstate
; CHECK: tBcc %bb.4, 0, killed $cpsr ; CHECK: tBcc %bb.4, 0 /* CC::eq */, killed $cpsr
; CHECK: bb.2.for.body.preheader: ; CHECK: bb.2.for.body.preheader:
; CHECK: successors: %bb.3(0x40000000), %bb.6(0x40000000) ; CHECK: successors: %bb.3(0x40000000), %bb.6(0x40000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
; CHECK: renamable $r4, dead $cpsr = tSUBi3 renamable $r3, 1, 14, $noreg ; CHECK: renamable $r4, dead $cpsr = tSUBi3 renamable $r3, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = t2ANDri renamable $r3, 3, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2ANDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: tCMPi8 killed renamable $r4, 3, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 killed renamable $r4, 3, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.6, 2, killed $cpsr ; CHECK: tBcc %bb.6, 2 /* CC::hs */, killed $cpsr
; CHECK: bb.3: ; CHECK: bb.3:
; CHECK: successors: %bb.8(0x80000000) ; CHECK: successors: %bb.8(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r12 ; CHECK: liveins: $r0, $r1, $r2, $r12
; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: tB %bb.8, 14, $noreg ; CHECK: tB %bb.8, 14 /* CC::al */, $noreg
; CHECK: bb.4.vector.ph: ; CHECK: bb.4.vector.ph:
; CHECK: successors: %bb.5(0x80000000) ; CHECK: successors: %bb.5(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: $lr = MVE_DLSTP_8 killed renamable $r3 ; CHECK: $lr = MVE_DLSTP_8 killed renamable $r3
; CHECK: bb.5.vector.body: ; CHECK: bb.5.vector.body:
; CHECK: successors: %bb.5(0x7c000000), %bb.11(0x04000000) ; CHECK: successors: %bb.5(0x7c000000), %bb.11(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: liveins: $lr, $r0, $r1, $r2
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 0, $noreg :: (load 16 from %ir.lsr.iv46, align 1) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 0, $noreg :: (load 16 from %ir.lsr.iv46, align 1)
; CHECK: renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 0, $noreg :: (load 16 from %ir.lsr.iv4749, align 1) ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 0, $noreg :: (load 16 from %ir.lsr.iv4749, align 1)
; CHECK: renamable $q0 = MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv5052, align 1) ; CHECK: renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv5052, align 1)
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5
; CHECK: tB %bb.11, 14, $noreg ; CHECK: tB %bb.11, 14 /* CC::al */, $noreg
; CHECK: bb.6.for.body.preheader.new: ; CHECK: bb.6.for.body.preheader.new:
; CHECK: successors: %bb.7(0x80000000) ; CHECK: successors: %bb.7(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r3, 19, 14, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: $lr = t2DLS killed renamable $lr
; CHECK: bb.7.for.body: ; CHECK: bb.7.for.body:
; CHECK: successors: %bb.7(0x7c000000), %bb.8(0x04000000) ; CHECK: successors: %bb.7(0x7c000000), %bb.8(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12
; CHECK: renamable $r4 = tLDRBr renamable $r1, $r3, 14, $noreg :: (load 1 from %ir.scevgep2453) ; CHECK: renamable $r4 = tLDRBr renamable $r1, $r3, 14 /* CC::al */, $noreg :: (load 1 from %ir.scevgep2453)
; CHECK: renamable $r9 = t2ADDrr renamable $r1, renamable $r3, 14, $noreg, $noreg ; CHECK: renamable $r9 = t2ADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r5 = tLDRBr renamable $r2, $r3, 14, $noreg :: (load 1 from %ir.scevgep2854) ; CHECK: renamable $r5 = tLDRBr renamable $r2, $r3, 14 /* CC::al */, $noreg :: (load 1 from %ir.scevgep2854)
; CHECK: renamable $r6, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg ; CHECK: renamable $r6, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r5, 14, $noreg ; CHECK: renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r5, 14 /* CC::al */, $noreg
; CHECK: tSTRBr killed renamable $r4, renamable $r0, $r3, 14, $noreg :: (store 1 into %ir.scevgep3255) ; CHECK: tSTRBr killed renamable $r4, renamable $r0, $r3, 14 /* CC::al */, $noreg :: (store 1 into %ir.scevgep3255)
; CHECK: renamable $r8 = t2LDRBi12 renamable $r9, 1, 14, $noreg :: (load 1 from %ir.scevgep40) ; CHECK: renamable $r8 = t2LDRBi12 renamable $r9, 1, 14 /* CC::al */, $noreg :: (load 1 from %ir.scevgep40)
; CHECK: renamable $r5 = tLDRBi renamable $r6, 1, 14, $noreg :: (load 1 from %ir.scevgep42) ; CHECK: renamable $r5 = tLDRBi renamable $r6, 1, 14 /* CC::al */, $noreg :: (load 1 from %ir.scevgep42)
; CHECK: renamable $r8 = tADDhirr killed renamable $r8, killed renamable $r5, 14, $noreg ; CHECK: renamable $r8 = tADDhirr killed renamable $r8, killed renamable $r5, 14 /* CC::al */, $noreg
; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14, $noreg ; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 4, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
; CHECK: t2STRBi12 killed renamable $r8, renamable $r5, 1, 14, $noreg :: (store 1 into %ir.scevgep44) ; CHECK: t2STRBi12 killed renamable $r8, renamable $r5, 1, 14 /* CC::al */, $noreg :: (store 1 into %ir.scevgep44)
; CHECK: renamable $r8 = t2LDRBi12 renamable $r9, 2, 14, $noreg :: (load 1 from %ir.scevgep34) ; CHECK: renamable $r8 = t2LDRBi12 renamable $r9, 2, 14 /* CC::al */, $noreg :: (load 1 from %ir.scevgep34)
; CHECK: renamable $r4 = tLDRBi renamable $r6, 2, 14, $noreg :: (load 1 from %ir.scevgep36) ; CHECK: renamable $r4 = tLDRBi renamable $r6, 2, 14 /* CC::al */, $noreg :: (load 1 from %ir.scevgep36)
; CHECK: renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r8, 14, $noreg ; CHECK: renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r8, 14 /* CC::al */, $noreg
; CHECK: tSTRBi killed renamable $r4, renamable $r5, 2, 14, $noreg :: (store 1 into %ir.scevgep38) ; CHECK: tSTRBi killed renamable $r4, renamable $r5, 2, 14 /* CC::al */, $noreg :: (store 1 into %ir.scevgep38)
; CHECK: renamable $r4 = t2LDRBi12 killed renamable $r9, 3, 14, $noreg :: (load 1 from %ir.scevgep22) ; CHECK: renamable $r4 = t2LDRBi12 killed renamable $r9, 3, 14 /* CC::al */, $noreg :: (load 1 from %ir.scevgep22)
; CHECK: renamable $r6 = tLDRBi killed renamable $r6, 3, 14, $noreg :: (load 1 from %ir.scevgep26) ; CHECK: renamable $r6 = tLDRBi killed renamable $r6, 3, 14 /* CC::al */, $noreg :: (load 1 from %ir.scevgep26)
; CHECK: renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r6, 14, $noreg ; CHECK: renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r6, 14 /* CC::al */, $noreg
; CHECK: tSTRBi killed renamable $r4, killed renamable $r5, 3, 14, $noreg :: (store 1 into %ir.scevgep30) ; CHECK: tSTRBi killed renamable $r4, killed renamable $r5, 3, 14 /* CC::al */, $noreg :: (store 1 into %ir.scevgep30)
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.7 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.7
; CHECK: bb.8.for.cond.cleanup.loopexit.unr-lcssa: ; CHECK: bb.8.for.cond.cleanup.loopexit.unr-lcssa:
; CHECK: successors: %bb.11(0x30000000), %bb.9(0x50000000) ; CHECK: successors: %bb.11(0x30000000), %bb.9(0x50000000)
; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12
; CHECK: t2CMPri renamable $r12, 0, 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPri renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.11, 0, killed $cpsr ; CHECK: tBcc %bb.11, 0 /* CC::eq */, killed $cpsr
; CHECK: bb.9.for.body.epil: ; CHECK: bb.9.for.body.epil:
; CHECK: successors: %bb.11(0x40000000), %bb.10(0x40000000) ; CHECK: successors: %bb.11(0x40000000), %bb.10(0x40000000)
; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12
; CHECK: renamable $r6 = tLDRBr renamable $r1, $r3, 14, $noreg :: (load 1 from %ir.arrayidx.epil) ; CHECK: renamable $r6 = tLDRBr renamable $r1, $r3, 14 /* CC::al */, $noreg :: (load 1 from %ir.arrayidx.epil)
; CHECK: t2CMPri renamable $r12, 1, 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPri renamable $r12, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: renamable $r5 = tLDRBr renamable $r2, $r3, 14, $noreg :: (load 1 from %ir.arrayidx1.epil) ; CHECK: renamable $r5 = tLDRBr renamable $r2, $r3, 14 /* CC::al */, $noreg :: (load 1 from %ir.arrayidx1.epil)
; CHECK: renamable $r6 = tADDhirr killed renamable $r6, killed renamable $r5, 14, $noreg ; CHECK: renamable $r6 = tADDhirr killed renamable $r6, killed renamable $r5, 14 /* CC::al */, $noreg
; CHECK: tSTRBr killed renamable $r6, renamable $r0, $r3, 14, $noreg :: (store 1 into %ir.arrayidx4.epil) ; CHECK: tSTRBr killed renamable $r6, renamable $r0, $r3, 14 /* CC::al */, $noreg :: (store 1 into %ir.arrayidx4.epil)
; CHECK: tBcc %bb.11, 0, killed $cpsr ; CHECK: tBcc %bb.11, 0 /* CC::eq */, killed $cpsr
; CHECK: bb.10.for.body.epil.1: ; CHECK: bb.10.for.body.epil.1:
; CHECK: successors: %bb.11(0x40000000), %bb.12(0x40000000) ; CHECK: successors: %bb.11(0x40000000), %bb.12(0x40000000)
; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12
; CHECK: renamable $r6, dead $cpsr = nuw tADDi3 renamable $r3, 1, 14, $noreg ; CHECK: renamable $r6, dead $cpsr = nuw tADDi3 renamable $r3, 1, 14 /* CC::al */, $noreg
; CHECK: t2CMPri killed renamable $r12, 2, 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPri killed renamable $r12, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: renamable $r5 = tLDRBr renamable $r1, $r6, 14, $noreg :: (load 1 from %ir.arrayidx.epil.1) ; CHECK: renamable $r5 = tLDRBr renamable $r1, $r6, 14 /* CC::al */, $noreg :: (load 1 from %ir.arrayidx.epil.1)
; CHECK: renamable $r4 = tLDRBr renamable $r2, $r6, 14, $noreg :: (load 1 from %ir.arrayidx1.epil.1) ; CHECK: renamable $r4 = tLDRBr renamable $r2, $r6, 14 /* CC::al */, $noreg :: (load 1 from %ir.arrayidx1.epil.1)
; CHECK: renamable $r5 = tADDhirr killed renamable $r5, killed renamable $r4, 14, $noreg ; CHECK: renamable $r5 = tADDhirr killed renamable $r5, killed renamable $r4, 14 /* CC::al */, $noreg
; CHECK: tSTRBr killed renamable $r5, renamable $r0, killed $r6, 14, $noreg :: (store 1 into %ir.arrayidx4.epil.1) ; CHECK: tSTRBr killed renamable $r5, renamable $r0, killed $r6, 14 /* CC::al */, $noreg :: (store 1 into %ir.arrayidx4.epil.1)
; CHECK: tBcc %bb.12, 1, killed $cpsr ; CHECK: tBcc %bb.12, 1 /* CC::ne */, killed $cpsr
; CHECK: bb.11.for.cond.cleanup: ; CHECK: bb.11.for.cond.cleanup:
; CHECK: $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r8, def $r9, def $r11 ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r11
; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
; CHECK: bb.12.for.body.epil.2: ; CHECK: bb.12.for.body.epil.2:
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 2, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 2, 14 /* CC::al */, $noreg
; CHECK: renamable $r1 = tLDRBr killed renamable $r1, $r3, 14, $noreg :: (load 1 from %ir.arrayidx.epil.2) ; CHECK: renamable $r1 = tLDRBr killed renamable $r1, $r3, 14 /* CC::al */, $noreg :: (load 1 from %ir.arrayidx.epil.2)
; CHECK: renamable $r2 = tLDRBr killed renamable $r2, $r3, 14, $noreg :: (load 1 from %ir.arrayidx1.epil.2) ; CHECK: renamable $r2 = tLDRBr killed renamable $r2, $r3, 14 /* CC::al */, $noreg :: (load 1 from %ir.arrayidx1.epil.2)
; CHECK: renamable $r1 = tADDhirr killed renamable $r1, killed renamable $r2, 14, $noreg ; CHECK: renamable $r1 = tADDhirr killed renamable $r1, killed renamable $r2, 14 /* CC::al */, $noreg
; CHECK: tSTRBr killed renamable $r1, killed renamable $r0, killed $r3, 14, $noreg :: (store 1 into %ir.arrayidx4.epil.2) ; CHECK: tSTRBr killed renamable $r1, killed renamable $r0, killed $r3, 14 /* CC::al */, $noreg :: (store 1 into %ir.arrayidx4.epil.2)
; CHECK: $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r8, def $r9, def $r11 ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r11
; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.11(0x30000000), %bb.1(0x50000000) successors: %bb.11(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8, $r9, $r11 liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8, $r9, $r11
frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 20 frame-setup CFI_INSTRUCTION def_cfa_offset 20
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
▲ Show 20 Lines • Show All 161 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-def.mir

Show First 20 Lines • Show All 89 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: do_copy ; CHECK-LABEL: name: do_copy
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r7, $lr ; CHECK: liveins: $r0, $r1, $r2, $r7, $lr
; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: $lr = tMOVr killed $r0, 14, $noreg ; CHECK: $lr = tMOVr killed $r0, 14 /* CC::al */, $noreg
; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg ; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = t2LSRri renamable $lr, 1, 14, $noreg, $noreg ; CHECK: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: bb.1.while.body: ; CHECK: bb.1.while.body:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: liveins: $lr, $r0, $r1, $r2
; CHECK: renamable $r3, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep7) ; CHECK: renamable $r3, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep7)
; CHECK: tCMPhir renamable $lr, renamable $r2, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPhir renamable $lr, renamable $r2, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14, $noreg, $noreg ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2IT 2, 8, implicit-def $itstate ; CHECK: t2IT 2, 8, implicit-def $itstate
; CHECK: renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2, killed $cpsr, implicit renamable $r3, implicit killed $itstate ; CHECK: renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2 /* CC::hs */, killed $cpsr, implicit renamable $r3, implicit killed $itstate
; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep4) ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep4)
; CHECK: t2CMPri renamable $lr, 0, 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPri renamable $lr, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.1, 4, killed $cpsr ; CHECK: tBcc %bb.1, 4 /* CC::mi */, killed $cpsr
; CHECK: tB %bb.2, 14, $noreg ; CHECK: tB %bb.2, 14 /* CC::al */, $noreg
; CHECK: bb.2.while.end: ; CHECK: bb.2.while.end:
; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
Show All 25 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir

Show First 20 Lines • Show All 89 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: do_copy ; CHECK-LABEL: name: do_copy
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r1, $r2, $r7 ; CHECK: liveins: $lr, $r1, $r2, $r7
; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg ; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = t2LSRri renamable $r0, 1, 14, $noreg, $noreg ; CHECK: renamable $r2 = t2LSRri renamable $r0, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $lr = tMOVr $r0, 14, $noreg ; CHECK: $lr = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: bb.1.while.body: ; CHECK: bb.1.while.body:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: liveins: $lr, $r0, $r1, $r2
; CHECK: renamable $r3, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep7) ; CHECK: renamable $r3, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep7)
; CHECK: tCMPhir renamable $lr, renamable $r2, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPhir renamable $lr, renamable $r2, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14, $noreg, $noreg ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2IT 2, 8, implicit-def $itstate ; CHECK: t2IT 2, 8, implicit-def $itstate
; CHECK: renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2, killed $cpsr, implicit killed renamable $r3, implicit killed $itstate ; CHECK: renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2 /* CC::hs */, killed $cpsr, implicit killed renamable $r3, implicit killed $itstate
; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep4) ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep4)
; CHECK: renamable $lr = tMOVr killed $lr, 14, $noreg ; CHECK: renamable $lr = tMOVr killed $lr, 14 /* CC::al */, $noreg
; CHECK: t2CMPri $lr, 0, 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPri $lr, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.1, 1, killed $cpsr ; CHECK: tBcc %bb.1, 1 /* CC::ne */, killed $cpsr
; CHECK: tB %bb.2, 14, $noreg ; CHECK: tB %bb.2, 14 /* CC::al */, $noreg
; CHECK: bb.2.while.end: ; CHECK: bb.2.while.end:
; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
Show All 25 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-use-after.mir

Show First 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: do_copy ; CHECK-LABEL: name: do_copy
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r2, $r7 ; CHECK: liveins: $lr, $r2, $r7
; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: renamable $r0 = t2SUBri killed renamable $lr, 4, 14, $noreg, def dead $cpsr ; CHECK: renamable $r0 = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, def dead $cpsr
; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg ; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: bb.1.preheader: ; CHECK: bb.1.preheader:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1 ; CHECK: liveins: $r0, $r1
; CHECK: $lr = tMOVr $r0, 14, $noreg ; CHECK: $lr = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: bb.2.while.body: ; CHECK: bb.2.while.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1 ; CHECK: liveins: $lr, $r0, $r1
; CHECK: renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6) ; CHECK: renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep6)
; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2) ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep2)
; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14, $noreg, def $cpsr ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
; CHECK: tBcc %bb.2, 1, killed $cpsr ; CHECK: tBcc %bb.2, 1 /* CC::ne */, killed $cpsr
; CHECK: tB %bb.3, 14, $noreg ; CHECK: tB %bb.3, 14 /* CC::al */, $noreg
; CHECK: bb.3.while.end: ; CHECK: bb.3.while.end:
; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r7, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
Show All 24 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-add-operand-liveout.mir

Show First 20 Lines • Show All 105 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: wrong_vctp_liveout ; CHECK-LABEL: name: wrong_vctp_liveout
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
; CHECK: tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 0, 4, implicit-def $itstate ; CHECK: t2IT 0, 4, implicit-def $itstate
; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
; CHECK: tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: dead $lr = t2DLS renamable $r12 ; CHECK: dead $lr = t2DLS renamable $r12
; CHECK: $r3 = tMOVr killed $r12, 14, $noreg ; CHECK: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg
; CHECK: bb.1.vector.body: ; CHECK: bb.1.vector.body:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $q1, $r0, $r1, $r2, $r3 ; CHECK: liveins: $q1, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0 ; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2)
; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2) ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2)
; CHECK: $lr = tMOVr $r3, 14, $noreg ; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.1 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.1
; CHECK: bb.2.middle.block: ; CHECK: bb.2.middle.block:
; CHECK: liveins: $q0, $q1, $r2 ; CHECK: liveins: $q0, $q1, $r2
; CHECK: renamable $r0, dead $cpsr = tADDi3 killed renamable $r2, 4, 14, $noreg ; CHECK: renamable $r0, dead $cpsr = tADDi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $vpr = MVE_VCTP32 killed renamable $r0, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 killed renamable $r0, 0, $noreg
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr
; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $lr, $r7 liveins: $r0, $r1, $r2, $lr, $r7
tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr
t2IT 0, 4, implicit-def $itstate t2IT 0, 4, implicit-def $itstate
renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate
tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate
▲ Show 20 Lines • Show All 41 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt-2.mir

Show First 20 Lines • Show All 101 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: test ; CHECK-LABEL: name: test
; CHECK: bb.0.bb: ; CHECK: bb.0.bb:
; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
; CHECK: frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: $r7 = frame-setup tMOVr $sp, 14, $noreg ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14, $noreg ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK: tCBZ $r2, %bb.3 ; CHECK: tCBZ $r2, %bb.3
; CHECK: bb.1.bb3: ; CHECK: bb.1.bb3:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: renamable $r12 = t2ADDri renamable $r2, 3, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2ADDri renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $lr = t2MOVi 1, 14, $noreg, $noreg ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: $vpr = VMSR_P0 killed $r3, 14, $noreg ; CHECK: $vpr = VMSR_P0 killed $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store 4 into %stack.0) ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.0)
; CHECK: $r3 = tMOVr $r0, 14, $noreg ; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: $lr = t2DLS killed renamable $lr
; CHECK: bb.2.bb9: ; CHECK: bb.2.bb9:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load 4 from %stack.0) ; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.0)
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv24, align 4) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv24, align 4)
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $vpr = MVE_VCMPi32r renamable $q0, $zr, 1, 1, killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPi32r renamable $q0, $zr, 1, 1, killed renamable $vpr
; CHECK: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1, align 4) ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1, align 4)
; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4) ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4)
; CHECK: $r0 = tMOVr $r3, 14, $noreg ; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.bb27: ; CHECK: bb.3.bb27:
; CHECK: $sp = tADDspi $sp, 1, 14, $noreg ; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.bb: bb.0.bb:
successors: %bb.3(0x30000000), %bb.1(0x50000000) successors: %bb.3(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $lr liveins: $r0, $r1, $r2, $r3, $lr
frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
▲ Show 20 Lines • Show All 45 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt.mir

Show First 20 Lines • Show All 98 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: test ; CHECK-LABEL: name: test
; CHECK: bb.0.bb: ; CHECK: bb.0.bb:
; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
; CHECK: frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: $r7 = frame-setup tMOVr $sp, 14, $noreg ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14, $noreg ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK: tCBZ $r2, %bb.3 ; CHECK: tCBZ $r2, %bb.3
; CHECK: bb.1.bb3: ; CHECK: bb.1.bb3:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: $vpr = VMSR_P0 killed $r3, 14, $noreg ; CHECK: $vpr = VMSR_P0 killed $r3, 14 /* CC::al */, $noreg
; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store 4 into %stack.0) ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.0)
; CHECK: $r3 = tMOVr $r0, 14, $noreg ; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2
; CHECK: bb.2.bb9: ; CHECK: bb.2.bb9:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r3
; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load 4 from %stack.0) ; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.0)
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv24, align 4) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv24, align 4)
; CHECK: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1, align 4) ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1, align 4)
; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4) ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4)
; CHECK: $r0 = tMOVr $r3, 14, $noreg ; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.bb27: ; CHECK: bb.3.bb27:
; CHECK: $sp = tADDspi $sp, 1, 14, $noreg ; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.bb: bb.0.bb:
successors: %bb.3(0x30000000), %bb.1(0x50000000) successors: %bb.3(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $lr liveins: $r0, $r1, $r2, $r3, $lr
frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
▲ Show 20 Lines • Show All 42 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subi3.mir

Show First 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: vctp_tsubi3 ; CHECK-LABEL: name: vctp_tsubi3
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7
; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: t2IT 11, 8, implicit-def $itstate
; CHECK: tPOP_RET 11, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
; CHECK: bb.1.vector.body: ; CHECK: bb.1.vector.body:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: liveins: $lr, $r0, $r1, $r2
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load 16 from %ir.lsr.iv13, align 4) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load 16 from %ir.lsr.iv13, align 4)
; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg :: (load 16 from %ir.lsr.iv1416, align 4) ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg :: (load 16 from %ir.lsr.iv1416, align 4)
; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv1719, align 4) ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv1719, align 4)
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK: bb.2.for.cond.cleanup: ; CHECK: bb.2.for.cond.cleanup:
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
Show All 30 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri.mir

Show First 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: vctp_tsubi3 ; CHECK-LABEL: name: vctp_tsubi3
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7
; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: t2IT 11, 8, implicit-def $itstate
; CHECK: tPOP_RET 11, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
; CHECK: bb.1.vector.body: ; CHECK: bb.1.vector.body:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: liveins: $lr, $r0, $r1, $r2
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load 16 from %ir.lsr.iv13, align 4) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load 16 from %ir.lsr.iv13, align 4)
; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg :: (load 16 from %ir.lsr.iv1416, align 4) ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg :: (load 16 from %ir.lsr.iv1416, align 4)
; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv1719, align 4) ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv1719, align 4)
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK: bb.2.for.cond.cleanup: ; CHECK: bb.2.for.cond.cleanup:
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
Show All 30 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri12.mir

Show First 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: vctp_tsubi3 ; CHECK-LABEL: name: vctp_tsubi3
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7
; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: t2IT 11, 8, implicit-def $itstate
; CHECK: tPOP_RET 11, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
; CHECK: bb.1.vector.body: ; CHECK: bb.1.vector.body:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: liveins: $lr, $r0, $r1, $r2
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load 16 from %ir.lsr.iv13, align 4) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load 16 from %ir.lsr.iv13, align 4)
; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg :: (load 16 from %ir.lsr.iv1416, align 4) ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg :: (load 16 from %ir.lsr.iv1416, align 4)
; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv1719, align 4) ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv1719, align 4)
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK: bb.2.for.cond.cleanup: ; CHECK: bb.2.for.cond.cleanup:
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
Show All 30 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp16-reduce.mir

Show First 20 Lines • Show All 108 Lines • ▼ Show 20 Lines - id: 0
alignment: 16 alignment: 16
isTargetSpecific: false isTargetSpecific: false
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: wrong_liveout_shift ; CHECK-LABEL: name: wrong_liveout_shift
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: liveins: $lr, $r0, $r1, $r2
; CHECK: tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 0, 2, implicit-def $itstate ; CHECK: t2IT 0, 2, implicit-def $itstate
; CHECK: renamable $r0 = t2MOVi16 32767, 0, $cpsr, implicit killed $r0, implicit $itstate ; CHECK: renamable $r0 = t2MOVi16 32767, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
; CHECK: renamable $r0 = tSXTH killed renamable $r0, 0, $cpsr, implicit killed $r0, implicit $itstate ; CHECK: renamable $r0 = tSXTH killed renamable $r0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
; CHECK: tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
; CHECK: frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: dead $r7 = frame-setup tMOVr $sp, 14, $noreg ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 7, 14, $noreg, $noreg ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 8, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 8, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, renamable $r12, 27, 14, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3 = tLEApcrel %const.0, 14, $noreg ; CHECK: renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 3, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load 16 from constant-pool) ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load 16 from constant-pool)
; CHECK: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r12, 26, 14, $noreg, $noreg ; CHECK: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r12, 26, 14 /* CC::al */, $noreg, $noreg
; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: $lr = t2DLS killed renamable $lr
; CHECK: bb.1.vector.body: ; CHECK: bb.1.vector.body:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg
; CHECK: $q1 = MVE_VORR killed $q0, killed $q0, 0, $noreg, undef $q1 ; CHECK: $q1 = MVE_VORR killed $q0, killed $q0, 0, $noreg, undef $q1
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r0, renamable $q0 = MVE_VLDRBU16_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv19, align 1) ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRBU16_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv19, align 1)
; CHECK: renamable $r1, renamable $q2 = MVE_VLDRBU16_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv2022, align 1) ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRBU16_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv2022, align 1)
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = nuw MVE_VMULi16 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nuw MVE_VMULi16 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: renamable $q0 = MVE_VSUBi16 renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VSUBi16 renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1
; CHECK: bb.2.middle.block: ; CHECK: bb.2.middle.block:
; CHECK: liveins: $q0, $q1, $r3 ; CHECK: liveins: $q0, $q1, $r3
; CHECK: renamable $vpr = MVE_VCTP16 killed renamable $r3, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP16 killed renamable $r3, 0, $noreg
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr
; CHECK: renamable $r0 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r0 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg
; CHECK: $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r7, def $lr ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr
; CHECK: renamable $r0 = tSXTH killed renamable $r0, 14, $noreg ; CHECK: renamable $r0 = tSXTH killed renamable $r0, 14 /* CC::al */, $noreg
; CHECK: tBX_RET 14, $noreg, implicit killed $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0
; CHECK: bb.3 (align 16): ; CHECK: bb.3 (align 16):
; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16 ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $lr liveins: $r0, $r1, $r2, $lr
tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr
t2IT 0, 2, implicit-def $itstate t2IT 0, 2, implicit-def $itstate
▲ Show 20 Lines • Show All 50 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmaxmin_vpred_r.mir

Show First 20 Lines • Show All 136 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: arm_elementwise_mul_s8 ; CHECK-LABEL: name: arm_elementwise_mul_s8
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000) ; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7
; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12
; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20
; CHECK: renamable $r12 = t2LDRi12 $sp, 44, 14, $noreg :: (load 4 from %fixed-stack.6, align 8) ; CHECK: renamable $r12 = t2LDRi12 $sp, 44, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.6, align 8)
; CHECK: $lr = MVE_WLSTP_32 killed renamable $r12, %bb.3 ; CHECK: $lr = MVE_WLSTP_32 killed renamable $r12, %bb.3
; CHECK: bb.1.for.body.lr.ph: ; CHECK: bb.1.for.body.lr.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
; CHECK: $r7, $r6 = t2LDRDi8 $sp, 36, 14, $noreg :: (load 4 from %fixed-stack.4, align 8), (load 4 from %fixed-stack.5) ; CHECK: $r7, $r6 = t2LDRDi8 $sp, 36, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.4, align 8), (load 4 from %fixed-stack.5)
; CHECK: $r5, $r4 = t2LDRDi8 $sp, 20, 14, $noreg :: (load 4 from %fixed-stack.0, align 8), (load 4 from %fixed-stack.1) ; CHECK: $r5, $r4 = t2LDRDi8 $sp, 20, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.0, align 8), (load 4 from %fixed-stack.1)
; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r6, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r6, 0, $noreg, undef renamable $q0
; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r7, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r7, 0, $noreg, undef renamable $q1
; CHECK: bb.2.for.body: ; CHECK: bb.2.for.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5 ; CHECK: liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5
; CHECK: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 0, $noreg :: (load 16 from %ir.input_2_cast, align 4) ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 0, $noreg :: (load 16 from %ir.input_2_cast, align 4)
; CHECK: renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 0, $noreg :: (load 16 from %ir.input_1_cast, align 4) ; CHECK: renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 0, $noreg :: (load 16 from %ir.input_1_cast, align 4)
; CHECK: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, undef renamable $q2
; CHECK: renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, undef renamable $q3 ; CHECK: renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, undef renamable $q3
; CHECK: renamable $q2 = MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2
; CHECK: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r4, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r4, 0, $noreg, undef renamable $q2
; CHECK: renamable $q2 = MVE_VMAXu32 killed renamable $q2, renamable $q1, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VMAXu32 killed renamable $q2, renamable $q1, 0, $noreg, undef renamable $q2
; CHECK: renamable $q2 = MVE_VMINu32 killed renamable $q2, renamable $q0, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VMINu32 killed renamable $q2, renamable $q0, 0, $noreg, undef renamable $q2
; CHECK: renamable $r5 = MVE_VSTRWU32_post killed renamable $q2, killed renamable $r5, 4, 0, killed $noreg :: (store 16 into %ir.output_cast, align 4) ; CHECK: renamable $r5 = MVE_VSTRWU32_post killed renamable $q2, killed renamable $r5, 4, 0, killed $noreg :: (store 16 into %ir.output_cast, align 4)
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x40000000), %bb.3(0x40000000) successors: %bb.1(0x40000000), %bb.3(0x40000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 20 frame-setup CFI_INSTRUCTION def_cfa_offset 20
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
▲ Show 20 Lines • Show All 45 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmldava_in_vpt.mir

Show First 20 Lines • Show All 133 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: vmldava_in_vpt ; CHECK-LABEL: name: vmldava_in_vpt
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000) ; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7
; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12
; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20
; CHECK: renamable $r7 = tLDRspi $sp, 10, 14, $noreg :: (load 4 from %fixed-stack.5) ; CHECK: renamable $r7 = tLDRspi $sp, 10, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.5)
; CHECK: renamable $r12 = t2MOVi 0, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: $lr = MVE_WLSTP_32 killed renamable $r7, %bb.3 ; CHECK: $lr = MVE_WLSTP_32 killed renamable $r7, %bb.3
; CHECK: bb.1.for.body.lr.ph: ; CHECK: bb.1.for.body.lr.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
; CHECK: $r5, $r12 = t2LDRDi8 $sp, 32, 14, $noreg :: (load 4 from %fixed-stack.3), (load 4 from %fixed-stack.4, align 8) ; CHECK: $r5, $r12 = t2LDRDi8 $sp, 32, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.3), (load 4 from %fixed-stack.4, align 8)
; CHECK: renamable $r4 = tLDRspi $sp, 5, 14, $noreg :: (load 4 from %fixed-stack.0, align 8) ; CHECK: renamable $r4 = tLDRspi $sp, 5, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.0, align 8)
; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r12, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r12, 0, $noreg, undef renamable $q0
; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r5, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r5, 0, $noreg, undef renamable $q1
; CHECK: renamable $r12 = t2MOVi 0, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: bb.2.for.body: ; CHECK: bb.2.for.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r12 ; CHECK: liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r12
; CHECK: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 0, $noreg :: (load 16 from %ir.input_2_cast, align 4) ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 0, $noreg :: (load 16 from %ir.input_2_cast, align 4)
; CHECK: renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 0, $noreg :: (load 16 from %ir.input_1_cast, align 4) ; CHECK: renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 0, $noreg :: (load 16 from %ir.input_1_cast, align 4)
; CHECK: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, undef renamable $q2
; CHECK: renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, undef renamable $q3 ; CHECK: renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, undef renamable $q3
; CHECK: renamable $q2 = MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2
; CHECK: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r4, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r4, 0, $noreg, undef renamable $q2
; CHECK: renamable $q2 = MVE_VMAXu32 killed renamable $q2, renamable $q1, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VMAXu32 killed renamable $q2, renamable $q1, 0, $noreg, undef renamable $q2
; CHECK: renamable $q3 = MVE_VMINu32 renamable $q2, renamable $q0, 0, $noreg, undef renamable $q3 ; CHECK: renamable $q3 = MVE_VMINu32 renamable $q2, renamable $q0, 0, $noreg, undef renamable $q3
; CHECK: renamable $r12 = MVE_VMLADAVas32 killed renamable $r12, killed renamable $q3, killed renamable $q2, 0, killed $noreg ; CHECK: renamable $r12 = MVE_VMLADAVas32 killed renamable $r12, killed renamable $q3, killed renamable $q2, 0, killed $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: liveins: $r12 ; CHECK: liveins: $r12
; CHECK: $r0 = tMOVr killed $r12, 14, $noreg ; CHECK: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x40000000), %bb.3(0x40000000) successors: %bb.1(0x40000000), %bb.3(0x40000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 20 frame-setup CFI_INSTRUCTION def_cfa_offset 20
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
▲ Show 20 Lines • Show All 52 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir

Show First 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: copy ; CHECK-LABEL: name: copy
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000) ; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: dead $lr = t2WLS $r2, %bb.3 ; CHECK: dead $lr = t2WLS $r2, %bb.3
; CHECK: bb.1.while.body.preheader: ; CHECK: bb.1.while.body.preheader:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 2, 14, $noreg ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 2, 14 /* CC::al */, $noreg
; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 2, 14, $noreg ; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 2, 14 /* CC::al */, $noreg
; CHECK: $lr = tMOVr killed $r2, 14, $noreg ; CHECK: $lr = tMOVr killed $r2, 14 /* CC::al */, $noreg
; CHECK: bb.2.while.body: ; CHECK: bb.2.while.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1 ; CHECK: liveins: $lr, $r0, $r1
; CHECK: renamable $r2, renamable $r1 = t2LDRH_PRE killed renamable $r1, 2, 14, $noreg :: (load 2 from %ir.scevgep4) ; CHECK: renamable $r2, renamable $r1 = t2LDRH_PRE killed renamable $r1, 2, 14 /* CC::al */, $noreg :: (load 2 from %ir.scevgep4)
; CHECK: early-clobber renamable $r0 = t2STRH_PRE killed renamable $r2, killed renamable $r0, 2, 14, $noreg :: (store 2 into %ir.scevgep7) ; CHECK: early-clobber renamable $r0 = t2STRH_PRE killed renamable $r2, killed renamable $r0, 2, 14 /* CC::al */, $noreg :: (store 2 into %ir.scevgep7)
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.while.end: ; CHECK: bb.3.while.end:
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x40000000), %bb.3(0x40000000) successors: %bb.1(0x40000000), %bb.3(0x40000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
Show All 25 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/wlstp.mir

Show First 20 Lines • Show All 185 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: test_wlstp8 ; CHECK-LABEL: name: test_wlstp8
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.3(0x40000000), %bb.1(0x40000000) ; CHECK: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4
; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8
; CHECK: $lr = MVE_WLSTP_8 killed renamable $r3, %bb.1 ; CHECK: $lr = MVE_WLSTP_8 killed renamable $r3, %bb.1
; CHECK: tB %bb.3, 14, $noreg ; CHECK: tB %bb.3, 14 /* CC::al */, $noreg
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: liveins: $lr, $r0, $r1, $r2
; CHECK: renamable $r12 = t2MOVi 0, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.3(0x04000000), %bb.2(0x7c000000) ; CHECK: successors: %bb.3(0x04000000), %bb.2(0x7c000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r12 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r12
; CHECK: renamable $r4 = t2ADDrr renamable $r1, renamable $r12, 14, $noreg, $noreg ; CHECK: renamable $r4 = t2ADDrr renamable $r1, renamable $r12, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VLDRBU8 killed renamable $r4, 0, 0, $noreg :: (load 16 from %ir.scevgep45, align 1) ; CHECK: renamable $q0 = MVE_VLDRBU8 killed renamable $r4, 0, 0, $noreg :: (load 16 from %ir.scevgep45, align 1)
; CHECK: renamable $r4 = t2ADDrr renamable $r2, renamable $r12, 14, $noreg, $noreg ; CHECK: renamable $r4 = t2ADDrr renamable $r2, renamable $r12, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q1 = MVE_VLDRBU8 killed renamable $r4, 0, 0, $noreg :: (load 16 from %ir.scevgep23, align 1) ; CHECK: renamable $q1 = MVE_VLDRBU8 killed renamable $r4, 0, 0, $noreg :: (load 16 from %ir.scevgep23, align 1)
; CHECK: renamable $r4 = t2ADDrr renamable $r0, renamable $r12, 14, $noreg, $noreg ; CHECK: renamable $r4 = t2ADDrr renamable $r0, renamable $r12, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2ADDri killed renamable $r12, 16, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2ADDri killed renamable $r12, 16, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VMULi8 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMULi8 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: MVE_VSTRBU8 killed renamable $q0, killed renamable $r4, 0, 0, killed $noreg :: (store 16 into %ir.scevgep1, align 1) ; CHECK: MVE_VSTRBU8 killed renamable $q0, killed renamable $r4, 0, 0, killed $noreg :: (store 16 into %ir.scevgep1, align 1)
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: tPOP_RET 14, $noreg, def $r4, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.3(0x40000000), %bb.1(0x40000000) successors: %bb.3(0x40000000), %bb.1(0x40000000)
liveins: $r0, $r1, $r2, $r3, $r4, $lr liveins: $r0, $r1, $r2, $r3, $r4, $lr
frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r4, -8 frame-setup CFI_INSTRUCTION offset $r4, -8
▲ Show 20 Lines • Show All 82 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: test_wlstp16 ; CHECK-LABEL: name: test_wlstp16
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7
; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: $lr = MVE_WLSTP_16 killed renamable $r3, %bb.1 ; CHECK: $lr = MVE_WLSTP_16 killed renamable $r3, %bb.1
; CHECK: tB %bb.2, 14, $noreg ; CHECK: tB %bb.2, 14 /* CC::al */, $noreg
; CHECK: bb.1.vector.body: ; CHECK: bb.1.vector.body:
; CHECK: successors: %bb.2(0x04000000), %bb.1(0x7c000000) ; CHECK: successors: %bb.2(0x04000000), %bb.1(0x7c000000)
; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: liveins: $lr, $r0, $r1, $r2
; CHECK: renamable $q0 = MVE_VLDRHU16 renamable $r1, 0, 0, $noreg :: (load 16 from %ir.lsr.iv57, align 2) ; CHECK: renamable $q0 = MVE_VLDRHU16 renamable $r1, 0, 0, $noreg :: (load 16 from %ir.lsr.iv57, align 2)
; CHECK: renamable $q1 = MVE_VLDRHU16 renamable $r2, 0, 0, $noreg :: (load 16 from %ir.lsr.iv24, align 2) ; CHECK: renamable $q1 = MVE_VLDRHU16 renamable $r2, 0, 0, $noreg :: (load 16 from %ir.lsr.iv24, align 2)
; CHECK: renamable $q0 = MVE_VMULi16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMULi16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: MVE_VSTRHU16 killed renamable $q0, renamable $r0, 0, 0, killed $noreg :: (store 16 into %ir.lsr.iv1, align 2) ; CHECK: MVE_VSTRHU16 killed renamable $q0, renamable $r0, 0, 0, killed $noreg :: (store 16 into %ir.lsr.iv1, align 2)
; CHECK: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 16, 14, $noreg ; CHECK: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 16, 14, $noreg ; CHECK: renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
; CHECK: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 16, 14, $noreg ; CHECK: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK: bb.2.for.cond.cleanup: ; CHECK: bb.2.for.cond.cleanup:
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.2(0x40000000), %bb.1(0x40000000) successors: %bb.2(0x40000000), %bb.1(0x40000000)
liveins: $r0, $r1, $r2, $r3, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: test_wlstp32 ; CHECK-LABEL: name: test_wlstp32
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.4(0x40000000), %bb.1(0x40000000) ; CHECK: successors: %bb.4(0x40000000), %bb.1(0x40000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2MOVi 0, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: $lr = t2WLS killed renamable $lr, %bb.1 ; CHECK: $lr = t2WLS killed renamable $lr, %bb.1
; CHECK: tB %bb.4, 14, $noreg ; CHECK: tB %bb.4, 14 /* CC::al */, $noreg
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: liveins: $lr, $r0, $r1, $r2
; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.3(0x04000000), %bb.2(0x7c000000) ; CHECK: successors: %bb.3(0x04000000), %bb.2(0x7c000000)
; CHECK: liveins: $lr, $q1, $r0, $r1, $r2 ; CHECK: liveins: $lr, $q1, $r0, $r1, $r2
; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0 ; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0
; CHECK: renamable $vpr = MVE_VCTP32 $r2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 $r2, 0, $noreg
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr :: (load 16 from %ir.lsr.iv24, align 4) ; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr :: (load 16 from %ir.lsr.iv24, align 4)
; CHECK: renamable $q2 = MVE_VLDRWU32 renamable $r1, 0, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1, align 4) ; CHECK: renamable $q2 = MVE_VLDRWU32 renamable $r1, 0, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1, align 4)
; CHECK: $r3 = tMOVr $r2, 14, $noreg ; CHECK: $r3 = tMOVr $r2, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
; CHECK: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 16, 14, $noreg ; CHECK: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
; CHECK: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 16, 14, $noreg ; CHECK: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed $r2, 4, 14, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed $r2, 4, 14 /* CC::al */, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $q1 = nsw MVE_VADDi32 killed renamable $q1, renamable $q0, 0, killed renamable $vpr, undef renamable $q1 ; CHECK: renamable $q1 = nsw MVE_VADDi32 killed renamable $q1, renamable $q0, 0, killed renamable $vpr, undef renamable $q1
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.middle.block: ; CHECK: bb.3.middle.block:
; CHECK: successors: %bb.4(0x80000000) ; CHECK: successors: %bb.4(0x80000000)
; CHECK: liveins: $q0, $q1, $r3 ; CHECK: liveins: $q0, $q1, $r3
; CHECK: renamable $vpr = MVE_VCTP32 killed renamable $r3, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 killed renamable $r3, 0, $noreg
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr
; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
; CHECK: bb.4.for.cond.cleanup: ; CHECK: bb.4.for.cond.cleanup:
; CHECK: liveins: $r12 ; CHECK: liveins: $r12
; CHECK: $r0 = tMOVr killed $r12, 14, $noreg ; CHECK: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.4(0x40000000), %bb.1(0x40000000) successors: %bb.4(0x40000000), %bb.1(0x40000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
▲ Show 20 Lines • Show All 50 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-liveout-lsr-shift.mir

Show First 20 Lines • Show All 108 Lines • ▼ Show 20 Lines - id: 0
alignment: 16 alignment: 16
isTargetSpecific: false isTargetSpecific: false
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: wrong_liveout_shift ; CHECK-LABEL: name: wrong_liveout_shift
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: liveins: $lr, $r0, $r1, $r2
; CHECK: tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 0, 2, implicit-def $itstate ; CHECK: t2IT 0, 2, implicit-def $itstate
; CHECK: renamable $r0 = t2MOVi16 32767, 0, $cpsr, implicit killed $r0, implicit $itstate ; CHECK: renamable $r0 = t2MOVi16 32767, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
; CHECK: renamable $r0 = tSXTH killed renamable $r0, 0, $cpsr, implicit killed $r0, implicit $itstate ; CHECK: renamable $r0 = tSXTH killed renamable $r0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
; CHECK: tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
; CHECK: frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: dead $r7 = frame-setup tMOVr $sp, 14, $noreg ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 7, 14, $noreg, $noreg ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 8, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 8, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, renamable $r12, 27, 14, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3 = tLEApcrel %const.0, 14, $noreg ; CHECK: renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 2, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 2, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load 16 from constant-pool) ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load 16 from constant-pool)
; CHECK: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r12, 26, 14, $noreg, $noreg ; CHECK: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r12, 26, 14 /* CC::al */, $noreg, $noreg
; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: $lr = t2DLS killed renamable $lr
; CHECK: bb.1.vector.body: ; CHECK: bb.1.vector.body:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg
; CHECK: $q1 = MVE_VORR killed $q0, killed $q0, 0, $noreg, undef $q1 ; CHECK: $q1 = MVE_VORR killed $q0, killed $q0, 0, $noreg, undef $q1
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r0, renamable $q0 = MVE_VLDRBU16_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv19, align 1) ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRBU16_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv19, align 1)
; CHECK: renamable $r1, renamable $q2 = MVE_VLDRBU16_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv2022, align 1) ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRBU16_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv2022, align 1)
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = nuw MVE_VMULi16 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nuw MVE_VMULi16 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: renamable $q0 = MVE_VSUBi16 renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VSUBi16 renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1
; CHECK: bb.2.middle.block: ; CHECK: bb.2.middle.block:
; CHECK: liveins: $q0, $q1, $r3 ; CHECK: liveins: $q0, $q1, $r3
; CHECK: renamable $vpr = MVE_VCTP16 killed renamable $r3, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP16 killed renamable $r3, 0, $noreg
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr
; CHECK: renamable $r0 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r0 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg
; CHECK: $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r7, def $lr ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr
; CHECK: renamable $r0 = tSXTH killed renamable $r0, 14, $noreg ; CHECK: renamable $r0 = tSXTH killed renamable $r0, 14 /* CC::al */, $noreg
; CHECK: tBX_RET 14, $noreg, implicit killed $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0
; CHECK: bb.3 (align 16): ; CHECK: bb.3 (align 16):
; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16 ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $lr liveins: $r0, $r1, $r2, $lr
tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr
t2IT 0, 2, implicit-def $itstate t2IT 0, 2, implicit-def $itstate
▲ Show 20 Lines • Show All 50 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-opcode-liveout.mir

Show First 20 Lines • Show All 110 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: wrong_vctp_liveout ; CHECK-LABEL: name: wrong_vctp_liveout
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
; CHECK: tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 0, 4, implicit-def $itstate ; CHECK: t2IT 0, 4, implicit-def $itstate
; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
; CHECK: tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: dead $lr = t2DLS renamable $r3 ; CHECK: dead $lr = t2DLS renamable $r3
; CHECK: $r12 = tMOVr killed $r3, 14, $noreg ; CHECK: $r12 = tMOVr killed $r3, 14 /* CC::al */, $noreg
; CHECK: $r3 = tMOVr $r2, 14, $noreg ; CHECK: $r3 = tMOVr $r2, 14 /* CC::al */, $noreg
; CHECK: bb.1.vector.body: ; CHECK: bb.1.vector.body:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $q1, $r0, $r1, $r2, $r3, $r12 ; CHECK: liveins: $q1, $r0, $r1, $r2, $r3, $r12
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg
; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0 ; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2)
; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2) ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2)
; CHECK: $lr = tMOVr $r12, 14, $noreg ; CHECK: $lr = tMOVr $r12, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
; CHECK: renamable $r12 = nsw t2SUBri killed $r12, 1, 14, $noreg, $noreg ; CHECK: renamable $r12 = nsw t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.1 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.1
; CHECK: bb.2.middle.block: ; CHECK: bb.2.middle.block:
; CHECK: liveins: $q0, $q1, $r2, $r3 ; CHECK: liveins: $q0, $q1, $r2, $r3
; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r2, 1, 14, $noreg ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r2, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $q2 = MVE_VDUP32 killed renamable $r0, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VDUP32 killed renamable $r0, 0, $noreg, undef renamable $q2
; CHECK: renamable $r0, dead $cpsr = tADDi3 killed renamable $r3, 4, 14, $noreg ; CHECK: renamable $r0, dead $cpsr = tADDi3 killed renamable $r3, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $vpr = MVE_VCMPu32r killed renamable $q2, killed renamable $r0, 8, 0, $noreg ; CHECK: renamable $vpr = MVE_VCMPu32r killed renamable $q2, killed renamable $r0, 8, 0, $noreg
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr
; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $lr, $r7 liveins: $r0, $r1, $r2, $lr, $r7
tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr
t2IT 0, 4, implicit-def $itstate t2IT 0, 4, implicit-def $itstate
renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate
tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate
▲ Show 20 Lines • Show All 44 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-operand-liveout.mir

Show First 20 Lines • Show All 102 Lines • ▼ Show 20 Lines
callSites: [] callSites: []
constants: [] constants: []
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: wrong_vctp_liveout ; CHECK-LABEL: name: wrong_vctp_liveout
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
; CHECK: tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 0, 4, implicit-def $itstate ; CHECK: t2IT 0, 4, implicit-def $itstate
; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
; CHECK: tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: dead $lr = t2DLS renamable $r12 ; CHECK: dead $lr = t2DLS renamable $r12
; CHECK: $r3 = tMOVr killed $r12, 14, $noreg ; CHECK: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg
; CHECK: bb.1.vector.body: ; CHECK: bb.1.vector.body:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $q1, $r0, $r1, $r2, $r3 ; CHECK: liveins: $q1, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0 ; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2)
; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2) ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2)
; CHECK: $lr = tMOVr $r3, 14, $noreg ; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.1 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.1
; CHECK: bb.2.middle.block: ; CHECK: bb.2.middle.block:
; CHECK: liveins: $q0, $q1, $r2 ; CHECK: liveins: $q0, $q1, $r2
; CHECK: renamable $vpr = MVE_VCTP32 killed renamable $r2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 killed renamable $r2, 0, $noreg
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr
; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $lr, $r7 liveins: $r0, $r1, $r2, $lr, $r7
tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr
t2IT 0, 4, implicit-def $itstate t2IT 0, 4, implicit-def $itstate
renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate
tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate
Show All 40 Lines

llvm/test/CodeGen/Thumb2/constant-islands-cbz.mir

Show All 17 Lines
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$r0', virtual-reg: '' } - { reg: '$r0', virtual-reg: '' }
- { reg: '$r1', virtual-reg: '' } - { reg: '$r1', virtual-reg: '' }
body: | body: |
; CHECK-LABEL: name: test_simple ; CHECK-LABEL: name: test_simple
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000) ; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000)
; CHECK: liveins: $r0, $r1
; CHECK: tCBZ $r0, %bb.2 ; CHECK: tCBZ $r0, %bb.2
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) ; CHECK: liveins: $r0
; CHECK: tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.x)
; CHECK: tTAILJMPdND @c, 14 /* CC::al */, $noreg, implicit $sp, implicit $sp, implicit killed $r0
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: tBX_RET 14, $noreg, implicit killed $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0
bb.0: bb.0:
successors: %bb.1(0x30000000), %bb.2(0x50000000) successors: %bb.1(0x30000000), %bb.2(0x50000000)
liveins: $r0, $r1 liveins: $r0, $r1
tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr
t2Bcc %bb.1, 0, killed $cpsr t2Bcc %bb.1, 0, killed $cpsr
bb.2: bb.2:
Show All 12 Lines
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$r0', virtual-reg: '' } - { reg: '$r0', virtual-reg: '' }
- { reg: '$r1', virtual-reg: '' } - { reg: '$r1', virtual-reg: '' }
body: | body: |
; CHECK-LABEL: name: test_notfirst ; CHECK-LABEL: name: test_notfirst
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000) ; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000)
; CHECK: renamable $r0, $cpsr = tADDrr killed renamable $r0, renamable $r1, 14, $noreg ; CHECK: liveins: $r0, $r1
; CHECK: renamable $r1 = t2ADDrs renamable $r0, killed renamable $r1, 18, 14, $noreg, $noreg ; CHECK: renamable $r0, $cpsr = tADDrr killed renamable $r0, renamable $r1, 14 /* CC::al */, $noreg
; CHECK: renamable $r1 = t2ADDrs renamable $r0, killed renamable $r1, 18, 14 /* CC::al */, $noreg, $noreg
; CHECK: tCBZ $r0, %bb.2 ; CHECK: tCBZ $r0, %bb.2
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) ; CHECK: liveins: $r0
; CHECK: tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.x)
; CHECK: tTAILJMPdND @c, 14 /* CC::al */, $noreg, implicit $sp, implicit $sp, implicit killed $r0
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: tBX_RET 14, $noreg, implicit killed $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0
bb.0: bb.0:
successors: %bb.1(0x30000000), %bb.2(0x50000000) successors: %bb.1(0x30000000), %bb.2(0x50000000)
liveins: $r0, $r1 liveins: $r0, $r1
renamable $r0, $cpsr = tADDrr killed renamable $r0, renamable $r1, 14, $noreg renamable $r0, $cpsr = tADDrr killed renamable $r0, renamable $r1, 14, $noreg
tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr
renamable $r1 = t2ADDrs renamable $r0, killed renamable $r1, 18, 14, $noreg, $noreg renamable $r1 = t2ADDrs renamable $r0, killed renamable $r1, 18, 14, $noreg, $noreg
t2Bcc %bb.1, 0, killed $cpsr t2Bcc %bb.1, 0, killed $cpsr
Show All 14 Lines
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$r0', virtual-reg: '' } - { reg: '$r0', virtual-reg: '' }
- { reg: '$r1', virtual-reg: '' } - { reg: '$r1', virtual-reg: '' }
body: | body: |
; CHECK-LABEL: name: test_redefined ; CHECK-LABEL: name: test_redefined
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000) ; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000)
; CHECK: tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr ; CHECK: liveins: $r0, $r1
; CHECK: renamable $r0 = t2ADDrs killed renamable $r0, killed renamable $r1, 18, 14, $noreg, $noreg ; CHECK: tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.2, 0, killed $cpsr ; CHECK: renamable $r0 = t2ADDrs killed renamable $r0, killed renamable $r1, 18, 14 /* CC::al */, $noreg, $noreg
; CHECK: tBcc %bb.2, 0 /* CC::eq */, killed $cpsr
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) ; CHECK: liveins: $r0
; CHECK: tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.x)
; CHECK: tTAILJMPdND @c, 14 /* CC::al */, $noreg, implicit $sp, implicit $sp, implicit killed $r0
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: tBX_RET 14, $noreg, implicit killed $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0
bb.0: bb.0:
successors: %bb.1(0x30000000), %bb.2(0x50000000) successors: %bb.1(0x30000000), %bb.2(0x50000000)
liveins: $r0, $r1 liveins: $r0, $r1
tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr
renamable $r0 = t2ADDrs killed renamable $r0, killed renamable $r1, 18, 14, $noreg, $noreg renamable $r0 = t2ADDrs killed renamable $r0, killed renamable $r1, 18, 14, $noreg, $noreg
t2Bcc %bb.1, 0, killed $cpsr t2Bcc %bb.1, 0, killed $cpsr
Show All 13 Lines
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$r0', virtual-reg: '' } - { reg: '$r0', virtual-reg: '' }
- { reg: '$r1', virtual-reg: '' } - { reg: '$r1', virtual-reg: '' }
body: | body: |
; CHECK-LABEL: name: test_notredefined ; CHECK-LABEL: name: test_notredefined
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000) ; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000)
; CHECK: renamable $r1 = t2ADDrs renamable $r0, killed renamable $r1, 18, 14, $noreg, $noreg ; CHECK: liveins: $r0, $r1
; CHECK: renamable $r1 = t2ADDrs renamable $r0, killed renamable $r1, 18, 14 /* CC::al */, $noreg, $noreg
; CHECK: tCBZ $r0, %bb.2 ; CHECK: tCBZ $r0, %bb.2
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) ; CHECK: liveins: $r0
; CHECK: tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.x)
; CHECK: tTAILJMPdND @c, 14 /* CC::al */, $noreg, implicit $sp, implicit $sp, implicit killed $r0
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: tBX_RET 14, $noreg, implicit killed $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0
bb.0: bb.0:
successors: %bb.1(0x30000000), %bb.2(0x50000000) successors: %bb.1(0x30000000), %bb.2(0x50000000)
liveins: $r0, $r1 liveins: $r0, $r1
tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr
renamable $r1 = t2ADDrs renamable $r0, killed renamable $r1, 18, 14, $noreg, $noreg renamable $r1 = t2ADDrs renamable $r0, killed renamable $r1, 18, 14, $noreg, $noreg
t2Bcc %bb.1, 0, killed $cpsr t2Bcc %bb.1, 0, killed $cpsr
Show All 13 Lines
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$r0', virtual-reg: '' } - { reg: '$r0', virtual-reg: '' }
- { reg: '$r1', virtual-reg: '' } - { reg: '$r1', virtual-reg: '' }
body: | body: |
; CHECK-LABEL: name: test_notcmp ; CHECK-LABEL: name: test_notcmp
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000) ; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000)
; CHECK: tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr ; CHECK: liveins: $r0, $r1
; CHECK: renamable $r1, $cpsr = tADDrr renamable $r0, killed renamable $r1, 14, $noreg ; CHECK: tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.2, 0, killed $cpsr ; CHECK: renamable $r1, $cpsr = tADDrr renamable $r0, killed renamable $r1, 14 /* CC::al */, $noreg
; CHECK: tBcc %bb.2, 0 /* CC::eq */, killed $cpsr
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) ; CHECK: liveins: $r0
; CHECK: tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.x)
; CHECK: tTAILJMPdND @c, 14 /* CC::al */, $noreg, implicit $sp, implicit $sp, implicit killed $r0
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: tBX_RET 14, $noreg, implicit killed $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0
bb.0: bb.0:
successors: %bb.1(0x30000000), %bb.2(0x50000000) successors: %bb.1(0x30000000), %bb.2(0x50000000)
liveins: $r0, $r1 liveins: $r0, $r1
tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr
renamable $r1, $cpsr = tADDrr renamable $r0, killed renamable $r1, 14, $noreg renamable $r1, $cpsr = tADDrr renamable $r0, killed renamable $r1, 14, $noreg
t2Bcc %bb.1, 0, killed $cpsr t2Bcc %bb.1, 0, killed $cpsr
Show All 13 Lines
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$r0', virtual-reg: '' } - { reg: '$r0', virtual-reg: '' }
- { reg: '$r1', virtual-reg: '' } - { reg: '$r1', virtual-reg: '' }
body: | body: |
; CHECK-LABEL: name: test_killflag_1 ; CHECK-LABEL: name: test_killflag_1
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000) ; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000)
; CHECK: renamable $r0 = t2ADDrs killed renamable $r0, killed renamable $r0, 18, 14, $noreg, $noreg ; CHECK: liveins: $r0, $r1
; CHECK: renamable $r0 = t2ADDrs killed renamable $r0, killed renamable $r0, 18, 14 /* CC::al */, $noreg, $noreg
; CHECK: tCBZ killed $r1, %bb.2 ; CHECK: tCBZ killed $r1, %bb.2
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) ; CHECK: liveins: $r0
; CHECK: tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.x)
; CHECK: tTAILJMPdND @c, 14 /* CC::al */, $noreg, implicit $sp, implicit $sp, implicit killed $r0
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: tBX_RET 14, $noreg, implicit killed $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0
bb.0: bb.0:
successors: %bb.1(0x30000000), %bb.2(0x50000000) successors: %bb.1(0x30000000), %bb.2(0x50000000)
liveins: $r0, $r1 liveins: $r0, $r1
tCMPi8 killed renamable $r1, 0, 14, $noreg, implicit-def $cpsr tCMPi8 killed renamable $r1, 0, 14, $noreg, implicit-def $cpsr
renamable $r0 = t2ADDrs killed renamable $r0, killed renamable $r0, 18, 14, $noreg, $noreg renamable $r0 = t2ADDrs killed renamable $r0, killed renamable $r0, 18, 14, $noreg, $noreg
t2Bcc %bb.1, 0, killed $cpsr t2Bcc %bb.1, 0, killed $cpsr
Show All 13 Lines
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$r0', virtual-reg: '' } - { reg: '$r0', virtual-reg: '' }
- { reg: '$r1', virtual-reg: '' } - { reg: '$r1', virtual-reg: '' }
body: | body: |
; CHECK-LABEL: name: test_killflag_2 ; CHECK-LABEL: name: test_killflag_2
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000) ; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000)
; CHECK: renamable $r0 = t2ADDrs renamable $r1, killed renamable $r0, 18, 14, $noreg, $noreg ; CHECK: liveins: $r0, $r1
; CHECK: renamable $r0 = t2ADDrs renamable $r1, killed renamable $r0, 18, 14 /* CC::al */, $noreg, $noreg
; CHECK: tCBZ killed $r1, %bb.2 ; CHECK: tCBZ killed $r1, %bb.2
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) ; CHECK: liveins: $r0
; CHECK: tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.x)
; CHECK: tTAILJMPdND @c, 14 /* CC::al */, $noreg, implicit $sp, implicit $sp, implicit killed $r0
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: tBX_RET 14, $noreg, implicit killed $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0
bb.0: bb.0:
successors: %bb.1(0x30000000), %bb.2(0x50000000) successors: %bb.1(0x30000000), %bb.2(0x50000000)
liveins: $r0, $r1 liveins: $r0, $r1
tCMPi8 renamable $r1, 0, 14, $noreg, implicit-def $cpsr tCMPi8 renamable $r1, 0, 14, $noreg, implicit-def $cpsr
renamable $r0 = t2ADDrs killed renamable $r1, killed renamable $r0, 18, 14, $noreg, $noreg renamable $r0 = t2ADDrs killed renamable $r1, killed renamable $r0, 18, 14, $noreg, $noreg
t2Bcc %bb.1, 0, killed $cpsr t2Bcc %bb.1, 0, killed $cpsr
Show All 13 Lines
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$r0', virtual-reg: '' } - { reg: '$r0', virtual-reg: '' }
- { reg: '$r1', virtual-reg: '' } - { reg: '$r1', virtual-reg: '' }
body: | body: |
; CHECK-LABEL: name: test_cpsr ; CHECK-LABEL: name: test_cpsr
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000) ; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000)
; CHECK: tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr ; CHECK: liveins: $r0, $r1
; CHECK: tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 0, 8, implicit-def $itstate ; CHECK: t2IT 0, 8, implicit-def $itstate
; CHECK: renamable $r1 = t2ADDri killed renamable $r1, 1, 1, $cpsr, $noreg, implicit killed $itstate ; CHECK: renamable $r1 = t2ADDri killed renamable $r1, 1, 1 /* CC::ne */, $cpsr, $noreg, implicit killed $itstate
; CHECK: tBcc %bb.2, 0, killed $cpsr ; CHECK: tBcc %bb.2, 0 /* CC::eq */, killed $cpsr
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) ; CHECK: liveins: $r0
; CHECK: tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.x)
; CHECK: tTAILJMPdND @c, 14 /* CC::al */, $noreg, implicit $sp, implicit $sp, implicit killed $r0
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: tBX_RET 14, $noreg, implicit killed $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0
bb.0: bb.0:
successors: %bb.1(0x30000000), %bb.2(0x50000000) successors: %bb.1(0x30000000), %bb.2(0x50000000)
liveins: $r0, $r1 liveins: $r0, $r1
tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr
t2IT 0, 8, implicit-def $itstate t2IT 0, 8, implicit-def $itstate
renamable $r1 = t2ADDri killed renamable $r1, 1, 1, $cpsr, $noreg, implicit killed $itstate renamable $r1 = t2ADDri killed renamable $r1, 1, 1, $cpsr, $noreg, implicit killed $itstate
t2Bcc %bb.1, 0, killed $cpsr t2Bcc %bb.1, 0, killed $cpsr
Show All 13 Lines

llvm/test/CodeGen/Thumb2/fp16-stacksplot.mir

Show All 10 Linesstack:
- { id: 1, name: '', type: default, offset: 0, size: 1200, alignment: 4, - { id: 1, name: '', type: default, offset: 0, size: 1200, alignment: 4,
stack-id: default, callee-saved-register: '', callee-saved-restored: true, stack-id: default, callee-saved-register: '', callee-saved-restored: true,
local-offset: -2, debug-info-variable: '', debug-info-expression: '', local-offset: -2, debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' } debug-info-location: '' }
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: func0 ; CHECK-LABEL: name: func0
; CHECK: liveins: $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr ; CHECK: liveins: $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr
; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8
; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12
; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16 ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16
; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20 ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24
; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28 ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28
; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36
; CHECK: $sp = frame-setup t2SUBspImm killed $sp, 1208, 14, $noreg, $noreg ; CHECK: $sp = frame-setup t2SUBspImm killed $sp, 1208, 14 /* CC::al */, $noreg, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 1244 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 1244
; CHECK: $r0 = IMPLICIT_DEF ; CHECK: $r0 = IMPLICIT_DEF
; CHECK: $r1 = IMPLICIT_DEF ; CHECK: $r1 = IMPLICIT_DEF
; CHECK: $r2 = IMPLICIT_DEF ; CHECK: $r2 = IMPLICIT_DEF
; CHECK: $r3 = IMPLICIT_DEF ; CHECK: $r3 = IMPLICIT_DEF
; CHECK: $r4 = IMPLICIT_DEF ; CHECK: $r4 = IMPLICIT_DEF
; CHECK: $r5 = IMPLICIT_DEF ; CHECK: $r5 = IMPLICIT_DEF
; CHECK: $r6 = IMPLICIT_DEF ; CHECK: $r6 = IMPLICIT_DEF
; CHECK: $r7 = IMPLICIT_DEF ; CHECK: $r7 = IMPLICIT_DEF
; CHECK: $r8 = IMPLICIT_DEF ; CHECK: $r8 = IMPLICIT_DEF
; CHECK: $r9 = IMPLICIT_DEF ; CHECK: $r9 = IMPLICIT_DEF
; CHECK: $r10 = IMPLICIT_DEF ; CHECK: $r10 = IMPLICIT_DEF
; CHECK: $r11 = IMPLICIT_DEF ; CHECK: $r11 = IMPLICIT_DEF
; CHECK: $r12 = IMPLICIT_DEF ; CHECK: $r12 = IMPLICIT_DEF
; CHECK: $lr = IMPLICIT_DEF ; CHECK: $lr = IMPLICIT_DEF
; CHECK: t2STRi12 killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.2) ; CHECK: t2STRi12 killed $r0, $sp, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.2)
; CHECK: $r0 = t2ADDri killed $sp, 1024, 14, $noreg, $noreg ; CHECK: $r0 = t2ADDri killed $sp, 1024, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $s4 = VLDRH killed $r0, 91, 14, $noreg :: (dereferenceable load 2 from %stack.0) ; CHECK: renamable $s4 = VLDRH killed $r0, 91, 14, $noreg :: (dereferenceable load 2 from %stack.0)
; CHECK: $r0 = t2LDRi12 $sp, 0, 14, $noreg :: (load 4 from %stack.2) ; CHECK: $r0 = t2LDRi12 $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.2)
; CHECK: KILL $r0 ; CHECK: KILL $r0
; CHECK: KILL $r1 ; CHECK: KILL $r1
; CHECK: KILL $r2 ; CHECK: KILL $r2
; CHECK: KILL $r3 ; CHECK: KILL $r3
; CHECK: KILL $r4 ; CHECK: KILL $r4
; CHECK: KILL $r5 ; CHECK: KILL $r5
; CHECK: KILL $r6 ; CHECK: KILL $r6
; CHECK: KILL $r7 ; CHECK: KILL $r7
Show All 38 Lines

llvm/test/CodeGen/Thumb2/high-reg-spill.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass regallocfast %s -o - | FileCheck %s # RUN: llc -run-pass regallocfast %s -o - | FileCheck %s
# This test examines register allocation and spilling with Fast Register # This test examines register allocation and spilling with Fast Register
# Allocator. The test uses inline assembler that requests an input variable to # Allocator. The test uses inline assembler that requests an input variable to
# be loaded in a high register but at the same time has r12 marked as clobbered. # be loaded in a high register but at the same time has r12 marked as clobbered.
# The allocator initially satisfies the load request by selecting r12 but then # The allocator initially satisfies the load request by selecting r12 but then
# needs to spill this register when it reaches the INLINEASM instruction and # needs to spill this register when it reaches the INLINEASM instruction and
# notices its clobber definition. # notices its clobber definition.
Show All 21 Lines
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: hgpr } - { id: 0, class: hgpr }
- { id: 1, class: tgpr } - { id: 1, class: tgpr }
stack: stack:
- { id: 0, name: i, size: 4, alignment: 4, stack-id: default, local-offset: -4 } - { id: 0, name: i, size: 4, alignment: 4, stack-id: default, local-offset: -4 }
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: constraint_h
; CHECK: renamable $r0 = tLDRspi %stack.0.i, 0, 14 /* CC::al */, $noreg :: (dereferenceable load 4 from %ir.i)
; CHECK: renamable $r12 = COPY killed renamable $r0
; CHECK: t2STRi12 killed $r12, %stack.1, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.1)
; CHECK: $r8 = t2LDRi12 %stack.1, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.1)
; CHECK: INLINEASM &"@ $0", 1, 589833, renamable $r8, 12, implicit-def early-clobber $r12
; CHECK: tBX_RET 14 /* CC::al */, $noreg
%1:tgpr = tLDRspi %stack.0.i, 0, 14, $noreg :: (dereferenceable load 4 from %ir.i) %1:tgpr = tLDRspi %stack.0.i, 0, 14, $noreg :: (dereferenceable load 4 from %ir.i)
%0:hgpr = COPY %1 %0:hgpr = COPY %1
INLINEASM &"@ $0", 1, 589833, %0, 12, implicit-def early-clobber $r12 INLINEASM &"@ $0", 1, 589833, %0, 12, implicit-def early-clobber $r12
tBX_RET 14, $noreg tBX_RET 14, $noreg
... ...
# CHECK: bb.0.entry:
# CHECK-NEXT: renamable $r0 = tLDRspi %stack.0.i, 0, 14, $noreg :: (dereferenceable load 4 from %ir.i)
# CHECK-NEXT: renamable $r12 = COPY killed renamable $r0
# CHECK-NEXT: t2STRi12 killed $r12, %stack.1, 0, 14, $noreg :: (store 4 into %stack.1)
# CHECK-NEXT: $r8 = t2LDRi12 %stack.1, 0, 14, $noreg :: (load 4 from %stack.1)
# CHECK-NEXT: INLINEASM &"@ $0", 1, 589833, renamable $r8, 12, implicit-def early-clobber $r12
# CHECK-NEXT: tBX_RET 14, $noreg

llvm/test/CodeGen/Thumb2/ifcvt-cbz.mir

Show All 20 Lines - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
body: | body: |
; CHECK-LABEL: name: f1 ; CHECK-LABEL: name: f1
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: liveins: $r0, $lr, $r7 ; CHECK: liveins: $r0, $lr, $r7
; CHECK: t2CMPri killed renamable $r0, 1, 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPri killed renamable $r0, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBX_RET 1, killed $cpsr ; CHECK: tBX_RET 1 /* CC::ne */, killed $cpsr
; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r7, killed $lr ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r7, killed $lr
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: $r0 = t2MOVi 0, 14, $noreg, $noreg ; CHECK: $r0 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: tBL 14, $noreg, @fn, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit-def $sp, implicit-def dead $r0 ; CHECK: tBL 14 /* CC::al */, $noreg, @fn, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit-def $sp, implicit-def dead $r0
; CHECK: $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r7, def $lr ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr
; CHECK: tBX_RET 14, $noreg ; CHECK: tBX_RET 14 /* CC::al */, $noreg
bb.0: bb.0:
successors: %bb.1(0x40000000), %bb.2(0x40000000) successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $r0, $lr, $r7 liveins: $r0, $lr, $r7
t2CMPri killed renamable $r0, 1, 14, $noreg, implicit-def $cpsr t2CMPri killed renamable $r0, 1, 14, $noreg, implicit-def $cpsr
t2Bcc %bb.2, 1, killed $cpsr t2Bcc %bb.2, 1, killed $cpsr
bb.1: bb.1:
Show All 26 Linesstack:
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
body: | body: |
; CHECK-LABEL: name: f2 ; CHECK-LABEL: name: f2
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK: liveins: $r0, $lr, $r7 ; CHECK: liveins: $r0, $lr, $r7
; CHECK: t2CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPri killed renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2Bcc %bb.2, 1, killed $cpsr ; CHECK: t2Bcc %bb.2, 1 /* CC::ne */, killed $cpsr
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: liveins: $r7, $lr ; CHECK: liveins: $r7, $lr
; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r7, killed $lr ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r7, killed $lr
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: $r0 = t2MOVi 0, 14, $noreg, $noreg ; CHECK: $r0 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: tBL 14, $noreg, @fn, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit-def $sp, implicit-def dead $r0 ; CHECK: tBL 14 /* CC::al */, $noreg, @fn, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit-def $sp, implicit-def dead $r0
; CHECK: $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r7, def $lr ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr
; CHECK: tBX_RET 14, $noreg ; CHECK: tBX_RET 14 /* CC::al */, $noreg
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: liveins: $lr, $r7 ; CHECK: liveins: $lr, $r7
; CHECK: tBX_RET 14, $noreg ; CHECK: tBX_RET 14 /* CC::al */, $noreg
bb.0: bb.0:
successors: %bb.1(0x40000000), %bb.2(0x40000000) successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $r0, $lr, $r7 liveins: $r0, $lr, $r7
t2CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr t2CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr
t2Bcc %bb.2, 1, killed $cpsr t2Bcc %bb.2, 1, killed $cpsr
bb.1: bb.1:
Show All 26 Linesstack:
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
body: | body: |
; CHECK-LABEL: name: f3 ; CHECK-LABEL: name: f3
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK: liveins: $r0, $lr, $r7 ; CHECK: liveins: $r0, $lr, $r7
; CHECK: t2CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr ; CHECK: t2CMPri killed renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: $r1 = t2MOVi 0, 14, $noreg, $noreg ; CHECK: $r1 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2Bcc %bb.2, 1, killed $cpsr ; CHECK: t2Bcc %bb.2, 1 /* CC::ne */, killed $cpsr
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: liveins: $r7, $lr ; CHECK: liveins: $r7, $lr
; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r7, killed $lr ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r7, killed $lr
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: $r0 = t2MOVi 0, 14, $noreg, $noreg ; CHECK: $r0 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: tBL 14, $noreg, @fn, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit-def $sp, implicit-def dead $r0 ; CHECK: tBL 14 /* CC::al */, $noreg, @fn, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit-def $sp, implicit-def dead $r0
; CHECK: $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r7, def $lr ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr
; CHECK: tBX_RET 14, $noreg ; CHECK: tBX_RET 14 /* CC::al */, $noreg
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: liveins: $lr, $r7 ; CHECK: liveins: $lr, $r7
; CHECK: tBX_RET 14, $noreg ; CHECK: tBX_RET 14 /* CC::al */, $noreg
bb.0: bb.0:
successors: %bb.1(0x40000000), %bb.2(0x40000000) successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $r0, $lr, $r7 liveins: $r0, $lr, $r7
t2CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr t2CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr
$r1 = t2MOVi 0, 14, $noreg, $noreg $r1 = t2MOVi 0, 14, $noreg, $noreg
t2Bcc %bb.2, 1, killed $cpsr t2Bcc %bb.2, 1, killed $cpsr
Show All 18 Lines

llvm/test/CodeGen/Thumb2/mve-stacksplot.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - %s -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -run-pass=stack-protector -run-pass=prologepilog | FileCheck %s # RUN: llc -o - %s -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -run-pass=stack-protector -run-pass=prologepilog | FileCheck %s
--- ---
name: func0 name: func0
tracksRegLiveness: true tracksRegLiveness: true
stack: stack:
- { id: 0, name: '', type: default, offset: 0, size: 16, alignment: 4, - { id: 0, name: '', type: default, offset: 0, size: 16, alignment: 4,
stack-id: default, callee-saved-register: '', callee-saved-restored: true, stack-id: default, callee-saved-register: '', callee-saved-restored: true,
local-offset: -16, debug-info-variable: '', debug-info-expression: '', local-offset: -16, debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' } debug-info-location: '' }
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: func0 ; CHECK-LABEL: name: func0
; CHECK: liveins: $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr ; CHECK: liveins: $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr
; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8
; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12
; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16 ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16
; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20 ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24
; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28 ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28
; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36
; CHECK: $sp = frame-setup tSUBspi $sp, 5, 14, $noreg ; CHECK: $sp = frame-setup tSUBspi $sp, 5, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 56 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 56
; CHECK: $r0 = IMPLICIT_DEF ; CHECK: $r0 = IMPLICIT_DEF
; CHECK: $r1 = IMPLICIT_DEF ; CHECK: $r1 = IMPLICIT_DEF
; CHECK: $r2 = IMPLICIT_DEF ; CHECK: $r2 = IMPLICIT_DEF
; CHECK: $r3 = IMPLICIT_DEF ; CHECK: $r3 = IMPLICIT_DEF
; CHECK: $r4 = IMPLICIT_DEF ; CHECK: $r4 = IMPLICIT_DEF
; CHECK: $r5 = IMPLICIT_DEF ; CHECK: $r5 = IMPLICIT_DEF
; CHECK: $r6 = IMPLICIT_DEF ; CHECK: $r6 = IMPLICIT_DEF
; CHECK: $r7 = IMPLICIT_DEF ; CHECK: $r7 = IMPLICIT_DEF
; CHECK: $r8 = IMPLICIT_DEF ; CHECK: $r8 = IMPLICIT_DEF
; CHECK: $r9 = IMPLICIT_DEF ; CHECK: $r9 = IMPLICIT_DEF
; CHECK: $r10 = IMPLICIT_DEF ; CHECK: $r10 = IMPLICIT_DEF
; CHECK: $r11 = IMPLICIT_DEF ; CHECK: $r11 = IMPLICIT_DEF
; CHECK: $r12 = IMPLICIT_DEF ; CHECK: $r12 = IMPLICIT_DEF
; CHECK: $lr = IMPLICIT_DEF ; CHECK: $lr = IMPLICIT_DEF
; CHECK: t2STRi12 killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.1) ; CHECK: t2STRi12 killed $r0, $sp, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.1)
; CHECK: $r0 = tMOVr killed $sp, 14, $noreg ; CHECK: $r0 = tMOVr killed $sp, 14 /* CC::al */, $noreg
; CHECK: renamable $q2 = MVE_VLDRBU32 killed $r0, 16, 0, $noreg :: (load 4 from %stack.0 + 12) ; CHECK: renamable $q2 = MVE_VLDRBU32 killed $r0, 16, 0, $noreg :: (load 4 from %stack.0 + 12)
; CHECK: $r0 = t2LDRi12 $sp, 0, 14, $noreg :: (load 4 from %stack.1) ; CHECK: $r0 = t2LDRi12 $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.1)
; CHECK: KILL $r0 ; CHECK: KILL $r0
; CHECK: KILL $r1 ; CHECK: KILL $r1
; CHECK: KILL $r2 ; CHECK: KILL $r2
; CHECK: KILL $r3 ; CHECK: KILL $r3
; CHECK: KILL $r4 ; CHECK: KILL $r4
; CHECK: KILL $r5 ; CHECK: KILL $r5
; CHECK: KILL $r6 ; CHECK: KILL $r6
; CHECK: KILL $r7 ; CHECK: KILL $r7
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Linesstack:
- { id: 1, name: '', type: default, offset: 0, size: 1200, alignment: 4, - { id: 1, name: '', type: default, offset: 0, size: 1200, alignment: 4,
stack-id: default, callee-saved-register: '', callee-saved-restored: true, stack-id: default, callee-saved-register: '', callee-saved-restored: true,
local-offset: -1200, debug-info-variable: '', debug-info-expression: '', local-offset: -1200, debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' } debug-info-location: '' }
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: func1 ; CHECK-LABEL: name: func1
; CHECK: liveins: $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr ; CHECK: liveins: $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr
; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8
; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12
; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16 ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16
; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20 ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24
; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28 ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28
; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36
; CHECK: $sp = frame-setup t2SUBspImm12 killed $sp, 1220, 14, $noreg ; CHECK: $sp = frame-setup t2SUBspImm12 killed $sp, 1220, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 1256 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 1256
; CHECK: $r0 = IMPLICIT_DEF ; CHECK: $r0 = IMPLICIT_DEF
; CHECK: $r1 = IMPLICIT_DEF ; CHECK: $r1 = IMPLICIT_DEF
; CHECK: $r2 = IMPLICIT_DEF ; CHECK: $r2 = IMPLICIT_DEF
; CHECK: $r3 = IMPLICIT_DEF ; CHECK: $r3 = IMPLICIT_DEF
; CHECK: $r4 = IMPLICIT_DEF ; CHECK: $r4 = IMPLICIT_DEF
; CHECK: $r5 = IMPLICIT_DEF ; CHECK: $r5 = IMPLICIT_DEF
; CHECK: $r6 = IMPLICIT_DEF ; CHECK: $r6 = IMPLICIT_DEF
; CHECK: $r7 = IMPLICIT_DEF ; CHECK: $r7 = IMPLICIT_DEF
; CHECK: $r8 = IMPLICIT_DEF ; CHECK: $r8 = IMPLICIT_DEF
; CHECK: $r9 = IMPLICIT_DEF ; CHECK: $r9 = IMPLICIT_DEF
; CHECK: $r10 = IMPLICIT_DEF ; CHECK: $r10 = IMPLICIT_DEF
; CHECK: $r11 = IMPLICIT_DEF ; CHECK: $r11 = IMPLICIT_DEF
; CHECK: $r12 = IMPLICIT_DEF ; CHECK: $r12 = IMPLICIT_DEF
; CHECK: $lr = IMPLICIT_DEF ; CHECK: $lr = IMPLICIT_DEF
; CHECK: t2STRi12 killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.2) ; CHECK: t2STRi12 killed $r0, $sp, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.2)
; CHECK: $r0 = t2ADDri killed $sp, 1152, 14, $noreg, $noreg ; CHECK: $r0 = t2ADDri killed $sp, 1152, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q2 = MVE_VLDRBU8 killed $r0, 52, 0, $noreg :: (load 4 from %stack.0) ; CHECK: renamable $q2 = MVE_VLDRBU8 killed $r0, 52, 0, $noreg :: (load 4 from %stack.0)
; CHECK: $r0 = t2LDRi12 $sp, 0, 14, $noreg :: (load 4 from %stack.2) ; CHECK: $r0 = t2LDRi12 $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.2)
; CHECK: KILL $r0 ; CHECK: KILL $r0
; CHECK: KILL $r1 ; CHECK: KILL $r1
; CHECK: KILL $r2 ; CHECK: KILL $r2
; CHECK: KILL $r3 ; CHECK: KILL $r3
; CHECK: KILL $r4 ; CHECK: KILL $r4
; CHECK: KILL $r5 ; CHECK: KILL $r5
; CHECK: KILL $r6 ; CHECK: KILL $r6
; CHECK: KILL $r7 ; CHECK: KILL $r7
Show All 38 Lines

llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-1-pred.mir

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Linesbody: |
bb.0: bb.0:
liveins: $lr, $q0, $q1, $q2, $q3, $q4, $q5, $r0, $r1, $r2, $r7, $r8, $r9, $r10, $r11, $r12 liveins: $lr, $q0, $q1, $q2, $q3, $q4, $q5, $r0, $r1, $r2, $r7, $r8, $r9, $r10, $r11, $r12
; CHECK-LABEL: name: vpt_2_blocks_1_pred ; CHECK-LABEL: name: vpt_2_blocks_1_pred
; CHECK: successors: %bb.0(0x80000000) ; CHECK: successors: %bb.0(0x80000000)
; CHECK: liveins: $lr, $q0, $q1, $q2, $q3, $q4, $q5, $r0, $r1, $r2, $r7, $r8, $r9, $r10, $r11, $r12 ; CHECK: liveins: $lr, $q0, $q1, $q2, $q3, $q4, $q5, $r0, $r1, $r2, $r7, $r8, $r9, $r10, $r11, $r12
; CHECK: renamable $r4 = t2ADDrr renamable $r2, renamable $r10, 14, $noreg, $noreg ; CHECK: renamable $r4 = t2ADDrr renamable $r2, renamable $r10, 14 /* CC::al */, $noreg, $noreg
; CHECK: BUNDLE implicit-def $vpr, implicit-def $q6, implicit-def $d12, implicit-def $s24, implicit-def $s25, implicit-def $d13, implicit-def $s26, implicit-def $s27, implicit $q1, implicit $q5, implicit killed $r4 { ; CHECK: BUNDLE implicit-def $vpr, implicit-def $q6, implicit-def $d12, implicit-def $s24, implicit-def $s25, implicit-def $d13, implicit-def $s26, implicit-def $s27, implicit $q1, implicit $q5, implicit killed $r4 {
; CHECK: MVE_VPTv4u32 8, renamable $q1, renamable $q5, 2, implicit-def $vpr ; CHECK: MVE_VPTv4u32 8, renamable $q1, renamable $q5, 2, implicit-def $vpr
; CHECK: renamable $q6 = MVE_VLDRBU32 killed renamable $r4, 0, 1, internal renamable $vpr ; CHECK: renamable $q6 = MVE_VLDRBU32 killed renamable $r4, 0, 1, internal renamable $vpr
; CHECK: } ; CHECK: }
; CHECK: renamable $r4 = t2ADDrr renamable $r11, renamable $r10, 14, $noreg, $noreg ; CHECK: renamable $r4 = t2ADDrr renamable $r11, renamable $r10, 14 /* CC::al */, $noreg, $noreg
; CHECK: BUNDLE implicit-def $q7, implicit-def $d14, implicit-def $s28, implicit-def $s29, implicit-def $d15, implicit-def $s30, implicit-def $s31, implicit killed $vpr, implicit killed $r4 { ; CHECK: BUNDLE implicit-def $q7, implicit-def $d14, implicit-def $s28, implicit-def $s29, implicit-def $d15, implicit-def $s30, implicit-def $s31, implicit killed $vpr, implicit killed $r4 {
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $q7 = MVE_VLDRBU32 killed renamable $r4, 0, 1, killed renamable $vpr ; CHECK: renamable $q7 = MVE_VLDRBU32 killed renamable $r4, 0, 1, killed renamable $vpr
; CHECK: } ; CHECK: }
; CHECK: t2LoopEnd renamable $lr, %bb.0, implicit-def dead $cpsr ; CHECK: t2LoopEnd renamable $lr, %bb.0, implicit-def dead $cpsr
; CHECK: t2B %bb.0, 14, $noreg ; CHECK: t2B %bb.0, 14 /* CC::al */, $noreg
renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q5, 2, 0, $noreg renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q5, 2, 0, $noreg
renamable $r4 = t2ADDrr renamable $r2, renamable $r10, 14, $noreg, $noreg renamable $r4 = t2ADDrr renamable $r2, renamable $r10, 14, $noreg, $noreg
renamable $q6 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr renamable $q6 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr
renamable $r4 = t2ADDrr renamable $r11, renamable $r10, 14, $noreg, $noreg renamable $r4 = t2ADDrr renamable $r11, renamable $r10, 14, $noreg, $noreg
renamable $q7 = MVE_VLDRBU32 killed renamable $r4, 0, 1, killed renamable $vpr renamable $q7 = MVE_VLDRBU32 killed renamable $r4, 0, 1, killed renamable $vpr
t2LoopEnd renamable $lr, %bb.0, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.0, implicit-def dead $cpsr
t2B %bb.0, 14, $noreg t2B %bb.0, 14, $noreg
... ...

llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-2-preds.mir

Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
stack: [] stack: []
constants: [] constants: []
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $q0, $q1, $q2, $r0, $r1 liveins: $q0, $q1, $q2, $r0, $r1
; CHECK-LABEL: name: vpt_2_blocks_2_preds ; CHECK-LABEL: name: vpt_2_blocks_2_preds
; CHECK: liveins: $q0, $q1, $q2, $r0, $r1 ; CHECK: liveins: $q0, $q1, $q2, $r0, $r1
; CHECK: $vpr = VMSR_P0 killed $r0, 14, $noreg ; CHECK: $vpr = VMSR_P0 killed $r0, 14 /* CC::al */, $noreg
; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3 ; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3
; CHECK: BUNDLE implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit killed $vpr, implicit killed $q1, implicit $q2, implicit killed $q3 { ; CHECK: BUNDLE implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit killed $vpr, implicit killed $q1, implicit $q2, implicit killed $q3 {
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, killed renamable $vpr, killed renamable $q3 ; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, killed renamable $vpr, killed renamable $q3
; CHECK: } ; CHECK: }
; CHECK: $vpr = VMSR_P0 killed $r1, 14, $noreg ; CHECK: $vpr = VMSR_P0 killed $r1, 14 /* CC::al */, $noreg
; CHECK: BUNDLE implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $q3, implicit killed $q2, implicit killed $q0 { ; CHECK: BUNDLE implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $q3, implicit killed $q2, implicit killed $q0 {
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 ; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
; CHECK: } ; CHECK: }
; CHECK: tBX_RET 14, $noreg, implicit $q0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
$vpr = VMSR_P0 killed $r0, 14, $noreg $vpr = VMSR_P0 killed $r0, 14, $noreg
$q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3 $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3
renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, killed renamable $vpr, killed renamable $q3 renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, killed renamable $vpr, killed renamable $q3
$vpr = VMSR_P0 killed $r1, 14, $noreg $vpr = VMSR_P0 killed $r1, 14, $noreg
renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
tBX_RET 14, $noreg, implicit $q0 tBX_RET 14, $noreg, implicit $q0
... ...

llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
fixedStack: [] fixedStack: []
stack: [] stack: []
constants: [] constants: []
body: | body: |
; CHECK-LABEL: name: vpt_2_blocks_ctrl_flow ; CHECK-LABEL: name: vpt_2_blocks_ctrl_flow
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $q0, $q1, $q2, $r0 ; CHECK: liveins: $q0, $q1, $q2, $r0
; CHECK: $vpr = VMSR_P0 killed $r0, 14, $noreg ; CHECK: $vpr = VMSR_P0 killed $r0, 14 /* CC::al */, $noreg
; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3 ; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3
; CHECK: BUNDLE implicit-def dead $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit $vpr, implicit killed $q1, implicit $q2, implicit killed $q3 { ; CHECK: BUNDLE implicit-def dead $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit $vpr, implicit killed $q1, implicit $q2, implicit killed $q3 {
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3 ; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3
; CHECK: renamable $q1 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, internal renamable $q3, 1, renamable $vpr, undef renamable $q1 ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, internal renamable $q3, 1, renamable $vpr, undef renamable $q1
; CHECK: } ; CHECK: }
; CHECK: bb.1.bb2: ; CHECK: bb.1.bb2:
; CHECK: liveins: $q0, $q1, $q2, $q3, $vpr ; CHECK: liveins: $q0, $q1, $q2, $q3, $vpr
; CHECK: BUNDLE implicit-def dead $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $q1, implicit killed $q2, implicit killed $q3, implicit killed $q0 { ; CHECK: BUNDLE implicit-def dead $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $q1, implicit killed $q2, implicit killed $q3, implicit killed $q0 {
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3 ; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3
; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 ; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
; CHECK: } ; CHECK: }
; CHECK: tBX_RET 14, $noreg, implicit $q0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
bb.0.entry: bb.0.entry:
liveins: $q0, $q1, $q2, $r0 liveins: $q0, $q1, $q2, $r0
$vpr = VMSR_P0 killed $r0, 14, $noreg $vpr = VMSR_P0 killed $r0, 14, $noreg
$q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3 $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3
renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3 renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3
renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, renamable $q3, 1, renamable $vpr, undef renamable $q1 renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, renamable $q3, 1, renamable $vpr, undef renamable $q1
bb.1.bb2: bb.1.bb2:
liveins: $q0, $q1, $q2, $q3, $vpr liveins: $q0, $q1, $q2, $q3, $vpr
renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3 renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3
renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
tBX_RET 14, $noreg, implicit $q0 tBX_RET 14, $noreg, implicit $q0
... ...

llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
constants: [] constants: []
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $q0, $q1, $q2, $r0 liveins: $q0, $q1, $q2, $r0
; CHECK-LABEL: name: vpt_2_blocks_non_consecutive_ins ; CHECK-LABEL: name: vpt_2_blocks_non_consecutive_ins
; CHECK: liveins: $q0, $q1, $q2, $r0 ; CHECK: liveins: $q0, $q1, $q2, $r0
; CHECK: $vpr = VMSR_P0 killed $r0, 14, $noreg ; CHECK: $vpr = VMSR_P0 killed $r0, 14 /* CC::al */, $noreg
; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3 ; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3
; CHECK: BUNDLE implicit-def dead $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit $vpr, implicit killed $q1, implicit $q2, implicit killed $q3 { ; CHECK: BUNDLE implicit-def dead $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit $vpr, implicit killed $q1, implicit $q2, implicit killed $q3 {
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3 ; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3
; CHECK: renamable $q1 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, internal renamable $q3, 1, renamable $vpr, undef renamable $q1 ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, internal renamable $q3, 1, renamable $vpr, undef renamable $q1
; CHECK: } ; CHECK: }
; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3 ; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3
; CHECK: BUNDLE implicit-def dead $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $q1, implicit killed $q2, implicit killed $q3, implicit killed $q0 { ; CHECK: BUNDLE implicit-def dead $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $q1, implicit killed $q2, implicit killed $q3, implicit killed $q0 {
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3 ; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3
; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 ; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
; CHECK: } ; CHECK: }
; CHECK: tBX_RET 14, $noreg, implicit $q0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
$vpr = VMSR_P0 killed $r0, 14, $noreg $vpr = VMSR_P0 killed $r0, 14, $noreg
$q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3 $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3
renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3 renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3
renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, renamable $q3, 1, renamable $vpr, undef renamable $q1 renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, renamable $q3, 1, renamable $vpr, undef renamable $q1
$q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3 $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3
renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3 renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3
renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
tBX_RET 14, $noreg, implicit $q0 tBX_RET 14, $noreg, implicit $q0
... ...

llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks.mir

Show First 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
stack: [] stack: []
constants: [] constants: []
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $q0, $q1, $q2, $q3, $r0 liveins: $q0, $q1, $q2, $q3, $r0
; CHECK-LABEL: name: vpt_2_blocks ; CHECK-LABEL: name: vpt_2_blocks
; CHECK: liveins: $q0, $q1, $q2, $q3, $r0 ; CHECK: liveins: $q0, $q1, $q2, $q3, $r0
; CHECK: $vpr = VMSR_P0 killed $r0, 14, $noreg ; CHECK: $vpr = VMSR_P0 killed $r0, 14 /* CC::al */, $noreg
; CHECK: BUNDLE implicit-def dead $q2, implicit-def $d4, implicit-def $s8, implicit-def $s9, implicit-def $d5, implicit-def $s10, implicit-def $s11, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit $vpr, implicit killed $q2, implicit $q3, implicit killed $q0 { ; CHECK: BUNDLE implicit-def dead $q2, implicit-def $d4, implicit-def $s8, implicit-def $s9, implicit-def $d5, implicit-def $s10, implicit-def $s11, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit $vpr, implicit killed $q2, implicit $q3, implicit killed $q0 {
; CHECK: MVE_VPST 1, implicit $vpr ; CHECK: MVE_VPST 1, implicit $vpr
; CHECK: renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, undef renamable $q2 ; CHECK: renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, undef renamable $q2
; CHECK: renamable $q2 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q2, internal renamable $q2, 1, renamable $vpr, internal undef renamable $q2 ; CHECK: renamable $q2 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q2, internal renamable $q2, 1, renamable $vpr, internal undef renamable $q2
; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q2, renamable $q3, 1, renamable $vpr, killed renamable $q0 ; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q2, renamable $q3, 1, renamable $vpr, killed renamable $q0
; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q0, renamable $q3, 1, renamable $vpr, internal undef renamable $q0 ; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q0, renamable $q3, 1, renamable $vpr, internal undef renamable $q0
; CHECK: } ; CHECK: }
; CHECK: BUNDLE implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit killed $vpr, implicit killed $q0, implicit killed $q3, implicit killed $q1 { ; CHECK: BUNDLE implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit killed $vpr, implicit killed $q0, implicit killed $q3, implicit killed $q1 {
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q0, killed renamable $q3, 1, killed renamable $vpr, killed renamable $q1 ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q0, killed renamable $q3, 1, killed renamable $vpr, killed renamable $q1
; CHECK: } ; CHECK: }
; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0 ; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0
; CHECK: tBX_RET 14, $noreg, implicit $q0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
$vpr = VMSR_P0 killed $r0, 14, $noreg $vpr = VMSR_P0 killed $r0, 14, $noreg
renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, undef renamable $q2 renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, undef renamable $q2
renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q2, 1, renamable $vpr, undef renamable $q2 renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q2, 1, renamable $vpr, undef renamable $q2
renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, killed renamable $q0 renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, killed renamable $q0
renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q0, renamable $q3, 1, renamable $vpr, undef renamable $q0 renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q0, renamable $q3, 1, renamable $vpr, undef renamable $q0
renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q0, killed renamable $q3, 1, killed renamable $vpr, killed renamable $q1 renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q0, killed renamable $q3, 1, killed renamable $vpr, killed renamable $q1
$q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0 $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0
tBX_RET 14, $noreg, implicit $q0 tBX_RET 14, $noreg, implicit $q0
... ...

llvm/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir

Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
stack: [] stack: []
constants: [] constants: []
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $q0, $q1, $q2, $r0 liveins: $q0, $q1, $q2, $r0
; CHECK-LABEL: name: vpt_3_blocks_kill_vpr ; CHECK-LABEL: name: vpt_3_blocks_kill_vpr
; CHECK: liveins: $q0, $q1, $q2, $r0 ; CHECK: liveins: $q0, $q1, $q2, $r0
; CHECK: $vpr = VMSR_P0 killed $r0, 14, $noreg ; CHECK: $vpr = VMSR_P0 killed $r0, 14 /* CC::al */, $noreg
; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3 ; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3
; CHECK: BUNDLE implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit $vpr, implicit killed $q1, implicit $q2, implicit killed $q3 { ; CHECK: BUNDLE implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit $vpr, implicit killed $q1, implicit $q2, implicit killed $q3 {
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3 ; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3
; CHECK: } ; CHECK: }
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg ; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
; CHECK: BUNDLE implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit $vpr, implicit killed $q3, implicit undef $q1 { ; CHECK: BUNDLE implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit $vpr, implicit killed $q3, implicit undef $q1 {
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, renamable $q3, 1, renamable $vpr, undef renamable $q1 ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, renamable $q3, 1, renamable $vpr, undef renamable $q1
; CHECK: } ; CHECK: }
; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3 ; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3
; CHECK: BUNDLE implicit-def dead $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $q1, implicit killed $q2, implicit killed $q3, implicit killed $q0 { ; CHECK: BUNDLE implicit-def dead $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $q1, implicit killed $q2, implicit killed $q3, implicit killed $q0 {
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3 ; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3
; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 ; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
; CHECK: } ; CHECK: }
; CHECK: tBX_RET 14, $noreg, implicit $q0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
$vpr = VMSR_P0 killed $r0, 14, $noreg $vpr = VMSR_P0 killed $r0, 14, $noreg
$q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3 $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3
renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3 renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, renamable $q3, 1, renamable $vpr, undef renamable $q1 renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, renamable $q3, 1, renamable $vpr, undef renamable $q1
$q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3 $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3
renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3 renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3
renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
tBX_RET 14, $noreg, implicit $q0 tBX_RET 14, $noreg, implicit $q0
... ...

llvm/test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir

Show First 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
stack: [] stack: []
constants: [] constants: []
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $q0, $q1, $q2, $r0 liveins: $q0, $q1, $q2, $r0
; CHECK-LABEL: name: vpt_block_1_ins ; CHECK-LABEL: name: vpt_block_1_ins
; CHECK: liveins: $q0, $q1, $q2, $r0 ; CHECK: liveins: $q0, $q1, $q2, $r0
; CHECK: $vpr = VMSR_P0 killed $r0, 14, $noreg ; CHECK: $vpr = VMSR_P0 killed $r0, 14 /* CC::al */, $noreg
; CHECK: BUNDLE implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $q1, implicit killed $q2, implicit killed $q0 { ; CHECK: BUNDLE implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $q1, implicit killed $q2, implicit killed $q0 {
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 ; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
; CHECK: } ; CHECK: }
; CHECK: tBX_RET 14, $noreg, implicit $q0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
$vpr = VMSR_P0 killed $r0, 14, $noreg $vpr = VMSR_P0 killed $r0, 14, $noreg
renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
tBX_RET 14, $noreg, implicit $q0 tBX_RET 14, $noreg, implicit $q0
... ...

llvm/test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir

Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
stack: [] stack: []
constants: [] constants: []
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $q0, $q1, $q2, $q3, $r0 liveins: $q0, $q1, $q2, $q3, $r0
; CHECK-LABEL: name: vpt_block_2_ins ; CHECK-LABEL: name: vpt_block_2_ins
; CHECK: liveins: $q0, $q1, $q2, $q3, $r0 ; CHECK: liveins: $q0, $q1, $q2, $q3, $r0
; CHECK: $vpr = VMSR_P0 killed $r0, 14, $noreg ; CHECK: $vpr = VMSR_P0 killed $r0, 14 /* CC::al */, $noreg
; CHECK: BUNDLE implicit-def dead $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit killed $vpr, implicit killed $q2, implicit killed $q3, implicit killed $q0, implicit killed $q1 { ; CHECK: BUNDLE implicit-def dead $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit killed $vpr, implicit killed $q2, implicit killed $q3, implicit killed $q0, implicit killed $q1 {
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, killed renamable $q0 ; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, killed renamable $q0
; CHECK: renamable $q1 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q0, killed renamable $q3, 1, killed renamable $vpr, killed renamable $q1 ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q0, killed renamable $q3, 1, killed renamable $vpr, killed renamable $q1
; CHECK: } ; CHECK: }
; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0 ; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0
; CHECK: tBX_RET 14, $noreg, implicit $q0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
$vpr = VMSR_P0 killed $r0, 14, $noreg $vpr = VMSR_P0 killed $r0, 14, $noreg
renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, killed renamable $q0 renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, killed renamable $q0
renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q0, killed renamable $q3, 1, killed renamable $vpr, killed renamable $q1 renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q0, killed renamable $q3, 1, killed renamable $vpr, killed renamable $q1
$q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0 $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0
tBX_RET 14, $noreg, implicit $q0 tBX_RET 14, $noreg, implicit $q0
... ...

llvm/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
stack: [] stack: []
constants: [] constants: []
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $q0, $q1, $q2, $q3, $r0 liveins: $q0, $q1, $q2, $q3, $r0
; CHECK-LABEL: name: vpt_block_4_ins ; CHECK-LABEL: name: vpt_block_4_ins
; CHECK: liveins: $q0, $q1, $q2, $q3, $r0 ; CHECK: liveins: $q0, $q1, $q2, $q3, $r0
; CHECK: $vpr = VMSR_P0 killed $r0, 14, $noreg ; CHECK: $vpr = VMSR_P0 killed $r0, 14 /* CC::al */, $noreg
; CHECK: BUNDLE implicit-def dead $q2, implicit-def $d4, implicit-def $s8, implicit-def $s9, implicit-def $d5, implicit-def $s10, implicit-def $s11, implicit-def dead $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit killed $vpr, implicit killed $q2, implicit killed $q3, implicit killed $q0, implicit killed $q1 { ; CHECK: BUNDLE implicit-def dead $q2, implicit-def $d4, implicit-def $s8, implicit-def $s9, implicit-def $d5, implicit-def $s10, implicit-def $s11, implicit-def dead $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit killed $vpr, implicit killed $q2, implicit killed $q3, implicit killed $q0, implicit killed $q1 {
; CHECK: MVE_VPST 1, implicit $vpr ; CHECK: MVE_VPST 1, implicit $vpr
; CHECK: renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, undef renamable $q2 ; CHECK: renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, undef renamable $q2
; CHECK: renamable $q2 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q2, internal renamable $q2, 1, renamable $vpr, internal undef renamable $q2 ; CHECK: renamable $q2 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q2, internal renamable $q2, 1, renamable $vpr, internal undef renamable $q2
; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q2, renamable $q3, 1, renamable $vpr, killed renamable $q0 ; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q2, renamable $q3, 1, renamable $vpr, killed renamable $q0
; CHECK: renamable $q1 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q0, killed renamable $q3, 1, killed renamable $vpr, killed renamable $q1 ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q0, killed renamable $q3, 1, killed renamable $vpr, killed renamable $q1
; CHECK: } ; CHECK: }
; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0 ; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0
; CHECK: tBX_RET 14, $noreg, implicit $q0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
$vpr = VMSR_P0 killed $r0, 14, $noreg $vpr = VMSR_P0 killed $r0, 14, $noreg
renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, undef renamable $q2 renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, undef renamable $q2
renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q2, 1, renamable $vpr, undef renamable $q2 renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q2, 1, renamable $vpr, undef renamable $q2
renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, killed renamable $q0 renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, killed renamable $q0
renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q0, killed renamable $q3, 1, killed renamable $vpr, killed renamable $q1 renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q0, killed renamable $q3, 1, killed renamable $vpr, killed renamable $q1
$q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0 $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0
tBX_RET 14, $noreg, implicit $q0 tBX_RET 14, $noreg, implicit $q0
... ...

llvm/test/CodeGen/Thumb2/mve-vpt-block-fold-vcmp.mir

Show First 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $q0, $r0, $r1, $r2, $lr liveins: $q0, $r0, $r1, $r2, $lr
; CHECK-LABEL: name: foo ; CHECK-LABEL: name: foo
; CHECK: liveins: $q0, $r0, $r1, $r2, $lr ; CHECK: liveins: $q0, $r0, $r1, $r2, $lr
; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r7, killed $lr ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r7, killed $lr
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: $r7 = frame-setup tMOVr killed $sp, 14, $noreg ; CHECK: $r7 = frame-setup tMOVr killed $sp, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
; CHECK: renamable $r12 = t2LDRi12 $r7, 16, 14, $noreg :: (load 4 from %fixed-stack.2) ; CHECK: renamable $r12 = t2LDRi12 $r7, 16, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.2)
; CHECK: renamable $lr = t2LDRi12 $r7, 12, 14, $noreg :: (load 4 from %fixed-stack.1) ; CHECK: renamable $lr = t2LDRi12 $r7, 12, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.1)
; CHECK: renamable $r3 = t2LDRi12 $r7, 8, 14, $noreg :: (load 4 from %fixed-stack.0) ; CHECK: renamable $r3 = t2LDRi12 $r7, 8, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.0)
; CHECK: BUNDLE implicit-def $vpr, implicit-def dead $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit $q0, implicit $zr, implicit killed $r0, implicit killed $r3, implicit killed $r1, implicit killed $lr { ; CHECK: BUNDLE implicit-def $vpr, implicit-def dead $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit $q0, implicit $zr, implicit killed $r0, implicit killed $r3, implicit killed $r1, implicit killed $lr {
; CHECK: MVE_VPTv4f32r 1, renamable $q0, $zr, 10, implicit-def $vpr ; CHECK: MVE_VPTv4f32r 1, renamable $q0, $zr, 10, implicit-def $vpr
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r0, 0, 1, internal renamable $vpr :: (load 16 from %ir.src, align 4) ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r0, 0, 1, internal renamable $vpr :: (load 16 from %ir.src, align 4)
; CHECK: MVE_VSTRWU32 internal killed renamable $q0, killed renamable $r3, 0, 1, internal renamable $vpr :: (store 16 into %ir.dest, align 4) ; CHECK: MVE_VSTRWU32 internal killed renamable $q0, killed renamable $r3, 0, 1, internal renamable $vpr :: (store 16 into %ir.dest, align 4)
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 1, internal renamable $vpr :: (load 16 from %ir.src2, align 4) ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 1, internal renamable $vpr :: (load 16 from %ir.src2, align 4)
; CHECK: MVE_VSTRWU32 internal killed renamable $q0, killed renamable $lr, 0, 1, internal renamable $vpr :: (store 16 into %ir.dest2, align 4) ; CHECK: MVE_VSTRWU32 internal killed renamable $q0, killed renamable $lr, 0, 1, internal renamable $vpr :: (store 16 into %ir.dest2, align 4)
; CHECK: } ; CHECK: }
; CHECK: BUNDLE implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $r2, implicit killed $r12 { ; CHECK: BUNDLE implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $r2, implicit killed $r12 {
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 1, renamable $vpr :: (load 16 from %ir.src3, align 4) ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 1, renamable $vpr :: (load 16 from %ir.src3, align 4)
; CHECK: MVE_VSTRWU32 internal renamable $q0, killed renamable $r12, 0, 1, killed renamable $vpr :: (store 16 into %ir.dest3, align 4) ; CHECK: MVE_VSTRWU32 internal renamable $q0, killed renamable $r12, 0, 1, killed renamable $vpr :: (store 16 into %ir.dest3, align 4)
; CHECK: } ; CHECK: }
; CHECK: $sp = t2LDMIA_RET $sp, 14, $noreg, def $r7, def $pc, implicit $q0 ; CHECK: $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r7, def $pc, implicit $q0
$sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r7, killed $lr $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r7, killed $lr
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
$r7 = frame-setup tMOVr killed $sp, 14, $noreg $r7 = frame-setup tMOVr killed $sp, 14, $noreg
frame-setup CFI_INSTRUCTION def_cfa_register $r7 frame-setup CFI_INSTRUCTION def_cfa_register $r7
renamable $r12 = t2LDRi12 $r7, 16, 14, $noreg :: (load 4 from %fixed-stack.1) renamable $r12 = t2LDRi12 $r7, 16, 14, $noreg :: (load 4 from %fixed-stack.1)
renamable $lr = t2LDRi12 $r7, 12, 14, $noreg :: (load 4 from %fixed-stack.2) renamable $lr = t2LDRi12 $r7, 12, 14, $noreg :: (load 4 from %fixed-stack.2)
Show All 11 Lines

llvm/test/CodeGen/Thumb2/mve-vpt-block-optnone.mir

Show First 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
constants: [] constants: []
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $q0, $q1, $q2, $r0 liveins: $q0, $q1, $q2, $r0
; CHECK-LABEL: name: test_vminnmq_m_f32_v2 ; CHECK-LABEL: name: test_vminnmq_m_f32_v2
; CHECK: liveins: $q0, $q1, $q2, $r0 ; CHECK: liveins: $q0, $q1, $q2, $r0
; CHECK: $vpr = VMSR_P0 killed $r0, 14, $noreg ; CHECK: $vpr = VMSR_P0 killed $r0, 14 /* CC::al */, $noreg
; CHECK: BUNDLE implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $q1, implicit killed $q2, implicit killed $q0 { ; CHECK: BUNDLE implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $q1, implicit killed $q2, implicit killed $q0 {
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 ; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
; CHECK: } ; CHECK: }
; CHECK: tBX_RET 14, $noreg, implicit $q0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
$vpr = VMSR_P0 killed $r0, 14, $noreg $vpr = VMSR_P0 killed $r0, 14, $noreg
renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
tBX_RET 14, $noreg, implicit $q0 tBX_RET 14, $noreg, implicit $q0
... ...

llvm/test/CodeGen/Thumb2/mve-vpt-nots.mir

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Lines bb.0.entry:
; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, internal killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, internal killed renamable $vpr
; CHECK: } ; CHECK: }
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg ; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
; CHECK: BUNDLE implicit-def $vpr, implicit killed $vpr, implicit killed $q2, implicit $zr { ; CHECK: BUNDLE implicit-def $vpr, implicit killed $vpr, implicit killed $q2, implicit $zr {
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr
; CHECK: } ; CHECK: }
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr
; CHECK: tBX_RET 14, $noreg, implicit $q0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg
renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr
renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr
tBX_RET 14, $noreg, implicit $q0 tBX_RET 14, $noreg, implicit $q0
... ...
Show All 17 Linesbody: |
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg ; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
; CHECK: bb.1.bb2: ; CHECK: bb.1.bb2:
; CHECK: liveins: $q0, $q1, $q2, $vpr ; CHECK: liveins: $q0, $q1, $q2, $vpr
; CHECK: BUNDLE implicit-def $vpr, implicit killed $vpr, implicit killed $q2, implicit $zr { ; CHECK: BUNDLE implicit-def $vpr, implicit killed $vpr, implicit killed $q2, implicit $zr {
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr
; CHECK: } ; CHECK: }
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr
; CHECK: tBX_RET 14, $noreg, implicit $q0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
bb.0.entry: bb.0.entry:
liveins: $q0, $q1, $q2 liveins: $q0, $q1, $q2
renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg
renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
bb.1.bb2: bb.1.bb2:
Show All 24 Lines bb.0.entry:
; CHECK: } ; CHECK: }
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg ; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg ; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
; CHECK: BUNDLE implicit-def $vpr, implicit killed $vpr, implicit killed $q2, implicit $zr { ; CHECK: BUNDLE implicit-def $vpr, implicit killed $vpr, implicit killed $q2, implicit $zr {
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr
; CHECK: } ; CHECK: }
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr
; CHECK: tBX_RET 14, $noreg, implicit $q0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg
renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr
renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr
tBX_RET 14, $noreg, implicit $q0 tBX_RET 14, $noreg, implicit $q0
Show All 21 Lines bb.0.entry:
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg ; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg ; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg ; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
; CHECK: BUNDLE implicit-def $vpr, implicit killed $vpr, implicit killed $q2, implicit $zr { ; CHECK: BUNDLE implicit-def $vpr, implicit killed $vpr, implicit killed $q2, implicit $zr {
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr
; CHECK: } ; CHECK: }
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr
; CHECK: tBX_RET 14, $noreg, implicit $q0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg
renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr
Show All 18 Lines bb.0.entry:
; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg ; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg ; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
; CHECK: BUNDLE implicit-def $vpr, implicit killed $vpr, implicit $q1, implicit $zr, implicit killed $q2 { ; CHECK: BUNDLE implicit-def $vpr, implicit killed $vpr, implicit $q1, implicit $zr, implicit killed $q2 {
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr
; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, internal killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, internal killed renamable $vpr
; CHECK: } ; CHECK: }
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr
; CHECK: tBX_RET 14, $noreg, implicit $q0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr
renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr
renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr
tBX_RET 14, $noreg, implicit $q0 tBX_RET 14, $noreg, implicit $q0
... ...
Show All 19 Lines bb.0.entry:
; CHECK: } ; CHECK: }
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg ; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
; CHECK: BUNDLE implicit-def $vpr, implicit killed $vpr, implicit killed $q2, implicit $zr { ; CHECK: BUNDLE implicit-def $vpr, implicit killed $vpr, implicit killed $q2, implicit $zr {
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr
; CHECK: } ; CHECK: }
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg ; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr
; CHECK: tBX_RET 14, $noreg, implicit $q0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr
tBX_RET 14, $noreg, implicit $q0 tBX_RET 14, $noreg, implicit $q0
... ...

llvm/test/CodeGen/Thumb2/mve-vpt-preuse.mir

Show First 20 Lines • Show All 59 Lines • ▼ Show 20 Linesbody: |
bb.0: bb.0:
liveins: $lr, $q0, $q1, $q2, $q3, $q4, $q5, $r0, $r1, $r2, $r7, $r8, $r9, $r10, $r11, $r12 liveins: $lr, $q0, $q1, $q2, $q3, $q4, $q5, $r0, $r1, $r2, $r7, $r8, $r9, $r10, $r11, $r12
; CHECK-LABEL: name: vpt_preuse ; CHECK-LABEL: name: vpt_preuse
; CHECK: successors: %bb.0(0x80000000) ; CHECK: successors: %bb.0(0x80000000)
; CHECK: liveins: $lr, $q0, $q1, $q2, $q3, $q4, $q5, $r0, $r1, $r2, $r7, $r8, $r9, $r10, $r11, $r12 ; CHECK: liveins: $lr, $q0, $q1, $q2, $q3, $q4, $q5, $r0, $r1, $r2, $r7, $r8, $r9, $r10, $r11, $r12
; CHECK: renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q5, 2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q5, 2, 0, $noreg
; CHECK: renamable $r4 = t2ADDrr renamable $r2, renamable $r10, 14, $noreg, $noreg ; CHECK: renamable $r4 = t2ADDrr renamable $r2, renamable $r10, 14 /* CC::al */, $noreg, $noreg
; CHECK: VSTR_P0_off renamable $vpr, $sp, 0, 14, $noreg ; CHECK: VSTR_P0_off renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg
; CHECK: BUNDLE implicit-def $q6, implicit-def $d12, implicit-def $s24, implicit-def $s25, implicit-def $d13, implicit-def $s26, implicit-def $s27, implicit $vpr, implicit killed $r4 { ; CHECK: BUNDLE implicit-def $q6, implicit-def $d12, implicit-def $s24, implicit-def $s25, implicit-def $d13, implicit-def $s26, implicit-def $s27, implicit $vpr, implicit killed $r4 {
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $q6 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr ; CHECK: renamable $q6 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr
; CHECK: } ; CHECK: }
; CHECK: t2LoopEnd renamable $lr, %bb.0, implicit-def dead $cpsr ; CHECK: t2LoopEnd renamable $lr, %bb.0, implicit-def dead $cpsr
; CHECK: t2B %bb.0, 14, $noreg ; CHECK: t2B %bb.0, 14 /* CC::al */, $noreg
renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q5, 2, 0, $noreg renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q5, 2, 0, $noreg
renamable $r4 = t2ADDrr renamable $r2, renamable $r10, 14, $noreg, $noreg renamable $r4 = t2ADDrr renamable $r2, renamable $r10, 14, $noreg, $noreg
VSTR_P0_off renamable $vpr, $sp, 0, 14, $noreg VSTR_P0_off renamable $vpr, $sp, 0, 14, $noreg
renamable $q6 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr renamable $q6 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr
t2LoopEnd renamable $lr, %bb.0, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.0, implicit-def dead $cpsr
t2B %bb.0, 14, $noreg t2B %bb.0, 14, $noreg
... ...

llvm/test/CodeGen/Thumb2/peephole-addsub.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=peephole-opt -verify-machineinstrs -o - %s | FileCheck %s # RUN: llc -run-pass=peephole-opt -verify-machineinstrs -o - %s | FileCheck %s
--- | --- |
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv7-none-eabi" target triple = "thumbv7-none-eabi"
define i32 @test(i32 %a, i32 %b) { define i32 @test(i32 %a, i32 %b) {
unreachable unreachable
} }
... ...
--- ---
name: test name: test
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$r1', virtual-reg: '%1' } - { reg: '$r1', virtual-reg: '%1' }
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $r0, $r1 liveins: $r0, $r1
; CHECK-LABEL: name: test
; CHECK: liveins: $r0, $r1
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[t2ADDrr:%[0-9]+]]:gprnopc = t2ADDrr [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg, $noreg
; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[t2ADDrr]], 0, 14 /* CC::al */, $noreg, def $cpsr
; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 0, 7 /* CC::vc */, $cpsr
; CHECK: $r0 = COPY [[t2MOVCCi]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%1:rgpr = COPY $r1 %1:rgpr = COPY $r1
%0:rgpr = COPY $r0 %0:rgpr = COPY $r0
%2:rgpr = t2MOVi 1, 14, $noreg, $noreg %2:rgpr = t2MOVi 1, 14, $noreg, $noreg
%3:gprnopc = t2ADDrr %0, %1, 14, $noreg, $noreg %3:gprnopc = t2ADDrr %0, %1, 14, $noreg, $noreg
%4:rgpr = t2SUBri %3, 0, 14, $noreg, def dead $cpsr %4:rgpr = t2SUBri %3, 0, 14, $noreg, def dead $cpsr
t2CMPri killed %3, 0, 14, $noreg, implicit-def $cpsr t2CMPri killed %3, 0, 14, $noreg, implicit-def $cpsr
%5:rgpr = t2MOVCCi %2, 0, 7, $cpsr %5:rgpr = t2MOVCCi %2, 0, 7, $cpsr
$r0 = COPY %5 $r0 = COPY %5
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
# CHECK-LABEL: name: test
# CHECK: %3:gprnopc = t2ADDrr %0, %1, 14, $noreg, $noreg
# CHECK-NEXT: %4:rgpr = t2SUBri %3, 0, 14, $noreg, def $cpsr
# CHECK-NEXT: %5:rgpr = t2MOVCCi %2, 0, 7, $cpsr
... ...

llvm/test/CodeGen/Thumb2/peephole-cmp.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=peephole-opt -verify-machineinstrs -o - %s | FileCheck %s # RUN: llc -run-pass=peephole-opt -verify-machineinstrs -o - %s | FileCheck %s
--- | --- |
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv7m-none-none-eabi" target triple = "thumbv7m-none-none-eabi"
define i32 @test_addir_frameindex(i32 %a) { define i32 @test_addir_frameindex(i32 %a) {
%f = alloca i32 %f = alloca i32
ret i32 %a ret i32 %a
} }
... ...
--- ---
name: test_addir_frameindex name: test_addir_frameindex
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
stack: stack:
- { id: 0, name: f, type: default, offset: 0, size: 1, alignment: 4, - { id: 0, name: f, type: default, offset: 0, size: 1, alignment: 4,
stack-id: default, callee-saved-register: '', callee-saved-restored: true, stack-id: default, callee-saved-register: '', callee-saved-restored: true,
local-offset: -4, debug-info-variable: '', debug-info-expression: '', local-offset: -4, debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' } debug-info-location: '' }
body: | body: |
; CHECK-LABEL: name: test_addir_frameindex
; CHECK: bb.0:
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri %stack.0.f, 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2CMPrr [[t2ADDri]], [[COPY]], 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2Bcc %bb.2, 3 /* CC::lo */, $cpsr
; CHECK: t2B %bb.1, 14 /* CC::al */, $noreg
; CHECK: bb.1:
; CHECK: $r0 = COPY [[t2ADDri]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg
; CHECK: bb.2:
; CHECK: $r0 = COPY [[COPY]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg
bb.0: bb.0:
successors: %bb.2(0x40000000), %bb.1(0x40000000) successors: %bb.2(0x40000000), %bb.1(0x40000000)
liveins: $r0 liveins: $r0
%0:rgpr = COPY $r0 %0:rgpr = COPY $r0
%1:rgpr = t2ADDri %stack.0.f, 0, 14, $noreg, $noreg %1:rgpr = t2ADDri %stack.0.f, 0, 14, $noreg, $noreg
t2CMPrr %1, %0, 14, $noreg, implicit-def $cpsr t2CMPrr %1, %0, 14, $noreg, implicit-def $cpsr
t2Bcc %bb.2, 3, $cpsr t2Bcc %bb.2, 3, $cpsr
t2B %bb.1, 14, $noreg t2B %bb.1, 14, $noreg
bb.1: bb.1:
$r0 = COPY %1 $r0 = COPY %1
tBX_RET 14, $noreg tBX_RET 14, $noreg
bb.2: bb.2:
$r0 = COPY %0 $r0 = COPY %0
tBX_RET 14, $noreg tBX_RET 14, $noreg
# CHECK-LABEL: name: test_addir_frameindex
# CHECK: %1:rgpr = t2ADDri %stack.0.f, 0, 14, $noreg, $noreg
# CHECK-NEXT: t2CMPrr %1, %0, 14, $noreg, implicit-def $cpsr
# CHECK-NEXT: t2Bcc %bb.2, 3, $cpsr
... ...

llvm/test/CodeGen/Thumb2/t2-teq-reduce.mir

Show First 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
liveins: liveins:
- { reg: '$r0', virtual-reg: '' } - { reg: '$r0', virtual-reg: '' }
- { reg: '$r1', virtual-reg: '' } - { reg: '$r1', virtual-reg: '' }
body: | body: |
; CHECK-LABEL: name: reg_reg_it_block ; CHECK-LABEL: name: reg_reg_it_block
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1 ; CHECK: liveins: $r0, $r1
; CHECK: t2B %bb.2, 14, $noreg ; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg
; CHECK: bb.1.while.body.end: ; CHECK: bb.1.while.body.end:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1 ; CHECK: liveins: $r0, $r1
; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.next.i.14) ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.next.i.14)
; CHECK: tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: BUNDLE implicit-def dead $itstate, implicit killed $cpsr, implicit $r0 { ; CHECK: BUNDLE implicit-def dead $itstate, implicit killed $cpsr, implicit $r0 {
; CHECK: t2IT 0, 8, implicit-def $itstate ; CHECK: t2IT 0, 8, implicit-def $itstate
; CHECK: tBX_RET 0, killed $cpsr, implicit $r0, implicit internal killed $itstate ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit internal killed $itstate
; CHECK: } ; CHECK: }
; CHECK: bb.2.while.begin: ; CHECK: bb.2.while.begin:
; CHECK: successors: %bb.4(0x04000000), %bb.3(0x7c000000) ; CHECK: successors: %bb.4(0x04000000), %bb.3(0x7c000000)
; CHECK: liveins: $r0, $r1 ; CHECK: liveins: $r0, $r1
; CHECK: renamable $r2 = tLDRi renamable $r0, 1, 14, $noreg :: (load 4 from %ir.info.i) ; CHECK: renamable $r2 = tLDRi renamable $r0, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.info.i)
; CHECK: renamable $r2 = tLDRHi killed renamable $r2, 0, 14, $noreg :: (load 2 from %ir.data16.i1) ; CHECK: renamable $r2 = tLDRHi killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (load 2 from %ir.data16.i1)
; CHECK: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg ; CHECK: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::al */, $noreg
; CHECK: t2Bcc %bb.4, 0, killed $cpsr ; CHECK: t2Bcc %bb.4, 0 /* CC::eq */, killed $cpsr
; CHECK: bb.3.while.body.a: ; CHECK: bb.3.while.body.a:
; CHECK: successors: %bb.4(0x4207fef8), %bb.1(0x3df80108) ; CHECK: successors: %bb.4(0x4207fef8), %bb.1(0x3df80108)
; CHECK: liveins: $r0, $r1 ; CHECK: liveins: $r0, $r1
; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.next.i2) ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.next.i2)
; CHECK: tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: BUNDLE implicit-def dead $itstate, implicit-def dead $r2, implicit-def $cpsr, implicit $r0, implicit killed $cpsr, implicit $r1 { ; CHECK: BUNDLE implicit-def dead $itstate, implicit-def dead $r2, implicit-def $cpsr, implicit $r0, implicit killed $cpsr, implicit $r1 {
; CHECK: t2IT 1, 30, implicit-def $itstate ; CHECK: t2IT 1, 30, implicit-def $itstate
; CHECK: renamable $r2 = tLDRi renamable $r0, 1, 1, $cpsr, implicit internal $itstate :: (load 4 from %ir.info.i.1) ; CHECK: renamable $r2 = tLDRi renamable $r0, 1, 1 /* CC::ne */, $cpsr, implicit internal $itstate :: (load 4 from %ir.info.i.1)
; CHECK: renamable $r2 = tLDRHi internal killed renamable $r2, 0, 1, $cpsr, implicit internal killed $r2, implicit internal $itstate :: (load 2 from %ir.data16.i.13) ; CHECK: renamable $r2 = tLDRHi internal killed renamable $r2, 0, 1 /* CC::ne */, $cpsr, implicit internal killed $r2, implicit internal $itstate :: (load 2 from %ir.data16.i.13)
; CHECK: t2TEQrr internal killed renamable $r2, renamable $r1, 1, killed $cpsr, implicit-def $cpsr, implicit internal killed $itstate ; CHECK: t2TEQrr internal killed renamable $r2, renamable $r1, 1 /* CC::ne */, killed $cpsr, implicit-def $cpsr, implicit internal killed $itstate
; CHECK: } ; CHECK: }
; CHECK: t2Bcc %bb.1, 1, killed $cpsr ; CHECK: t2Bcc %bb.1, 1 /* CC::ne */, killed $cpsr
; CHECK: bb.4.exit: ; CHECK: bb.4.exit:
; CHECK: liveins: $r0 ; CHECK: liveins: $r0
; CHECK: tBX_RET 14, $noreg, implicit killed $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1 liveins: $r0, $r1
t2B %bb.1, 14, $noreg t2B %bb.1, 14, $noreg
bb.3.while.body.end: bb.3.while.body.end:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
liveins: liveins:
- { reg: '$r0', virtual-reg: '' } - { reg: '$r0', virtual-reg: '' }
- { reg: '$r1', virtual-reg: '' } - { reg: '$r1', virtual-reg: '' }
body: | body: |
; CHECK-LABEL: name: op_not_killed ; CHECK-LABEL: name: op_not_killed
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $r0, $r1 ; CHECK: liveins: $r0, $r1
; CHECK: $r2 = tMOVr $r0, 14, $noreg ; CHECK: $r2 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: bb.1.while.begin: ; CHECK: bb.1.while.begin:
; CHECK: successors: %bb.5(0x04000000), %bb.2(0x7c000000) ; CHECK: successors: %bb.5(0x04000000), %bb.2(0x7c000000)
; CHECK: liveins: $r1, $r2 ; CHECK: liveins: $r1, $r2
; CHECK: renamable $r0 = tLDRi renamable $r2, 1, 14, $noreg :: (load 4 from %ir.info.i) ; CHECK: renamable $r0 = tLDRi renamable $r2, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.info.i)
; CHECK: renamable $r0 = tLDRHi killed renamable $r0, 0, 14, $noreg :: (load 2 from %ir.data16.i1) ; CHECK: renamable $r0 = tLDRHi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 2 from %ir.data16.i1)
; CHECK: t2TEQrr renamable $r0, renamable $r1, 14, $noreg, implicit-def $cpsr ; CHECK: t2TEQrr renamable $r0, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2Bcc %bb.5, 0, killed $cpsr ; CHECK: t2Bcc %bb.5, 0 /* CC::eq */, killed $cpsr
; CHECK: bb.2.while.body.a: ; CHECK: bb.2.while.body.a:
; CHECK: successors: %bb.5(0x04000000), %bb.3(0x7c000000) ; CHECK: successors: %bb.5(0x04000000), %bb.3(0x7c000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: renamable $r2 = tLDRi killed renamable $r2, 0, 14, $noreg :: (load 4 from %ir.next.i2) ; CHECK: renamable $r2 = tLDRi killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.next.i2)
; CHECK: tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2Bcc %bb.5, 0, killed $cpsr ; CHECK: t2Bcc %bb.5, 0 /* CC::eq */, killed $cpsr
; CHECK: bb.3.it.block: ; CHECK: bb.3.it.block:
; CHECK: successors: %bb.5(0x04000000), %bb.4(0x7c000000) ; CHECK: successors: %bb.5(0x04000000), %bb.4(0x7c000000)
; CHECK: liveins: $r1, $r2 ; CHECK: liveins: $r1, $r2
; CHECK: renamable $r0 = tLDRi renamable $r2, 1, 14, $noreg :: (load 4 from %ir.info.i.1) ; CHECK: renamable $r0 = tLDRi renamable $r2, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.info.i.1)
; CHECK: renamable $r0 = tLDRHi killed renamable $r0, 0, 14, $noreg :: (load 2 from %ir.data16.i.13) ; CHECK: renamable $r0 = tLDRHi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 2 from %ir.data16.i.13)
; CHECK: t2TEQrr renamable $r0, renamable $r1, 14, $noreg, implicit-def $cpsr ; CHECK: t2TEQrr renamable $r0, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2Bcc %bb.5, 0, killed $cpsr ; CHECK: t2Bcc %bb.5, 0 /* CC::eq */, killed $cpsr
; CHECK: bb.4.while.body.end: ; CHECK: bb.4.while.body.end:
; CHECK: successors: %bb.5(0x04000000), %bb.1(0x7c000000) ; CHECK: successors: %bb.5(0x04000000), %bb.1(0x7c000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: renamable $r2 = tLDRi killed renamable $r2, 0, 14, $noreg :: (load 4 from %ir.next.i.14) ; CHECK: renamable $r2 = tLDRi killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.next.i.14)
; CHECK: tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2Bcc %bb.1, 1, killed $cpsr ; CHECK: t2Bcc %bb.1, 1 /* CC::ne */, killed $cpsr
; CHECK: bb.5.exit: ; CHECK: bb.5.exit:
; CHECK: liveins: $r0 ; CHECK: liveins: $r0
; CHECK: tBX_RET 14, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1 liveins: $r0, $r1
$r2 = tMOVr $r0, 14, $noreg $r2 = tMOVr $r0, 14, $noreg
bb.1.while.begin: bb.1.while.begin:
successors: %bb.5(0x04000000), %bb.2(0x7c000000) successors: %bb.5(0x04000000), %bb.2(0x7c000000)
Show All 38 Lines

llvm/test/CodeGen/Thumb2/t2sizereduction.mir

Show All 37 Lines
liveins: liveins:
- { reg: '$r0', virtual-reg: '' } - { reg: '$r0', virtual-reg: '' }
- { reg: '$r1', virtual-reg: '' } - { reg: '$r1', virtual-reg: '' }
body: | body: |
; CHECK-LABEL: name: test ; CHECK-LABEL: name: test
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK: liveins: $r0, $r1 ; CHECK: liveins: $r0, $r1
; CHECK: $r2 = tMOVr $r0, 14, $noreg ; CHECK: $r2 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: $r0, dead $cpsr = tMOVi8 1, 14, $noreg ; CHECK: $r0, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: tCMPi8 $r1, 1, 14, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2Bcc %bb.2, 11, killed $cpsr ; CHECK: t2Bcc %bb.2, 11 /* CC::lt */, killed $cpsr
; CHECK: bb.1.for.body: ; CHECK: bb.1.for.body:
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: $r0, dead $cpsr = tMUL $r2, killed $r0, 14, $noreg ; CHECK: $r0, dead $cpsr = tMUL $r2, killed $r0, 14 /* CC::al */, $noreg
; CHECK: $r2, dead $cpsr = tADDi8 killed $r2, 1, 14, $noreg ; CHECK: $r2, dead $cpsr = tADDi8 killed $r2, 1, 14 /* CC::al */, $noreg
; CHECK: $r1, $cpsr = tSUBi8 killed $r1, 1, 14, $noreg ; CHECK: $r1, $cpsr = tSUBi8 killed $r1, 1, 14 /* CC::al */, $noreg
; CHECK: t2Bcc %bb.1, 1, killed $cpsr ; CHECK: t2Bcc %bb.1, 1 /* CC::ne */, killed $cpsr
; CHECK: bb.2.for.cond.cleanup: ; CHECK: bb.2.for.cond.cleanup:
; CHECK: liveins: $r0 ; CHECK: liveins: $r0
; CHECK: tBX_RET 14, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
bb.0.entry: bb.0.entry:
successors: %bb.1.for.body, %bb.2.for.cond.cleanup successors: %bb.1.for.body, %bb.2.for.cond.cleanup
liveins: $r0, $r1 liveins: $r0, $r1
$r2 = tMOVr $r0, 14, _ $r2 = tMOVr $r0, 14, _
$r0 = t2MOVi 1, 14, _, _ $r0 = t2MOVi 1, 14, _, _
t2CMPri $r1, 1, 14, _, implicit-def $cpsr t2CMPri $r1, 1, 14, _, implicit-def $cpsr
t2Bcc %bb.2.for.cond.cleanup, 11, killed $cpsr t2Bcc %bb.2.for.cond.cleanup, 11, killed $cpsr
Show All 16 Lines

llvm/test/DebugInfo/MIR/ARM/live-debug-values-reg-copy.mir

# RUN: llc -run-pass=livedebugvalues %s -o - | FileCheck %s # RUN: llc -run-pass=livedebugvalues %s -o - | FileCheck %s
# #
# This test tests tracking variables value transferring from one register to another. # This test tests tracking variables value transferring from one register to another.
# This example is altered additionally in order to test transferring from one float register # This example is altered additionally in order to test transferring from one float register
# to another. The altered instructions are labeled below. # to another. The altered instructions are labeled below.
# #
# CHECK: ![[ARG1:.*]] = !DILocalVariable(name: "arg1" # CHECK: ![[ARG1:.*]] = !DILocalVariable(name: "arg1"
# CHECK: DBG_VALUE $r4, $noreg, ![[ARG1]], !DIExpression(), debug-location # CHECK: DBG_VALUE $r4, $noreg, ![[ARG1]], !DIExpression(), debug-location
# CHECK: $r5 = MOVr killed $r4, 14, $noreg, $noreg, debug-location # CHECK: $r5 = MOVr killed $r4, 14 /* CC::al */, $noreg, $noreg, debug-location
# CHECK-NEXT: DBG_VALUE $r5, $noreg, ![[ARG1]], !DIExpression(), debug-location # CHECK-NEXT: DBG_VALUE $r5, $noreg, ![[ARG1]], !DIExpression(), debug-location
--- | --- |
; ModuleID = 'live-debug-values-reg-copy.ll' ; ModuleID = 'live-debug-values-reg-copy.ll'
source_filename = "live-debug-values-reg-copy.c" source_filename = "live-debug-values-reg-copy.c"
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "armv4t--" target triple = "armv4t--"
define dso_local arm_aapcscc i32 @foo(i32 %arg1) local_unnamed_addr !dbg !8 { define dso_local arm_aapcscc i32 @foo(i32 %arg1) local_unnamed_addr !dbg !8 {
▲ Show 20 Lines • Show All 130 Lines • Show Last 20 Lines