[ELF][PPC32] Support --emit-relocs link of R_PPC_PLTREL24

[MaskRay]

Summary

Similar to R_MIPS_GPREL16 and R_MIPS_GPREL32 (D45972).

If the addend of an R_PPC_PLTREL24 is >= 0x8000, it indicates that r30
is relative to the input section .got2.

addis 30, 30, .got2+0x8000-.L1$pb@ha
addi 30, 30, .got2+0x8000-.L1$pb@l
...
bl foo+0x8000@PLT

After linking, the relocation will be relative to the output section .got2.
To compensate for the shift address(input section .got2) - address(output section .got2) = ppc32Got2OutSecOff, adjust by ppc32Got2OutSecOff:

addis 30, 30, .got2+0x8000-.L1+ppc32Got2OutSecOff$pb@ha
addi 30, 30, .got2+0x8000-.L1+ppc32Got2OutSecOff$pb@ha$pb@l
...
bl foo+0x8000+ppc32Got2OutSecOff@PLT

This rule applys in a relocatable link or in a non-relocatable link with --emit-relocs.

[merge_guards_bot]

Unit tests: pass. 62253 tests passed, 0 failed and 816 were skipped.

clang-tidy: pass.

clang-format: pass.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

Pre-merge checks is in beta. Report issue. Please join beta or enable it for your project.

[Bdragon28]

I am now able to load pf.ko on FreeBSD powerpc32 without it crashing.

Examining the .ko, it now appears to properly have separate plt stubs for the different .got2 offsets.

Excellent!

I will do a buildworld test and ensure this doesn't break FreeBSD powerpc32 userland, but it's looking great so far.

[MaskRay]

Improve tests

[Bdragon28]

Looks correct to me, works great, and fixes the last lld-related problem I am aware of currently on FreeBSD powerpc32.

[merge_guards_bot]

Unit tests: fail. 62268 tests passed, 3 failed and 827 were skipped.

failed: Clang.CodeGenOpenCL/amdgpu-features.cl
failed: Clang.CodeGenOpenCL/builtins-amdgcn-mfma.cl
failed: Clang.SemaOpenCL/builtins-amdgcn-error-gfx908-param.cl

clang-tidy: pass.

clang-format: pass.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

Pre-merge checks is in beta. Report issue. Please join beta or enable it for your project.

lld/ELF/InputSection.cpp

if (sym.type == STT_SECTION) {
         // addend and save it back to the file.
         addend += sec->getFile<ELFT>()->mipsGp0;
       }
 
       if (RelTy::IsRela)
         p->r_addend = sym.getVA(addend) - section->getOutputSection()->addr;
       else if (config->relocatable && type != target->noneRel)
         sec->relocations.push_back({R_ABS, type, rel.r_offset, addend, &sym});
+    } else if (config->emachine == EM_PPC && type == R_PPC_PLTREL24 &&
+               p->r_addend >= 0x8000) {
+      // Similar to R_MIPS_GPREL{16,32}. If the addend of R_PPC_PLTREL24
+      // indicates that r30 is relative to the input section .got2
+      // (r_addend>=0x8000), after linking, r30 should be relative to the output
+      // section .got2 . To compensate for the shift, adjust r_addend by
+      // ppc32Got2OutSecOff.
+      p->r_addend += sec->file->ppc32Got2OutSecOff;
     }
   }
 }
 
 // The ARM and AArch64 ABI handle pc-relative relocations to undefined weak
 // references specially. The general rule is that the value of the symbol in
 // this context is the address of the place P. A further special case is that
 // branch relocations to an undefined weak reference resolve to the next

lld/test/ELF/ppc32-relocatable-got2.s

+# REQUIRES: ppc
+## Test addend adjustment of R_PPC_PLTREL24 when copying relocations.
+## If r_addend indicates .got2, adjust it by the local .got2's output section offset.
+
+# RUN: llvm-mc -filetype=obj -triple=powerpc %s -o %t.o
+# RUN: ld.lld -r %t.o %t.o -o %t
+# RUN: llvm-readobj -r %t | FileCheck %s
+
+# RUN: ld.lld -shared --emit-relocs %t.o %t.o -o %t.so
+# RUN: llvm-readobj -r %t.so | FileCheck %s
+
+# CHECK:      .rela.adjust {
+# CHECK-NEXT:   R_PPC_REL16_HA .got2 0x8002
+# CHECK-NEXT:   R_PPC_REL16_LO .got2 0x8006
+# CHECK-NEXT:   R_PPC_PLTREL24 foo 0x8000
+# CHECK-NEXT:   R_PPC_PLTREL24 bar 0x8000
+# CHECK-NEXT:   R_PPC_REL16_HA .got2 0x8006
+# CHECK-NEXT:   R_PPC_REL16_LO .got2 0x800A
+# CHECK-NEXT:   R_PPC_PLTREL24 foo 0x8004
+# CHECK-NEXT:   R_PPC_PLTREL24 bar 0x8004
+# CHECK-NEXT: }
+# CHECK-NEXT: .rela.no_adjust {
+# CHECK-NEXT:   R_PPC_PLTREL24 foo 0x0
+# CHECK-NEXT:   R_PPC_PLTREL24 foo 0x0
+# CHECK-NEXT: }
+.section .got2,"aw"
+.long 0
+
+.section .adjust,"ax"
+bcl 20,30,.L0
+.L0:
+addis 30,30,.got2+0x8000-.L0@ha
+addi 30,30,.got2+0x8000-.L0@l
+
+## Refers to .got2+addend, adjust.
+bl foo+0x8000@plt
+bl bar+0x8000@plt
+
+.section .no_adjust,"ax"
+## Refers to .got, no adjustment.
+bl foo@plt