[ELF][PPC32] Support --emit-relocs link of R_PPC_PLTREL24

[MaskRay]

Summary

Similar to R_MIPS_GPREL16 and R_MIPS_GPREL32 (D45972).

If the addend of an R_PPC_PLTREL24 is >= 0x8000, it indicates that r30
is relative to the input section .got2.

addis 30, 30, .got2+0x8000-.L1$pb@ha
addi 30, 30, .got2+0x8000-.L1$pb@l
...
bl foo+0x8000@PLT

After linking, the relocation will be relative to the output section .got2.
To compensate for the shift address(input section .got2) - address(output section .got2) = ppc32Got2OutSecOff, adjust by ppc32Got2OutSecOff:

addis 30, 30, .got2+0x8000-.L1+ppc32Got2OutSecOff$pb@ha
addi 30, 30, .got2+0x8000-.L1+ppc32Got2OutSecOff$pb@ha$pb@l
...
bl foo+0x8000+ppc32Got2OutSecOff@PLT

This rule applys in a relocatable link or in a non-relocatable link with --emit-relocs.

[merge_guards_bot]

Unit tests: pass. 62253 tests passed, 0 failed and 816 were skipped.

clang-tidy: pass.

clang-format: pass.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

Pre-merge checks is in beta. Report issue. Please join beta or enable it for your project.

[Bdragon28]

I am now able to load pf.ko on FreeBSD powerpc32 without it crashing.

Examining the .ko, it now appears to properly have separate plt stubs for the different .got2 offsets.

Excellent!

I will do a buildworld test and ensure this doesn't break FreeBSD powerpc32 userland, but it's looking great so far.

[MaskRay]

Improve tests

[Bdragon28]

Looks correct to me, works great, and fixes the last lld-related problem I am aware of currently on FreeBSD powerpc32.

[merge_guards_bot]

Unit tests: fail. 62268 tests passed, 3 failed and 827 were skipped.

failed: Clang.CodeGenOpenCL/amdgpu-features.cl
failed: Clang.CodeGenOpenCL/builtins-amdgcn-mfma.cl
failed: Clang.SemaOpenCL/builtins-amdgcn-error-gfx908-param.cl

clang-tidy: pass.

clang-format: pass.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

Pre-merge checks is in beta. Report issue. Please join beta or enable it for your project.

lld/ELF/InputSection.cpp

if (sym.type == STT_SECTION) {
         continue;
       }
 
       int64_t addend = getAddend<ELFT>(rel);
       const uint8_t *bufLoc = sec->data().begin() + rel.r_offset;
       if (!RelTy::IsRela)
         addend = target->getImplicitAddend(bufLoc, type);
 
-      if (config->emachine == EM_MIPS && config->relocatable &&
+      if (config->relocatable && config->emachine == EM_MIPS &&
           target->getRelExpr(type, sym, bufLoc) == R_MIPS_GOTREL) {
         // Some MIPS relocations depend on "gp" value. By default,
         // this value has 0x7ff0 offset from a .got section. But
         // relocatable files produced by a compiler or a linker
         // might redefine this default value and we must use it
         // for a calculation of the relocation result. When we
         // generate EXE or DSO it's trivial. Generating a relocatable
         // output is more difficult case because the linker does
         // not calculate relocations in this mode and loses
         // individual "gp" values used by each input object file.
         // As a workaround we add the "gp" value to the relocation
         // addend and save it back to the file.
         addend += sec->getFile<ELFT>()->mipsGp0;
       }
 
       if (RelTy::IsRela)
         p->r_addend = sym.getVA(addend) - section->getOutputSection()->addr;
       else if (config->relocatable && type != target->noneRel)
         sec->relocations.push_back({R_ABS, type, rel.r_offset, addend, &sym});
+    } else if (config->relocatable && config->emachine == EM_PPC &&
+               type == R_PPC_PLTREL24 && p->r_addend >= 0x8000) {
+      // Similar to R_MIPS_GOTREL{16,32}, if r_addend indicates .got2
+      // (>=0x8000), adjust it by the local .got2's output section offset. If
+      // r_addend=0, don't adjust. The PLT call stub is relative to .got.
+      // Because .got should not exist as an input section, the adjustment is 0.
+      p->r_addend += sec->file->ppc32Got2OutSecOff;
     }
   }
 }
 
 // The ARM and AArch64 ABI handle pc-relative relocations to undefined weak
 // references specially. The general rule is that the value of the symbol in
 // this context is the address of the place P. A further special case is that
 // branch relocations to an undefined weak reference resolve to the next

lld/test/ELF/ppc32-relocatable-pltrel24.s

+# REQUIRES: ppc
+## Test addend adjustment of R_PPC_PLTREL24 in -r mode. If r_addend indicates
+## .got2, adjust it by the local .got2's output section offset.
+
+# RUN: llvm-mc -filetype=obj -triple=powerpc %s -o %t.o
+# RUN: ld.lld -r %t.o %t.o %t.o -o %t
+# RUN: llvm-readobj -r %t | FileCheck %s
+
+# RUN: ld.lld -shared --emit-relocs %t.o %t.o %t.o -o %t.so
+# RUN: llvm-readobj -r %t.so | FileCheck --check-prefix=DSO %s
+
+# CHECK:      .rela.adjust {
+# CHECK-NEXT:   0x0 R_PPC_PLTREL24 foo 0x8000
+# CHECK-NEXT:   0x4 R_PPC_PLTREL24 bar 0x8000
+# CHECK-NEXT:   0x8 R_PPC_PLTREL24 foo 0x8004
+# CHECK-NEXT:   0xC R_PPC_PLTREL24 bar 0x8004
+# CHECK-NEXT:   0x10 R_PPC_PLTREL24 foo 0x8008
+# CHECK-NEXT:   0x14 R_PPC_PLTREL24 bar 0x8008
+# CHECK-NEXT: }
+# CHECK-NEXT: .rela.no_adjust {
+# CHECK-NEXT:   0x0 R_PPC_PLTREL24 foo 0x0
+# CHECK-NEXT:   0x4 R_PPC_PLTREL24 foo 0x0
+# CHECK-NEXT:   0x8 R_PPC_PLTREL24 foo 0x0
+# CHECK-NEXT: }
+
+## No adjustment in non -r mode.
+# DSO:      .rela.adjust {
+# DSO-NEXT:   R_PPC_PLTREL24 foo 0x8000
+# DSO-NEXT:   R_PPC_PLTREL24 bar 0x8000
+# DSO-NEXT:   R_PPC_PLTREL24 foo 0x8000
+# DSO-NEXT:   R_PPC_PLTREL24 bar 0x8000
+# DSO-NEXT:   R_PPC_PLTREL24 foo 0x8000
+# DSO-NEXT:   R_PPC_PLTREL24 bar 0x8000
+# DSO-NEXT: }
+.section .got2,"aw"
+.long 0
+
+.section .adjust,"ax"
+## Refers to .got2+addend, adjust.
+bl foo+0x8000@plt
+bl bar+0x8000@plt
+
+.section .no_adjust,"ax"
+## Refers to .got, no adjustment.
+bl foo@plt