[mlir][spirv] Support implied extensions and capabilities

[antiagainst]

Summary

In SPIR-V, when a new version is introduced, it is possible some
existing extensions will be incorporated into it so that it becomes
implicitly declared if targeting the new version. This affects
conversion target specification because we need to take this into
account when allowing what extensions to use.

For a capability, it may also implies some other capabilities,
for example, the Shader capability implies Matrix the capability.
This should also be taken into consideration when preparing the
conversion target: when we specify an capability is allowed, all
its recursively implied capabilities are also allowed.

This commit adds utility functions to query implied extensions for
a given version and implied capabilities for a given capability
and updated SPIRVConversionTarget to use them.

This commit also fixes a bug in availability spec. When a symbol
(op or enum case) can be enabled by an extension, we should drop
it's minimal version requirement. Being enabled by an extension
naturally means the symbol can be used by *any* SPIR-V version
as long as the extension is supported. The grammar still encodes
the 'version' field for such cases, but it should be interpreted
as a different way: rather than meaning a minimal version
requirement, it says the symbol becomes core at that specific
version.

[merge_guards_bot]

Unit tests: pass. 61884 tests passed, 0 failed and 782 were skipped.

clang-tidy: unknown.

clang-format: pass.

Build artifacts: diff.json, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

[rriddle]

mlir/lib/Dialect/SPIRV/SPIRVTypes.cpp

90

I would imagine this would be much simpler/efficient if you used a SetVector instead.

mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp

1307

This seems unnecessarily inefficient. Can you just split the format below and use interleaveComma over the defs instead.

[benvanik]

mlir/include/mlir/Dialect/SPIRV/SPIRVTypes.h

53

nit: wouldn't this just be std::vector?

[antiagainst]

Address comments

[antiagainst]

mlir/include/mlir/Dialect/SPIRV/SPIRVTypes.h

53

According to LLVM programmer's manual, SmallVector<..., 0> has advantages over std::vector: http://llvm.org/docs/ProgrammersManual.html#llvm-adt-smallvector-h

mlir/lib/Dialect/SPIRV/SPIRVTypes.cpp

90

Indeed. Thanks for the suggestion! :)

mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp

1307

Good point! Done.

[merge_guards_bot]

Unit tests: pass. 61936 tests passed, 0 failed and 783 were skipped.

clang-tidy: unknown.

clang-format: pass.

Build artifacts: diff.json, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

mlir/include/mlir/Dialect/SPIRV/CMakeLists.txt

 add_mlir_dialect(SPIRVOps SPIRVOps)
 
 set(LLVM_TARGET_DEFINITIONS SPIRVBase.td)
 mlir_tablegen(SPIRVEnums.h.inc -gen-enum-decls)
 mlir_tablegen(SPIRVEnums.cpp.inc -gen-enum-defs)
 add_public_tablegen_target(MLIRSPIRVEnumsIncGen)
 
 set(LLVM_TARGET_DEFINITIONS SPIRVBase.td)
 mlir_tablegen(SPIRVEnumAvailability.h.inc -gen-spirv-enum-avail-decls)
 mlir_tablegen(SPIRVEnumAvailability.cpp.inc -gen-spirv-enum-avail-defs)
+mlir_tablegen(SPIRVCapabilityImplication.inc -gen-spirv-capability-implication)
 add_public_tablegen_target(MLIRSPIRVEnumAvailabilityIncGen)
 
 set(LLVM_TARGET_DEFINITIONS SPIRVOps.td)
 mlir_tablegen(SPIRVAvailability.h.inc -gen-avail-interface-decls)
 mlir_tablegen(SPIRVAvailability.cpp.inc -gen-avail-interface-defs)
 mlir_tablegen(SPIRVOpAvailabilityImpl.inc -gen-spirv-avail-impls)
 add_public_tablegen_target(MLIRSPIRVAvailabilityIncGen)
 

mlir/include/mlir/Dialect/SPIRV/SPIRVBase.td

 }
 def SPV_C_SubgroupVoteKHR                           : I32EnumAttrCase<"SubgroupVoteKHR", 4431> {
   list<Availability> availability = [
     Extension<[SPV_KHR_subgroup_vote]>
   ];
 }
 def SPV_C_StorageBuffer16BitAccess                  : I32EnumAttrCase<"StorageBuffer16BitAccess", 4433> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_3>,
     Extension<[SPV_KHR_16bit_storage]>
   ];
 }
 def SPV_C_StoragePushConstant16                     : I32EnumAttrCase<"StoragePushConstant16", 4435> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_3>,
     Extension<[SPV_KHR_16bit_storage]>
   ];
 }
 def SPV_C_StorageInputOutput16                      : I32EnumAttrCase<"StorageInputOutput16", 4436> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_3>,
     Extension<[SPV_KHR_16bit_storage]>
   ];
 }
 def SPV_C_DeviceGroup                               : I32EnumAttrCase<"DeviceGroup", 4437> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_3>,
     Extension<[SPV_KHR_device_group]>
   ];
 }
 def SPV_C_AtomicStorageOps                          : I32EnumAttrCase<"AtomicStorageOps", 4445> {
   list<Availability> availability = [
     Extension<[SPV_KHR_shader_atomic_counter_ops]>
   ];
 }
 def SPV_C_SampleMaskPostDepthCoverage               : I32EnumAttrCase<"SampleMaskPostDepthCoverage", 4447> {
   list<Availability> availability = [
     Extension<[SPV_KHR_post_depth_coverage]>
   ];
 }
 def SPV_C_StorageBuffer8BitAccess                   : I32EnumAttrCase<"StorageBuffer8BitAccess", 4448> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>,
     Extension<[SPV_KHR_8bit_storage]>
   ];
 }
 def SPV_C_StoragePushConstant8                      : I32EnumAttrCase<"StoragePushConstant8", 4450> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>,
     Extension<[SPV_KHR_8bit_storage]>
   ];
 }
 def SPV_C_DenormPreserve                            : I32EnumAttrCase<"DenormPreserve", 4464> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_4>,
     Extension<[SPV_KHR_float_controls]>
   ];
 }
 def SPV_C_DenormFlushToZero                         : I32EnumAttrCase<"DenormFlushToZero", 4465> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_4>,
     Extension<[SPV_KHR_float_controls]>
   ];
 }
 def SPV_C_SignedZeroInfNanPreserve                  : I32EnumAttrCase<"SignedZeroInfNanPreserve", 4466> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_4>,
     Extension<[SPV_KHR_float_controls]>
   ];
 }
 def SPV_C_RoundingModeRTE                           : I32EnumAttrCase<"RoundingModeRTE", 4467> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_4>,
     Extension<[SPV_KHR_float_controls]>
   ];
 }
 def SPV_C_RoundingModeRTZ                           : I32EnumAttrCase<"RoundingModeRTZ", 4468> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_4>,
     Extension<[SPV_KHR_float_controls]>
   ];
 }
 def SPV_C_ImageFootprintNV                          : I32EnumAttrCase<"ImageFootprintNV", 5282> {
   list<Availability> availability = [
     Extension<[SPV_NV_shader_image_footprint]>
   ];
 }
def SPV_C_GroupNonUniformQuad                       : I32EnumAttrCase<"GroupNonUniformQuad", 68> {
   list<I32EnumAttrCase> implies = [SPV_C_GroupNonUniform];
   list<Availability> availability = [
     MinVersion<SPV_V_1_3>
   ];
 }
 def SPV_C_StorageUniform16                          : I32EnumAttrCase<"StorageUniform16", 4434> {
   list<I32EnumAttrCase> implies = [SPV_C_StorageBuffer16BitAccess];
   list<Availability> availability = [
-    MinVersion<SPV_V_1_3>,
     Extension<[SPV_KHR_16bit_storage]>
   ];
 }
 def SPV_C_UniformAndStorageBuffer8BitAccess         : I32EnumAttrCase<"UniformAndStorageBuffer8BitAccess", 4449> {
   list<I32EnumAttrCase> implies = [SPV_C_StorageBuffer8BitAccess];
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>,
     Extension<[SPV_KHR_8bit_storage]>
   ];
 }
 def SPV_C_UniformTexelBufferArrayDynamicIndexing    : I32EnumAttrCase<"UniformTexelBufferArrayDynamicIndexing", 5304> {
   list<I32EnumAttrCase> implies = [SPV_C_SampledBuffer];
   list<Availability> availability = [
     MinVersion<SPV_V_1_5>
   ];
def SPV_C_PipeStorage                               : I32EnumAttrCase<"PipeStorage", 60> {
   list<I32EnumAttrCase> implies = [SPV_C_Pipes];
   list<Availability> availability = [
     MinVersion<SPV_V_1_1>
   ];
 }
 def SPV_C_DrawParameters                            : I32EnumAttrCase<"DrawParameters", 4427> {
   list<I32EnumAttrCase> implies = [SPV_C_Shader];
   list<Availability> availability = [
-    MinVersion<SPV_V_1_3>,
     Extension<[SPV_KHR_shader_draw_parameters]>
   ];
 }
 def SPV_C_MultiView                                 : I32EnumAttrCase<"MultiView", 4439> {
   list<I32EnumAttrCase> implies = [SPV_C_Shader];
   list<Availability> availability = [
-    MinVersion<SPV_V_1_3>,
     Extension<[SPV_KHR_multiview]>
   ];
 }
 def SPV_C_VariablePointersStorageBuffer             : I32EnumAttrCase<"VariablePointersStorageBuffer", 4441> {
   list<I32EnumAttrCase> implies = [SPV_C_Shader];
   list<Availability> availability = [
-    MinVersion<SPV_V_1_3>,
     Extension<[SPV_KHR_variable_pointers]>
   ];
 }
 def SPV_C_Float16ImageAMD                           : I32EnumAttrCase<"Float16ImageAMD", 5008> {
   list<I32EnumAttrCase> implies = [SPV_C_Shader];
   list<Availability> availability = [
     Extension<[SPV_AMD_gpu_shader_half_float_fetch]>
   ];
def SPV_C_RayTracingNV                              : I32EnumAttrCase<"RayTracingNV", 5340> {
   list<I32EnumAttrCase> implies = [SPV_C_Shader];
   list<Availability> availability = [
     Extension<[SPV_NV_ray_tracing]>
   ];
 }
 def SPV_C_PhysicalStorageBufferAddresses            : I32EnumAttrCase<"PhysicalStorageBufferAddresses", 5347> {
   list<I32EnumAttrCase> implies = [SPV_C_Shader];
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>,
     Extension<[SPV_EXT_physical_storage_buffer, SPV_KHR_physical_storage_buffer]>
   ];
 }
 def SPV_C_CooperativeMatrixNV                       : I32EnumAttrCase<"CooperativeMatrixNV", 5357> {
   list<I32EnumAttrCase> implies = [SPV_C_Shader];
   list<Availability> availability = [
     Extension<[SPV_NV_cooperative_matrix]>
   ];
def SPV_C_GeometryStreams                           : I32EnumAttrCase<"GeometryStreams", 54> {
   list<I32EnumAttrCase> implies = [SPV_C_Geometry];
 }
 def SPV_C_MultiViewport                             : I32EnumAttrCase<"MultiViewport", 57> {
   list<I32EnumAttrCase> implies = [SPV_C_Geometry];
 }
 def SPV_C_VariablePointers                          : I32EnumAttrCase<"VariablePointers", 4442> {
   list<I32EnumAttrCase> implies = [SPV_C_VariablePointersStorageBuffer];
   list<Availability> availability = [
-    MinVersion<SPV_V_1_3>,
     Extension<[SPV_KHR_variable_pointers]>
   ];
 }
 def SPV_C_SampleMaskOverrideCoverageNV              : I32EnumAttrCase<"SampleMaskOverrideCoverageNV", 5249> {
   list<I32EnumAttrCase> implies = [SPV_C_SampleRateShading];
   list<Availability> availability = [
     Extension<[SPV_NV_sample_mask_override_coverage]>
   ];

 }
 def SPV_AM_Physical64              : I32EnumAttrCase<"Physical64", 2> {
   list<Availability> availability = [
     Capability<[SPV_C_Addresses]>
   ];
 }
 def SPV_AM_PhysicalStorageBuffer64 : I32EnumAttrCase<"PhysicalStorageBuffer64", 5348> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>,
     Extension<[SPV_EXT_physical_storage_buffer, SPV_KHR_physical_storage_buffer]>,
     Capability<[SPV_C_PhysicalStorageBufferAddresses]>
   ];
 }
 
 def SPV_AddressingModelAttr :
     SPV_I32EnumAttr<"AddressingModel", "valid SPIR-V AddressingModel", [
       SPV_AM_Logical, SPV_AM_Physical32, SPV_AM_Physical64,

 def SPV_BI_SubgroupLtMask              : I32EnumAttrCase<"SubgroupLtMask", 4420> {
   list<Availability> availability = [
     MinVersion<SPV_V_1_3>,
     Capability<[SPV_C_GroupNonUniformBallot, SPV_C_SubgroupBallotKHR]>
   ];
 }
 def SPV_BI_BaseVertex                  : I32EnumAttrCase<"BaseVertex", 4424> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_3>,
     Extension<[SPV_KHR_shader_draw_parameters]>,
     Capability<[SPV_C_DrawParameters]>
   ];
 }
 def SPV_BI_BaseInstance                : I32EnumAttrCase<"BaseInstance", 4425> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_3>,
     Extension<[SPV_KHR_shader_draw_parameters]>,
     Capability<[SPV_C_DrawParameters]>
   ];
 }
 def SPV_BI_DrawIndex                   : I32EnumAttrCase<"DrawIndex", 4426> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_3>,
     Extension<[SPV_KHR_shader_draw_parameters, SPV_NV_mesh_shader]>,
     Capability<[SPV_C_DrawParameters, SPV_C_MeshShadingNV]>
   ];
 }
 def SPV_BI_DeviceIndex                 : I32EnumAttrCase<"DeviceIndex", 4438> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_3>,
     Extension<[SPV_KHR_device_group]>,
     Capability<[SPV_C_DeviceGroup]>
   ];
 }
 def SPV_BI_ViewIndex                   : I32EnumAttrCase<"ViewIndex", 4440> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_3>,
     Extension<[SPV_KHR_multiview]>,
     Capability<[SPV_C_MultiView]>
   ];
 }
 def SPV_BI_BaryCoordNoPerspAMD         : I32EnumAttrCase<"BaryCoordNoPerspAMD", 4992> {
   list<Availability> availability = [
     Extension<[SPV_AMD_shader_explicit_vertex_parameter]>
   ];

 def SPV_D_MaxByteOffsetId             : I32EnumAttrCase<"MaxByteOffsetId", 47> {
   list<Availability> availability = [
     MinVersion<SPV_V_1_2>,
     Capability<[SPV_C_Addresses]>
   ];
 }
 def SPV_D_NoSignedWrap                : I32EnumAttrCase<"NoSignedWrap", 4469> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_4>,
     Extension<[SPV_KHR_no_integer_wrap_decoration]>
   ];
 }
 def SPV_D_NoUnsignedWrap              : I32EnumAttrCase<"NoUnsignedWrap", 4470> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_4>,
     Extension<[SPV_KHR_no_integer_wrap_decoration]>
   ];
 }
 def SPV_D_ExplicitInterpAMD           : I32EnumAttrCase<"ExplicitInterpAMD", 4999> {
   list<Availability> availability = [
     Extension<[SPV_AMD_shader_explicit_vertex_parameter]>
   ];
 }

 def SPV_D_NonUniform                  : I32EnumAttrCase<"NonUniform", 5300> {
   list<Availability> availability = [
     MinVersion<SPV_V_1_5>,
     Capability<[SPV_C_ShaderNonUniform]>
   ];
 }
 def SPV_D_RestrictPointer             : I32EnumAttrCase<"RestrictPointer", 5355> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>,
     Extension<[SPV_EXT_physical_storage_buffer, SPV_KHR_physical_storage_buffer]>,
     Capability<[SPV_C_PhysicalStorageBufferAddresses]>
   ];
 }
 def SPV_D_AliasedPointer              : I32EnumAttrCase<"AliasedPointer", 5356> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>,
     Extension<[SPV_EXT_physical_storage_buffer, SPV_KHR_physical_storage_buffer]>,
     Capability<[SPV_C_PhysicalStorageBufferAddresses]>
   ];
 }
 def SPV_D_CounterBuffer               : I32EnumAttrCase<"CounterBuffer", 5634> {
   list<Availability> availability = [
     MinVersion<SPV_V_1_4>
   ];

 def SPV_EM_PostDepthCoverage                : I32EnumAttrCase<"PostDepthCoverage", 4446> {
   list<Availability> availability = [
     Extension<[SPV_KHR_post_depth_coverage]>,
     Capability<[SPV_C_SampleMaskPostDepthCoverage]>
   ];
 }
 def SPV_EM_DenormPreserve                   : I32EnumAttrCase<"DenormPreserve", 4459> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_4>,
     Extension<[SPV_KHR_float_controls]>,
     Capability<[SPV_C_DenormPreserve]>
   ];
 }
 def SPV_EM_DenormFlushToZero                : I32EnumAttrCase<"DenormFlushToZero", 4460> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_4>,
     Extension<[SPV_KHR_float_controls]>,
     Capability<[SPV_C_DenormFlushToZero]>
   ];
 }
 def SPV_EM_SignedZeroInfNanPreserve         : I32EnumAttrCase<"SignedZeroInfNanPreserve", 4461> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_4>,
     Extension<[SPV_KHR_float_controls]>,
     Capability<[SPV_C_SignedZeroInfNanPreserve]>
   ];
 }
 def SPV_EM_RoundingModeRTE                  : I32EnumAttrCase<"RoundingModeRTE", 4462> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_4>,
     Extension<[SPV_KHR_float_controls]>,
     Capability<[SPV_C_RoundingModeRTE]>
   ];
 }
 def SPV_EM_RoundingModeRTZ                  : I32EnumAttrCase<"RoundingModeRTZ", 4463> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_4>,
     Extension<[SPV_KHR_float_controls]>,
     Capability<[SPV_C_RoundingModeRTZ]>
   ];
 }
 def SPV_EM_StencilRefReplacingEXT           : I32EnumAttrCase<"StencilRefReplacingEXT", 5027> {
   list<Availability> availability = [
     Extension<[SPV_EXT_shader_stencil_export]>,
     Capability<[SPV_C_StencilExportEXT]>

 }
 def SPV_MM_OpenCL  : I32EnumAttrCase<"OpenCL", 2> {
   list<Availability> availability = [
     Capability<[SPV_C_Kernel]>
   ];
 }
 def SPV_MM_Vulkan  : I32EnumAttrCase<"Vulkan", 3> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>,
     Extension<[SPV_KHR_vulkan_memory_model]>,
     Capability<[SPV_C_VulkanMemoryModel]>
   ];
 }
 
 def SPV_MemoryModelAttr :
     SPV_I32EnumAttr<"MemoryModel", "valid SPIR-V MemoryModel", [
       SPV_MM_Simple, SPV_MM_GLSL450, SPV_MM_OpenCL, SPV_MM_Vulkan

 def SPV_MS_MakeVisible            : BitEnumAttrCase<"MakeVisible", 0x4000> {
   list<Availability> availability = [
     MinVersion<SPV_V_1_5>,
     Capability<[SPV_C_VulkanMemoryModel]>
   ];
 }
 def SPV_MS_Volatile               : BitEnumAttrCase<"Volatile", 0x8000> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>,
     Extension<[SPV_KHR_vulkan_memory_model]>,
     Capability<[SPV_C_VulkanMemoryModel]>
   ];
 }
 
 def SPV_MemorySemanticsAttr :
     SPV_BitEnumAttr<"MemorySemantics", "valid SPIR-V MemorySemantics", [
       SPV_MS_None, SPV_MS_Acquire, SPV_MS_Release, SPV_MS_AcquireRelease,

 def SPV_SC_AtomicCounter          : I32EnumAttrCase<"AtomicCounter", 10> {
   list<Availability> availability = [
     Capability<[SPV_C_AtomicStorage]>
   ];
 }
 def SPV_SC_Image                  : I32EnumAttrCase<"Image", 11>;
 def SPV_SC_StorageBuffer          : I32EnumAttrCase<"StorageBuffer", 12> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_3>,
     Extension<[SPV_KHR_storage_buffer_storage_class, SPV_KHR_variable_pointers]>,
     Capability<[SPV_C_Shader]>
   ];
 }
 def SPV_SC_CallableDataNV         : I32EnumAttrCase<"CallableDataNV", 5328> {
   list<Availability> availability = [
     Extension<[SPV_NV_ray_tracing]>,
     Capability<[SPV_C_RayTracingNV]>

 def SPV_SC_ShaderRecordBufferNV   : I32EnumAttrCase<"ShaderRecordBufferNV", 5343> {
   list<Availability> availability = [
     Extension<[SPV_NV_ray_tracing]>,
     Capability<[SPV_C_RayTracingNV]>
   ];
 }
 def SPV_SC_PhysicalStorageBuffer  : I32EnumAttrCase<"PhysicalStorageBuffer", 5349> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>,
     Extension<[SPV_EXT_physical_storage_buffer, SPV_KHR_physical_storage_buffer]>,
     Capability<[SPV_C_PhysicalStorageBufferAddresses]>
   ];
 }
 
 def SPV_StorageClassAttr :
     SPV_I32EnumAttr<"StorageClass", "valid SPIR-V StorageClass", [
       SPV_SC_UniformConstant, SPV_SC_Input, SPV_SC_Uniform, SPV_SC_Output,

mlir/include/mlir/Dialect/SPIRV/SPIRVTypes.h

 
 #ifndef MLIR_DIALECT_SPIRV_SPIRVTYPES_H_
 #define MLIR_DIALECT_SPIRV_SPIRVTYPES_H_
 
 #include "mlir/IR/StandardTypes.h"
 #include "mlir/IR/TypeSupport.h"
 #include "mlir/IR/Types.h"
 
+#include <tuple>
+
 // Forward declare enum classes related to op availability. Their definitions
 // are in the TableGen'erated SPIRVEnums.h.inc and can be referenced by other
 // declarations in SPIRVEnums.h.inc.
 namespace mlir {
 namespace spirv {
 enum class Version : uint32_t;
 enum class Extension;
 enum class Capability : uint32_t;
 } // namespace spirv
 } // namespace mlir
 
 // Pull in all enum type definitions and utility function declarations
 #include "mlir/Dialect/SPIRV/SPIRVEnums.h.inc"
 // Pull in all enum type availability query function declarations
 #include "mlir/Dialect/SPIRV/SPIRVEnumAvailability.h.inc"
 
-#include <tuple>
-
 namespace mlir {
 namespace spirv {
+/// Returns the implied extensions for the given version. These extensions are
+/// incorporated into the current version so they are implicitly declared when
+/// targeting the given version.
+ArrayRef<Extension> getImpliedExtensions(Version version);
+
+/// Returns the directly implied capabilities for the given capability. These
+/// capabilities are implicitly declared by the given capability.
+ArrayRef<Capability> getDirectImpliedCapabilities(Capability cap);
+/// Returns the recursively implied capabilities for the given capability. These
+/// capabilities are implicitly declared by the given capability. Compared to
+/// the above function, this function collects implied capabilities recursively:
+/// if an implicitly declared capability implicitly declares a third one, the
+/// third one will also be returned.
+SmallVector<Capability, 0> getRecursiveImpliedCapabilities(Capability cap);
 
 namespace detail {
 struct ArrayTypeStorage;
 struct ImageTypeStorage;
 struct PointerTypeStorage;
 struct RuntimeArrayTypeStorage;
 struct StructTypeStorage;
 } // namespace detail

mlir/include/mlir/TableGen/Attribute.h

private:
   const llvm::Record *def;
 };
 
 // Wrapper class providing helper methods for accessing enum attribute cases
 // defined in TableGen. This is used for enum attribute case backed by both
 // StringAttr and IntegerAttr.
 class EnumAttrCase : public Attribute {
 public:
+  explicit EnumAttrCase(const llvm::Record *record);
   explicit EnumAttrCase(const llvm::DefInit *init);
 
   // Returns true if this EnumAttrCase is backed by a StringAttr.
   bool isStrCase() const;
 
   // Returns the symbol of this enum attribute case.
   StringRef getSymbol() const;
 

mlir/lib/Dialect/SPIRV/SPIRVLowering.cpp

 spirv::SPIRVConversionTarget::SPIRVConversionTarget(
     spirv::TargetEnvAttr targetEnv, MLIRContext *context)
     : ConversionTarget(*context),
       givenVersion(static_cast<spirv::Version>(targetEnv.version().getInt())) {
   for (Attribute extAttr : targetEnv.extensions())
     givenExtensions.insert(
         *spirv::symbolizeExtension(extAttr.cast<StringAttr>().getValue()));
 
-  for (Attribute capAttr : targetEnv.capabilities())
-    givenCapabilities.insert(
-        static_cast<spirv::Capability>(capAttr.cast<IntegerAttr>().getInt()));
+  // Add extensions implied by the current version.
+  for (spirv::Extension ext : spirv::getImpliedExtensions(givenVersion))
+    givenExtensions.insert(ext);
+
+  for (Attribute capAttr : targetEnv.capabilities()) {
+    auto cap =
+        static_cast<spirv::Capability>(capAttr.cast<IntegerAttr>().getInt());
+    givenCapabilities.insert(cap);
+
+    // Add capabilities implied by the current capability.
+    for (spirv::Capability c : spirv::getRecursiveImpliedCapabilities(cap))
+      givenCapabilities.insert(c);
+  }
 }
 
 bool spirv::SPIRVConversionTarget::isLegalOp(Operation *op) {
   // Make sure this op is available at the given version. Ops not implementing
   // QueryMinVersionInterface/QueryMaxVersionInterface are available to all
   // SPIR-V versions.
   if (auto minVersion = dyn_cast<spirv::QueryMinVersionInterface>(op))
     if (minVersion.getMinVersion() > givenVersion) {

mlir/lib/Dialect/SPIRV/SPIRVTypes.cpp

 //===- SPIRVTypes.cpp - MLIR SPIR-V Types ---------------------------------===//
 //
 // Part of the MLIR Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines the types in the SPIR-V dialect.
 //
 //===----------------------------------------------------------------------===//
 
 #include "mlir/Dialect/SPIRV/SPIRVTypes.h"
 #include "mlir/IR/Attributes.h"
 #include "mlir/IR/Identifier.h"
 #include "mlir/IR/StandardTypes.h"
+#include "llvm/ADT/SetVector.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringSwitch.h"
 
 using namespace mlir;
 using namespace mlir::spirv;
 
 // Pull in all enum utility function definitions
 #include "mlir/Dialect/SPIRV/SPIRVEnums.cpp.inc"
 // Pull in all enum type availability query function definitions
 #include "mlir/Dialect/SPIRV/SPIRVEnumAvailability.cpp.inc"
 
 //===----------------------------------------------------------------------===//
+// Availability relationship
+//===----------------------------------------------------------------------===//
+
+ArrayRef<Extension> spirv::getImpliedExtensions(Version version) {
+  // Note: the following lists are from "Appendix A: Changes" of the spec.
+
+#define V_1_3_IMPLIED_EXTS                                                     \
+  Extension::SPV_KHR_shader_draw_parameters, Extension::SPV_KHR_16bit_storage, \
+      Extension::SPV_KHR_device_group, Extension::SPV_KHR_multiview,           \
+      Extension::SPV_KHR_storage_buffer_storage_class,                         \
+      Extension::SPV_KHR_variable_pointers
+
+#define V_1_4_IMPLIED_EXTS                                                     \
+  Extension::SPV_KHR_no_integer_wrap_decoration,                               \
+      Extension::SPV_GOOGLE_decorate_string,                                   \
+      Extension::SPV_GOOGLE_hlsl_functionality1,                               \
+      Extension::SPV_KHR_float_controls
+
+#define V_1_5_IMPLIED_EXTS                                                     \
+  Extension::SPV_KHR_8bit_storage, Extension::SPV_EXT_descriptor_indexing,     \
+      Extension::SPV_EXT_shader_viewport_index_layer,                          \
+      Extension::SPV_EXT_physical_storage_buffer,                              \
+      Extension::SPV_KHR_physical_storage_buffer,                              \
+      Extension::SPV_KHR_vulkan_memory_model
+
+  switch (version) {
+  default:
+    return {};
+  case Version::V_1_3: {
+    static Extension exts[] = {V_1_3_IMPLIED_EXTS};
+    return exts;
+  }
+  case Version::V_1_4: {
+    static Extension exts[] = {V_1_3_IMPLIED_EXTS, V_1_4_IMPLIED_EXTS};
+    return exts;
+  }
+  case Version::V_1_5: {
+    static Extension exts[] = {V_1_3_IMPLIED_EXTS, V_1_4_IMPLIED_EXTS,
+                               V_1_5_IMPLIED_EXTS};
+    return exts;
+  }
+  }
+
+#undef V_1_5_IMPLIED_EXTS
+#undef V_1_4_IMPLIED_EXTS
+#undef V_1_3_IMPLIED_EXTS
+}
+
+// Pull in utility function definition for implied capabilities
+#include "mlir/Dialect/SPIRV/SPIRVCapabilityImplication.inc"
+
+SmallVector<Capability, 0>
+spirv::getRecursiveImpliedCapabilities(Capability cap) {
+  ArrayRef<Capability> directCaps = getDirectImpliedCapabilities(cap);
+  llvm::SetVector<Capability, SmallVector<Capability, 0>> allCaps(
+      directCaps.begin(), directCaps.end());
+
+  // TODO(antiagainst): This is insufficient; find a better way to handle this
+  // (e.g., using static lists) if this turns out to be a bottleneck.
+  for (unsigned i = 0; i < allCaps.size(); ++i)
+    for (Capability c : getDirectImpliedCapabilities(allCaps[i]))
+      allCaps.insert(c);
+
+  return allCaps.takeVector();
+}
+
+//===----------------------------------------------------------------------===//
 // ArrayType
 //===----------------------------------------------------------------------===//
 
 struct spirv::detail::ArrayTypeStorage : public TypeStorage {
   using KeyTy = std::tuple<Type, unsigned, ArrayType::LayoutInfo>;
 
   static ArrayTypeStorage *construct(TypeStorageAllocator &allocator,
                                      const KeyTy &key) {

mlir/lib/TableGen/Attribute.cpp

 tblgen::Attribute tblgen::ConstantAttr::getAttribute() const {
   return Attribute(def->getValueAsDef("attr"));
 }
 
 StringRef tblgen::ConstantAttr::getConstantValue() const {
   return def->getValueAsString("value");
 }
 
-tblgen::EnumAttrCase::EnumAttrCase(const llvm::DefInit *init)
-    : Attribute(init) {
+tblgen::EnumAttrCase::EnumAttrCase(const llvm::Record *record)
+    : Attribute(record) {
   assert(isSubClassOf("EnumAttrCaseInfo") &&
          "must be subclass of TableGen 'EnumAttrInfo' class");
 }
 
+tblgen::EnumAttrCase::EnumAttrCase(const llvm::DefInit *init)
+    : EnumAttrCase(init->getDef()) {}
+
 bool tblgen::EnumAttrCase::isStrCase() const {
   return isSubClassOf("StrEnumAttrCase");
 }
 
 StringRef tblgen::EnumAttrCase::getSymbol() const {
   return def->getValueAsString("symbol");
 }
 

mlir/test/Dialect/SPIRV/TestAvailability.cpp

 };
 
 struct ConvertToAtomCmpExchangeWeak : public RewritePattern {
   ConvertToAtomCmpExchangeWeak(MLIRContext *context);
   PatternMatchResult matchAndRewrite(Operation *op,
                                      PatternRewriter &rewriter) const override;
 };
 
+struct ConvertToBitReverse : public RewritePattern {
+  ConvertToBitReverse(MLIRContext *context);
+  PatternMatchResult matchAndRewrite(Operation *op,
+                                     PatternRewriter &rewriter) const override;
+};
+
 struct ConvertToGroupNonUniformBallot : public RewritePattern {
   ConvertToGroupNonUniformBallot(MLIRContext *context);
   PatternMatchResult matchAndRewrite(Operation *op,
                                      PatternRewriter &rewriter) const override;
 };
 
+struct ConvertToModule : public RewritePattern {
+  ConvertToModule(MLIRContext *context);
+  PatternMatchResult matchAndRewrite(Operation *op,
+                                     PatternRewriter &rewriter) const override;
+};
+
 struct ConvertToSubgroupBallot : public RewritePattern {
   ConvertToSubgroupBallot(MLIRContext *context);
   PatternMatchResult matchAndRewrite(Operation *op,
                                      PatternRewriter &rewriter) const override;
 };
 } // end anonymous namespace
 
 void ConvertToTargetEnv::runOnFunction() {
   MLIRContext *context = &getContext();
   FuncOp fn = getFunction();
 
   auto targetEnv = fn.getOperation()
                        ->getAttr(spirv::getTargetEnvAttrName())
                        .cast<spirv::TargetEnvAttr>();
   auto target = spirv::SPIRVConversionTarget::get(targetEnv, context);
 
   OwningRewritePatternList patterns;
-  patterns.insert<ConvertToAtomCmpExchangeWeak, ConvertToGroupNonUniformBallot,
+  patterns.insert<ConvertToAtomCmpExchangeWeak, ConvertToBitReverse,
+                  ConvertToGroupNonUniformBallot, ConvertToModule,
                   ConvertToSubgroupBallot>(context);
 
   if (failed(applyPartialConversion(fn, *target, patterns)))
     return signalPassFailure();
 }
 
 ConvertToAtomCmpExchangeWeak::ConvertToAtomCmpExchangeWeak(MLIRContext *context)
     : RewritePattern("test.convert_to_atomic_compare_exchange_weak_op",
ConvertToAtomCmpExchangeWeak::matchAndRewrite(Operation *op,
   rewriter.replaceOpWithNewOp<spirv::AtomicCompareExchangeWeakOp>(
       op, value.getType(), ptr, spirv::Scope::Workgroup,
       spirv::MemorySemantics::AcquireRelease |
           spirv::MemorySemantics::AtomicCounterMemory,
       spirv::MemorySemantics::Acquire, value, comparator);
   return matchSuccess();
 }
 
+ConvertToBitReverse::ConvertToBitReverse(MLIRContext *context)
+    : RewritePattern("test.convert_to_bit_reverse_op", {"spv.BitReverse"}, 1,
+                     context) {}
+
+PatternMatchResult
+ConvertToBitReverse::matchAndRewrite(Operation *op,
+                                     PatternRewriter &rewriter) const {
+  Value predicate = op->getOperand(0);
+
+  rewriter.replaceOpWithNewOp<spirv::BitReverseOp>(
+      op, op->getResult(0).getType(), predicate);
+  return matchSuccess();
+}
+
 ConvertToGroupNonUniformBallot::ConvertToGroupNonUniformBallot(
     MLIRContext *context)
     : RewritePattern("test.convert_to_group_non_uniform_ballot_op",
                      {"spv.GroupNonUniformBallot"}, 1, context) {}
 
 PatternMatchResult ConvertToGroupNonUniformBallot::matchAndRewrite(
     Operation *op, PatternRewriter &rewriter) const {
   Value predicate = op->getOperand(0);
 
   rewriter.replaceOpWithNewOp<spirv::GroupNonUniformBallotOp>(
       op, op->getResult(0).getType(), spirv::Scope::Workgroup, predicate);
   return matchSuccess();
 }
 
+ConvertToModule::ConvertToModule(MLIRContext *context)
+    : RewritePattern("test.convert_to_module_op", {"spv.module"}, 1, context) {}
+
+PatternMatchResult
+ConvertToModule::matchAndRewrite(Operation *op,
+                                 PatternRewriter &rewriter) const {
+  rewriter.replaceOpWithNewOp<spirv::ModuleOp>(
+      op, spirv::AddressingModel::PhysicalStorageBuffer64,
+      spirv::MemoryModel::Vulkan);
+  return matchSuccess();
+}
+
 ConvertToSubgroupBallot::ConvertToSubgroupBallot(MLIRContext *context)
     : RewritePattern("test.convert_to_subgroup_ballot_op",
                      {"spv.SubgroupBallotKHR"}, 1, context) {}
 
 PatternMatchResult
 ConvertToSubgroupBallot::matchAndRewrite(Operation *op,
                                          PatternRewriter &rewriter) const {
   Value predicate = op->getOperand(0);

mlir/test/Dialect/SPIRV/availability.mlir

func @module_logical_glsl450() {
   // CHECK: spv.module extensions: [ ]
   // CHECK: spv.module capabilities: [ [Shader] ]
   spv.module "Logical" "GLSL450" { }
   return
 }
 
 // CHECK-LABEL: module_physical_storage_buffer64_vulkan
 func @module_physical_storage_buffer64_vulkan() {
-  // CHECK: spv.module min version: V_1_5
+  // CHECK: spv.module min version: V_1_0
   // CHECK: spv.module max version: V_1_5
   // CHECK: spv.module extensions: [ [SPV_EXT_physical_storage_buffer, SPV_KHR_physical_storage_buffer] [SPV_KHR_vulkan_memory_model] ]
   // CHECK: spv.module capabilities: [ [PhysicalStorageBufferAddresses] [VulkanMemoryModel] ]
   spv.module "PhysicalStorageBuffer64" "Vulkan" { }
   return
 }

mlir/test/Dialect/SPIRV/target-env.mlir

 // RUN: mlir-opt -disable-pass-threading -test-spirv-target-env %s | FileCheck %s
 
 // Note: The following tests check that a spv.target_env can properly control
 // the conversion target and filter unavailable ops during the conversion.
 // We don't care about the op argument consistency too much; so certain enum
 // values for enum attributes may not make much sense for the test op.
 
 // spv.AtomicCompareExchangeWeak is available from SPIR-V 1.0 to 1.3 under
 // Kernel capability.
 // spv.AtomicCompareExchangeWeak has two memory semantics enum attribute,
 // whose value, if containing AtomicCounterMemory bit, additionally requires
 // AtomicStorage capability.
 
+// spv.BitReverse is available in all SPIR-V versiosn under Shader capability.
+
 // spv.GroupNonUniformBallot is available starting from SPIR-V 1.3 under
 // GroupNonUniform capability.
 
 // spv.SubgroupBallotKHR is available under in all SPIR-V versions under
 // SubgroupBallotKHR capability and SPV_KHR_shader_ballot extension.
 
+// The GeometryPointSize capability implies the Geometry capability, which
+// implies the Shader capability.
+
+// PhysicalStorageBuffer64 addressing model is available via extension
+// SPV_EXT_physical_storage_buffer or SPV_KHR_physical_storage_buffer;
+// both extensions are incorporated into SPIR-V 1.5.
+
+// Vulkan memory model is available via extension SPV_KHR_vulkan_memory_model,
+// which extensions are incorporated into SPIR-V 1.5.
+
 // Enum case symbol (value) map:
-// Version: 1.0 (0), 1.1 (1), 1.2 (2), 1.3 (3), 1.4 (4)
-// Capability: Kernel (6), AtomicStorage (21), GroupNonUniformBallot (64),
-//             SubgroupBallotKHR (4423)
+// Version: 1.0 (0), 1.1 (1), 1.2 (2), 1.3 (3), 1.4 (4), 1.5 (5)
+// Capability: Shader (1), Geometry (2), Kernel (6), AtomicStorage (21),
+//             GeometryPointSize (24), GroupNonUniformBallot (64),
+//             SubgroupBallotKHR (4423), VulkanMemoryModel (5345),
+//             PhysicalStorageBufferAddresses (5347)
 
 //===----------------------------------------------------------------------===//
 // MaxVersion
 //===----------------------------------------------------------------------===//
 
 // CHECK-LABEL: @cmp_exchange_weak_suitable_version_capabilities
 func @cmp_exchange_weak_suitable_version_capabilities(%ptr: !spv.ptr<i32, Workgroup>, %value: i32, %comparator: i32) -> i32 attributes {
   spv.target_env = {version = 1: i32, extensions = [], capabilities = [6: i32, 21: i32]}

 func @subgroup_ballot_missing_capability(%predicate: i1) -> vector<4xi32> attributes {
   spv.target_env = {version = 4: i32, extensions = ["SPV_KHR_shader_ballot"], capabilities = []}
 } {
   // CHECK: test.convert_to_subgroup_ballot_op
   %0 = "test.convert_to_subgroup_ballot_op"(%predicate): (i1) -> (vector<4xi32>)
   return %0: vector<4xi32>
 }
 
+// CHECK-LABEL: @bit_reverse_directly_implied_capability
+func @bit_reverse_directly_implied_capability(%operand: i32) -> i32 attributes {
+  spv.target_env = {version = 0: i32, extensions = [], capabilities = [2: i32]}
+} {
+  // CHECK: spv.BitReverse
+  %0 = "test.convert_to_bit_reverse_op"(%operand): (i32) -> (i32)
+  return %0: i32
+}
+
+// CHECK-LABEL: @bit_reverse_recursively_implied_capability
+func @bit_reverse_recursively_implied_capability(%operand: i32) -> i32 attributes {
+  spv.target_env = {version = 0: i32, extensions = [], capabilities = [24: i32]}
+} {
+  // CHECK: spv.BitReverse
+  %0 = "test.convert_to_bit_reverse_op"(%operand): (i32) -> (i32)
+  return %0: i32
+}
+
 //===----------------------------------------------------------------------===//
 // Extension
 //===----------------------------------------------------------------------===//
 
 // CHECK-LABEL: @subgroup_ballot_suitable_extension
 func @subgroup_ballot_suitable_extension(%predicate: i1) -> vector<4xi32> attributes {
   spv.target_env = {version = 4: i32, extensions = ["SPV_KHR_shader_ballot"], capabilities = [4423: i32]}
 } {
   // CHECK: spv.SubgroupBallotKHR
   %0 = "test.convert_to_subgroup_ballot_op"(%predicate): (i1) -> (vector<4xi32>)
   return %0: vector<4xi32>
 }
 
 // CHECK-LABEL: @subgroup_ballot_missing_extension
 func @subgroup_ballot_missing_extension(%predicate: i1) -> vector<4xi32> attributes {
   spv.target_env = {version = 4: i32, extensions = [], capabilities = [4423: i32]}
 } {
   // CHECK: test.convert_to_subgroup_ballot_op
   %0 = "test.convert_to_subgroup_ballot_op"(%predicate): (i1) -> (vector<4xi32>)
   return %0: vector<4xi32>
 }
+
+// CHECK-LABEL: @module_suitable_extension1
+func @module_suitable_extension1() attributes {
+  spv.target_env = {version = 0: i32, extensions = ["SPV_KHR_vulkan_memory_model", "SPV_EXT_physical_storage_buffer"], capabilities = [5345: i32, 5347: i32]}
+} {
+  // CHECK: spv.module "PhysicalStorageBuffer64" "Vulkan"
+  "test.convert_to_module_op"() : () ->()
+  return
+}
+
+// CHECK-LABEL: @module_suitable_extension2
+func @module_suitable_extension2() attributes {
+  spv.target_env = {version = 0: i32, extensions = ["SPV_KHR_vulkan_memory_model", "SPV_KHR_physical_storage_buffer"], capabilities = [5345: i32, 5347: i32]}
+} {
+  // CHECK: spv.module "PhysicalStorageBuffer64" "Vulkan"
+  "test.convert_to_module_op"() : () -> ()
+  return
+}
+
+// CHECK-LABEL: @module_missing_extension_mm
+func @module_missing_extension_mm() attributes {
+  spv.target_env = {version = 0: i32, extensions = ["SPV_KHR_physical_storage_buffer"], capabilities = [5345: i32, 5347: i32]}
+} {
+  // CHECK: test.convert_to_module_op
+  "test.convert_to_module_op"() : () -> ()
+  return
+}
+
+// CHECK-LABEL: @module_missing_extension_am
+func @module_missing_extension_am() attributes {
+  spv.target_env = {version = 0: i32, extensions = ["SPV_KHR_vulkan_memory_model"], capabilities = [5345: i32, 5347: i32]}
+} {
+  // CHECK: test.convert_to_module_op
+  "test.convert_to_module_op"() : () -> ()
+  return
+}
+
+// CHECK-LABEL: @module_implied_extension
+func @module_implied_extension() attributes {
+  // Version 1.5 implies SPV_KHR_vulkan_memory_model and SPV_KHR_physical_storage_buffer.
+  spv.target_env = {version = 5: i32, extensions = [], capabilities = [5345: i32, 5347: i32]}
+} {
+  // CHECK: spv.module "PhysicalStorageBuffer64" "Vulkan"
+  "test.convert_to_module_op"() : () -> ()
+  return
+}

mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp

 //===- SPIRVSerializationGen.cpp - SPIR-V serialization utility generator -===//
 //
 // Part of the MLIR Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // SPIRVSerializationGen generates common utility functions for SPIR-V
 // serialization.
 //
 //===----------------------------------------------------------------------===//
 
+#include "mlir/Support/STLExtras.h"
 #include "mlir/Support/StringExtras.h"
 #include "mlir/TableGen/Attribute.h"
 #include "mlir/TableGen/Format.h"
 #include "mlir/TableGen/GenInfo.h"
 #include "mlir/TableGen/Operator.h"
 #include "llvm/ADT/Sequence.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringExtras.h"

 //===----------------------------------------------------------------------===//
 
 static mlir::GenRegistration
     genOpAvailabilityImpl("gen-spirv-avail-impls",
                           "Generate SPIR-V operation utility definitions",
                           [](const RecordKeeper &records, raw_ostream &os) {
                             return emitAvailabilityImpl(records, os);
                           });
+
+//===----------------------------------------------------------------------===//
+// SPIR-V Capability Implication AutoGen
+//===----------------------------------------------------------------------===//
+
+static bool emitCapabilityImplication(const RecordKeeper &recordKeeper,
+                                      raw_ostream &os) {
+  llvm::emitSourceFileHeader("SPIR-V Capability Implication", os);
+
+  EnumAttr enumAttr(recordKeeper.getDef("SPV_CapabilityAttr"));
+
+  os << "ArrayRef<Capability> "
+        "spirv::getDirectImpliedCapabilities(Capability cap) {\n"
+     << "  switch (cap) {\n"
+     << "  default: return {};\n";
+  for (const EnumAttrCase &enumerant : enumAttr.getAllCases()) {
+    const Record &def = enumerant.getDef();
+    if (!def.getValue("implies"))
+      continue;
+
+    os << "  case Capability::" << enumerant.getSymbol()
+       << ": {static Capability implies[] = {";
+    std::vector<Record *> impliedCapsDefs = def.getValueAsListOfDefs("implies");
+    mlir::interleaveComma(impliedCapsDefs, os, [&](const Record *capDef) {
+      os << "Capability::" << EnumAttrCase(capDef).getSymbol();
+    });
+    os << "}; return implies; }\n";
+  }
+  os << "  }\n";
+  os << "}\n";
+
+  return false;
+}
+
+//===----------------------------------------------------------------------===//
+// SPIR-V Capability Implication Hook Registration
+//===----------------------------------------------------------------------===//
+
+static mlir::GenRegistration
+    genCapabilityImplication("gen-spirv-capability-implication",
+                             "Generate utilty function to return implied "
+                             "capabilities for a given capability",
+                             [](const RecordKeeper &records, raw_ostream &os) {
+                               return emitCapabilityImplication(records, os);
+                             });

mlir/utils/spirv/gen_spirv_dialect.py

def get_availability_spec(enum_case, capability_mapping, for_op, for_cap):
   # TODO(antiagainst): delete this once ODS can support dialect-specific content
   # and we can use omission to mean no requirements.
   if for_op and not max_version:
     max_version = 'MaxVersion<SPV_V_1_5>'
 
   exts = enum_case.get('extensions', [])
   if exts:
     exts = 'Extension<[{}]>'.format(', '.join(sorted(set(exts))))
+    # We need to strip the minimal version requirement if this symbol is
+    # available via an extension, which means *any* SPIR-V version can support
+    # it as long as the extension is provided. The grammar's 'version' field
+    # under such case should be interpreted as this symbol is introduced as
+    # a core symbol since the given version, rather than a minimal version
+    # requirement.
+    min_version = 'MinVersion<SPV_V_1_0>' if for_op else ''
   # TODO(antiagainst): delete this once ODS can support dialect-specific content
   # and we can use omission to mean no requirements.
   if for_op and not exts:
     exts = 'Extension<[]>'
 
   caps = enum_case.get('capabilities', [])
   implies = ''
   if caps: