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[SelectionDAG] ComputeKnownBits - minimum leading/trailing zero bits in LSHR/SHL (PR44526)
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Authored by RKSimon on Jan 12 2020, 9:20 AM.

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Summary

PR44526 - as detailed in https://blog.regehr.org/archives/1709 we don't make use of the known leading/trailing zeros for shifted values in cases where we don't know the shift amount value.

This patch adds support to SelectionDAG::ComputeKnownBits to use KnownBits::countMinTrailingZeros and countMinLeadingZeros to set the minimum guaranteed leading/trailing known zero bits.

Diff Detail

Event Timeline

RKSimon created this revision.Jan 12 2020, 9:20 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 12 2020, 9:20 AM
lebedev.ri added inline comments.Jan 12 2020, 9:35 AM
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
2870–2871

Same for signbit given arithmetic right-shift?

RKSimon added inline comments.Jan 12 2020, 9:41 AM
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
2870–2871

ComputeNumSignBits already does something similar for ISA::SRA - it always gets the number of sign bits of Op0 and increases it if the shift amount is constant

lebedev.ri accepted this revision.Jan 12 2020, 10:00 AM

LG, thank you.

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
2837

Could also have getValidMinimumShiftAmountConstant() branch like for ISD::SRL?

2870–2871

Ah indeed, but then ComputeNumSignBits() doesn't handle ISD::SRL like it does ISA::SRA.

This revision is now accepted and ready to land.Jan 12 2020, 10:00 AM
This revision was automatically updated to reflect the committed changes.
RKSimon marked 2 inline comments as done.Jan 13 2020, 6:38 AM
RKSimon added inline comments.
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
2837

Done in a number of follow up commits.

2870–2871

Yup, ISD::SRL ComputeNumSignBits() calls use the default fallback to call ComputeKnownBits() as we're only interested in leading zero bits anyway.