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Differential D72392

[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
ClosedPublic

Authored by foad on Jan 8 2020, 3:50 AM.

Details

Reviewers
atrick
MatzeB
t.p.northover
arsenm
hfinkel
craig.topper
fhahn
Commits
rG62fd7f767c41: [MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
Summary

tryLatency compares two sched candidates. For the top zone it prefers
the one with lesser depth, but only if that depth is greater than the
total latency of the instructions we've already scheduled -- otherwise
its latency would be hidden and there would be no stall.

Unfortunately it only tests the depth of one of the candidates. This can
lead to situations where the TopDepthReduce heuristic does not kick in,
but a lower priority heuristic chooses the other candidate, whose depth
*is* greater than the already scheduled latency, which causes a stall.

The fix is to apply the heuristic if the depth of *either* candidate is
greater than the already scheduled latency.

All this also applies to the BotHeightReduce heuristic in the bottom
zone.

Diff Detail

Event Timeline

foad created this revision.Jan 8 2020, 3:50 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 8 2020, 3:50 AM
Herald added subscribers: herhut, asbirlea, jsji and 8 others. · View Herald Transcript
merge_guards_bot added a subscriber: merge_guards_bot.Jan 8 2020, 4:00 AM

Unit tests: pass. 61306 tests passed, 0 failed and 736 were skipped.

clang-tidy: fail. Please fix clang-tidy findings.

clang-format: pass.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

Herald added a subscriber: • wuzish. · View Herald TranscriptJan 8 2020, 4:00 AM
Harbormaster failed remote builds in B43497: Diff 236792!Jan 8 2020, 4:00 AM
fhahn added a subscriber: fhahn.Jan 9 2020, 2:58 AM

There's a lot of small test changes (expected), but IMO I would be good to have an isolated test only tests the new behavior and shows an improvement (probably best as MIR machine-scheduler only test).

Also, do you have any performance/codesize numbers for impacted targets?

foad added a comment.Jan 9 2020, 3:57 AM

The diff in llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll is:

        adrp    x8, .LCPI0_0
-       ldr     h0, [x8, :lo12:.LCPI0_0]
        movi    v1.2d, #0000000000000000
        movi    v2.2d, #0000000000000000
+       ldr     h0, [x8, :lo12:.LCPI0_0]
        movi    v3.2d, #0000000000000000

The scheduler prefers not to put the ldr immediately after the adrp because of the register dependency on x8 with latency 1.

foad added a comment.Jan 9 2020, 3:59 AM

The diff in llvm/test/CodeGen/X86/testb-je-fusion.ll is:

        movl    %edi, %eax
-       addl    $-512, %eax             # imm = 0xFE00
        movb    $1, (%rsi)
+       addl    $-512, %eax             # imm = 0xFE00
        je      .LBB2_2
...
        movl    %edi, %eax
-       decl    %eax
        movb    $1, (%rsi)
+       decl    %eax
        je      .LBB3_2

The scheduler prefers not to put the addl/decl immediately after the first movl because of the register dependency on eax with latency 1.

foad added a comment.Jan 9 2020, 4:10 AM
In D72392#1811691, @fhahn wrote:

Also, do you have any performance/codesize numbers for impacted targets?

I did some performance testing of graphics shaders on the AMDGPU target. Out of ~350 shaders the average performance changed by less than 0.01%, only 5 shaders changed by more than 1%, and the biggest swings were -4%/+3%. So I think there is no significant overall trend.

I would welcome any help with performance testing on AArch64/PowerPC/X86.

fhahn added a comment.Jan 9 2020, 4:12 AM
In D72392#1811735, @foad wrote:

The diff in llvm/test/CodeGen/X86/testb-je-fusion.ll is:

        movl    %edi, %eax
-       addl    $-512, %eax             # imm = 0xFE00
        movb    $1, (%rsi)
+       addl    $-512, %eax             # imm = 0xFE00
        je      .LBB2_2
...
        movl    %edi, %eax
-       decl    %eax
        movb    $1, (%rsi)
+       decl    %eax
        je      .LBB3_2

The scheduler prefers not to put the addl/decl immediately after the first movl because of the register dependency on eax with latency 1.

Great. My main point about the tests was that I think it would be good to have a dedicated small test that just checks on rod the improved cases, with a clear explanation, to guard against regressions by other scheduler changes with a lot of test changes

foad updated this revision to Diff 237332.Jan 10 2020, 7:58 AM

New tests for this specific fix:
test/CodeGen/PowerPC/botheightreduce.mir
test/CodeGen/PowerPC/topdepthreduce-postra.mir
test/CodeGen/X86/topdepthreduce-postra.mir

merge_guards_bot added a comment.Jan 10 2020, 8:12 AM

Unit tests: pass. 61747 tests passed, 0 failed and 780 were skipped.

clang-tidy: pass.

clang-format: pass.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

Harbormaster completed remote builds in B43682: Diff 237332.Jan 10 2020, 8:12 AM
foad updated this revision to Diff 238215.Jan 15 2020, 3:58 AM

Rebase.

foad added a reviewer: fhahn.Jan 15 2020, 3:59 AM
merge_guards_bot added a comment.Jan 15 2020, 4:32 AM

Unit tests: pass. 61887 tests passed, 0 failed and 782 were skipped.

clang-tidy: unknown.

clang-format: pass.

Build artifacts: diff.json, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

Harbormaster completed remote builds in B44031: Diff 238215.Jan 15 2020, 4:38 AM
foad added a comment.Jan 29 2020, 8:32 AM

Ping!

Herald added a subscriber: kerbowa. · View Herald TranscriptJan 29 2020, 8:32 AM
rampitec added a subscriber: rampitec.Feb 3 2020, 5:34 PM
foad added a child revision: D73957: [AMDGPU] getMemOperandsWithOffset: add vaddr operand for stack access BUF instructions.Feb 4 2020, 5:31 AM
foad added a comment.Feb 11 2020, 11:23 AM

Ping! @fhahn do you have any further comments?

foad added a comment.Feb 27 2020, 7:54 AM

Ping!

foad added a comment.Mar 12 2020, 9:24 AM

Ping!

foad added a comment.Jul 16 2020, 7:46 AM

Ping.

arsenm accepted this revision.Jul 16 2020, 8:56 AM
This revision is now accepted and ready to land.Jul 16 2020, 8:56 AM
fhahn accepted this revision.Jul 16 2020, 9:03 AM

Looks reasonable, thanks for adding the MIR test as well. Sorry for the delay, it dropped off my radar.

llvm/lib/CodeGen/MachineScheduler.cpp
2727–2731

It might be good to add a comment here explaining what we are checking here. (same as below).

Closed by commit rG62fd7f767c41: [MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics (authored by foad). · Explain WhyJul 17 2020, 3:02 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

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Diff 278698

llvm/lib/CodeGen/MachineScheduler.cpp

Show First 20 Lines • Show All 2,718 Lines • ▼ Show 20 Linesbool tryGreater(int TryVal, int CandVal,
} }
return false; return false;
} }
bool tryLatency(GenericSchedulerBase::SchedCandidate &TryCand, bool tryLatency(GenericSchedulerBase::SchedCandidate &TryCand,
GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::SchedCandidate &Cand,
SchedBoundary &Zone) { SchedBoundary &Zone) {
if (Zone.isTop()) { if (Zone.isTop()) {
if (Cand.SU->getDepth() > Zone.getScheduledLatency()) { // Prefer the candidate with the lesser depth, but only if one of them has
// depth greater than the total latency scheduled so far, otherwise either
// of them could be scheduled now with no stall.
if (std::max(TryCand.SU->getDepth(), Cand.SU->getDepth()) >
Zone.getScheduledLatency()) {
fhahnUnsubmitted
Not Done
ReplyInline Actions

It might be good to add a comment here explaining what we are checking here. (same as below).

fhahn: It might be good to add a comment here explaining what we are checking here. (same as below).
if (tryLess(TryCand.SU->getDepth(), Cand.SU->getDepth(), if (tryLess(TryCand.SU->getDepth(), Cand.SU->getDepth(),
TryCand, Cand, GenericSchedulerBase::TopDepthReduce)) TryCand, Cand, GenericSchedulerBase::TopDepthReduce))
return true; return true;
} }
if (tryGreater(TryCand.SU->getHeight(), Cand.SU->getHeight(), if (tryGreater(TryCand.SU->getHeight(), Cand.SU->getHeight(),
TryCand, Cand, GenericSchedulerBase::TopPathReduce)) TryCand, Cand, GenericSchedulerBase::TopPathReduce))
return true; return true;
} else { } else {
if (Cand.SU->getHeight() > Zone.getScheduledLatency()) { // Prefer the candidate with the lesser height, but only if one of them has
// height greater than the total latency scheduled so far, otherwise either
// of them could be scheduled now with no stall.
if (std::max(TryCand.SU->getHeight(), Cand.SU->getHeight()) >
Zone.getScheduledLatency()) {
if (tryLess(TryCand.SU->getHeight(), Cand.SU->getHeight(), if (tryLess(TryCand.SU->getHeight(), Cand.SU->getHeight(),
TryCand, Cand, GenericSchedulerBase::BotHeightReduce)) TryCand, Cand, GenericSchedulerBase::BotHeightReduce))
return true; return true;
} }
if (tryGreater(TryCand.SU->getDepth(), Cand.SU->getDepth(), if (tryGreater(TryCand.SU->getDepth(), Cand.SU->getDepth(),
TryCand, Cand, GenericSchedulerBase::BotPathReduce)) TryCand, Cand, GenericSchedulerBase::BotPathReduce))
return true; return true;
} }
▲ Show 20 Lines • Show All 1,061 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll

Show All 21 Lines
; NONEFP: ldr h0,{{.*}} ; NONEFP: ldr h0,{{.*}}
; NONEFP: fmov s1, wzr ; NONEFP: fmov s1, wzr
; NONEFP: fmov d2, xzr ; NONEFP: fmov d2, xzr
; NONEFP: movi{{(.16b)?}} v3{{(.2d)?}}, #0 ; NONEFP: movi{{(.16b)?}} v3{{(.2d)?}}, #0
; NONE16: fmov h0, wzr ; NONE16: fmov h0, wzr
; NONE16: fmov s1, wzr ; NONE16: fmov s1, wzr
; NONE16: fmov d2, xzr ; NONE16: fmov d2, xzr
; NONE16: movi{{(.16b)?}} v3{{(.2d)?}}, #0 ; NONE16: movi{{(.16b)?}} v3{{(.2d)?}}, #0
; ZEROFP: ldr h0,{{.*}} ; ZEROFP-DAG: ldr h0,{{.*}}
; ZEROFP: movi v{{[0-3]+}}.2d, #0 ; ZEROFP-DAG: movi v{{[0-3]+}}.2d, #0
; ZEROFP: movi v{{[0-3]+}}.2d, #0 ; ZEROFP-DAG: movi v{{[0-3]+}}.2d, #0
; ZEROFP: movi v{{[0-3]+}}.2d, #0 ; ZEROFP-DAG: movi v{{[0-3]+}}.2d, #0
; ZERO16: movi v{{[0-3]+}}.2d, #0 ; ZERO16: movi v{{[0-3]+}}.2d, #0
; ZERO16: movi v{{[0-3]+}}.2d, #0 ; ZERO16: movi v{{[0-3]+}}.2d, #0
; ZERO16: movi v{{[0-3]+}}.2d, #0 ; ZERO16: movi v{{[0-3]+}}.2d, #0
; ZERO16: movi v{{[0-3]+}}.2d, #0 ; ZERO16: movi v{{[0-3]+}}.2d, #0
tail call void @bar(half 0.000000e+00, float 0.000000e+00, double 0.000000e+00, <2 x double> <double 0.000000e+00, double 0.000000e+00>) nounwind tail call void @bar(half 0.000000e+00, float 0.000000e+00, double 0.000000e+00, <2 x double> <double 0.000000e+00, double 0.000000e+00>) nounwind
ret void ret void
} }
▲ Show 20 Lines • Show All 190 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll

Show First 20 Lines • Show All 584 Lines • ▼ Show 20 Lines
; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 2 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
; SI-NEXT: s_mov_b32 s2, 0 ; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_load_ubyte v2, v[0:1], s[0:3], 0 addr64 ; SI-NEXT: buffer_load_ubyte v2, v[0:1], s[0:3], 0 addr64
; SI-NEXT: buffer_load_ubyte v3, v[0:1], s[0:3], 0 addr64 offset:1 ; SI-NEXT: buffer_load_ubyte v3, v[0:1], s[0:3], 0 addr64 offset:1
; SI-NEXT: buffer_load_ubyte v4, v[0:1], s[0:3], 0 addr64 offset:2 ; SI-NEXT: buffer_load_ubyte v4, v[0:1], s[0:3], 0 addr64 offset:2
; SI-NEXT: buffer_load_ubyte v0, v[0:1], s[0:3], 0 addr64 offset:3 ; SI-NEXT: buffer_load_ubyte v0, v[0:1], s[0:3], 0 addr64 offset:3
; SI-NEXT: s_movk_i32 s6, 0xff ; SI-NEXT: s_movk_i32 s0, 0xff
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_mov_b64 s[6:7], s[2:3]
; SI-NEXT: s_waitcnt vmcnt(3) ; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_and_b32_e32 v1, s6, v2 ; SI-NEXT: v_and_b32_e32 v1, s0, v2
; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_and_b32_e32 v2, s6, v3 ; SI-NEXT: v_and_b32_e32 v2, s0, v3
; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v3, s6, v4 ; SI-NEXT: v_and_b32_e32 v3, s0, v4
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v4, s6, v0 ; SI-NEXT: v_and_b32_e32 v4, s0, v0
; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v1 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v1
; SI-NEXT: v_cvt_f32_ubyte0_e32 v1, v2 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v1, v2
; SI-NEXT: v_cvt_f32_ubyte0_e32 v2, v3 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v2, v3
; SI-NEXT: v_cvt_f32_ubyte0_e32 v3, v4 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v3, v4
; SI-NEXT: s_mov_b64 s[6:7], s[2:3]
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: load_v4i8_to_v4f32_unaligned: ; VI-LABEL: load_v4i8_to_v4f32_unaligned:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
▲ Show 20 Lines • Show All 218 Lines • ▼ Show 20 Lines
; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 2 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
; SI-NEXT: s_mov_b32 s2, 0 ; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_load_ubyte v2, v[0:1], s[0:3], 0 addr64 ; SI-NEXT: buffer_load_ubyte v2, v[0:1], s[0:3], 0 addr64
; SI-NEXT: buffer_load_ubyte v3, v[0:1], s[0:3], 0 addr64 offset:1 ; SI-NEXT: buffer_load_ubyte v3, v[0:1], s[0:3], 0 addr64 offset:1
; SI-NEXT: buffer_load_ubyte v4, v[0:1], s[0:3], 0 addr64 offset:2 ; SI-NEXT: buffer_load_ubyte v4, v[0:1], s[0:3], 0 addr64 offset:2
; SI-NEXT: buffer_load_ubyte v0, v[0:1], s[0:3], 0 addr64 offset:3 ; SI-NEXT: buffer_load_ubyte v0, v[0:1], s[0:3], 0 addr64 offset:3
; SI-NEXT: s_movk_i32 s6, 0xff ; SI-NEXT: s_movk_i32 s0, 0xff
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_mov_b64 s[6:7], s[2:3]
; SI-NEXT: s_waitcnt vmcnt(3) ; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_and_b32_e32 v1, s6, v2 ; SI-NEXT: v_and_b32_e32 v1, s0, v2
; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_and_b32_e32 v2, s6, v3 ; SI-NEXT: v_and_b32_e32 v2, s0, v3
; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v3, s6, v4 ; SI-NEXT: v_and_b32_e32 v3, s0, v4
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v4, s6, v0 ; SI-NEXT: v_and_b32_e32 v4, s0, v0
; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v1 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v1
; SI-NEXT: v_cvt_f32_ubyte0_e32 v1, v2 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v1, v2
; SI-NEXT: v_cvt_f32_ubyte0_e32 v2, v3 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v2, v3
; SI-NEXT: v_cvt_f32_ubyte0_e32 v3, v4 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v3, v4
; SI-NEXT: s_mov_b64 s[6:7], s[2:3]
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: v4i8_zext_v4i32_to_v4f32: ; VI-LABEL: v4i8_zext_v4i32_to_v4f32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
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llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll

Show First 20 Lines • Show All 135 Lines • ▼ Show 20 Lines
; CHECK-NEXT: s_waitcnt lgkmcnt(0) ; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: s_cmp_lg_u32 s4, 0 ; CHECK-NEXT: s_cmp_lg_u32 s4, 0
; CHECK-NEXT: s_cselect_b32 s4, 1, 0 ; CHECK-NEXT: s_cselect_b32 s4, 1, 0
; CHECK-NEXT: s_xor_b32 s4, s4, 1 ; CHECK-NEXT: s_xor_b32 s4, s4, 1
; CHECK-NEXT: s_and_b32 s4, s4, 1 ; CHECK-NEXT: s_and_b32 s4, s4, 1
; CHECK-NEXT: s_cmp_lg_u32 s4, 0 ; CHECK-NEXT: s_cmp_lg_u32 s4, 0
; CHECK-NEXT: s_cbranch_scc0 BB4_6 ; CHECK-NEXT: s_cbranch_scc0 BB4_6
; CHECK-NEXT: ; %bb.1: ; %bb2 ; CHECK-NEXT: ; %bb.1: ; %bb2
; CHECK-NEXT: s_getpc_b64 s[6:7] ; CHECK-NEXT: s_getpc_b64 s[4:5]
; CHECK-NEXT: s_add_u32 s6, s6, const.ptr@gotpcrel32@lo+4 ; CHECK-NEXT: s_add_u32 s4, s4, const.ptr@gotpcrel32@lo+4
; CHECK-NEXT: s_addc_u32 s7, s7, const.ptr@gotpcrel32@hi+4 ; CHECK-NEXT: s_addc_u32 s5, s5, const.ptr@gotpcrel32@hi+4
; CHECK-NEXT: s_load_dwordx2 s[6:7], s[6:7], 0x0 ; CHECK-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
; CHECK-NEXT: s_mov_b32 s4, -1 ; CHECK-NEXT: v_cmp_ne_u32_e64 s[6:7], 0, 1
; CHECK-NEXT: s_waitcnt lgkmcnt(0) ; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: s_load_dwordx2 s[6:7], s[6:7], 0x0 ; CHECK-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
; CHECK-NEXT: s_waitcnt lgkmcnt(0) ; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_mov_b32_e32 v0, s6 ; CHECK-NEXT: v_mov_b32_e32 v0, s4
; CHECK-NEXT: v_mov_b32_e32 v1, s7 ; CHECK-NEXT: v_mov_b32_e32 v1, s5
; CHECK-NEXT: flat_load_dword v0, v[0:1] ; CHECK-NEXT: flat_load_dword v0, v[0:1]
; CHECK-NEXT: v_cmp_ne_u32_e64 s[6:7], 0, 1 ; CHECK-NEXT: s_mov_b32 s4, -1
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_cmp_gt_f32_e32 vcc, 1.0, v0 ; CHECK-NEXT: v_cmp_gt_f32_e32 vcc, 1.0, v0
; CHECK-NEXT: s_xor_b64 s[8:9], vcc, s[6:7] ; CHECK-NEXT: s_xor_b64 s[8:9], vcc, s[6:7]
; CHECK-NEXT: s_and_saveexec_b64 s[6:7], s[8:9] ; CHECK-NEXT: s_and_saveexec_b64 s[6:7], s[8:9]
; CHECK-NEXT: ; %bb.2: ; %bb7 ; CHECK-NEXT: ; %bb.2: ; %bb7
; CHECK-NEXT: s_mov_b32 s4, 0 ; CHECK-NEXT: s_mov_b32 s4, 0
; CHECK-NEXT: ; %bb.3: ; %bb8 ; CHECK-NEXT: ; %bb.3: ; %bb8
; CHECK-NEXT: s_or_b64 exec, exec, s[6:7] ; CHECK-NEXT: s_or_b64 exec, exec, s[6:7]
▲ Show 20 Lines • Show All 89 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll

Show First 20 Lines • Show All 1,549 Lines • ▼ Show 20 Lines; GFX9-NEXT: s_endpgm
ret void ret void
} }
define amdgpu_kernel void @nocse_lds_atomic_inc_ret_i32(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 addrspace(3)* %ptr) #0 { define amdgpu_kernel void @nocse_lds_atomic_inc_ret_i32(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 addrspace(3)* %ptr) #0 {
; CI-LABEL: nocse_lds_atomic_inc_ret_i32: ; CI-LABEL: nocse_lds_atomic_inc_ret_i32:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; CI-NEXT: s_load_dword s4, s[4:5], 0x4 ; CI-NEXT: s_load_dword s4, s[4:5], 0x4
; CI-NEXT: v_mov_b32_e32 v2, 42 ; CI-NEXT: v_mov_b32_e32 v0, 42
; CI-NEXT: s_mov_b32 m0, -1 ; CI-NEXT: s_mov_b32 m0, -1
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s2 ; CI-NEXT: v_mov_b32_e32 v2, s2
; CI-NEXT: v_mov_b32_e32 v3, s4 ; CI-NEXT: v_mov_b32_e32 v1, s4
; CI-NEXT: ds_inc_rtn_u32 v4, v3, v2 ; CI-NEXT: ds_inc_rtn_u32 v4, v1, v0
; CI-NEXT: ds_inc_rtn_u32 v5, v3, v2 ; CI-NEXT: ds_inc_rtn_u32 v5, v1, v0
; CI-NEXT: v_mov_b32_e32 v3, s1 ; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: v_mov_b32_e32 v2, s0 ; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: v_mov_b32_e32 v1, s3 ; CI-NEXT: v_mov_b32_e32 v3, s3
; CI-NEXT: s_waitcnt lgkmcnt(1) ; CI-NEXT: s_waitcnt lgkmcnt(1)
; CI-NEXT: flat_store_dword v[2:3], v4 ; CI-NEXT: flat_store_dword v[0:1], v4
; CI-NEXT: s_waitcnt lgkmcnt(1) ; CI-NEXT: s_waitcnt lgkmcnt(1)
; CI-NEXT: flat_store_dword v[0:1], v5 ; CI-NEXT: flat_store_dword v[2:3], v5
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; VI-LABEL: nocse_lds_atomic_inc_ret_i32: ; VI-LABEL: nocse_lds_atomic_inc_ret_i32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; VI-NEXT: s_load_dword s4, s[4:5], 0x10 ; VI-NEXT: s_load_dword s4, s[4:5], 0x10
; VI-NEXT: v_mov_b32_e32 v2, 42 ; VI-NEXT: v_mov_b32_e32 v0, 42
; VI-NEXT: s_mov_b32 m0, -1 ; VI-NEXT: s_mov_b32 m0, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s2 ; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s4 ; VI-NEXT: v_mov_b32_e32 v1, s4
; VI-NEXT: ds_inc_rtn_u32 v4, v3, v2 ; VI-NEXT: ds_inc_rtn_u32 v4, v1, v0
; VI-NEXT: ds_inc_rtn_u32 v5, v3, v2 ; VI-NEXT: ds_inc_rtn_u32 v5, v1, v0
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v2, s0 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: s_waitcnt lgkmcnt(1) ; VI-NEXT: s_waitcnt lgkmcnt(1)
; VI-NEXT: flat_store_dword v[2:3], v4 ; VI-NEXT: flat_store_dword v[0:1], v4
; VI-NEXT: s_waitcnt lgkmcnt(1) ; VI-NEXT: s_waitcnt lgkmcnt(1)
; VI-NEXT: flat_store_dword v[0:1], v5 ; VI-NEXT: flat_store_dword v[2:3], v5
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: nocse_lds_atomic_inc_ret_i32: ; GFX9-LABEL: nocse_lds_atomic_inc_ret_i32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX9-NEXT: s_load_dword s4, s[4:5], 0x10 ; GFX9-NEXT: s_load_dword s4, s[4:5], 0x10
; GFX9-NEXT: v_mov_b32_e32 v0, 42 ; GFX9-NEXT: v_mov_b32_e32 v0, 42
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
Show All 23 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll

Show First 20 Lines • Show All 842 Lines • ▼ Show 20 Lines
; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX7-NEXT: v_lshl_b64 v[1:2], v[0:1], 2 ; GFX7-NEXT: v_lshl_b64 v[1:2], v[0:1], 2
; GFX7-NEXT: s_mov_b32 s2, 0 ; GFX7-NEXT: s_mov_b32 s2, 0
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_mov_b64 s[0:1], s[6:7] ; GFX7-NEXT: s_mov_b64 s[0:1], s[6:7]
; GFX7-NEXT: buffer_load_dword v3, v[1:2], s[0:3], 0 addr64 ; GFX7-NEXT: buffer_load_dword v3, v[1:2], s[0:3], 0 addr64
; GFX7-NEXT: buffer_load_dword v4, v[1:2], s[0:3], 0 addr64 offset:4 ; GFX7-NEXT: buffer_load_dword v4, v[1:2], s[0:3], 0 addr64 offset:4
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX7-NEXT: buffer_load_dword v1, v[1:2], s[0:3], 0 addr64 offset:8
; GFX7-NEXT: buffer_load_dword v0, v[1:2], s[0:3], 0 addr64 offset:8
; GFX7-NEXT: s_cmp_lg_u32 s8, 0 ; GFX7-NEXT: s_cmp_lg_u32 s8, 0
; GFX7-NEXT: s_cselect_b32 s6, 1, 0 ; GFX7-NEXT: s_cselect_b32 s0, 1, 0
; GFX7-NEXT: s_and_b32 s0, 1, s6 ; GFX7-NEXT: s_and_b32 s0, 1, s0
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX7-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0 ; GFX7-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0
; GFX7-NEXT: s_mov_b32 s2, -1 ; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_and_b64 vcc, vcc, s[0:1] ; GFX7-NEXT: s_and_b64 vcc, vcc, s[0:1]
; GFX7-NEXT: s_mov_b64 s[6:7], s[2:3] ; GFX7-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_div_fmas_f32 v0, v3, v4, v0 ; GFX7-NEXT: v_div_fmas_f32 v0, v3, v4, v1
; GFX7-NEXT: buffer_store_dword v0, off, s[4:7], 0 offset:8 ; GFX7-NEXT: buffer_store_dword v0, off, s[4:7], 0 offset:8
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX8-LABEL: test_div_fmas_f32_logical_cond_to_vcc: ; GFX8-LABEL: test_div_fmas_f32_logical_cond_to_vcc:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX8-NEXT: s_load_dword s2, s[0:1], 0x54 ; GFX8-NEXT: s_load_dword s2, s[0:1], 0x54
; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
▲ Show 20 Lines • Show All 290 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll

Show First 20 Lines • Show All 944 Lines • ▼ Show 20 Lines
; Make sure that SimplifyDemandedBits doesn't cause the and to be ; Make sure that SimplifyDemandedBits doesn't cause the and to be
; reduced to the bits demanded by the bfe. ; reduced to the bits demanded by the bfe.
; XXX: The operand to v_bfe_u32 could also just directly be the load register. ; XXX: The operand to v_bfe_u32 could also just directly be the load register.
define amdgpu_kernel void @simplify_bfe_u32_multi_use_arg(i32 addrspace(1)* %out0, define amdgpu_kernel void @simplify_bfe_u32_multi_use_arg(i32 addrspace(1)* %out0,
; GFX6-LABEL: simplify_bfe_u32_multi_use_arg: ; GFX6-LABEL: simplify_bfe_u32_multi_use_arg:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd
; GFX6-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xb
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX6-NEXT: s_load_dword s8, s[2:3], 0x0
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_and_b32 s0, s0, 63 ; GFX6-NEXT: s_and_b32 s8, s8, 63
; GFX6-NEXT: s_bfe_u32 s1, s0, 0x20002 ; GFX6-NEXT: s_bfe_u32 s9, s8, 0x20002
; GFX6-NEXT: v_mov_b32_e32 v1, s1 ; GFX6-NEXT: v_mov_b32_e32 v1, s9
; GFX6-NEXT: v_mov_b32_e32 v0, s0 ; GFX6-NEXT: v_mov_b32_e32 v0, s8
; GFX6-NEXT: buffer_store_dword v1, off, s[4:7], 0 ; GFX6-NEXT: buffer_store_dword v1, off, s[4:7], 0
; GFX6-NEXT: buffer_store_dword v0, off, s[8:11], 0 ; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
i32 addrspace(1)* %out1, i32 addrspace(1)* %out1,
i32 addrspace(1)* %in) #0 { i32 addrspace(1)* %in) #0 {
%src = load i32, i32 addrspace(1)* %in, align 4 %src = load i32, i32 addrspace(1)* %in, align 4
%and = and i32 %src, 63 %and = and i32 %src, 63
%bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 %and, i32 2, i32 2) %bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 %and, i32 2, i32 2)
store i32 %bfe_u32, i32 addrspace(1)* %out0, align 4 store i32 %bfe_u32, i32 addrspace(1)* %out0, align 4
store i32 %and, i32 addrspace(1)* %out1, align 4 store i32 %and, i32 addrspace(1)* %out1, align 4
▲ Show 20 Lines • Show All 104 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll

Show All 14 Lines
; GFX9-UNALIGNED-NEXT: s_waitcnt vmcnt(0) ; GFX9-UNALIGNED-NEXT: s_waitcnt vmcnt(0)
; GFX9-UNALIGNED-NEXT: s_setpc_b64 s[30:31] ; GFX9-UNALIGNED-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-NOUNALIGNED-LABEL: v_load_constant_v3i32_align1: ; GFX9-NOUNALIGNED-LABEL: v_load_constant_v3i32_align1:
; GFX9-NOUNALIGNED: ; %bb.0: ; GFX9-NOUNALIGNED: ; %bb.0:
; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NOUNALIGNED-NEXT: v_add_co_u32_e32 v2, vcc, 11, v0 ; GFX9-NOUNALIGNED-NEXT: v_add_co_u32_e32 v2, vcc, 11, v0
; GFX9-NOUNALIGNED-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc ; GFX9-NOUNALIGNED-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v6, v[2:3], off offset:-6 ; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v4, v[2:3], off offset:-6
; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v7, v[2:3], off offset:-5 ; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v5, v[2:3], off offset:-5
; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v8, v[2:3], off offset:-4 ; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v6, v[2:3], off offset:-4
; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v9, v[2:3], off offset:-3 ; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v7, v[2:3], off offset:-3
; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v10, v[2:3], off offset:-2 ; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v8, v[2:3], off offset:-2
; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v11, v[2:3], off offset:-1 ; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v9, v[2:3], off offset:-1
; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v12, v[2:3], off ; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v10, v[2:3], off
; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v0, v[0:1], off ; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v0, v[0:1], off
; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v1, v[2:3], off offset:-10 ; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v1, v[2:3], off offset:-10
; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v13, v[2:3], off offset:-9 ; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v11, v[2:3], off offset:-9
; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v14, v[2:3], off offset:-8 ; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v12, v[2:3], off offset:-8
; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v2, v[2:3], off offset:-7 ; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v2, v[2:3], off offset:-7
; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v4, 0xff ; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v3, 0xff
; GFX9-NOUNALIGNED-NEXT: s_movk_i32 s4, 0xff ; GFX9-NOUNALIGNED-NEXT: s_movk_i32 s4, 0xff
; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v13, 8
; GFX9-NOUNALIGNED-NEXT: s_mov_b32 s5, 8 ; GFX9-NOUNALIGNED-NEXT: s_mov_b32 s5, 8
; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v5, 8
; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(11) ; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(11)
; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_sdwa v6, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_sdwa v4, v13, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(10) ; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(10)
; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v7, v7, v4 ; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v5, v5, v3
; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(9) ; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(9)
; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v8, v8, v4 ; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v6, v6, v3
; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(7) ; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(7)
; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_sdwa v5, v5, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_sdwa v8, v13, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(6) ; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(6)
; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v10, v11, v4 ; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v9, v9, v3
; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(5) ; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(5)
; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v11, v12, v4 ; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v10, v10, v3
; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(3) ; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(3)
; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_sdwa v1, s5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_sdwa v1, s5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(2) ; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(2)
; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v3, s4, v13 ; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v11, s4, v11
; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(1) ; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(1)
; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v13, s4, v14 ; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v12, s4, v12
; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(0) ; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(0)
; GFX9-NOUNALIGNED-NEXT: v_and_or_b32 v2, v2, v4, v6 ; GFX9-NOUNALIGNED-NEXT: v_and_or_b32 v2, v2, v3, v4
; GFX9-NOUNALIGNED-NEXT: v_and_or_b32 v0, v0, s4, v1 ; GFX9-NOUNALIGNED-NEXT: v_and_or_b32 v0, v0, s4, v1
; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v1, 16, v3 ; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v1, 16, v11
; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v3, 24, v13 ; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v11, 24, v12
; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v6, 16, v7 ; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v4, 16, v5
; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v7, 24, v8 ; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v5, 24, v6
; GFX9-NOUNALIGNED-NEXT: v_and_or_b32 v4, v9, v4, v5 ; GFX9-NOUNALIGNED-NEXT: v_and_or_b32 v3, v7, v3, v8
; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v5, 16, v10 ; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v6, 16, v9
; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v8, 24, v11 ; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v7, 24, v10
; GFX9-NOUNALIGNED-NEXT: v_or3_b32 v0, v0, v1, v3 ; GFX9-NOUNALIGNED-NEXT: v_or3_b32 v0, v0, v1, v11
; GFX9-NOUNALIGNED-NEXT: v_or3_b32 v1, v2, v6, v7 ; GFX9-NOUNALIGNED-NEXT: v_or3_b32 v1, v2, v4, v5
; GFX9-NOUNALIGNED-NEXT: v_or3_b32 v2, v4, v5, v8 ; GFX9-NOUNALIGNED-NEXT: v_or3_b32 v2, v3, v6, v7
; GFX9-NOUNALIGNED-NEXT: s_setpc_b64 s[30:31] ; GFX9-NOUNALIGNED-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX7-UNALIGNED-LABEL: v_load_constant_v3i32_align1: ; GFX7-UNALIGNED-LABEL: v_load_constant_v3i32_align1:
; GFX7-UNALIGNED: ; %bb.0: ; GFX7-UNALIGNED: ; %bb.0:
; GFX7-UNALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-UNALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-UNALIGNED-NEXT: s_mov_b32 s6, 0 ; GFX7-UNALIGNED-NEXT: s_mov_b32 s6, 0
; GFX7-UNALIGNED-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-UNALIGNED-NEXT: s_mov_b32 s7, 0xf000
; GFX7-UNALIGNED-NEXT: s_mov_b64 s[4:5], 0 ; GFX7-UNALIGNED-NEXT: s_mov_b64 s[4:5], 0
; GFX7-UNALIGNED-NEXT: buffer_load_dwordx3 v[0:2], v[0:1], s[4:7], 0 addr64 ; GFX7-UNALIGNED-NEXT: buffer_load_dwordx3 v[0:2], v[0:1], s[4:7], 0 addr64
; GFX7-UNALIGNED-NEXT: s_waitcnt vmcnt(0) ; GFX7-UNALIGNED-NEXT: s_waitcnt vmcnt(0)
; GFX7-UNALIGNED-NEXT: s_setpc_b64 s[30:31] ; GFX7-UNALIGNED-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX7-NOUNALIGNED-LABEL: v_load_constant_v3i32_align1: ; GFX7-NOUNALIGNED-LABEL: v_load_constant_v3i32_align1:
; GFX7-NOUNALIGNED: ; %bb.0: ; GFX7-NOUNALIGNED: ; %bb.0:
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NOUNALIGNED-NEXT: s_mov_b32 s6, 0 ; GFX7-NOUNALIGNED-NEXT: s_mov_b32 s6, 0
; GFX7-NOUNALIGNED-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NOUNALIGNED-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NOUNALIGNED-NEXT: s_mov_b64 s[4:5], 0 ; GFX7-NOUNALIGNED-NEXT: s_mov_b64 s[4:5], 0
; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v3, v[0:1], s[4:7], 0 addr64 offset:5 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v2, v[0:1], s[4:7], 0 addr64
; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v4, v[0:1], s[4:7], 0 addr64 offset:6 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v3, v[0:1], s[4:7], 0 addr64 offset:1
; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v5, v[0:1], s[4:7], 0 addr64 offset:7 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v4, v[0:1], s[4:7], 0 addr64 offset:2
; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v6, v[0:1], s[4:7], 0 addr64 offset:8 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v5, v[0:1], s[4:7], 0 addr64 offset:3
; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v7, v[0:1], s[4:7], 0 addr64 offset:9 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v6, v[0:1], s[4:7], 0 addr64 offset:4
; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v8, v[0:1], s[4:7], 0 addr64 offset:10 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v7, v[0:1], s[4:7], 0 addr64 offset:5
; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v9, v[0:1], s[4:7], 0 addr64 offset:11 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v8, v[0:1], s[4:7], 0 addr64 offset:6
; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v10, v[0:1], s[4:7], 0 addr64 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v9, v[0:1], s[4:7], 0 addr64 offset:7
; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v11, v[0:1], s[4:7], 0 addr64 offset:1 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v10, v[0:1], s[4:7], 0 addr64 offset:8
; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v12, v[0:1], s[4:7], 0 addr64 offset:2 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v11, v[0:1], s[4:7], 0 addr64 offset:9
; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v13, v[0:1], s[4:7], 0 addr64 offset:3 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v12, v[0:1], s[4:7], 0 addr64 offset:10
; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 offset:4 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 offset:11
; GFX7-NOUNALIGNED-NEXT: v_mov_b32_e32 v2, 0xff ; GFX7-NOUNALIGNED-NEXT: v_mov_b32_e32 v1, 0xff
; GFX7-NOUNALIGNED-NEXT: s_movk_i32 s8, 0xff ; GFX7-NOUNALIGNED-NEXT: s_movk_i32 s4, 0xff
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(11) ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(11)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v3, v3, v2 ; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v2, s4, v2
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(10) ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(10)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v4, v4, v2 ; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v3, s4, v3
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(9) ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(9)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v5, v5, v2 ; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v4, s4, v4
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(8) ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(8)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v6, v6, v2 ; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v5, s4, v5
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(7) ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(7)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v7, v7, v2 ; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v6, s4, v6
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(6) ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(6)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v8, v8, v2 ; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v7, v7, v1
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(5) ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(5)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v2, v9, v2 ; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v8, v8, v1
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(4) ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(4)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v1, s8, v10 ; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v9, v9, v1
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(3) ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(3)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v10, s8, v11 ; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v10, v10, v1
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(2) ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(2)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v11, s8, v12 ; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v11, v11, v1
; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v9, 8, v10 ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(1)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v12, v12, v1
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(0) ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(0)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v0, s8, v0 ; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v0, v0, v1
; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v3, 8, v3 ; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v1, 8, v3
; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v7, 8, v7 ; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v3, 16, v4
; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v4, 24, v5
; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v5, 8, v7
; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v7, 16, v8
; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v8, 24, v9
; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v9, 8, v11
; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v11, 16, v12
; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v12, 24, v0
; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v0, v2, v1
; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v1, v6, v5
; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v2, v10, v9
; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v0, v0, v3 ; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v0, v0, v3
; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v1, v1, v7
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v12, s8, v13 ; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v2, v2, v11
; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v10, 16, v11 ; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v0, v0, v4
; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v1, v1, v9 ; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v1, v1, v8
; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v8, 16, v8 ; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v2, v2, v12
; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v3, v6, v7
; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v11, 24, v12
; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v5, 24, v5
; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v2, 24, v2
; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v3, v3, v8
; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v1, v1, v10
; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v4, v0, v4
; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v0, v1, v11
; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v1, v4, v5
; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v2, v3, v2
; GFX7-NOUNALIGNED-NEXT: s_setpc_b64 s[30:31] ; GFX7-NOUNALIGNED-NEXT: s_setpc_b64 s[30:31]
%load = load <3 x i32>, <3 x i32> addrspace(4)* %ptr, align 1 %load = load <3 x i32>, <3 x i32> addrspace(4)* %ptr, align 1
ret <3 x i32> %load ret <3 x i32> %load
} }
define <3 x i32> @v_load_constant_v3i32_align2(<3 x i32> addrspace(4)* %ptr) { define <3 x i32> @v_load_constant_v3i32_align2(<3 x i32> addrspace(4)* %ptr) {
; GFX9-UNALIGNED-LABEL: v_load_constant_v3i32_align2: ; GFX9-UNALIGNED-LABEL: v_load_constant_v3i32_align2:
; GFX9-UNALIGNED: ; %bb.0: ; GFX9-UNALIGNED: ; %bb.0:
; GFX9-UNALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-UNALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-UNALIGNED-NEXT: global_load_dwordx3 v[0:2], v[0:1], off ; GFX9-UNALIGNED-NEXT: global_load_dwordx3 v[0:2], v[0:1], off
; GFX9-UNALIGNED-NEXT: s_waitcnt vmcnt(0) ; GFX9-UNALIGNED-NEXT: s_waitcnt vmcnt(0)
; GFX9-UNALIGNED-NEXT: s_setpc_b64 s[30:31] ; GFX9-UNALIGNED-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-NOUNALIGNED-LABEL: v_load_constant_v3i32_align2: ; GFX9-NOUNALIGNED-LABEL: v_load_constant_v3i32_align2:
; GFX9-NOUNALIGNED: ; %bb.0: ; GFX9-NOUNALIGNED: ; %bb.0:
; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NOUNALIGNED-NEXT: v_add_co_u32_e32 v2, vcc, 10, v0 ; GFX9-NOUNALIGNED-NEXT: v_add_co_u32_e32 v2, vcc, 10, v0
; GFX9-NOUNALIGNED-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc ; GFX9-NOUNALIGNED-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
; GFX9-NOUNALIGNED-NEXT: global_load_ushort v5, v[2:3], off ; GFX9-NOUNALIGNED-NEXT: global_load_ushort v4, v[2:3], off
; GFX9-NOUNALIGNED-NEXT: global_load_ushort v0, v[0:1], off ; GFX9-NOUNALIGNED-NEXT: global_load_ushort v0, v[0:1], off
; GFX9-NOUNALIGNED-NEXT: global_load_ushort v1, v[2:3], off offset:-8 ; GFX9-NOUNALIGNED-NEXT: global_load_ushort v1, v[2:3], off offset:-8
; GFX9-NOUNALIGNED-NEXT: global_load_ushort v6, v[2:3], off offset:-6 ; GFX9-NOUNALIGNED-NEXT: global_load_ushort v5, v[2:3], off offset:-6
; GFX9-NOUNALIGNED-NEXT: global_load_ushort v7, v[2:3], off offset:-4 ; GFX9-NOUNALIGNED-NEXT: global_load_ushort v6, v[2:3], off offset:-4
; GFX9-NOUNALIGNED-NEXT: global_load_ushort v2, v[2:3], off offset:-2 ; GFX9-NOUNALIGNED-NEXT: global_load_ushort v2, v[2:3], off offset:-2
; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v4, 0xffff ; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v3, 0xffff
; GFX9-NOUNALIGNED-NEXT: s_mov_b32 s4, 0xffff ; GFX9-NOUNALIGNED-NEXT: s_mov_b32 s4, 0xffff
; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(5) ; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(5)
; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v5, v5, v4 ; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v4, v4, v3
; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v5, 16, v5 ; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(3) ; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(3)
; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v1, s4, v1 ; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v1, s4, v1
; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(1) ; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(1)
; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v3, v7, v4 ; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v6, v6, v3
; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX9-NOUNALIGNED-NEXT: v_and_or_b32 v0, v0, s4, v1 ; GFX9-NOUNALIGNED-NEXT: v_and_or_b32 v0, v0, s4, v1
; GFX9-NOUNALIGNED-NEXT: v_and_or_b32 v1, v6, v4, v3 ; GFX9-NOUNALIGNED-NEXT: v_and_or_b32 v1, v5, v3, v6
; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(0) ; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(0)
; GFX9-NOUNALIGNED-NEXT: v_and_or_b32 v2, v2, v4, v5 ; GFX9-NOUNALIGNED-NEXT: v_and_or_b32 v2, v2, v3, v4
; GFX9-NOUNALIGNED-NEXT: s_setpc_b64 s[30:31] ; GFX9-NOUNALIGNED-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX7-UNALIGNED-LABEL: v_load_constant_v3i32_align2: ; GFX7-UNALIGNED-LABEL: v_load_constant_v3i32_align2:
; GFX7-UNALIGNED: ; %bb.0: ; GFX7-UNALIGNED: ; %bb.0:
; GFX7-UNALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-UNALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-UNALIGNED-NEXT: s_mov_b32 s6, 0 ; GFX7-UNALIGNED-NEXT: s_mov_b32 s6, 0
; GFX7-UNALIGNED-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-UNALIGNED-NEXT: s_mov_b32 s7, 0xf000
; GFX7-UNALIGNED-NEXT: s_mov_b64 s[4:5], 0 ; GFX7-UNALIGNED-NEXT: s_mov_b64 s[4:5], 0
; GFX7-UNALIGNED-NEXT: buffer_load_dwordx3 v[0:2], v[0:1], s[4:7], 0 addr64 ; GFX7-UNALIGNED-NEXT: buffer_load_dwordx3 v[0:2], v[0:1], s[4:7], 0 addr64
; GFX7-UNALIGNED-NEXT: s_waitcnt vmcnt(0) ; GFX7-UNALIGNED-NEXT: s_waitcnt vmcnt(0)
; GFX7-UNALIGNED-NEXT: s_setpc_b64 s[30:31] ; GFX7-UNALIGNED-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX7-NOUNALIGNED-LABEL: v_load_constant_v3i32_align2: ; GFX7-NOUNALIGNED-LABEL: v_load_constant_v3i32_align2:
; GFX7-NOUNALIGNED: ; %bb.0: ; GFX7-NOUNALIGNED: ; %bb.0:
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NOUNALIGNED-NEXT: s_mov_b32 s6, 0 ; GFX7-NOUNALIGNED-NEXT: s_mov_b32 s6, 0
; GFX7-NOUNALIGNED-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NOUNALIGNED-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NOUNALIGNED-NEXT: s_mov_b64 s[4:5], 0 ; GFX7-NOUNALIGNED-NEXT: s_mov_b64 s[4:5], 0
; GFX7-NOUNALIGNED-NEXT: buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 offset:10 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 offset:10
; GFX7-NOUNALIGNED-NEXT: buffer_load_ushort v3, v[0:1], s[4:7], 0 addr64 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ushort v3, v[0:1], s[4:7], 0 addr64
; GFX7-NOUNALIGNED-NEXT: buffer_load_ushort v4, v[0:1], s[4:7], 0 addr64 offset:2 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ushort v4, v[0:1], s[4:7], 0 addr64 offset:2
; GFX7-NOUNALIGNED-NEXT: buffer_load_ushort v5, v[0:1], s[4:7], 0 addr64 offset:4 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ushort v5, v[0:1], s[4:7], 0 addr64 offset:4
; GFX7-NOUNALIGNED-NEXT: buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:6 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:6
; GFX7-NOUNALIGNED-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64 offset:8 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64 offset:8
; GFX7-NOUNALIGNED-NEXT: s_mov_b32 s8, 0xffff ; GFX7-NOUNALIGNED-NEXT: s_mov_b32 s4, 0xffff
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(4) ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(4)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v1, s8, v3 ; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v1, s4, v3
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(3) ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(3)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v3, s8, v4 ; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v3, s4, v4
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(2) ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(2)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v4, s8, v5 ; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v4, s4, v5
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(1) ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(1)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v5, s8, v6 ; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v5, s4, v6
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(0) ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(0)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v6, s8, v0 ; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v6, s4, v0
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v0, s8, v2 ; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v0, s4, v2
; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v2, 16, v3 ; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v3, 16, v5 ; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v3, 16, v5
; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v5, 16, v0 ; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v5, 16, v0
; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v0, v1, v2 ; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v0, v1, v2
; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v1, v4, v3 ; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v1, v4, v3
; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v2, v6, v5 ; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v2, v6, v5
; GFX7-NOUNALIGNED-NEXT: s_setpc_b64 s[30:31] ; GFX7-NOUNALIGNED-NEXT: s_setpc_b64 s[30:31]
%load = load <3 x i32>, <3 x i32> addrspace(4)* %ptr, align 2 %load = load <3 x i32>, <3 x i32> addrspace(4)* %ptr, align 2
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; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v15, s3 ; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v15, s3
; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v14, s2 ; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v14, s2
; GFX9-NOUNALIGNED-NEXT: s_add_u32 s2, s0, 8 ; GFX9-NOUNALIGNED-NEXT: s_add_u32 s2, s0, 8
; GFX9-NOUNALIGNED-NEXT: s_addc_u32 s3, s1, 0 ; GFX9-NOUNALIGNED-NEXT: s_addc_u32 s3, s1, 0
; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v17, s3 ; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v17, s3
; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v16, s2 ; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v16, s2
; GFX9-NOUNALIGNED-NEXT: s_add_u32 s2, s0, 9 ; GFX9-NOUNALIGNED-NEXT: s_add_u32 s2, s0, 9
; GFX9-NOUNALIGNED-NEXT: s_addc_u32 s3, s1, 0 ; GFX9-NOUNALIGNED-NEXT: s_addc_u32 s3, s1, 0
; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v20, v[10:11], off ; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v19, s3
; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v12, v[12:13], off ; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v18, s2
; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v11, s3
; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v10, s2
; GFX9-NOUNALIGNED-NEXT: s_add_u32 s2, s0, 10 ; GFX9-NOUNALIGNED-NEXT: s_add_u32 s2, s0, 10
; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NOUNALIGNED-NEXT: s_addc_u32 s3, s1, 0 ; GFX9-NOUNALIGNED-NEXT: s_addc_u32 s3, s1, 0
; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NOUNALIGNED-NEXT: s_add_u32 s0, s0, 11 ; GFX9-NOUNALIGNED-NEXT: s_add_u32 s0, s0, 11
; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v13, v[14:15], off ; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v20, v[10:11], off
; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v14, v[16:17], off ; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v21, v[12:13], off
; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v15, v[10:11], off ; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v14, v[14:15], off
; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v15, v[16:17], off
; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v16, v[18:19], off
; GFX9-NOUNALIGNED-NEXT: s_addc_u32 s1, s1, 0
; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v11, s3 ; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v11, s3
; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v13, s1
; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v10, s2 ; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v10, s2
; GFX9-NOUNALIGNED-NEXT: s_addc_u32 s1, s1, 0 ; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v12, s0
; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v16, v[10:11], off
; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v11, s1
; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v10, s0
; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v10, v[10:11], off ; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v10, v[10:11], off
; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v11, v[12:13], off
; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v0, v[0:1], off ; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v0, v[0:1], off
; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v1, v[2:3], off ; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v1, v[2:3], off
; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v2, v[4:5], off ; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v2, v[4:5], off
; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v3, v[6:7], off ; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v3, v[6:7], off
; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v4, v[8:9], off ; GFX9-NOUNALIGNED-NEXT: global_load_ubyte v4, v[8:9], off
; GFX9-NOUNALIGNED-NEXT: s_mov_b32 s5, 8 ; GFX9-NOUNALIGNED-NEXT: s_mov_b32 s1, 8
; GFX9-NOUNALIGNED-NEXT: s_movk_i32 s4, 0xff ; GFX9-NOUNALIGNED-NEXT: s_movk_i32 s0, 0xff
; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v18, 0xff ; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v5, 0xff
; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v19, 8 ; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v6, 8
; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(3) ; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(3)
; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_sdwa v1, s5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_sdwa v1, s1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NOUNALIGNED-NEXT: v_and_or_b32 v0, v0, s4, v1 ; GFX9-NOUNALIGNED-NEXT: v_and_or_b32 v0, v0, s0, v1
; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(2) ; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(2)
; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v1, s4, v2 ; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v1, s0, v2
; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(1) ; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(1)
; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v2, s4, v3 ; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v2, s0, v3
; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v2, 24, v2 ; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v2, 24, v2
; GFX9-NOUNALIGNED-NEXT: v_or3_b32 v0, v0, v1, v2 ; GFX9-NOUNALIGNED-NEXT: v_or3_b32 v0, v0, v1, v2
; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v1, v12, v18 ; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v1, v21, v5
; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v2, v13, v18 ; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v2, v14, v5
; GFX9-NOUNALIGNED-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NOUNALIGNED-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_sdwa v0, v19, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_sdwa v0, v6, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(0) ; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(0)
; GFX9-NOUNALIGNED-NEXT: v_and_or_b32 v0, v4, v18, v0 ; GFX9-NOUNALIGNED-NEXT: v_and_or_b32 v0, v4, v5, v0
; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v2, 24, v2 ; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v2, 24, v2
; GFX9-NOUNALIGNED-NEXT: v_or3_b32 v1, v0, v1, v2 ; GFX9-NOUNALIGNED-NEXT: v_or3_b32 v1, v0, v1, v2
; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_sdwa v0, v19, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_sdwa v0, v6, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v2, v10, v18 ; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v2, v11, v5
; GFX9-NOUNALIGNED-NEXT: v_readfirstlane_b32 s1, v1 ; GFX9-NOUNALIGNED-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v1, v16, v18 ; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v1, v10, v5
; GFX9-NOUNALIGNED-NEXT: v_and_or_b32 v0, v14, v18, v0 ; GFX9-NOUNALIGNED-NEXT: v_and_or_b32 v0, v15, v5, v0
; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v2, 24, v2 ; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v2, 24, v2
; GFX9-NOUNALIGNED-NEXT: v_or3_b32 v2, v0, v1, v2 ; GFX9-NOUNALIGNED-NEXT: v_or3_b32 v2, v0, v1, v2
; GFX9-NOUNALIGNED-NEXT: v_readfirstlane_b32 s2, v2 ; GFX9-NOUNALIGNED-NEXT: v_readfirstlane_b32 s2, v2
; GFX9-NOUNALIGNED-NEXT: ; return to shader part epilog ; GFX9-NOUNALIGNED-NEXT: ; return to shader part epilog
; ;
; GFX7-UNALIGNED-LABEL: s_load_constant_v3i32_align1: ; GFX7-UNALIGNED-LABEL: s_load_constant_v3i32_align1:
; GFX7-UNALIGNED: ; %bb.0: ; GFX7-UNALIGNED: ; %bb.0:
; GFX7-UNALIGNED-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x0 ; GFX7-UNALIGNED-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x0
; GFX7-UNALIGNED-NEXT: s_load_dword s0, s[0:1], 0x2 ; GFX7-UNALIGNED-NEXT: s_load_dword s0, s[0:1], 0x2
; GFX7-UNALIGNED-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-UNALIGNED-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-UNALIGNED-NEXT: v_mov_b32_e32 v0, s6 ; GFX7-UNALIGNED-NEXT: v_mov_b32_e32 v0, s6
; GFX7-UNALIGNED-NEXT: v_mov_b32_e32 v2, s8 ; GFX7-UNALIGNED-NEXT: v_mov_b32_e32 v2, s8
; GFX7-UNALIGNED-NEXT: v_mov_b32_e32 v2, s0 ; GFX7-UNALIGNED-NEXT: v_mov_b32_e32 v2, s0
; GFX7-UNALIGNED-NEXT: v_mov_b32_e32 v1, s7 ; GFX7-UNALIGNED-NEXT: v_mov_b32_e32 v1, s7
; GFX7-UNALIGNED-NEXT: v_readfirstlane_b32 s0, v0 ; GFX7-UNALIGNED-NEXT: v_readfirstlane_b32 s0, v0
; GFX7-UNALIGNED-NEXT: v_readfirstlane_b32 s1, v1 ; GFX7-UNALIGNED-NEXT: v_readfirstlane_b32 s1, v1
; GFX7-UNALIGNED-NEXT: v_readfirstlane_b32 s2, v2 ; GFX7-UNALIGNED-NEXT: v_readfirstlane_b32 s2, v2
; GFX7-UNALIGNED-NEXT: ; return to shader part epilog ; GFX7-UNALIGNED-NEXT: ; return to shader part epilog
; ;
; GFX7-NOUNALIGNED-LABEL: s_load_constant_v3i32_align1: ; GFX7-NOUNALIGNED-LABEL: s_load_constant_v3i32_align1:
; GFX7-NOUNALIGNED: ; %bb.0: ; GFX7-NOUNALIGNED: ; %bb.0:
; GFX7-NOUNALIGNED-NEXT: s_mov_b32 s2, -1 ; GFX7-NOUNALIGNED-NEXT: s_mov_b32 s2, -1
; GFX7-NOUNALIGNED-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NOUNALIGNED-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v1, off, s[0:3], 0 offset:5 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v0, off, s[0:3], 0
; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v2, off, s[0:3], 0 offset:6 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v1, off, s[0:3], 0 offset:1
; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v3, off, s[0:3], 0 offset:7 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v2, off, s[0:3], 0 offset:2
; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v4, off, s[0:3], 0 offset:8 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v3, off, s[0:3], 0 offset:3
; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v5, off, s[0:3], 0 offset:9 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v4, off, s[0:3], 0 offset:4
; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v6, off, s[0:3], 0 offset:10 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v5, off, s[0:3], 0 offset:5
; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v7, off, s[0:3], 0 offset:11 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v6, off, s[0:3], 0 offset:6
; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v8, off, s[0:3], 0 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v7, off, s[0:3], 0 offset:7
; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v9, off, s[0:3], 0 offset:1 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v8, off, s[0:3], 0 offset:8
; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v10, off, s[0:3], 0 offset:2 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v9, off, s[0:3], 0 offset:9
; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v11, off, s[0:3], 0 offset:3 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v10, off, s[0:3], 0 offset:10
; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v12, off, s[0:3], 0 offset:4 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v11, off, s[0:3], 0 offset:11
; GFX7-NOUNALIGNED-NEXT: v_mov_b32_e32 v0, 0xff ; GFX7-NOUNALIGNED-NEXT: v_mov_b32_e32 v12, 0xff
; GFX7-NOUNALIGNED-NEXT: s_movk_i32 s4, 0xff ; GFX7-NOUNALIGNED-NEXT: s_movk_i32 s0, 0xff
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(11) ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(11)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v1, v1, v0 ; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v0, s0, v0
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(10) ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(10)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v2, v2, v0 ; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v1, s0, v1
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(9) ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(9)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v3, v3, v0 ; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v2, s0, v2
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(8) ; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v4, v4, v0
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(7) ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(7)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v5, v5, v0 ; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v4, s0, v4
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(6) ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(6)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v6, v6, v0 ; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v5, v5, v12
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(5)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v6, v6, v12
; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v5, 8, v5 ; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(4)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v8, s4, v8
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(3) ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(3)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v9, s4, v9 ; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v8, v8, v12
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v0, v7, v0
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(2) ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(2)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v10, s4, v10 ; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v9, v9, v12
; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v7, 8, v9
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(1) ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(1)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v11, s4, v11 ; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v10, v10, v12
; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v9, 8, v9
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v3, s0, v3
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v7, v7, v12
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(0) ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(0)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v12, s4, v12 ; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v11, v11, v12
; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v1, 8, v1 ; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v9, 16, v10
; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v10, 24, v11
; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v11, 24, v0
; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v0, v8, v7
; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v1, v12, v1 ; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v1, v4, v5
; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v6, 16, v6 ; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v4, v4, v5 ; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v0, v0, v9 ; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v4, v8, v9
; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v1, v1, v2 ; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v0, v0, v2
; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v2, v4, v6
; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v3, 24, v3 ; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v3, 24, v3
; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v0, v0, v10 ; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v7, 24, v7
; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v1, v1, v3 ; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v1, v1, v6
; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v11, 24, v11
; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v2, v4, v10
; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v0, v0, v3
; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v1, v1, v7
; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v2, v2, v11 ; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v2, v2, v11
; GFX7-NOUNALIGNED-NEXT: v_readfirstlane_b32 s0, v0 ; GFX7-NOUNALIGNED-NEXT: v_readfirstlane_b32 s0, v0
; GFX7-NOUNALIGNED-NEXT: v_readfirstlane_b32 s1, v1 ; GFX7-NOUNALIGNED-NEXT: v_readfirstlane_b32 s1, v1
; GFX7-NOUNALIGNED-NEXT: v_readfirstlane_b32 s2, v2 ; GFX7-NOUNALIGNED-NEXT: v_readfirstlane_b32 s2, v2
; GFX7-NOUNALIGNED-NEXT: ; return to shader part epilog ; GFX7-NOUNALIGNED-NEXT: ; return to shader part epilog
%load = load <3 x i32>, <3 x i32> addrspace(4)* %ptr, align 1 %load = load <3 x i32>, <3 x i32> addrspace(4)* %ptr, align 1
ret <3 x i32> %load ret <3 x i32> %load
} }
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; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v10, s0 ; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v10, s0
; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v8, s2 ; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v8, s2
; GFX9-NOUNALIGNED-NEXT: global_load_ushort v10, v[10:11], off ; GFX9-NOUNALIGNED-NEXT: global_load_ushort v10, v[10:11], off
; GFX9-NOUNALIGNED-NEXT: global_load_ushort v0, v[0:1], off ; GFX9-NOUNALIGNED-NEXT: global_load_ushort v0, v[0:1], off
; GFX9-NOUNALIGNED-NEXT: global_load_ushort v1, v[2:3], off ; GFX9-NOUNALIGNED-NEXT: global_load_ushort v1, v[2:3], off
; GFX9-NOUNALIGNED-NEXT: global_load_ushort v2, v[4:5], off ; GFX9-NOUNALIGNED-NEXT: global_load_ushort v2, v[4:5], off
; GFX9-NOUNALIGNED-NEXT: global_load_ushort v3, v[6:7], off ; GFX9-NOUNALIGNED-NEXT: global_load_ushort v3, v[6:7], off
; GFX9-NOUNALIGNED-NEXT: global_load_ushort v4, v[8:9], off ; GFX9-NOUNALIGNED-NEXT: global_load_ushort v4, v[8:9], off
; GFX9-NOUNALIGNED-NEXT: s_mov_b32 s4, 0xffff ; GFX9-NOUNALIGNED-NEXT: s_mov_b32 s0, 0xffff
; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v12, 0xffff ; GFX9-NOUNALIGNED-NEXT: v_mov_b32_e32 v5, 0xffff
; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(3) ; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(3)
; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v1, s4, v1 ; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v1, s0, v1
; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NOUNALIGNED-NEXT: v_and_or_b32 v0, v0, s4, v1 ; GFX9-NOUNALIGNED-NEXT: v_and_or_b32 v0, v0, s0, v1
; GFX9-NOUNALIGNED-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NOUNALIGNED-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(1) ; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(1)
; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v0, v3, v12 ; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v0, v3, v5
; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v0, 16, v0 ; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX9-NOUNALIGNED-NEXT: v_and_or_b32 v1, v2, v12, v0 ; GFX9-NOUNALIGNED-NEXT: v_and_or_b32 v1, v2, v5, v0
; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v0, v10, v12 ; GFX9-NOUNALIGNED-NEXT: v_and_b32_e32 v0, v10, v5
; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v0, 16, v0 ; GFX9-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(0) ; GFX9-NOUNALIGNED-NEXT: s_waitcnt vmcnt(0)
; GFX9-NOUNALIGNED-NEXT: v_and_or_b32 v2, v4, v12, v0 ; GFX9-NOUNALIGNED-NEXT: v_and_or_b32 v2, v4, v5, v0
; GFX9-NOUNALIGNED-NEXT: v_readfirstlane_b32 s1, v1 ; GFX9-NOUNALIGNED-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NOUNALIGNED-NEXT: v_readfirstlane_b32 s2, v2 ; GFX9-NOUNALIGNED-NEXT: v_readfirstlane_b32 s2, v2
; GFX9-NOUNALIGNED-NEXT: ; return to shader part epilog ; GFX9-NOUNALIGNED-NEXT: ; return to shader part epilog
; ;
; GFX7-UNALIGNED-LABEL: s_load_constant_v3i32_align2: ; GFX7-UNALIGNED-LABEL: s_load_constant_v3i32_align2:
; GFX7-UNALIGNED: ; %bb.0: ; GFX7-UNALIGNED: ; %bb.0:
; GFX7-UNALIGNED-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x0 ; GFX7-UNALIGNED-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x0
; GFX7-UNALIGNED-NEXT: s_load_dword s0, s[0:1], 0x2 ; GFX7-UNALIGNED-NEXT: s_load_dword s0, s[0:1], 0x2
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; GFX7-NOUNALIGNED-NEXT: s_mov_b32 s2, -1 ; GFX7-NOUNALIGNED-NEXT: s_mov_b32 s2, -1
; GFX7-NOUNALIGNED-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NOUNALIGNED-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NOUNALIGNED-NEXT: buffer_load_ushort v0, off, s[0:3], 0 offset:10 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ushort v0, off, s[0:3], 0 offset:10
; GFX7-NOUNALIGNED-NEXT: buffer_load_ushort v1, off, s[0:3], 0 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ushort v1, off, s[0:3], 0
; GFX7-NOUNALIGNED-NEXT: buffer_load_ushort v2, off, s[0:3], 0 offset:2 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ushort v2, off, s[0:3], 0 offset:2
; GFX7-NOUNALIGNED-NEXT: buffer_load_ushort v3, off, s[0:3], 0 offset:4 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ushort v3, off, s[0:3], 0 offset:4
; GFX7-NOUNALIGNED-NEXT: buffer_load_ushort v4, off, s[0:3], 0 offset:6 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ushort v4, off, s[0:3], 0 offset:6
; GFX7-NOUNALIGNED-NEXT: buffer_load_ushort v5, off, s[0:3], 0 offset:8 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ushort v5, off, s[0:3], 0 offset:8
; GFX7-NOUNALIGNED-NEXT: s_mov_b32 s4, 0xffff ; GFX7-NOUNALIGNED-NEXT: s_mov_b32 s0, 0xffff
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(5) ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(5)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v0, s4, v0 ; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v0, s0, v0
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(4) ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(4)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v1, s4, v1 ; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v1, s0, v1
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(3) ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(3)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v2, s4, v2 ; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v2, s0, v2
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(2) ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(2)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v3, s4, v3 ; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v3, s0, v3
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(1) ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(1)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v4, s4, v4 ; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v4, s0, v4
; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(0) ; GFX7-NOUNALIGNED-NEXT: s_waitcnt vmcnt(0)
; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v5, s4, v5 ; GFX7-NOUNALIGNED-NEXT: v_and_b32_e32 v5, s0, v5
; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v6, 16, v0 ; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; GFX7-NOUNALIGNED-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v0, v1, v2 ; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v0, v1, v2
; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v1, v3, v4 ; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v1, v3, v4
; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v2, v5, v6 ; GFX7-NOUNALIGNED-NEXT: v_or_b32_e32 v2, v5, v6
; GFX7-NOUNALIGNED-NEXT: v_readfirstlane_b32 s0, v0 ; GFX7-NOUNALIGNED-NEXT: v_readfirstlane_b32 s0, v0
; GFX7-NOUNALIGNED-NEXT: v_readfirstlane_b32 s1, v1 ; GFX7-NOUNALIGNED-NEXT: v_readfirstlane_b32 s1, v1
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llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll

Show First 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
; GFX9-NEXT: s_cbranch_scc0 BB1_2 ; GFX9-NEXT: s_cbranch_scc0 BB1_2
; GFX9-NEXT: ; %bb.1: ; %bb1 ; GFX9-NEXT: ; %bb.1: ; %bb1
; GFX9-NEXT: s_getpc_b64 s[2:3] ; GFX9-NEXT: s_getpc_b64 s[2:3]
; GFX9-NEXT: s_add_u32 s2, s2, gv2@gotpcrel32@lo+4 ; GFX9-NEXT: s_add_u32 s2, s2, gv2@gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s3, s3, gv2@gotpcrel32@hi+4 ; GFX9-NEXT: s_addc_u32 s3, s3, gv2@gotpcrel32@hi+4
; GFX9-NEXT: s_getpc_b64 s[4:5] ; GFX9-NEXT: s_getpc_b64 s[4:5]
; GFX9-NEXT: s_add_u32 s4, s4, gv3@gotpcrel32@lo+4 ; GFX9-NEXT: s_add_u32 s4, s4, gv3@gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, gv3@gotpcrel32@hi+4 ; GFX9-NEXT: s_addc_u32 s5, s5, gv3@gotpcrel32@hi+4
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_mov_b32 s0, 0 ; GFX9-NEXT: s_mov_b32 s0, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s2 ; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: global_store_dword v[0:1], v2, off ; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v2, 1 ; GFX9-NEXT: v_mov_b32_e32 v2, 1
; GFX9-NEXT: v_mov_b32_e32 v1, s5 ; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: global_store_dword v[0:1], v2, off ; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: BB1_2: ; %Flow ; GFX9-NEXT: BB1_2: ; %Flow
; GFX9-NEXT: s_and_b32 s0, s0, 1 ; GFX9-NEXT: s_and_b32 s0, s0, 1
; GFX9-NEXT: s_cmp_lg_u32 s0, 0 ; GFX9-NEXT: s_cmp_lg_u32 s0, 0
; GFX9-NEXT: s_cbranch_scc0 BB1_4 ; GFX9-NEXT: s_cbranch_scc0 BB1_4
; GFX9-NEXT: ; %bb.3: ; %bb0 ; GFX9-NEXT: ; %bb.3: ; %bb0
; GFX9-NEXT: s_getpc_b64 s[0:1] ; GFX9-NEXT: s_getpc_b64 s[0:1]
; GFX9-NEXT: s_add_u32 s0, s0, gv0@gotpcrel32@lo+4 ; GFX9-NEXT: s_add_u32 s0, s0, gv0@gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s1, s1, gv0@gotpcrel32@hi+4 ; GFX9-NEXT: s_addc_u32 s1, s1, gv0@gotpcrel32@hi+4
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX9-NEXT: s_getpc_b64 s[2:3] ; GFX9-NEXT: s_getpc_b64 s[2:3]
; GFX9-NEXT: s_add_u32 s2, s2, gv1@gotpcrel32@lo+4 ; GFX9-NEXT: s_add_u32 s2, s2, gv1@gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s3, s3, gv1@gotpcrel32@hi+4 ; GFX9-NEXT: s_addc_u32 s3, s3, gv1@gotpcrel32@hi+4
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: v_mov_b32_e32 v3, 1 ; GFX9-NEXT: v_mov_b32_e32 v3, 1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: global_store_dword v[0:1], v2, off ; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: v_mov_b32_e32 v0, s2 ; GFX9-NEXT: v_mov_b32_e32 v0, s2
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llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll

Show First 20 Lines • Show All 156 Lines • ▼ Show 20 Lines
; ;
; GFX6-LABEL: zextload_global_i32_to_i96: ; GFX6-LABEL: zextload_global_i32_to_i96:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s6, 0 ; GFX6-NEXT: s_mov_b32 s6, 0
; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: s_mov_b64 s[4:5], 0 ; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64 ; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64
; GFX6-NEXT: s_mov_b32 s8, 0 ; GFX6-NEXT: s_mov_b32 s4, 0
; GFX6-NEXT: v_mov_b32_e32 v1, 0 ; GFX6-NEXT: v_mov_b32_e32 v1, 0
; GFX6-NEXT: v_mov_b32_e32 v2, s8 ; GFX6-NEXT: v_mov_b32_e32 v2, s4
; GFX6-NEXT: s_waitcnt vmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: s_setpc_b64 s[30:31] ; GFX6-NEXT: s_setpc_b64 s[30:31]
%load = load i32, i32 addrspace(1)* %ptr %load = load i32, i32 addrspace(1)* %ptr
%ext = zext i32 %load to i96 %ext = zext i32 %load to i96
ret i96 %ext ret i96 %ext
} }
define i128 @zextload_global_i32_to_i128(i32 addrspace(1)* %ptr) { define i128 @zextload_global_i32_to_i128(i32 addrspace(1)* %ptr) {
; GFX9-LABEL: zextload_global_i32_to_i128: ; GFX9-LABEL: zextload_global_i32_to_i128:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: global_load_dword v0, v[0:1], off ; GFX9-NEXT: global_load_dword v0, v[0:1], off
; GFX9-NEXT: s_mov_b32 s4, 0 ; GFX9-NEXT: s_mov_b32 s4, 0
; GFX9-NEXT: s_mov_b32 s5, 0 ; GFX9-NEXT: s_mov_b32 s5, 0
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: v_mov_b32_e32 v2, s5 ; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_mov_b32_e32 v3, s4 ; GFX9-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-LABEL: zextload_global_i32_to_i128: ; GFX8-LABEL: zextload_global_i32_to_i128:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: flat_load_dword v0, v[0:1] ; GFX8-NEXT: flat_load_dword v0, v[0:1]
; GFX8-NEXT: s_mov_b32 s4, 0 ; GFX8-NEXT: s_mov_b32 s4, 0
; GFX8-NEXT: s_mov_b32 s5, 0 ; GFX8-NEXT: s_mov_b32 s5, 0
; GFX8-NEXT: v_mov_b32_e32 v1, 0 ; GFX8-NEXT: v_mov_b32_e32 v1, 0
; GFX8-NEXT: v_mov_b32_e32 v2, s5 ; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: v_mov_b32_e32 v3, s4 ; GFX8-NEXT: v_mov_b32_e32 v3, s5
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX6-LABEL: zextload_global_i32_to_i128: ; GFX6-LABEL: zextload_global_i32_to_i128:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s6, 0 ; GFX6-NEXT: s_mov_b32 s6, 0
; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: s_mov_b64 s[4:5], 0 ; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64 ; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64
; GFX6-NEXT: s_mov_b32 s8, 0
; GFX6-NEXT: s_mov_b32 s4, 0 ; GFX6-NEXT: s_mov_b32 s4, 0
; GFX6-NEXT: s_mov_b32 s5, 0
; GFX6-NEXT: v_mov_b32_e32 v1, 0 ; GFX6-NEXT: v_mov_b32_e32 v1, 0
; GFX6-NEXT: v_mov_b32_e32 v2, s4 ; GFX6-NEXT: v_mov_b32_e32 v2, s4
; GFX6-NEXT: v_mov_b32_e32 v3, s8 ; GFX6-NEXT: v_mov_b32_e32 v3, s5
; GFX6-NEXT: s_waitcnt vmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: s_setpc_b64 s[30:31] ; GFX6-NEXT: s_setpc_b64 s[30:31]
%load = load i32, i32 addrspace(1)* %ptr %load = load i32, i32 addrspace(1)* %ptr
%ext = zext i32 %load to i128 %ext = zext i32 %load to i128
ret i128 %ext ret i128 %ext
} }

llvm/test/CodeGen/AMDGPU/add.v2i16.ll

Show First 20 Lines • Show All 99 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @v_test_add_v2i16_neg_constant(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 {
%add = add <2 x i16> %a, <i16 -845, i16 -991> %add = add <2 x i16> %a, <i16 -845, i16 -991>
store <2 x i16> %add, <2 x i16> addrspace(1)* %out store <2 x i16> %add, <2 x i16> addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}v_test_add_v2i16_inline_neg1: ; GCN-LABEL: {{^}}v_test_add_v2i16_inline_neg1:
; GFX9: v_pk_sub_u16 v{{[0-9]+}}, v{{[0-9]+}}, 1 op_sel_hi:[1,0]{{$}} ; GFX9: v_pk_sub_u16 v{{[0-9]+}}, v{{[0-9]+}}, 1 op_sel_hi:[1,0]{{$}}
; VI: v_mov_b32_e32 v[[SCONST:[0-9]+]], -1 ; VI-DAG: v_mov_b32_e32 v[[SCONST:[0-9]+]], -1
; VI: flat_load_dword [[LOAD:v[0-9]+]] ; VI-DAG: flat_load_dword [[LOAD:v[0-9]+]]
; VI-DAG: v_add_u16_sdwa v{{[0-9]+}}, [[LOAD]], v[[SCONST]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; VI-DAG: v_add_u16_sdwa v{{[0-9]+}}, [[LOAD]], v[[SCONST]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-DAG: v_add_u16_e32 v{{[0-9]+}}, -1, [[LOAD]] ; VI-DAG: v_add_u16_e32 v{{[0-9]+}}, -1, [[LOAD]]
; VI: v_or_b32_e32 ; VI: v_or_b32_e32
define amdgpu_kernel void @v_test_add_v2i16_inline_neg1(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 { define amdgpu_kernel void @v_test_add_v2i16_inline_neg1(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid
%gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid %gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid
%a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0 %a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0
▲ Show 20 Lines • Show All 169 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 5,053 Lines • ▼ Show 20 Lines
define amdgpu_kernel void @udiv_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x) { define amdgpu_kernel void @udiv_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x) {
; CHECK-LABEL: @udiv_i64_pow2k_denom( ; CHECK-LABEL: @udiv_i64_pow2k_denom(
; CHECK-NEXT: [[R:%.*]] = udiv i64 [[X:%.*]], 4096 ; CHECK-NEXT: [[R:%.*]] = udiv i64 [[X:%.*]], 4096
; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4 ; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; GCN-LABEL: udiv_i64_pow2k_denom: ; GCN-LABEL: udiv_i64_pow2k_denom:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s0, s4 ; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: s_mov_b32 s1, s5 ; GCN-NEXT: s_mov_b32 s5, s1
; GCN-NEXT: s_lshr_b64 s[4:5], s[6:7], 12 ; GCN-NEXT: s_lshr_b64 s[0:1], s[2:3], 12
; GCN-NEXT: v_mov_b32_e32 v0, s4 ; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s5 ; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
%r = udiv i64 %x, 4096 %r = udiv i64 %x, 4096
store i64 %r, i64 addrspace(1)* %out store i64 %r, i64 addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @udiv_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 %x, i64 %y) { define amdgpu_kernel void @udiv_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 %x, i64 %y) {
; CHECK-LABEL: @udiv_i64_pow2_shl_denom( ; CHECK-LABEL: @udiv_i64_pow2_shl_denom(
▲ Show 20 Lines • Show All 618 Lines • ▼ Show 20 Lines
define amdgpu_kernel void @sdiv_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x) { define amdgpu_kernel void @sdiv_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x) {
; CHECK-LABEL: @sdiv_i64_pow2k_denom( ; CHECK-LABEL: @sdiv_i64_pow2k_denom(
; CHECK-NEXT: [[R:%.*]] = sdiv i64 [[X:%.*]], 4096 ; CHECK-NEXT: [[R:%.*]] = sdiv i64 [[X:%.*]], 4096
; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4 ; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; GCN-LABEL: sdiv_i64_pow2k_denom: ; GCN-LABEL: sdiv_i64_pow2k_denom:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s0, s4 ; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: s_ashr_i32 s4, s7, 31 ; GCN-NEXT: s_ashr_i32 s0, s3, 31
; GCN-NEXT: s_lshr_b32 s4, s4, 20 ; GCN-NEXT: s_lshr_b32 s0, s0, 20
; GCN-NEXT: s_add_u32 s4, s6, s4 ; GCN-NEXT: s_add_u32 s0, s2, s0
; GCN-NEXT: s_mov_b32 s1, s5 ; GCN-NEXT: s_mov_b32 s5, s1
; GCN-NEXT: s_addc_u32 s5, s7, 0 ; GCN-NEXT: s_addc_u32 s1, s3, 0
; GCN-NEXT: s_ashr_i64 s[4:5], s[4:5], 12 ; GCN-NEXT: s_ashr_i64 s[0:1], s[0:1], 12
; GCN-NEXT: v_mov_b32_e32 v0, s4 ; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s5 ; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
%r = sdiv i64 %x, 4096 %r = sdiv i64 %x, 4096
store i64 %r, i64 addrspace(1)* %out store i64 %r, i64 addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 %x, i64 %y) { define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 %x, i64 %y) {
; CHECK-LABEL: @sdiv_i64_pow2_shl_denom( ; CHECK-LABEL: @sdiv_i64_pow2_shl_denom(
▲ Show 20 Lines • Show All 1,258 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/bitreverse.ll

Show First 20 Lines • Show All 333 Lines • ▼ Show 20 Lines
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
; SI-NEXT: s_mov_b32 s7, 0xf000 ; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s2, 0 ; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s3, s7 ; SI-NEXT: s_mov_b32 s3, s7
; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; SI-NEXT: v_mov_b32_e32 v1, 0 ; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[0:3], 0 addr64 ; SI-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_mov_b32 s6, 0xff00ff ; SI-NEXT: s_mov_b32 s0, 0xff00ff
; SI-NEXT: s_mov_b32 s8, 0xf0f0f0f ; SI-NEXT: s_mov_b32 s1, 0xf0f0f0f
; SI-NEXT: s_mov_b32 s9, 0xf0f0f0f0 ; SI-NEXT: s_mov_b32 s2, 0xf0f0f0f0
; SI-NEXT: s_mov_b32 s10, 0x33333333 ; SI-NEXT: s_mov_b32 s3, 0x33333333
; SI-NEXT: s_mov_b32 s11, 0xcccccccc ; SI-NEXT: s_mov_b32 s6, 0xcccccccc
; SI-NEXT: s_mov_b32 s0, 0x55555555
; SI-NEXT: s_mov_b32 s1, 0xaaaaaaaa
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_alignbit_b32 v2, v0, v0, 8 ; SI-NEXT: v_alignbit_b32 v2, v0, v0, 8
; SI-NEXT: v_alignbit_b32 v0, v0, v0, 24 ; SI-NEXT: v_alignbit_b32 v0, v0, v0, 24
; SI-NEXT: v_alignbit_b32 v3, v1, v1, 8 ; SI-NEXT: v_alignbit_b32 v3, v1, v1, 8
; SI-NEXT: v_alignbit_b32 v1, v1, v1, 24 ; SI-NEXT: v_alignbit_b32 v1, v1, v1, 24
; SI-NEXT: v_bfi_b32 v2, s6, v0, v2 ; SI-NEXT: v_bfi_b32 v2, s0, v0, v2
; SI-NEXT: v_bfi_b32 v4, s6, v1, v3 ; SI-NEXT: v_bfi_b32 v4, s0, v1, v3
; SI-NEXT: v_and_b32_e32 v1, s8, v2 ; SI-NEXT: v_and_b32_e32 v1, s1, v2
; SI-NEXT: v_and_b32_e32 v0, s8, v4 ; SI-NEXT: v_and_b32_e32 v0, s1, v4
; SI-NEXT: v_and_b32_e32 v3, s9, v2 ; SI-NEXT: v_and_b32_e32 v3, s2, v2
; SI-NEXT: v_and_b32_e32 v2, s9, v4 ; SI-NEXT: v_and_b32_e32 v2, s2, v4
; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 4 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 4
; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 4 ; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 4
; SI-NEXT: s_mov_b32 s6, -1 ; SI-NEXT: s_mov_b32 s0, 0x55555555
; SI-NEXT: v_or_b32_e32 v3, v3, v1 ; SI-NEXT: v_or_b32_e32 v3, v3, v1
; SI-NEXT: v_or_b32_e32 v2, v2, v0 ; SI-NEXT: v_or_b32_e32 v2, v2, v0
; SI-NEXT: v_and_b32_e32 v1, s10, v3 ; SI-NEXT: v_and_b32_e32 v1, s3, v3
; SI-NEXT: v_and_b32_e32 v0, s10, v2 ; SI-NEXT: v_and_b32_e32 v0, s3, v2
; SI-NEXT: v_and_b32_e32 v3, s11, v3 ; SI-NEXT: v_and_b32_e32 v3, s6, v3
; SI-NEXT: v_and_b32_e32 v2, s11, v2 ; SI-NEXT: v_and_b32_e32 v2, s6, v2
; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 2 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 2 ; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 2
; SI-NEXT: s_mov_b32 s1, 0xaaaaaaaa
; SI-NEXT: v_or_b32_e32 v3, v3, v1 ; SI-NEXT: v_or_b32_e32 v3, v3, v1
; SI-NEXT: v_or_b32_e32 v2, v2, v0 ; SI-NEXT: v_or_b32_e32 v2, v2, v0
; SI-NEXT: v_and_b32_e32 v1, s0, v3 ; SI-NEXT: v_and_b32_e32 v1, s0, v3
; SI-NEXT: v_and_b32_e32 v0, s0, v2 ; SI-NEXT: v_and_b32_e32 v0, s0, v2
; SI-NEXT: v_and_b32_e32 v3, s1, v3 ; SI-NEXT: v_and_b32_e32 v3, s1, v3
; SI-NEXT: v_and_b32_e32 v2, s1, v2 ; SI-NEXT: v_and_b32_e32 v2, s1, v2
; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 1 ; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 1
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: v_or_b32_e32 v1, v3, v1 ; SI-NEXT: v_or_b32_e32 v1, v3, v1
; SI-NEXT: v_or_b32_e32 v0, v2, v0 ; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; FLAT-LABEL: v_brev_i64: ; FLAT-LABEL: v_brev_i64:
; FLAT: ; %bb.0: ; FLAT: ; %bb.0:
; FLAT-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; FLAT-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; FLAT-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c ; FLAT-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
; FLAT-NEXT: v_lshlrev_b32_e32 v0, 3, v0 ; FLAT-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; FLAT-NEXT: s_mov_b32 s6, 0x10203 ; FLAT-NEXT: s_mov_b32 s2, 0xf0f0f0f0
; FLAT-NEXT: s_mov_b32 s2, 0x33333333 ; FLAT-NEXT: s_mov_b32 s3, 0x33333333
; FLAT-NEXT: s_mov_b32 s3, 0xcccccccc ; FLAT-NEXT: s_mov_b32 s6, 0xcccccccc
; FLAT-NEXT: s_waitcnt lgkmcnt(0) ; FLAT-NEXT: s_waitcnt lgkmcnt(0)
; FLAT-NEXT: v_mov_b32_e32 v1, s1 ; FLAT-NEXT: v_mov_b32_e32 v1, s1
; FLAT-NEXT: v_add_u32_e32 v0, vcc, s0, v0 ; FLAT-NEXT: v_add_u32_e32 v0, vcc, s0, v0
; FLAT-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; FLAT-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; FLAT-NEXT: flat_load_dwordx2 v[0:1], v[0:1] ; FLAT-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; FLAT-NEXT: s_mov_b32 s0, 0xf0f0f0f ; FLAT-NEXT: s_mov_b32 s0, 0x10203
; FLAT-NEXT: s_mov_b32 s1, 0xf0f0f0f0 ; FLAT-NEXT: s_mov_b32 s1, 0xf0f0f0f
; FLAT-NEXT: s_mov_b32 s7, 0xf000 ; FLAT-NEXT: s_mov_b32 s7, 0xf000
; FLAT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; FLAT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; FLAT-NEXT: v_perm_b32 v2, 0, v0, s6 ; FLAT-NEXT: v_perm_b32 v2, 0, v0, s0
; FLAT-NEXT: v_perm_b32 v4, 0, v1, s6 ; FLAT-NEXT: v_perm_b32 v4, 0, v1, s0
; FLAT-NEXT: v_and_b32_e32 v1, s0, v2 ; FLAT-NEXT: v_and_b32_e32 v1, s1, v2
; FLAT-NEXT: v_and_b32_e32 v0, s0, v4 ; FLAT-NEXT: v_and_b32_e32 v0, s1, v4
; FLAT-NEXT: v_and_b32_e32 v3, s1, v2 ; FLAT-NEXT: v_and_b32_e32 v3, s2, v2
; FLAT-NEXT: v_and_b32_e32 v2, s1, v4 ; FLAT-NEXT: v_and_b32_e32 v2, s2, v4
; FLAT-NEXT: v_lshlrev_b64 v[0:1], 4, v[0:1] ; FLAT-NEXT: v_lshlrev_b64 v[0:1], 4, v[0:1]
; FLAT-NEXT: v_lshrrev_b64 v[2:3], 4, v[2:3] ; FLAT-NEXT: v_lshrrev_b64 v[2:3], 4, v[2:3]
; FLAT-NEXT: s_mov_b32 s0, 0x55555555 ; FLAT-NEXT: s_mov_b32 s0, 0x55555555
; FLAT-NEXT: v_or_b32_e32 v3, v3, v1 ; FLAT-NEXT: v_or_b32_e32 v3, v3, v1
; FLAT-NEXT: v_or_b32_e32 v2, v2, v0 ; FLAT-NEXT: v_or_b32_e32 v2, v2, v0
; FLAT-NEXT: v_and_b32_e32 v1, s2, v3 ; FLAT-NEXT: v_and_b32_e32 v1, s3, v3
; FLAT-NEXT: v_and_b32_e32 v0, s2, v2 ; FLAT-NEXT: v_and_b32_e32 v0, s3, v2
; FLAT-NEXT: v_and_b32_e32 v3, s3, v3 ; FLAT-NEXT: v_and_b32_e32 v3, s6, v3
; FLAT-NEXT: v_and_b32_e32 v2, s3, v2 ; FLAT-NEXT: v_and_b32_e32 v2, s6, v2
; FLAT-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1] ; FLAT-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
; FLAT-NEXT: v_lshrrev_b64 v[2:3], 2, v[2:3] ; FLAT-NEXT: v_lshrrev_b64 v[2:3], 2, v[2:3]
; FLAT-NEXT: s_mov_b32 s1, 0xaaaaaaaa ; FLAT-NEXT: s_mov_b32 s1, 0xaaaaaaaa
; FLAT-NEXT: v_or_b32_e32 v3, v3, v1 ; FLAT-NEXT: v_or_b32_e32 v3, v3, v1
; FLAT-NEXT: v_or_b32_e32 v2, v2, v0 ; FLAT-NEXT: v_or_b32_e32 v2, v2, v0
; FLAT-NEXT: v_and_b32_e32 v1, s0, v3 ; FLAT-NEXT: v_and_b32_e32 v1, s0, v3
; FLAT-NEXT: v_and_b32_e32 v0, s0, v2 ; FLAT-NEXT: v_and_b32_e32 v0, s0, v2
; FLAT-NEXT: v_and_b32_e32 v3, s1, v3 ; FLAT-NEXT: v_and_b32_e32 v3, s1, v3
▲ Show 20 Lines • Show All 171 Lines • ▼ Show 20 Lines
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
; SI-NEXT: s_mov_b32 s7, 0xf000 ; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s2, 0 ; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s3, s7 ; SI-NEXT: s_mov_b32 s3, s7
; SI-NEXT: v_lshlrev_b32_e32 v0, 4, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 4, v0
; SI-NEXT: v_mov_b32_e32 v1, 0 ; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 addr64 ; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_mov_b32 s8, 0xff00ff ; SI-NEXT: s_mov_b32 s0, 0xff00ff
; SI-NEXT: s_mov_b32 s9, 0xf0f0f0f ; SI-NEXT: s_mov_b32 s1, 0xf0f0f0f
; SI-NEXT: s_mov_b32 s10, 0xf0f0f0f0 ; SI-NEXT: s_mov_b32 s2, 0xf0f0f0f0
; SI-NEXT: s_mov_b32 s11, 0x33333333 ; SI-NEXT: s_mov_b32 s3, 0x33333333
; SI-NEXT: s_mov_b32 s12, 0xcccccccc ; SI-NEXT: s_mov_b32 s8, 0xcccccccc
; SI-NEXT: s_mov_b32 s13, 0x55555555 ; SI-NEXT: s_mov_b32 s9, 0x55555555
; SI-NEXT: s_mov_b32 s14, 0xaaaaaaaa ; SI-NEXT: s_mov_b32 s10, 0xaaaaaaaa
; SI-NEXT: s_mov_b32 s6, -1 ; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_alignbit_b32 v4, v2, v2, 8 ; SI-NEXT: v_alignbit_b32 v4, v2, v2, 8
; SI-NEXT: v_alignbit_b32 v2, v2, v2, 24 ; SI-NEXT: v_alignbit_b32 v2, v2, v2, 24
; SI-NEXT: v_alignbit_b32 v5, v3, v3, 8 ; SI-NEXT: v_alignbit_b32 v5, v3, v3, 8
; SI-NEXT: v_alignbit_b32 v6, v0, v0, 8 ; SI-NEXT: v_alignbit_b32 v6, v0, v0, 8
; SI-NEXT: v_alignbit_b32 v0, v0, v0, 24 ; SI-NEXT: v_alignbit_b32 v0, v0, v0, 24
; SI-NEXT: v_alignbit_b32 v7, v1, v1, 8 ; SI-NEXT: v_alignbit_b32 v7, v1, v1, 8
; SI-NEXT: v_alignbit_b32 v1, v1, v1, 24 ; SI-NEXT: v_alignbit_b32 v1, v1, v1, 24
; SI-NEXT: v_alignbit_b32 v3, v3, v3, 24 ; SI-NEXT: v_alignbit_b32 v3, v3, v3, 24
; SI-NEXT: v_bfi_b32 v2, s8, v2, v4 ; SI-NEXT: v_bfi_b32 v2, s0, v2, v4
; SI-NEXT: v_bfi_b32 v4, s8, v3, v5 ; SI-NEXT: v_bfi_b32 v4, s0, v3, v5
; SI-NEXT: v_bfi_b32 v6, s8, v0, v6 ; SI-NEXT: v_bfi_b32 v6, s0, v0, v6
; SI-NEXT: v_bfi_b32 v8, s8, v1, v7 ; SI-NEXT: v_bfi_b32 v8, s0, v1, v7
; SI-NEXT: v_and_b32_e32 v1, s9, v2 ; SI-NEXT: v_and_b32_e32 v1, s1, v2
; SI-NEXT: v_and_b32_e32 v0, s9, v4 ; SI-NEXT: v_and_b32_e32 v0, s1, v4
; SI-NEXT: v_and_b32_e32 v3, s10, v2 ; SI-NEXT: v_and_b32_e32 v3, s2, v2
; SI-NEXT: v_and_b32_e32 v2, s10, v4 ; SI-NEXT: v_and_b32_e32 v2, s2, v4
; SI-NEXT: v_and_b32_e32 v5, s9, v6 ; SI-NEXT: v_and_b32_e32 v5, s1, v6
; SI-NEXT: v_and_b32_e32 v4, s9, v8 ; SI-NEXT: v_and_b32_e32 v4, s1, v8
; SI-NEXT: v_and_b32_e32 v7, s10, v6 ; SI-NEXT: v_and_b32_e32 v7, s2, v6
; SI-NEXT: v_and_b32_e32 v6, s10, v8 ; SI-NEXT: v_and_b32_e32 v6, s2, v8
; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 4 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 4
; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 4 ; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 4
; SI-NEXT: v_lshl_b64 v[4:5], v[4:5], 4 ; SI-NEXT: v_lshl_b64 v[4:5], v[4:5], 4
; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 4 ; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 4
; SI-NEXT: v_or_b32_e32 v3, v3, v1 ; SI-NEXT: v_or_b32_e32 v3, v3, v1
; SI-NEXT: v_or_b32_e32 v2, v2, v0 ; SI-NEXT: v_or_b32_e32 v2, v2, v0
; SI-NEXT: v_or_b32_e32 v7, v7, v5 ; SI-NEXT: v_or_b32_e32 v7, v7, v5
; SI-NEXT: v_or_b32_e32 v6, v6, v4 ; SI-NEXT: v_or_b32_e32 v6, v6, v4
; SI-NEXT: v_and_b32_e32 v1, s11, v3 ; SI-NEXT: v_and_b32_e32 v1, s3, v3
; SI-NEXT: v_and_b32_e32 v0, s11, v2 ; SI-NEXT: v_and_b32_e32 v0, s3, v2
; SI-NEXT: v_and_b32_e32 v5, s11, v7 ; SI-NEXT: v_and_b32_e32 v5, s3, v7
; SI-NEXT: v_and_b32_e32 v4, s11, v6 ; SI-NEXT: v_and_b32_e32 v4, s3, v6
; SI-NEXT: v_and_b32_e32 v3, s12, v3 ; SI-NEXT: v_and_b32_e32 v3, s8, v3
; SI-NEXT: v_and_b32_e32 v2, s12, v2 ; SI-NEXT: v_and_b32_e32 v2, s8, v2
; SI-NEXT: v_and_b32_e32 v7, s12, v7 ; SI-NEXT: v_and_b32_e32 v7, s8, v7
; SI-NEXT: v_and_b32_e32 v6, s12, v6 ; SI-NEXT: v_and_b32_e32 v6, s8, v6
; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 2 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 2 ; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 2
; SI-NEXT: v_lshl_b64 v[4:5], v[4:5], 2 ; SI-NEXT: v_lshl_b64 v[4:5], v[4:5], 2
; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 2 ; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 2
; SI-NEXT: v_or_b32_e32 v3, v3, v1 ; SI-NEXT: v_or_b32_e32 v3, v3, v1
; SI-NEXT: v_or_b32_e32 v2, v2, v0 ; SI-NEXT: v_or_b32_e32 v2, v2, v0
; SI-NEXT: v_or_b32_e32 v7, v7, v5 ; SI-NEXT: v_or_b32_e32 v7, v7, v5
; SI-NEXT: v_or_b32_e32 v6, v6, v4 ; SI-NEXT: v_or_b32_e32 v6, v6, v4
; SI-NEXT: v_and_b32_e32 v1, s13, v3 ; SI-NEXT: v_and_b32_e32 v1, s9, v3
; SI-NEXT: v_and_b32_e32 v0, s13, v2 ; SI-NEXT: v_and_b32_e32 v0, s9, v2
; SI-NEXT: v_and_b32_e32 v5, s13, v7 ; SI-NEXT: v_and_b32_e32 v5, s9, v7
; SI-NEXT: v_and_b32_e32 v4, s13, v6 ; SI-NEXT: v_and_b32_e32 v4, s9, v6
; SI-NEXT: v_and_b32_e32 v3, s14, v3 ; SI-NEXT: v_and_b32_e32 v3, s10, v3
; SI-NEXT: v_and_b32_e32 v2, s14, v2 ; SI-NEXT: v_and_b32_e32 v2, s10, v2
; SI-NEXT: v_and_b32_e32 v7, s14, v7 ; SI-NEXT: v_and_b32_e32 v7, s10, v7
; SI-NEXT: v_and_b32_e32 v6, s14, v6 ; SI-NEXT: v_and_b32_e32 v6, s10, v6
; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 1 ; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 1
; SI-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 ; SI-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 1 ; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 1
; SI-NEXT: v_or_b32_e32 v3, v3, v1 ; SI-NEXT: v_or_b32_e32 v3, v3, v1
; SI-NEXT: v_or_b32_e32 v2, v2, v0 ; SI-NEXT: v_or_b32_e32 v2, v2, v0
; SI-NEXT: v_or_b32_e32 v1, v7, v5 ; SI-NEXT: v_or_b32_e32 v1, v7, v5
; SI-NEXT: v_or_b32_e32 v0, v6, v4 ; SI-NEXT: v_or_b32_e32 v0, v6, v4
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; FLAT-LABEL: v_brev_v2i64: ; FLAT-LABEL: v_brev_v2i64:
; FLAT: ; %bb.0: ; FLAT: ; %bb.0:
; FLAT-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; FLAT-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; FLAT-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c ; FLAT-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
; FLAT-NEXT: v_lshlrev_b32_e32 v0, 4, v0 ; FLAT-NEXT: v_lshlrev_b32_e32 v0, 4, v0
; FLAT-NEXT: s_mov_b32 s10, 0x10203 ; FLAT-NEXT: s_mov_b32 s2, 0xf0f0f0f0
; FLAT-NEXT: s_mov_b32 s2, 0x33333333 ; FLAT-NEXT: s_mov_b32 s3, 0x33333333
; FLAT-NEXT: s_mov_b32 s3, 0xcccccccc ; FLAT-NEXT: s_mov_b32 s8, 0xcccccccc
; FLAT-NEXT: s_waitcnt lgkmcnt(0) ; FLAT-NEXT: s_waitcnt lgkmcnt(0)
; FLAT-NEXT: v_mov_b32_e32 v1, s1 ; FLAT-NEXT: v_mov_b32_e32 v1, s1
; FLAT-NEXT: v_add_u32_e32 v0, vcc, s0, v0 ; FLAT-NEXT: v_add_u32_e32 v0, vcc, s0, v0
; FLAT-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; FLAT-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; FLAT-NEXT: flat_load_dwordx4 v[0:3], v[0:1] ; FLAT-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; FLAT-NEXT: s_mov_b32 s0, 0xf0f0f0f ; FLAT-NEXT: s_mov_b32 s0, 0x10203
; FLAT-NEXT: s_mov_b32 s1, 0xf0f0f0f0 ; FLAT-NEXT: s_mov_b32 s1, 0xf0f0f0f
; FLAT-NEXT: s_mov_b32 s8, 0x55555555 ; FLAT-NEXT: s_mov_b32 s9, 0x55555555
; FLAT-NEXT: s_mov_b32 s9, 0xaaaaaaaa ; FLAT-NEXT: s_mov_b32 s10, 0xaaaaaaaa
; FLAT-NEXT: s_mov_b32 s7, 0xf000 ; FLAT-NEXT: s_mov_b32 s7, 0xf000
; FLAT-NEXT: s_mov_b32 s6, -1 ; FLAT-NEXT: s_mov_b32 s6, -1
; FLAT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; FLAT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; FLAT-NEXT: v_perm_b32 v6, 0, v0, s10 ; FLAT-NEXT: v_perm_b32 v6, 0, v0, s0
; FLAT-NEXT: v_perm_b32 v4, 0, v3, s10 ; FLAT-NEXT: v_perm_b32 v4, 0, v3, s0
; FLAT-NEXT: v_perm_b32 v2, 0, v2, s10 ; FLAT-NEXT: v_perm_b32 v2, 0, v2, s0
; FLAT-NEXT: v_perm_b32 v8, 0, v1, s10 ; FLAT-NEXT: v_perm_b32 v8, 0, v1, s0
; FLAT-NEXT: v_and_b32_e32 v1, s0, v2 ; FLAT-NEXT: v_and_b32_e32 v1, s1, v2
; FLAT-NEXT: v_and_b32_e32 v0, s0, v4 ; FLAT-NEXT: v_and_b32_e32 v0, s1, v4
; FLAT-NEXT: v_and_b32_e32 v3, s1, v2 ; FLAT-NEXT: v_and_b32_e32 v3, s2, v2
; FLAT-NEXT: v_and_b32_e32 v2, s1, v4 ; FLAT-NEXT: v_and_b32_e32 v2, s2, v4
; FLAT-NEXT: v_and_b32_e32 v5, s0, v6 ; FLAT-NEXT: v_and_b32_e32 v5, s1, v6
; FLAT-NEXT: v_and_b32_e32 v4, s0, v8 ; FLAT-NEXT: v_and_b32_e32 v4, s1, v8
; FLAT-NEXT: v_and_b32_e32 v7, s1, v6 ; FLAT-NEXT: v_and_b32_e32 v7, s2, v6
; FLAT-NEXT: v_and_b32_e32 v6, s1, v8 ; FLAT-NEXT: v_and_b32_e32 v6, s2, v8
; FLAT-NEXT: v_lshlrev_b64 v[0:1], 4, v[0:1] ; FLAT-NEXT: v_lshlrev_b64 v[0:1], 4, v[0:1]
; FLAT-NEXT: v_lshrrev_b64 v[2:3], 4, v[2:3] ; FLAT-NEXT: v_lshrrev_b64 v[2:3], 4, v[2:3]
; FLAT-NEXT: v_lshlrev_b64 v[4:5], 4, v[4:5] ; FLAT-NEXT: v_lshlrev_b64 v[4:5], 4, v[4:5]
; FLAT-NEXT: v_lshrrev_b64 v[6:7], 4, v[6:7] ; FLAT-NEXT: v_lshrrev_b64 v[6:7], 4, v[6:7]
; FLAT-NEXT: v_or_b32_e32 v3, v3, v1 ; FLAT-NEXT: v_or_b32_e32 v3, v3, v1
; FLAT-NEXT: v_or_b32_e32 v2, v2, v0 ; FLAT-NEXT: v_or_b32_e32 v2, v2, v0
; FLAT-NEXT: v_or_b32_e32 v7, v7, v5 ; FLAT-NEXT: v_or_b32_e32 v7, v7, v5
; FLAT-NEXT: v_or_b32_e32 v6, v6, v4 ; FLAT-NEXT: v_or_b32_e32 v6, v6, v4
; FLAT-NEXT: v_and_b32_e32 v1, s2, v3 ; FLAT-NEXT: v_and_b32_e32 v1, s3, v3
; FLAT-NEXT: v_and_b32_e32 v0, s2, v2 ; FLAT-NEXT: v_and_b32_e32 v0, s3, v2
; FLAT-NEXT: v_and_b32_e32 v5, s2, v7 ; FLAT-NEXT: v_and_b32_e32 v5, s3, v7
; FLAT-NEXT: v_and_b32_e32 v4, s2, v6 ; FLAT-NEXT: v_and_b32_e32 v4, s3, v6
; FLAT-NEXT: v_and_b32_e32 v3, s3, v3 ; FLAT-NEXT: v_and_b32_e32 v3, s8, v3
; FLAT-NEXT: v_and_b32_e32 v2, s3, v2 ; FLAT-NEXT: v_and_b32_e32 v2, s8, v2
; FLAT-NEXT: v_and_b32_e32 v7, s3, v7 ; FLAT-NEXT: v_and_b32_e32 v7, s8, v7
; FLAT-NEXT: v_and_b32_e32 v6, s3, v6 ; FLAT-NEXT: v_and_b32_e32 v6, s8, v6
; FLAT-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1] ; FLAT-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
; FLAT-NEXT: v_lshrrev_b64 v[2:3], 2, v[2:3] ; FLAT-NEXT: v_lshrrev_b64 v[2:3], 2, v[2:3]
; FLAT-NEXT: v_lshlrev_b64 v[4:5], 2, v[4:5] ; FLAT-NEXT: v_lshlrev_b64 v[4:5], 2, v[4:5]
; FLAT-NEXT: v_lshrrev_b64 v[6:7], 2, v[6:7] ; FLAT-NEXT: v_lshrrev_b64 v[6:7], 2, v[6:7]
; FLAT-NEXT: v_or_b32_e32 v3, v3, v1 ; FLAT-NEXT: v_or_b32_e32 v3, v3, v1
; FLAT-NEXT: v_or_b32_e32 v2, v2, v0 ; FLAT-NEXT: v_or_b32_e32 v2, v2, v0
; FLAT-NEXT: v_or_b32_e32 v7, v7, v5 ; FLAT-NEXT: v_or_b32_e32 v7, v7, v5
; FLAT-NEXT: v_or_b32_e32 v6, v6, v4 ; FLAT-NEXT: v_or_b32_e32 v6, v6, v4
; FLAT-NEXT: v_and_b32_e32 v1, s8, v3 ; FLAT-NEXT: v_and_b32_e32 v1, s9, v3
; FLAT-NEXT: v_and_b32_e32 v0, s8, v2 ; FLAT-NEXT: v_and_b32_e32 v0, s9, v2
; FLAT-NEXT: v_and_b32_e32 v5, s8, v7 ; FLAT-NEXT: v_and_b32_e32 v5, s9, v7
; FLAT-NEXT: v_and_b32_e32 v4, s8, v6 ; FLAT-NEXT: v_and_b32_e32 v4, s9, v6
; FLAT-NEXT: v_and_b32_e32 v3, s9, v3 ; FLAT-NEXT: v_and_b32_e32 v3, s10, v3
; FLAT-NEXT: v_and_b32_e32 v2, s9, v2 ; FLAT-NEXT: v_and_b32_e32 v2, s10, v2
; FLAT-NEXT: v_and_b32_e32 v7, s9, v7 ; FLAT-NEXT: v_and_b32_e32 v7, s10, v7
; FLAT-NEXT: v_and_b32_e32 v6, s9, v6 ; FLAT-NEXT: v_and_b32_e32 v6, s10, v6
; FLAT-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1] ; FLAT-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
; FLAT-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3] ; FLAT-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3]
; FLAT-NEXT: v_lshlrev_b64 v[4:5], 1, v[4:5] ; FLAT-NEXT: v_lshlrev_b64 v[4:5], 1, v[4:5]
; FLAT-NEXT: v_lshrrev_b64 v[6:7], 1, v[6:7] ; FLAT-NEXT: v_lshrrev_b64 v[6:7], 1, v[6:7]
; FLAT-NEXT: v_or_b32_e32 v3, v3, v1 ; FLAT-NEXT: v_or_b32_e32 v3, v3, v1
; FLAT-NEXT: v_or_b32_e32 v2, v2, v0 ; FLAT-NEXT: v_or_b32_e32 v2, v2, v0
; FLAT-NEXT: v_or_b32_e32 v1, v7, v5 ; FLAT-NEXT: v_or_b32_e32 v1, v7, v5
; FLAT-NEXT: v_or_b32_e32 v0, v6, v4 ; FLAT-NEXT: v_or_b32_e32 v0, v6, v4
Show All 35 Lines

llvm/test/CodeGen/AMDGPU/bswap.ll

Show All 27 Lines
; SI-NEXT: v_alignbit_b32 v1, s4, s4, 24 ; SI-NEXT: v_alignbit_b32 v1, s4, s4, 24
; SI-NEXT: s_mov_b32 s4, 0xff00ff ; SI-NEXT: s_mov_b32 s4, 0xff00ff
; SI-NEXT: v_bfi_b32 v0, s4, v1, v0 ; SI-NEXT: v_bfi_b32 v0, s4, v1, v0
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: test_bswap_i32: ; VI-LABEL: test_bswap_i32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_mov_b32_e32 v0, 0x10203 ; VI-NEXT: v_mov_b32_e32 v0, 0x10203
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s7, 0xf000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s6, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: s_mov_b32 s4, s0
; VI-NEXT: s_load_dword s4, s[6:7], 0x0 ; VI-NEXT: s_load_dword s0, s[2:3], 0x0
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s5, s1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_perm_b32 v0, 0, s4, v0 ; VI-NEXT: v_perm_b32 v0, 0, s0, v0
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%val = load i32, i32 addrspace(1)* %in, align 4 %val = load i32, i32 addrspace(1)* %in, align 4
%bswap = call i32 @llvm.bswap.i32(i32 %val) nounwind readnone %bswap = call i32 @llvm.bswap.i32(i32 %val) nounwind readnone
store i32 %bswap, i32 addrspace(1)* %out, align 4 store i32 %bswap, i32 addrspace(1)* %out, align 4
ret void ret void
} }
define amdgpu_kernel void @test_bswap_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) nounwind { define amdgpu_kernel void @test_bswap_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) nounwind {
Show All 12 Lines
; SI-NEXT: v_alignbit_b32 v3, s4, s4, 24 ; SI-NEXT: v_alignbit_b32 v3, s4, s4, 24
; SI-NEXT: v_bfi_b32 v1, s6, v1, v0 ; SI-NEXT: v_bfi_b32 v1, s6, v1, v0
; SI-NEXT: v_bfi_b32 v0, s6, v3, v2 ; SI-NEXT: v_bfi_b32 v0, s6, v3, v2
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: test_bswap_v2i32: ; VI-LABEL: test_bswap_v2i32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_mov_b32_e32 v0, 0x10203 ; VI-NEXT: v_mov_b32_e32 v0, 0x10203
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s7, 0xf000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s6, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s4, s0
; VI-NEXT: s_load_dwordx2 s[4:5], s[6:7], 0x0 ; VI-NEXT: s_mov_b32 s5, s1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_perm_b32 v1, 0, s5, v0 ; VI-NEXT: v_perm_b32 v1, 0, s3, v0
; VI-NEXT: v_perm_b32 v0, 0, s4, v0 ; VI-NEXT: v_perm_b32 v0, 0, s2, v0
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%val = load <2 x i32>, <2 x i32> addrspace(1)* %in, align 8 %val = load <2 x i32>, <2 x i32> addrspace(1)* %in, align 8
%bswap = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %val) nounwind readnone %bswap = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %val) nounwind readnone
store <2 x i32> %bswap, <2 x i32> addrspace(1)* %out, align 8 store <2 x i32> %bswap, <2 x i32> addrspace(1)* %out, align 8
ret void ret void
} }
define amdgpu_kernel void @test_bswap_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) nounwind { define amdgpu_kernel void @test_bswap_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) nounwind {
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; ;
; VI-LABEL: test_bswap_v4i32: ; VI-LABEL: test_bswap_v4i32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: v_mov_b32_e32 v0, 0x10203 ; VI-NEXT: v_mov_b32_e32 v0, 0x10203
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_load_dwordx4 s[8:11], s[6:7], 0x0
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: s_mov_b32 s0, s4
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s1, s5
; VI-NEXT: s_load_dwordx4 s[4:7], s[6:7], 0x0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_perm_b32 v3, 0, s7, v0 ; VI-NEXT: v_perm_b32 v3, 0, s11, v0
; VI-NEXT: v_perm_b32 v2, 0, s6, v0 ; VI-NEXT: v_perm_b32 v2, 0, s10, v0
; VI-NEXT: v_perm_b32 v1, 0, s5, v0 ; VI-NEXT: v_perm_b32 v1, 0, s9, v0
; VI-NEXT: v_perm_b32 v0, 0, s4, v0 ; VI-NEXT: v_perm_b32 v0, 0, s8, v0
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%val = load <4 x i32>, <4 x i32> addrspace(1)* %in, align 16 %val = load <4 x i32>, <4 x i32> addrspace(1)* %in, align 16
%bswap = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %val) nounwind readnone %bswap = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %val) nounwind readnone
store <4 x i32> %bswap, <4 x i32> addrspace(1)* %out, align 16 store <4 x i32> %bswap, <4 x i32> addrspace(1)* %out, align 16
ret void ret void
} }
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; SI-NEXT: v_alignbit_b32 v3, s5, s5, 24 ; SI-NEXT: v_alignbit_b32 v3, s5, s5, 24
; SI-NEXT: v_bfi_b32 v1, s6, v1, v0 ; SI-NEXT: v_bfi_b32 v1, s6, v1, v0
; SI-NEXT: v_bfi_b32 v0, s6, v3, v2 ; SI-NEXT: v_bfi_b32 v0, s6, v3, v2
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: test_bswap_i64: ; VI-LABEL: test_bswap_i64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_mov_b32_e32 v0, 0x10203 ; VI-NEXT: v_mov_b32_e32 v0, 0x10203
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s7, 0xf000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s6, -1
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s0, s4
; VI-NEXT: s_mov_b32 s1, s5
; VI-NEXT: s_load_dwordx2 s[4:5], s[6:7], 0x0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_perm_b32 v1, 0, s4, v0 ; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; VI-NEXT: v_perm_b32 v0, 0, s5, v0 ; VI-NEXT: s_mov_b32 s4, s0
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; VI-NEXT: s_mov_b32 s5, s1
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_perm_b32 v1, 0, s2, v0
; VI-NEXT: v_perm_b32 v0, 0, s3, v0
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%val = load i64, i64 addrspace(1)* %in, align 8 %val = load i64, i64 addrspace(1)* %in, align 8
%bswap = call i64 @llvm.bswap.i64(i64 %val) nounwind readnone %bswap = call i64 @llvm.bswap.i64(i64 %val) nounwind readnone
store i64 %bswap, i64 addrspace(1)* %out, align 8 store i64 %bswap, i64 addrspace(1)* %out, align 8
ret void ret void
} }
define amdgpu_kernel void @test_bswap_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) nounwind { define amdgpu_kernel void @test_bswap_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) nounwind {
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; ;
; VI-LABEL: test_bswap_v2i64: ; VI-LABEL: test_bswap_v2i64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: v_mov_b32_e32 v0, 0x10203 ; VI-NEXT: v_mov_b32_e32 v0, 0x10203
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_load_dwordx4 s[8:11], s[6:7], 0x0
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: s_mov_b32 s0, s4
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s1, s5
; VI-NEXT: s_load_dwordx4 s[4:7], s[6:7], 0x0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_perm_b32 v3, 0, s6, v0 ; VI-NEXT: v_perm_b32 v3, 0, s10, v0
; VI-NEXT: v_perm_b32 v2, 0, s7, v0 ; VI-NEXT: v_perm_b32 v2, 0, s11, v0
; VI-NEXT: v_perm_b32 v1, 0, s4, v0 ; VI-NEXT: v_perm_b32 v1, 0, s8, v0
; VI-NEXT: v_perm_b32 v0, 0, s5, v0 ; VI-NEXT: v_perm_b32 v0, 0, s9, v0
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%val = load <2 x i64>, <2 x i64> addrspace(1)* %in, align 16 %val = load <2 x i64>, <2 x i64> addrspace(1)* %in, align 16
%bswap = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %val) nounwind readnone %bswap = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %val) nounwind readnone
store <2 x i64> %bswap, <2 x i64> addrspace(1)* %out, align 16 store <2 x i64> %bswap, <2 x i64> addrspace(1)* %out, align 16
ret void ret void
} }
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llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll

Show First 20 Lines • Show All 193 Lines • ▼ Show 20 Lines
; GCN-LABEL: vload2_private: ; GCN-LABEL: vload2_private:
; GCN: ; %bb.0: ; %entry ; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_add_u32 flat_scratch_lo, s6, s9 ; GCN-NEXT: s_add_u32 flat_scratch_lo, s6, s9
; GCN-NEXT: s_addc_u32 flat_scratch_hi, s7, 0 ; GCN-NEXT: s_addc_u32 flat_scratch_hi, s7, 0
; GCN-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0 ; GCN-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GCN-NEXT: s_add_u32 s0, s0, s9 ; GCN-NEXT: s_add_u32 s0, s0, s9
; GCN-NEXT: s_addc_u32 s1, s1, 0 ; GCN-NEXT: s_addc_u32 s1, s1, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v2, s4 ; GCN-NEXT: v_mov_b32_e32 v0, s4
; GCN-NEXT: v_mov_b32_e32 v3, s5 ; GCN-NEXT: v_mov_b32_e32 v1, s5
; GCN-NEXT: global_load_ushort v4, v[2:3], off ; GCN-NEXT: global_load_ushort v2, v[0:1], off
; GCN-NEXT: v_mov_b32_e32 v0, s6
; GCN-NEXT: v_mov_b32_e32 v1, s7
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_store_short v4, off, s[0:3], 0 offset:4 ; GCN-NEXT: buffer_store_short v2, off, s[0:3], 0 offset:4
; GCN-NEXT: global_load_ushort v4, v[2:3], off offset:2 ; GCN-NEXT: global_load_ushort v2, v[0:1], off offset:2
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_store_short v4, off, s[0:3], 0 offset:6 ; GCN-NEXT: buffer_store_short v2, off, s[0:3], 0 offset:6
; GCN-NEXT: global_load_ushort v2, v[2:3], off offset:4 ; GCN-NEXT: global_load_ushort v2, v[0:1], off offset:4
; GCN-NEXT: v_mov_b32_e32 v0, s6
; GCN-NEXT: v_mov_b32_e32 v1, s7
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_store_short v2, off, s[0:3], 0 offset:8 ; GCN-NEXT: buffer_store_short v2, off, s[0:3], 0 offset:8
; GCN-NEXT: buffer_load_ushort v2, off, s[0:3], 0 offset:4 ; GCN-NEXT: buffer_load_ushort v2, off, s[0:3], 0 offset:4
; GCN-NEXT: buffer_load_ushort v4, off, s[0:3], 0 offset:6 ; GCN-NEXT: buffer_load_ushort v4, off, s[0:3], 0 offset:6
; GCN-NEXT: s_waitcnt vmcnt(1) ; GCN-NEXT: s_waitcnt vmcnt(1)
; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v3, v4 ; GCN-NEXT: v_mov_b32_e32 v3, v4
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llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines; VI-NEXT: s_endpgm
store <4 x i8> %val, <4 x i8> addrspace(1)* %out, align 4 store <4 x i8> %val, <4 x i8> addrspace(1)* %out, align 4
ret void ret void
} }
define amdgpu_kernel void @test_copy_v4i8_x2(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %in) nounwind { define amdgpu_kernel void @test_copy_v4i8_x2(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %in) nounwind {
; SI-LABEL: test_copy_v4i8_x2: ; SI-LABEL: test_copy_v4i8_x2:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s11, 0xf000
; SI-NEXT: s_mov_b32 s10, 0 ; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s11, s3 ; SI-NEXT: s_mov_b32 s3, s11
; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SI-NEXT: v_mov_b32_e32 v1, 0 ; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64 ; SI-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s10, -1
; SI-NEXT: s_mov_b32 s0, s4 ; SI-NEXT: s_mov_b32 s8, s4
; SI-NEXT: s_mov_b32 s1, s5 ; SI-NEXT: s_mov_b32 s9, s5
; SI-NEXT: s_mov_b32 s12, s6 ; SI-NEXT: s_mov_b32 s2, s10
; SI-NEXT: s_mov_b32 s13, s7 ; SI-NEXT: s_mov_b32 s0, s6
; SI-NEXT: s_mov_b32 s14, s2 ; SI-NEXT: s_mov_b32 s1, s7
; SI-NEXT: s_mov_b32 s15, s3
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: buffer_store_dword v0, off, s[12:15], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: test_copy_v4i8_x2: ; VI-LABEL: test_copy_v4i8_x2:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_mov_b32 s10, s2
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s8, s6
; VI-NEXT: v_mov_b32_e32 v1, s1 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v0, v[0:1]
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: s_mov_b32 s0, s4
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s1, s5
; VI-NEXT: s_mov_b32 s9, s7
; VI-NEXT: s_mov_b32 s10, s2
; VI-NEXT: s_mov_b32 s11, s3 ; VI-NEXT: s_mov_b32 s11, s3
; VI-NEXT: s_mov_b32 s8, s6
; VI-NEXT: s_mov_b32 s9, s7
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0 ; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%tid.x = call i32 @llvm.amdgcn.workitem.id.x() %tid.x = call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid.x %gep = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid.x
%val = load <4 x i8>, <4 x i8> addrspace(1)* %gep, align 4 %val = load <4 x i8>, <4 x i8> addrspace(1)* %gep, align 4
store <4 x i8> %val, <4 x i8> addrspace(1)* %out0, align 4 store <4 x i8> %val, <4 x i8> addrspace(1)* %out0, align 4
store <4 x i8> %val, <4 x i8> addrspace(1)* %out1, align 4 store <4 x i8> %val, <4 x i8> addrspace(1)* %out1, align 4
ret void ret void
} }
define amdgpu_kernel void @test_copy_v4i8_x3(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %out2, <4 x i8> addrspace(1)* %in) nounwind { define amdgpu_kernel void @test_copy_v4i8_x3(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %out2, <4 x i8> addrspace(1)* %in) nounwind {
; SI-LABEL: test_copy_v4i8_x3: ; SI-LABEL: test_copy_v4i8_x3:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s11, 0xf000 ; SI-NEXT: s_mov_b32 s11, 0xf000
; SI-NEXT: s_mov_b32 s22, 0 ; SI-NEXT: s_mov_b32 s14, 0
; SI-NEXT: s_mov_b32 s23, s11 ; SI-NEXT: s_mov_b32 s15, s11
; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b64 s[20:21], s[6:7] ; SI-NEXT: s_mov_b64 s[12:13], s[6:7]
; SI-NEXT: v_mov_b32_e32 v1, 0 ; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: buffer_load_dword v0, v[0:1], s[20:23], 0 addr64 ; SI-NEXT: buffer_load_dword v0, v[0:1], s[12:15], 0 addr64
; SI-NEXT: s_mov_b32 s10, -1 ; SI-NEXT: s_mov_b32 s10, -1
; SI-NEXT: s_mov_b32 s8, s0 ; SI-NEXT: s_mov_b32 s8, s0
; SI-NEXT: s_mov_b32 s9, s1 ; SI-NEXT: s_mov_b32 s9, s1
; SI-NEXT: s_mov_b32 s14, s10
; SI-NEXT: s_mov_b32 s6, s10
; SI-NEXT: s_mov_b32 s7, s11
; SI-NEXT: s_mov_b32 s12, s2 ; SI-NEXT: s_mov_b32 s12, s2
; SI-NEXT: s_mov_b32 s13, s3 ; SI-NEXT: s_mov_b32 s13, s3
; SI-NEXT: s_mov_b32 s14, s10
; SI-NEXT: s_mov_b32 s15, s11
; SI-NEXT: s_mov_b32 s16, s4
; SI-NEXT: s_mov_b32 s17, s5
; SI-NEXT: s_mov_b32 s18, s10
; SI-NEXT: s_mov_b32 s19, s11
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0 ; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0
; SI-NEXT: buffer_store_dword v0, off, s[12:15], 0 ; SI-NEXT: buffer_store_dword v0, off, s[12:15], 0
; SI-NEXT: buffer_store_dword v0, off, s[16:19], 0 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: test_copy_v4i8_x3: ; VI-LABEL: test_copy_v4i8_x3:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; VI-NEXT: s_mov_b32 s11, 0xf000 ; VI-NEXT: s_mov_b32 s11, 0xf000
; VI-NEXT: s_mov_b32 s10, -1 ; VI-NEXT: s_mov_b32 s10, -1
; VI-NEXT: s_mov_b32 s14, s10 ; VI-NEXT: s_mov_b32 s14, s10
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s7 ; VI-NEXT: v_mov_b32_e32 v1, s7
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v0, v[0:1]
; VI-NEXT: s_mov_b32 s8, s0 ; VI-NEXT: s_mov_b32 s8, s0
; VI-NEXT: s_mov_b32 s9, s1 ; VI-NEXT: s_mov_b32 s9, s1
; VI-NEXT: s_mov_b32 s15, s11
; VI-NEXT: s_mov_b32 s6, s10
; VI-NEXT: s_mov_b32 s7, s11
; VI-NEXT: s_mov_b32 s12, s2 ; VI-NEXT: s_mov_b32 s12, s2
; VI-NEXT: s_mov_b32 s13, s3 ; VI-NEXT: s_mov_b32 s13, s3
; VI-NEXT: s_mov_b32 s15, s11
; VI-NEXT: s_mov_b32 s16, s4
; VI-NEXT: s_mov_b32 s17, s5
; VI-NEXT: s_mov_b32 s18, s10
; VI-NEXT: s_mov_b32 s19, s11
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0 ; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0
; VI-NEXT: buffer_store_dword v0, off, s[12:15], 0 ; VI-NEXT: buffer_store_dword v0, off, s[12:15], 0
; VI-NEXT: buffer_store_dword v0, off, s[16:19], 0 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%tid.x = call i32 @llvm.amdgcn.workitem.id.x() %tid.x = call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid.x %gep = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid.x
%val = load <4 x i8>, <4 x i8> addrspace(1)* %gep, align 4 %val = load <4 x i8>, <4 x i8> addrspace(1)* %gep, align 4
store <4 x i8> %val, <4 x i8> addrspace(1)* %out0, align 4 store <4 x i8> %val, <4 x i8> addrspace(1)* %out0, align 4
store <4 x i8> %val, <4 x i8> addrspace(1)* %out1, align 4 store <4 x i8> %val, <4 x i8> addrspace(1)* %out1, align 4
store <4 x i8> %val, <4 x i8> addrspace(1)* %out2, align 4 store <4 x i8> %val, <4 x i8> addrspace(1)* %out2, align 4
ret void ret void
} }
define amdgpu_kernel void @test_copy_v4i8_x4(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %out2, <4 x i8> addrspace(1)* %out3, <4 x i8> addrspace(1)* %in) nounwind { define amdgpu_kernel void @test_copy_v4i8_x4(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %out2, <4 x i8> addrspace(1)* %out3, <4 x i8> addrspace(1)* %in) nounwind {
; SI-LABEL: test_copy_v4i8_x4: ; SI-LABEL: test_copy_v4i8_x4:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x11
; SI-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x11 ; SI-NEXT: s_mov_b32 s11, 0xf000
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s6, 0
; SI-NEXT: s_mov_b32 s14, 0 ; SI-NEXT: s_mov_b32 s7, s11
; SI-NEXT: s_mov_b32 s15, s3
; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SI-NEXT: v_mov_b32_e32 v1, 0 ; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_load_dword v0, v[0:1], s[12:15], 0 addr64 ; SI-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s0, s4 ; SI-NEXT: s_mov_b32 s10, -1
; SI-NEXT: s_mov_b32 s1, s5 ; SI-NEXT: s_mov_b32 s14, s10
; SI-NEXT: s_mov_b32 s20, s8 ; SI-NEXT: s_mov_b32 s15, s11
; SI-NEXT: s_mov_b32 s21, s9 ; SI-NEXT: s_mov_b32 s18, s10
; SI-NEXT: s_mov_b32 s8, s10 ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s9, s11 ; SI-NEXT: s_mov_b32 s8, s0
; SI-NEXT: s_mov_b32 s16, s6 ; SI-NEXT: s_mov_b32 s9, s1
; SI-NEXT: s_mov_b32 s17, s7 ; SI-NEXT: s_mov_b32 s19, s11
; SI-NEXT: s_mov_b32 s18, s2 ; SI-NEXT: s_mov_b32 s22, s10
; SI-NEXT: s_mov_b32 s19, s3 ; SI-NEXT: s_mov_b32 s23, s11
; SI-NEXT: s_mov_b32 s22, s2 ; SI-NEXT: s_mov_b32 s12, s2
; SI-NEXT: s_mov_b32 s23, s3 ; SI-NEXT: s_mov_b32 s13, s3
; SI-NEXT: s_mov_b32 s10, s2 ; SI-NEXT: s_mov_b32 s16, s4
; SI-NEXT: s_mov_b32 s11, s3 ; SI-NEXT: s_mov_b32 s17, s5
; SI-NEXT: s_mov_b32 s20, s6
; SI-NEXT: s_mov_b32 s21, s7
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0
; SI-NEXT: buffer_store_dword v0, off, s[12:15], 0
; SI-NEXT: buffer_store_dword v0, off, s[16:19], 0 ; SI-NEXT: buffer_store_dword v0, off, s[16:19], 0
; SI-NEXT: buffer_store_dword v0, off, s[20:23], 0 ; SI-NEXT: buffer_store_dword v0, off, s[20:23], 0
; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: test_copy_v4i8_x4: ; VI-LABEL: test_copy_v4i8_x4:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x44
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x44
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s11, 0xf000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s10, -1
; VI-NEXT: s_mov_b32 s14, s10
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s16, s8 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_mov_b32_e32 v1, s1 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v0, v[0:1]
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s15, s11
; VI-NEXT: s_mov_b32 s17, s9 ; VI-NEXT: s_mov_b32 s18, s10
; VI-NEXT: s_mov_b32 s8, s10 ; VI-NEXT: s_mov_b32 s19, s11
; VI-NEXT: s_mov_b32 s9, s11 ; VI-NEXT: s_mov_b32 s22, s10
; VI-NEXT: s_mov_b32 s12, s6 ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s13, s7 ; VI-NEXT: s_mov_b32 s8, s0
; VI-NEXT: s_mov_b32 s14, s2 ; VI-NEXT: s_mov_b32 s9, s1
; VI-NEXT: s_mov_b32 s15, s3 ; VI-NEXT: s_mov_b32 s23, s11
; VI-NEXT: s_mov_b32 s18, s2 ; VI-NEXT: s_mov_b32 s12, s2
; VI-NEXT: s_mov_b32 s19, s3 ; VI-NEXT: s_mov_b32 s13, s3
; VI-NEXT: s_mov_b32 s10, s2 ; VI-NEXT: s_mov_b32 s16, s4
; VI-NEXT: s_mov_b32 s11, s3 ; VI-NEXT: s_mov_b32 s17, s5
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_mov_b32 s20, s6
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: s_mov_b32 s21, s7
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0
; VI-NEXT: buffer_store_dword v0, off, s[12:15], 0 ; VI-NEXT: buffer_store_dword v0, off, s[12:15], 0
; VI-NEXT: buffer_store_dword v0, off, s[16:19], 0 ; VI-NEXT: buffer_store_dword v0, off, s[16:19], 0
; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0 ; VI-NEXT: buffer_store_dword v0, off, s[20:23], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%tid.x = call i32 @llvm.amdgcn.workitem.id.x() %tid.x = call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid.x %gep = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid.x
%val = load <4 x i8>, <4 x i8> addrspace(1)* %gep, align 4 %val = load <4 x i8>, <4 x i8> addrspace(1)* %gep, align 4
store <4 x i8> %val, <4 x i8> addrspace(1)* %out0, align 4 store <4 x i8> %val, <4 x i8> addrspace(1)* %out0, align 4
store <4 x i8> %val, <4 x i8> addrspace(1)* %out1, align 4 store <4 x i8> %val, <4 x i8> addrspace(1)* %out1, align 4
store <4 x i8> %val, <4 x i8> addrspace(1)* %out2, align 4 store <4 x i8> %val, <4 x i8> addrspace(1)* %out2, align 4
store <4 x i8> %val, <4 x i8> addrspace(1)* %out3, align 4 store <4 x i8> %val, <4 x i8> addrspace(1)* %out3, align 4
ret void ret void
} }
define amdgpu_kernel void @test_copy_v4i8_extra_use(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %in) nounwind { define amdgpu_kernel void @test_copy_v4i8_extra_use(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %in) nounwind {
; SI-LABEL: test_copy_v4i8_extra_use: ; SI-LABEL: test_copy_v4i8_extra_use:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s11, 0xf000
; SI-NEXT: s_mov_b32 s10, 0 ; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s11, s3 ; SI-NEXT: s_mov_b32 s3, s11
; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SI-NEXT: v_mov_b32_e32 v1, 0 ; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64 ; SI-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_mov_b32 s12, 0xff00 ; SI-NEXT: s_mov_b32 s12, 0xff00
; SI-NEXT: s_movk_i32 s13, 0xff ; SI-NEXT: s_movk_i32 s13, 0xff
; SI-NEXT: s_mov_b32 s0, s4 ; SI-NEXT: s_mov_b32 s10, -1
; SI-NEXT: s_mov_b32 s1, s5 ; SI-NEXT: s_mov_b32 s8, s4
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s9, s5
; SI-NEXT: s_mov_b32 s4, s6 ; SI-NEXT: s_mov_b32 s2, s10
; SI-NEXT: s_mov_b32 s5, s7 ; SI-NEXT: s_mov_b32 s0, s6
; SI-NEXT: s_mov_b32 s6, s2 ; SI-NEXT: s_mov_b32 s1, s7
; SI-NEXT: s_mov_b32 s7, s3
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v3, vcc, 9, v0 ; SI-NEXT: v_add_i32_e32 v3, vcc, 9, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0 ; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; SI-NEXT: v_and_b32_e32 v4, s12, v1 ; SI-NEXT: v_and_b32_e32 v4, s12, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 9, v1 ; SI-NEXT: v_add_i32_e32 v1, vcc, 9, v1
; SI-NEXT: v_and_b32_e32 v2, s12, v0 ; SI-NEXT: v_and_b32_e32 v2, s12, v0
; SI-NEXT: v_and_b32_e32 v3, s13, v3 ; SI-NEXT: v_and_b32_e32 v3, s13, v3
; SI-NEXT: v_or_b32_e32 v2, v2, v3 ; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v1, s13, v1 ; SI-NEXT: v_and_b32_e32 v1, s13, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x900, v2 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x900, v2
; SI-NEXT: v_or_b32_e32 v1, v4, v1 ; SI-NEXT: v_or_b32_e32 v1, v4, v1
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v1, v2 ; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x9000000, v1 ; SI-NEXT: v_add_i32_e32 v1, vcc, 0x9000000, v1
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0
; SI-NEXT: buffer_store_dword v1, off, s[4:7], 0 ; SI-NEXT: buffer_store_dword v1, off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: test_copy_v4i8_extra_use: ; VI-LABEL: test_copy_v4i8_extra_use:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; VI-NEXT: s_movk_i32 s10, 0x900 ; VI-NEXT: s_movk_i32 s12, 0xff00
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_movk_i32 s13, 0xff
; VI-NEXT: s_movk_i32 s14, 0x900
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v1, s9 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
; VI-NEXT: v_add_u32_e32 v0, vcc, s8, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v0, v[0:1]
; VI-NEXT: s_movk_i32 s8, 0xff00 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_movk_i32 s9, 0xff
; VI-NEXT: s_mov_b32 s1, s5
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_mov_b32 s4, s6 ; VI-NEXT: s_mov_b32 s0, s4
; VI-NEXT: s_mov_b32 s5, s7 ; VI-NEXT: s_mov_b32 s1, s5
; VI-NEXT: s_mov_b32 s6, s2 ; VI-NEXT: s_mov_b32 s10, s2
; VI-NEXT: s_mov_b32 s7, s3 ; VI-NEXT: s_mov_b32 s11, s3
; VI-NEXT: s_mov_b32 s8, s6
; VI-NEXT: s_mov_b32 s9, s7
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v0 ; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; VI-NEXT: v_and_b32_e32 v4, s8, v1 ; VI-NEXT: v_and_b32_e32 v4, s12, v1
; VI-NEXT: v_add_u16_e32 v1, 9, v1 ; VI-NEXT: v_add_u16_e32 v1, 9, v1
; VI-NEXT: v_add_u16_e32 v3, 9, v0 ; VI-NEXT: v_add_u16_e32 v3, 9, v0
; VI-NEXT: v_and_b32_e32 v1, s9, v1 ; VI-NEXT: v_and_b32_e32 v1, s13, v1
; VI-NEXT: v_or_b32_e32 v1, v4, v1 ; VI-NEXT: v_or_b32_e32 v1, v4, v1
; VI-NEXT: v_and_b32_e32 v2, s8, v0 ; VI-NEXT: v_and_b32_e32 v2, s12, v0
; VI-NEXT: v_and_b32_e32 v3, s9, v3 ; VI-NEXT: v_and_b32_e32 v3, s13, v3
; VI-NEXT: v_or_b32_e32 v2, v2, v3 ; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u16_e32 v1, s10, v1 ; VI-NEXT: v_add_u16_e32 v1, s14, v1
; VI-NEXT: v_add_u16_e32 v2, s10, v2 ; VI-NEXT: v_add_u16_e32 v2, s14, v2
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_or_b32_e32 v1, v2, v1 ; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0 ; VI-NEXT: buffer_store_dword v1, off, s[8:11], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%tid.x = call i32 @llvm.amdgcn.workitem.id.x() %tid.x = call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid.x %gep = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid.x
%val = load <4 x i8>, <4 x i8> addrspace(1)* %gep, align 4 %val = load <4 x i8>, <4 x i8> addrspace(1)* %gep, align 4
%add = add <4 x i8> %val, <i8 9, i8 9, i8 9, i8 9> %add = add <4 x i8> %val, <i8 9, i8 9, i8 9, i8 9>
store <4 x i8> %val, <4 x i8> addrspace(1)* %out0, align 4 store <4 x i8> %val, <4 x i8> addrspace(1)* %out0, align 4
store <4 x i8> %add, <4 x i8> addrspace(1)* %out1, align 4 store <4 x i8> %add, <4 x i8> addrspace(1)* %out1, align 4
ret void ret void
} }
; FIXME: Need to handle non-uniform case for function below (load without gep). ; FIXME: Need to handle non-uniform case for function below (load without gep).
define amdgpu_kernel void @test_copy_v4i8_x2_extra_use(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %out2, <4 x i8> addrspace(1)* %in) nounwind { define amdgpu_kernel void @test_copy_v4i8_x2_extra_use(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %out2, <4 x i8> addrspace(1)* %in) nounwind {
; SI-LABEL: test_copy_v4i8_x2_extra_use: ; SI-LABEL: test_copy_v4i8_x2_extra_use:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s11, 0xf000 ; SI-NEXT: s_mov_b32 s11, 0xf000
; SI-NEXT: s_mov_b32 s18, 0 ; SI-NEXT: s_mov_b32 s14, 0
; SI-NEXT: s_mov_b32 s19, s11 ; SI-NEXT: s_mov_b32 s15, s11
; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b64 s[16:17], s[6:7] ; SI-NEXT: s_mov_b64 s[12:13], s[6:7]
; SI-NEXT: v_mov_b32_e32 v1, 0 ; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: buffer_load_dword v0, v[0:1], s[16:19], 0 addr64 ; SI-NEXT: buffer_load_dword v0, v[0:1], s[12:15], 0 addr64
; SI-NEXT: s_mov_b32 s12, s4 ; SI-NEXT: s_mov_b32 s16, 0xff00
; SI-NEXT: s_mov_b32 s13, s5 ; SI-NEXT: s_movk_i32 s17, 0xff
; SI-NEXT: s_mov_b32 s4, 0xff00
; SI-NEXT: s_movk_i32 s5, 0xff
; SI-NEXT: s_mov_b32 s10, -1 ; SI-NEXT: s_mov_b32 s10, -1
; SI-NEXT: s_mov_b32 s14, s10
; SI-NEXT: s_mov_b32 s8, s0 ; SI-NEXT: s_mov_b32 s8, s0
; SI-NEXT: s_mov_b32 s9, s1 ; SI-NEXT: s_mov_b32 s9, s1
; SI-NEXT: s_mov_b32 s0, s2 ; SI-NEXT: s_mov_b32 s12, s2
; SI-NEXT: s_mov_b32 s1, s3 ; SI-NEXT: s_mov_b32 s13, s3
; SI-NEXT: s_mov_b32 s2, s10 ; SI-NEXT: s_mov_b32 s6, s10
; SI-NEXT: s_mov_b32 s3, s11 ; SI-NEXT: s_mov_b32 s7, s11
; SI-NEXT: s_mov_b32 s14, s10
; SI-NEXT: s_mov_b32 s15, s11
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v3, vcc, 9, v0 ; SI-NEXT: v_add_i32_e32 v3, vcc, 9, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0 ; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; SI-NEXT: v_and_b32_e32 v4, s4, v1 ; SI-NEXT: v_and_b32_e32 v4, s16, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 9, v1 ; SI-NEXT: v_add_i32_e32 v1, vcc, 9, v1
; SI-NEXT: v_and_b32_e32 v2, s4, v0 ; SI-NEXT: v_and_b32_e32 v2, s16, v0
; SI-NEXT: v_and_b32_e32 v3, s5, v3 ; SI-NEXT: v_and_b32_e32 v3, s17, v3
; SI-NEXT: v_or_b32_e32 v2, v2, v3 ; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v1, s5, v1 ; SI-NEXT: v_and_b32_e32 v1, s17, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x900, v2 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x900, v2
; SI-NEXT: v_or_b32_e32 v1, v4, v1 ; SI-NEXT: v_or_b32_e32 v1, v4, v1
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v1, v2 ; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x9000000, v1 ; SI-NEXT: v_add_i32_e32 v1, vcc, 0x9000000, v1
; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0 ; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0
; SI-NEXT: buffer_store_dword v1, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v1, off, s[12:15], 0
; SI-NEXT: buffer_store_dword v0, off, s[12:15], 0 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: test_copy_v4i8_x2_extra_use: ; VI-LABEL: test_copy_v4i8_x2_extra_use:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; VI-NEXT: s_mov_b32 s11, 0xf000 ; VI-NEXT: s_movk_i32 s16, 0xff00
; VI-NEXT: s_mov_b32 s10, -1 ; VI-NEXT: s_movk_i32 s17, 0xff
; VI-NEXT: s_mov_b32 s14, s10 ; VI-NEXT: s_movk_i32 s18, 0x900
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v0
; VI-NEXT: v_mov_b32_e32 v1, s7 ; VI-NEXT: v_mov_b32_e32 v1, s7
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v0, v[0:1]
; VI-NEXT: s_mov_b32 s12, s4 ; VI-NEXT: s_mov_b32 s11, 0xf000
; VI-NEXT: s_movk_i32 s4, 0xff00 ; VI-NEXT: s_mov_b32 s10, -1
; VI-NEXT: s_mov_b32 s13, s5 ; VI-NEXT: s_mov_b32 s14, s10
; VI-NEXT: s_movk_i32 s5, 0xff ; VI-NEXT: s_mov_b32 s15, s11
; VI-NEXT: s_movk_i32 s6, 0x900
; VI-NEXT: s_mov_b32 s8, s0 ; VI-NEXT: s_mov_b32 s8, s0
; VI-NEXT: s_mov_b32 s9, s1 ; VI-NEXT: s_mov_b32 s9, s1
; VI-NEXT: s_mov_b32 s0, s2 ; VI-NEXT: s_mov_b32 s12, s2
; VI-NEXT: s_mov_b32 s1, s3 ; VI-NEXT: s_mov_b32 s13, s3
; VI-NEXT: s_mov_b32 s2, s10 ; VI-NEXT: s_mov_b32 s6, s10
; VI-NEXT: s_mov_b32 s3, s11 ; VI-NEXT: s_mov_b32 s7, s11
; VI-NEXT: s_mov_b32 s15, s11
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v0 ; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; VI-NEXT: v_and_b32_e32 v4, s4, v1 ; VI-NEXT: v_and_b32_e32 v4, s16, v1
; VI-NEXT: v_add_u16_e32 v1, 9, v1 ; VI-NEXT: v_add_u16_e32 v1, 9, v1
; VI-NEXT: v_add_u16_e32 v3, 9, v0 ; VI-NEXT: v_add_u16_e32 v3, 9, v0
; VI-NEXT: v_and_b32_e32 v1, s5, v1 ; VI-NEXT: v_and_b32_e32 v1, s17, v1
; VI-NEXT: v_or_b32_e32 v1, v4, v1 ; VI-NEXT: v_or_b32_e32 v1, v4, v1
; VI-NEXT: v_and_b32_e32 v2, s4, v0 ; VI-NEXT: v_and_b32_e32 v2, s16, v0
; VI-NEXT: v_and_b32_e32 v3, s5, v3 ; VI-NEXT: v_and_b32_e32 v3, s17, v3
; VI-NEXT: v_or_b32_e32 v2, v2, v3 ; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u16_e32 v1, s6, v1 ; VI-NEXT: v_add_u16_e32 v1, s18, v1
; VI-NEXT: v_add_u16_e32 v2, s6, v2 ; VI-NEXT: v_add_u16_e32 v2, s18, v2
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_or_b32_e32 v1, v2, v1 ; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0 ; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0
; VI-NEXT: buffer_store_dword v1, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v1, off, s[12:15], 0
; VI-NEXT: buffer_store_dword v0, off, s[12:15], 0 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%tid.x = call i32 @llvm.amdgcn.workitem.id.x() %tid.x = call i32 @llvm.amdgcn.workitem.id.x()
%in.ptr = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid.x %in.ptr = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid.x
%val = load <4 x i8>, <4 x i8> addrspace(1)* %in.ptr, align 4 %val = load <4 x i8>, <4 x i8> addrspace(1)* %in.ptr, align 4
%add = add <4 x i8> %val, <i8 9, i8 9, i8 9, i8 9> %add = add <4 x i8> %val, <i8 9, i8 9, i8 9, i8 9>
store <4 x i8> %val, <4 x i8> addrspace(1)* %out0, align 4 store <4 x i8> %val, <4 x i8> addrspace(1)* %out0, align 4
store <4 x i8> %add, <4 x i8> addrspace(1)* %out1, align 4 store <4 x i8> %add, <4 x i8> addrspace(1)* %out1, align 4
store <4 x i8> %val, <4 x i8> addrspace(1)* %out2, align 4 store <4 x i8> %val, <4 x i8> addrspace(1)* %out2, align 4
ret void ret void
} }
define amdgpu_kernel void @test_copy_v3i8_align4(<3 x i8> addrspace(1)* %out, <3 x i8> addrspace(1)* %in) nounwind { define amdgpu_kernel void @test_copy_v3i8_align4(<3 x i8> addrspace(1)* %out, <3 x i8> addrspace(1)* %in) nounwind {
; SI-LABEL: test_copy_v3i8_align4: ; SI-LABEL: test_copy_v3i8_align4:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s10, 0 ; SI-NEXT: s_mov_b32 s6, 0
; SI-NEXT: s_mov_b32 s11, s3 ; SI-NEXT: s_mov_b32 s7, s3
; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b64 s[8:9], s[6:7] ; SI-NEXT: s_mov_b64 s[4:5], s[10:11]
; SI-NEXT: v_mov_b32_e32 v1, 0 ; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64 ; SI-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_mov_b32 s0, s4 ; SI-NEXT: s_mov_b32 s0, s8
; SI-NEXT: s_mov_b32 s1, s5 ; SI-NEXT: s_mov_b32 s1, s9
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0 ; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
; SI-NEXT: buffer_store_byte v1, off, s[0:3], 0 offset:2 ; SI-NEXT: buffer_store_byte v1, off, s[0:3], 0 offset:2
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: test_copy_v3i8_align4: ; VI-LABEL: test_copy_v3i8_align4:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s7 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v0, v[0:1]
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v0 ; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
; VI-NEXT: buffer_store_byte v1, off, s[0:3], 0 offset:2 ; VI-NEXT: buffer_store_byte v1, off, s[0:3], 0 offset:2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%tid.x = call i32 @llvm.amdgcn.workitem.id.x() %tid.x = call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr <3 x i8>, <3 x i8> addrspace(1)* %in, i32 %tid.x %gep = getelementptr <3 x i8>, <3 x i8> addrspace(1)* %in, i32 %tid.x
%val = load <3 x i8>, <3 x i8> addrspace(1)* %gep, align 4 %val = load <3 x i8>, <3 x i8> addrspace(1)* %gep, align 4
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llvm/test/CodeGen/AMDGPU/ctlz.ll

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; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 ; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: v_ctlz_i64: ; VI-LABEL: v_ctlz_i64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 ; VI-NEXT: v_lshlrev_b32_e32 v3, 3, v0
; VI-NEXT: v_mov_b32_e32 v5, 0 ; VI-NEXT: v_mov_b32_e32 v4, 0
; VI-NEXT: v_mov_b32_e32 v1, 0 ; VI-NEXT: v_mov_b32_e32 v2, 0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v6, s3 ; VI-NEXT: v_mov_b32_e32 v5, s3
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v3
; VI-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc
; VI-NEXT: flat_load_dwordx2 v[2:3], v[2:3] ; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; VI-NEXT: v_add_u32_e32 v4, vcc, s2, v0 ; VI-NEXT: v_add_u32_e32 v3, vcc, s2, v3
; VI-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc ; VI-NEXT: v_addc_u32_e32 v4, vcc, v5, v4, vcc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_ffbh_u32_e32 v0, v2 ; VI-NEXT: v_ffbh_u32_e32 v5, v0
; VI-NEXT: v_add_u32_e32 v0, vcc, 32, v0 ; VI-NEXT: v_add_u32_e32 v5, vcc, 32, v5
; VI-NEXT: v_ffbh_u32_e32 v6, v3 ; VI-NEXT: v_ffbh_u32_e32 v6, v1
; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 ; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: v_or_b32_e32 v2, v2, v3 ; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; VI-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc ; VI-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; VI-NEXT: v_cndmask_b32_e32 v0, 64, v0, vcc ; VI-NEXT: v_cndmask_b32_e32 v1, 64, v1, vcc
; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1] ; VI-NEXT: flat_store_dwordx2 v[3:4], v[1:2]
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; EG-LABEL: v_ctlz_i64: ; EG-LABEL: v_ctlz_i64:
; EG: ; %bb.0: ; EG: ; %bb.0:
; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6 ; EG-NEXT: TEX 0 @6
; EG-NEXT: ALU 10, @11, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 10, @11, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
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; VI-NEXT: v_lshlrev_b32_e32 v1, 3, v0 ; VI-NEXT: v_lshlrev_b32_e32 v1, 3, v0
; VI-NEXT: v_mov_b32_e32 v4, 0 ; VI-NEXT: v_mov_b32_e32 v4, 0
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v5, s3 ; VI-NEXT: v_mov_b32_e32 v5, s3
; VI-NEXT: v_mov_b32_e32 v2, s1 ; VI-NEXT: v_mov_b32_e32 v2, s1
; VI-NEXT: v_add_u32_e32 v1, vcc, s0, v1 ; VI-NEXT: v_add_u32_e32 v1, vcc, s0, v1
; VI-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc ; VI-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc
; VI-NEXT: flat_load_dwordx2 v[1:2], v[1:2]
; VI-NEXT: v_add_u32_e32 v3, vcc, s2, v0 ; VI-NEXT: v_add_u32_e32 v3, vcc, s2, v0
; VI-NEXT: flat_load_dwordx2 v[0:1], v[1:2]
; VI-NEXT: v_addc_u32_e32 v4, vcc, v5, v4, vcc ; VI-NEXT: v_addc_u32_e32 v4, vcc, v5, v4, vcc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_ffbh_u32_e32 v2, v0 ; VI-NEXT: v_ffbh_u32_e32 v0, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, 32, v0
; VI-NEXT: v_ffbh_u32_e32 v5, v1 ; VI-NEXT: v_ffbh_u32_e32 v5, v2
; VI-NEXT: v_or_b32_e32 v0, v0, v1 ; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc ; VI-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
; VI-NEXT: v_cndmask_b32_e32 v0, 64, v1, vcc ; VI-NEXT: v_cndmask_b32_e32 v0, 64, v0, vcc
; VI-NEXT: flat_store_dword v[3:4], v0 ; VI-NEXT: flat_store_dword v[3:4], v0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; EG-LABEL: v_ctlz_i64_trunc: ; EG-LABEL: v_ctlz_i64_trunc:
; EG: ; %bb.0: ; EG: ; %bb.0:
; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6 ; EG-NEXT: TEX 0 @6
; EG-NEXT: ALU 10, @11, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 10, @11, KC0[CB0:0-32], KC1[]
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llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll

Show First 20 Lines • Show All 171 Lines • ▼ Show 20 Lines
; SI-NOSDWA: v_or_b32_e32 ; SI-NOSDWA: v_or_b32_e32
; SI-NOSDWA: v_or_b32_e32 ; SI-NOSDWA: v_or_b32_e32
; SI-NOSDWA: v_or_b32_e32 ; SI-NOSDWA: v_or_b32_e32
; SI-NOSDWA: v_or_b32_e32 ; SI-NOSDWA: v_or_b32_e32
; SI-NOSDWA: v_or_b32_e32 [[VAL1:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}} ; SI-NOSDWA: v_or_b32_e32 [[VAL1:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
; SI-NOSDWA: v_or_b32_e32 [[VAL2:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}} ; SI-NOSDWA: v_or_b32_e32 [[VAL2:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
; SI-NOSDWA: v_ffbl_b32_e32 v{{[0-9]+}}, [[VAL1]] ; SI-NOSDWA: v_ffbl_b32_e32 v{{[0-9]+}}, [[VAL1]]
; SI-NOSDWA: v_ffbl_b32_e32 v{{[0-9]+}}, [[VAL2]] ; SI-NOSDWA: v_ffbl_b32_e32 v{{[0-9]+}}, [[VAL2]]
; SI-SDWA: v_or_b32_e32
; SI-SDWA: v_or_b32_sdwa ; SI-SDWA: v_or_b32_sdwa
; SI-SDWA: v_or_b32_e32
; SI-SDWA: v_or_b32_e32
; SI-SDWA: v_or_b32_e32 [[VAL1:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}} ; SI-SDWA: v_or_b32_e32 [[VAL1:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
; SI-SDWA: v_ffbl_b32_e32 v{{[0-9]+}}, [[VAL1]] ; SI-SDWA: v_ffbl_b32_e32 v{{[0-9]+}}, [[VAL1]]
; SI-SDWA: v_or_b32_e32
; SI-SDWA: v_or_b32_sdwa ; SI-SDWA: v_or_b32_sdwa
; SI-SDWA: v_or_b32_e32 [[VAL2:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}} ; SI-SDWA: v_or_b32_e32 [[VAL2:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
; SI-SDWA: v_ffbl_b32_e32 v{{[0-9]+}}, [[VAL2]] ; SI-SDWA: v_ffbl_b32_e32 v{{[0-9]+}}, [[VAL2]]
; SI: v_cmp_eq_u32_e32 vcc, 0 ; SI: v_cmp_eq_u32_e32 vcc, 0
; SI: v_cmp_ne_u64_e32 vcc, 0 ; SI: v_cmp_ne_u64_e32 vcc, 0
; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]] ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
define amdgpu_kernel void @v_cttz_zero_undef_i64_with_select(i64 addrspace(1)* noalias %out, i64 addrspace(1)* nocapture readonly %arrayidx) nounwind { define amdgpu_kernel void @v_cttz_zero_undef_i64_with_select(i64 addrspace(1)* noalias %out, i64 addrspace(1)* nocapture readonly %arrayidx) nounwind {
%val = load i64, i64 addrspace(1)* %arrayidx, align 1 %val = load i64, i64 addrspace(1)* %arrayidx, align 1
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llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll

Show First 20 Lines • Show All 630 Lines • ▼ Show 20 Lines; VI-NEXT: s_endpgm
ret void ret void
} }
; FIXME: Need to handle non-uniform case for function below (load without gep). ; FIXME: Need to handle non-uniform case for function below (load without gep).
; Instructions still emitted to repack bytes for add use. ; Instructions still emitted to repack bytes for add use.
define amdgpu_kernel void @load_v4i8_to_v4f32_2_uses(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %out2, <4 x i8> addrspace(1)* noalias %in) nounwind { define amdgpu_kernel void @load_v4i8_to_v4f32_2_uses(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %out2, <4 x i8> addrspace(1)* noalias %in) nounwind {
; SI-LABEL: load_v4i8_to_v4f32_2_uses: ; SI-LABEL: load_v4i8_to_v4f32_2_uses:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd
; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xb ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd ; SI-NEXT: s_mov_b32 s6, 0
; SI-NEXT: s_mov_b32 s11, 0xf000 ; SI-NEXT: s_mov_b32 s7, s3
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s3, s11
; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SI-NEXT: v_mov_b32_e32 v1, 0 ; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_load_dword v4, v[0:1], s[0:3], 0 addr64 ; SI-NEXT: buffer_load_dword v4, v[0:1], s[4:7], 0 addr64
; SI-NEXT: s_mov_b32 s10, -1 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s6, s10 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
; SI-NEXT: s_mov_b32 s7, s11 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_movk_i32 s12, 0xff ; SI-NEXT: s_movk_i32 s8, 0xff
; SI-NEXT: s_mov_b32 s6, s2
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v4 ; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v4
; SI-NEXT: v_lshrrev_b32_e32 v6, 24, v4 ; SI-NEXT: v_lshrrev_b32_e32 v6, 24, v4
; SI-NEXT: v_and_b32_e32 v7, 0xff00, v4 ; SI-NEXT: v_and_b32_e32 v7, 0xff00, v4
; SI-NEXT: v_cvt_f32_ubyte3_e32 v3, v4 ; SI-NEXT: v_cvt_f32_ubyte3_e32 v3, v4
; SI-NEXT: v_cvt_f32_ubyte2_e32 v2, v4 ; SI-NEXT: v_cvt_f32_ubyte2_e32 v2, v4
; SI-NEXT: v_cvt_f32_ubyte1_e32 v1, v4 ; SI-NEXT: v_cvt_f32_ubyte1_e32 v1, v4
; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v4 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 9, v4 ; SI-NEXT: v_add_i32_e32 v4, vcc, 9, v4
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, s12, v4 ; SI-NEXT: v_and_b32_e32 v0, s8, v4
; SI-NEXT: v_add_i32_e32 v2, vcc, 9, v5 ; SI-NEXT: v_add_i32_e32 v2, vcc, 9, v5
; SI-NEXT: v_or_b32_e32 v0, v7, v0 ; SI-NEXT: v_or_b32_e32 v0, v7, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v6 ; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v6
; SI-NEXT: v_and_b32_e32 v2, s12, v2 ; SI-NEXT: v_and_b32_e32 v2, s8, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x900, v0 ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x900, v0
; SI-NEXT: v_or_b32_e32 v1, v1, v2 ; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0 ; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x9000000, v0 ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x9000000, v0
; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: load_v4i8_to_v4f32_2_uses: ; VI-LABEL: load_v4i8_to_v4f32_2_uses:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x2c
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; VI-NEXT: s_mov_b32 s11, 0xf000 ; VI-NEXT: v_mov_b32_e32 v5, 9
; VI-NEXT: s_mov_b32 s10, -1 ; VI-NEXT: s_movk_i32 s8, 0x900
; VI-NEXT: s_mov_b32 s6, s10
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_mov_b32_e32 v1, s1 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v5, v[0:1] ; VI-NEXT: flat_load_dword v4, v[0:1]
; VI-NEXT: v_mov_b32_e32 v4, 9 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; VI-NEXT: s_mov_b32 s7, s11 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
; VI-NEXT: s_movk_i32 s0, 0x900 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_mov_b32 s6, s2
; VI-NEXT: s_mov_b32 s7, s3
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v6, 24, v5 ; VI-NEXT: v_lshrrev_b32_e32 v6, 24, v4
; VI-NEXT: v_cvt_f32_ubyte3_e32 v3, v5 ; VI-NEXT: v_cvt_f32_ubyte3_e32 v3, v4
; VI-NEXT: v_cvt_f32_ubyte2_e32 v2, v5 ; VI-NEXT: v_cvt_f32_ubyte2_e32 v2, v4
; VI-NEXT: v_cvt_f32_ubyte1_e32 v1, v5 ; VI-NEXT: v_cvt_f32_ubyte1_e32 v1, v4
; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v5 ; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v4
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; VI-NEXT: v_and_b32_e32 v7, 0xffffff00, v5 ; VI-NEXT: v_and_b32_e32 v7, 0xffffff00, v4
; VI-NEXT: v_add_u16_e32 v8, 9, v5 ; VI-NEXT: v_add_u16_e32 v8, 9, v4
; VI-NEXT: v_add_u16_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; VI-NEXT: v_add_u16_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v6 ; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v6
; VI-NEXT: v_or_b32_sdwa v0, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; VI-NEXT: v_or_b32_sdwa v0, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; VI-NEXT: v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; VI-NEXT: v_mov_b32_e32 v2, s0 ; VI-NEXT: v_mov_b32_e32 v2, s8
; VI-NEXT: v_add_u16_e32 v0, s0, v0 ; VI-NEXT: v_add_u16_e32 v0, s8, v0
; VI-NEXT: v_add_u16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI-NEXT: v_add_u16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v0, v1 ; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%tid.x = call i32 @llvm.amdgcn.workitem.id.x() %tid.x = call i32 @llvm.amdgcn.workitem.id.x()
%in.ptr = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid.x %in.ptr = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid.x
%load = load <4 x i8>, <4 x i8> addrspace(1)* %in.ptr, align 4 %load = load <4 x i8>, <4 x i8> addrspace(1)* %in.ptr, align 4
%cvt = uitofp <4 x i8> %load to <4 x float> %cvt = uitofp <4 x i8> %load to <4 x float>
store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16 store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16
%add = add <4 x i8> %load, <i8 9, i8 9, i8 9, i8 9> ; Second use of %load %add = add <4 x i8> %load, <i8 9, i8 9, i8 9, i8 9> ; Second use of %load
store <4 x i8> %add, <4 x i8> addrspace(1)* %out2, align 4 store <4 x i8> %add, <4 x i8> addrspace(1)* %out2, align 4
ret void ret void
} }
; Make sure this doesn't crash. ; Make sure this doesn't crash.
define amdgpu_kernel void @load_v7i8_to_v7f32(<7 x float> addrspace(1)* noalias %out, <7 x i8> addrspace(1)* noalias %in) nounwind { define amdgpu_kernel void @load_v7i8_to_v7f32(<7 x float> addrspace(1)* noalias %out, <7 x i8> addrspace(1)* noalias %in) nounwind {
; SI-LABEL: load_v7i8_to_v7f32: ; SI-LABEL: load_v7i8_to_v7f32:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
; SI-NEXT: s_mov_b32 s7, 0xf000 ; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s2, 0 ; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s3, s7 ; SI-NEXT: s_mov_b32 s3, s7
; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; SI-NEXT: v_mov_b32_e32 v1, 0 ; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_load_ubyte v2, v[0:1], s[0:3], 0 addr64 offset:5 ; SI-NEXT: buffer_load_ubyte v2, v[0:1], s[0:3], 0 addr64
; SI-NEXT: buffer_load_ubyte v3, v[0:1], s[0:3], 0 addr64 offset:6 ; SI-NEXT: buffer_load_ubyte v3, v[0:1], s[0:3], 0 addr64 offset:1
; SI-NEXT: buffer_load_ubyte v4, v[0:1], s[0:3], 0 addr64
; SI-NEXT: buffer_load_ubyte v5, v[0:1], s[0:3], 0 addr64 offset:1
; SI-NEXT: buffer_load_ubyte v6, v[0:1], s[0:3], 0 addr64 offset:2 ; SI-NEXT: buffer_load_ubyte v6, v[0:1], s[0:3], 0 addr64 offset:2
; SI-NEXT: buffer_load_ubyte v7, v[0:1], s[0:3], 0 addr64 offset:3 ; SI-NEXT: buffer_load_ubyte v4, v[0:1], s[0:3], 0 addr64 offset:3
; SI-NEXT: buffer_load_ubyte v8, v[0:1], s[0:3], 0 addr64 offset:4 ; SI-NEXT: buffer_load_ubyte v7, v[0:1], s[0:3], 0 addr64 offset:4
; SI-NEXT: buffer_load_ubyte v5, v[0:1], s[0:3], 0 addr64 offset:5
; SI-NEXT: buffer_load_ubyte v8, v[0:1], s[0:3], 0 addr64 offset:6
; SI-NEXT: s_mov_b32 s6, -1 ; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt vmcnt(4) ; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v4 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v2
; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_cvt_f32_ubyte2_e32 v1, v3
; SI-NEXT: s_waitcnt vmcnt(3) ; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_cvt_f32_ubyte2_e32 v1, v5 ; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v4
; SI-NEXT: v_cvt_f32_ubyte2_e32 v5, v2 ; SI-NEXT: v_or_b32_e32 v2, v9, v6
; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v7 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v4, v7
; SI-NEXT: v_or_b32_e32 v2, v7, v6
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_ubyte0_e32 v4, v8
; SI-NEXT: v_cvt_f32_ubyte0_e32 v8, v3
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_ubyte0_e32 v7, v8
; SI-NEXT: v_cvt_f32_ubyte3_e32 v3, v2 ; SI-NEXT: v_cvt_f32_ubyte3_e32 v3, v2
; SI-NEXT: v_cvt_f32_ubyte2_e32 v5, v5
; SI-NEXT: v_cvt_f32_ubyte2_e32 v2, v2 ; SI-NEXT: v_cvt_f32_ubyte2_e32 v2, v2
; SI-NEXT: buffer_store_dword v8, off, s[4:7], 0 offset:24 ; SI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:24
; SI-NEXT: buffer_store_dwordx2 v[4:5], off, s[4:7], 0 offset:16 ; SI-NEXT: buffer_store_dwordx2 v[4:5], off, s[4:7], 0 offset:16
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: load_v7i8_to_v7f32: ; VI-LABEL: load_v7i8_to_v7f32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
▲ Show 20 Lines • Show All 538 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/fcmp.f16.ll

Show First 20 Lines • Show All 603 Lines • ▼ Show 20 Lines
; GCN-DAG: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]] ; GCN-DAG: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
; SI-DAG: v_cvt_f32_f16_e32 v[[B_F32_0:[0-9]+]], v[[B_V2_F16]] ; SI-DAG: v_cvt_f32_f16_e32 v[[B_F32_0:[0-9]+]], v[[B_V2_F16]]
; SI-DAG: v_cmp_nlt_f32_e32 vcc, v[[A_F32_0]], v[[B_F32_0]] ; SI-DAG: v_cmp_nlt_f32_e32 vcc, v[[A_F32_0]], v[[B_F32_0]]
; GCN-DAG: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]] ; GCN-DAG: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]]
; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]] ; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]]
; SI-DAG: v_cvt_f32_f16_e32 v[[B_F32_1:[0-9]+]], v[[B_F16_1]] ; SI-DAG: v_cvt_f32_f16_e32 v[[B_F32_1:[0-9]+]], v[[B_F16_1]]
; SI-DAG: v_cmp_nlt_f32_e32 vcc, v[[A_F32_1]], v[[B_F32_1]] ; SI-DAG: v_cmp_nlt_f32_e32 vcc, v[[A_F32_1]], v[[B_F32_1]]
; VI-DAG: v_cmp_nlt_f16_e32 vcc, v[[A_V2_F16]], v[[B_V2_F16]] ; VI-DAG: v_cmp_nlt_f16_e32 vcc, v[[B_V2_F16]], v[[A_V2_F16]]
; GCN: v_cndmask_b32_e64 v[[R_I32_0:[0-9]+]] ; GCN: v_cndmask_b32_e64 v[[R_I32_0:[0-9]+]]
; VI: v_cmp_nlt_f16_e32 vcc, v[[A_F16_1]], v[[B_F16_1]] ; VI: v_cmp_nlt_f16_e32 vcc, v[[B_F16_1]], v[[A_F16_1]]
; GCN: v_cndmask_b32_e64 v[[R_I32_1:[0-9]+]] ; GCN: v_cndmask_b32_e64 v[[R_I32_1:[0-9]+]]
; GCN: buffer_store_dwordx2 v{{\[}}[[R_I32_0]]:[[R_I32_1]]{{\]}} ; GCN: buffer_store_dwordx2 v{{\[}}[[R_I32_0]]:[[R_I32_1]]{{\]}}
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @fcmp_v2f16_nlt( define amdgpu_kernel void @fcmp_v2f16_nlt(
<2 x i32> addrspace(1)* %r, <2 x i32> addrspace(1)* %r,
<2 x half> addrspace(1)* %a, <2 x half> addrspace(1)* %a,
<2 x half> addrspace(1)* %b) { <2 x half> addrspace(1)* %b) {
entry: entry:
Show All 12 Lines

llvm/test/CodeGen/AMDGPU/fneg-combines.ll

Show First 20 Lines • Show All 185 Lines • ▼ Show 20 Lines
} }
; GCN-LABEL: {{^}}v_fneg_add_multi_use_fneg_x_f32: ; GCN-LABEL: {{^}}v_fneg_add_multi_use_fneg_x_f32:
; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
; GCN-SAFE-DAG: v_mul_f32_e64 [[MUL:v[0-9]+]], -[[A]], s{{[0-9]+}} ; GCN-SAFE-DAG: v_mul_f32_e64 [[MUL:v[0-9]+]], -[[A]], s{{[0-9]+}}
; GCN-SAFE-DAG: v_sub_f32_e32 [[ADD:v[0-9]+]], [[B]], [[A]] ; GCN-SAFE-DAG: v_sub_f32_e32 [[ADD:v[0-9]+]], [[B]], [[A]]
; GCN-SAFE: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, [[ADD]] ; GCN-SAFE-DAG: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, [[ADD]]
; GCN-NSZ-DAG: v_sub_f32_e32 [[NEG_ADD:v[0-9]+]], [[A]], [[B]] ; GCN-NSZ-DAG: v_sub_f32_e32 [[NEG_ADD:v[0-9]+]], [[A]], [[B]]
; GCN-NSZ-DAG: v_mul_f32_e64 [[MUL:v[0-9]+]], -[[A]], s{{[0-9]+}} ; GCN-NSZ-DAG: v_mul_f32_e64 [[MUL:v[0-9]+]], -[[A]], s{{[0-9]+}}
; GCN-NSZ-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[NEG_ADD]] ; GCN-NSZ-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[NEG_ADD]]
; GCN-NSZ-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL]] ; GCN-NSZ-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL]]
define amdgpu_kernel void @v_fneg_add_multi_use_fneg_x_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float %c) #0 { define amdgpu_kernel void @v_fneg_add_multi_use_fneg_x_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float %c) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
▲ Show 20 Lines • Show All 1,135 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @v_fneg_fma_store_use_fneg_x_y_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float addrspace(1)* %c.ptr) #0 {
ret void ret void
} }
; GCN-LABEL: {{^}}v_fneg_fma_multi_use_fneg_x_y_f32: ; GCN-LABEL: {{^}}v_fneg_fma_multi_use_fneg_x_y_f32:
; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[C:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[C:v[0-9]+]]
; GCN: v_mul_f32_e64 [[MUL:v[0-9]+]], -[[A]], s{{[0-9]+}} ; GCN-DAG: v_mul_f32_e64 [[MUL:v[0-9]+]], -[[A]], s{{[0-9]+}}
; GCN-SAFE: v_fma_f32 [[FMA:v[0-9]+]] ; GCN-SAFE-DAG: v_fma_f32 [[FMA:v[0-9]+]]
; GCN-SAFE: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, [[FMA]] ; GCN-SAFE-DAG: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, [[FMA]]
; GCN-NSZ-DAG: v_fma_f32 [[NEG_FMA:v[0-9]+]], [[A]], [[B]], -[[C]] ; GCN-NSZ-DAG: v_fma_f32 [[NEG_FMA:v[0-9]+]], [[A]], [[B]], -[[C]]
; GCN-NSZ-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[NEG_FMA]] ; GCN-NSZ-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[NEG_FMA]]
; GCN-NSZ-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL]] ; GCN-NSZ-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL]]
define amdgpu_kernel void @v_fneg_fma_multi_use_fneg_x_y_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float addrspace(1)* %c.ptr, float %d) #0 { define amdgpu_kernel void @v_fneg_fma_multi_use_fneg_x_y_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float addrspace(1)* %c.ptr, float %d) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
▲ Show 20 Lines • Show All 1,211 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/idiv-licm.ll

Show First 20 Lines • Show All 283 Lines • ▼ Show 20 Linesbb3: ; preds = %bb3, %bb
%tmp7 = add nuw nsw i16 %tmp, 1 %tmp7 = add nuw nsw i16 %tmp, 1
%tmp8 = icmp eq i16 %tmp7, 1024 %tmp8 = icmp eq i16 %tmp7, 1024
br i1 %tmp8, label %bb2, label %bb3 br i1 %tmp8, label %bb2, label %bb3
} }
define amdgpu_kernel void @urem16_invariant_denom(i16 addrspace(1)* nocapture %arg, i16 %arg1) { define amdgpu_kernel void @urem16_invariant_denom(i16 addrspace(1)* nocapture %arg, i16 %arg1) {
; GFX9-LABEL: urem16_invariant_denom: ; GFX9-LABEL: urem16_invariant_denom:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_load_dword s3, s[0:1], 0x2c ; GFX9-NEXT: s_load_dword s2, s[0:1], 0x2c
; GFX9-NEXT: s_mov_b32 s2, 0xffff ; GFX9-NEXT: s_mov_b32 s4, 0xffff
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x24
; GFX9-NEXT: v_mov_b32_e32 v3, 0 ; GFX9-NEXT: v_mov_b32_e32 v3, 0
; GFX9-NEXT: s_movk_i32 s6, 0x400 ; GFX9-NEXT: s_movk_i32 s8, 0x400
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_and_b32 s3, s2, s3 ; GFX9-NEXT: s_and_b32 s5, s4, s2
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s3 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s5
; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v0
; GFX9-NEXT: BB5_1: ; %bb3 ; GFX9-NEXT: BB5_1: ; %bb3
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_and_b32_e32 v2, s2, v4 ; GFX9-NEXT: v_and_b32_e32 v2, s4, v4
; GFX9-NEXT: v_cvt_f32_u32_e32 v8, v2 ; GFX9-NEXT: v_cvt_f32_u32_e32 v8, v2
; GFX9-NEXT: v_lshlrev_b64 v[5:6], 1, v[2:3] ; GFX9-NEXT: v_lshlrev_b64 v[5:6], 1, v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v7, s5
; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], s4, v5
; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1]
; GFX9-NEXT: v_mul_f32_e32 v7, v8, v1
; GFX9-NEXT: v_trunc_f32_e32 v7, v7
; GFX9-NEXT: v_cvt_u32_f32_e32 v9, v7
; GFX9-NEXT: v_mad_f32 v7, -v7, v0, v8
; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v7|, v0
; GFX9-NEXT: v_add_u16_e32 v4, 1, v4 ; GFX9-NEXT: v_add_u16_e32 v4, 1, v4
; GFX9-NEXT: v_addc_co_u32_e64 v7, s[0:1], 0, v9, s[0:1] ; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, s8, v4
; GFX9-NEXT: v_mul_lo_u32 v7, v7, s3 ; GFX9-NEXT: v_mul_f32_e32 v9, v8, v1
; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, s6, v4 ; GFX9-NEXT: v_trunc_f32_e32 v9, v9
; GFX9-NEXT: v_cvt_u32_f32_e32 v10, v9
; GFX9-NEXT: v_mad_f32 v8, -v9, v0, v8
; GFX9-NEXT: v_cmp_ge_f32_e64 s[2:3], |v8|, v0
; GFX9-NEXT: v_mov_b32_e32 v7, s7
; GFX9-NEXT: v_addc_co_u32_e64 v8, s[2:3], 0, v10, s[2:3]
; GFX9-NEXT: v_mul_lo_u32 v8, v8, s5
; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], s6, v5
; GFX9-NEXT: s_and_b64 vcc, exec, vcc ; GFX9-NEXT: s_and_b64 vcc, exec, vcc
; GFX9-NEXT: v_sub_u32_e32 v2, v2, v7 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1]
; GFX9-NEXT: v_sub_u32_e32 v2, v2, v8
; GFX9-NEXT: global_store_short v[5:6], v2, off ; GFX9-NEXT: global_store_short v[5:6], v2, off
; GFX9-NEXT: s_cbranch_vccz BB5_1 ; GFX9-NEXT: s_cbranch_vccz BB5_1
; GFX9-NEXT: ; %bb.2: ; %bb2 ; GFX9-NEXT: ; %bb.2: ; %bb2
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
bb: bb:
br label %bb3 br label %bb3
bb2: ; preds = %bb3 bb2: ; preds = %bb3
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Linesbb3: ; preds = %bb3, %bb
%tmp8 = icmp eq i16 %tmp7, 1024 %tmp8 = icmp eq i16 %tmp7, 1024
br i1 %tmp8, label %bb2, label %bb3 br i1 %tmp8, label %bb2, label %bb3
} }
define amdgpu_kernel void @srem16_invariant_denom(i16 addrspace(1)* nocapture %arg, i16 %arg1) { define amdgpu_kernel void @srem16_invariant_denom(i16 addrspace(1)* nocapture %arg, i16 %arg1) {
; GFX9-LABEL: srem16_invariant_denom: ; GFX9-LABEL: srem16_invariant_denom:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_load_dword s2, s[0:1], 0x2c ; GFX9-NEXT: s_load_dword s2, s[0:1], 0x2c
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x24
; GFX9-NEXT: v_mov_b32_e32 v3, 0 ; GFX9-NEXT: v_mov_b32_e32 v3, 0
; GFX9-NEXT: s_movk_i32 s3, 0x400 ; GFX9-NEXT: s_movk_i32 s5, 0x400
; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_sext_i32_i16 s2, s2 ; GFX9-NEXT: s_sext_i32_i16 s4, s2
; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s2 ; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s4
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v0
; GFX9-NEXT: BB7_1: ; %bb3 ; GFX9-NEXT: BB7_1: ; %bb3
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_bfe_i32 v7, v4, 0, 16 ; GFX9-NEXT: v_bfe_i32 v7, v4, 0, 16
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v4
; GFX9-NEXT: v_cvt_f32_i32_e32 v10, v7 ; GFX9-NEXT: v_cvt_f32_i32_e32 v10, v7
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v4
; GFX9-NEXT: v_xor_b32_e32 v9, s4, v7
; GFX9-NEXT: v_lshlrev_b64 v[5:6], 1, v[2:3] ; GFX9-NEXT: v_lshlrev_b64 v[5:6], 1, v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v8, s5
; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], s4, v5
; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v8, v6, s[0:1]
; GFX9-NEXT: v_mul_f32_e32 v8, v10, v1
; GFX9-NEXT: v_xor_b32_e32 v9, s2, v7
; GFX9-NEXT: v_trunc_f32_e32 v8, v8
; GFX9-NEXT: v_ashrrev_i32_e32 v2, 30, v9 ; GFX9-NEXT: v_ashrrev_i32_e32 v2, 30, v9
; GFX9-NEXT: v_cvt_i32_f32_e32 v9, v8 ; GFX9-NEXT: v_mul_f32_e32 v9, v10, v1
; GFX9-NEXT: v_mad_f32 v8, -v8, v0, v10 ; GFX9-NEXT: v_trunc_f32_e32 v9, v9
; GFX9-NEXT: v_cvt_i32_f32_e32 v11, v9
; GFX9-NEXT: v_mad_f32 v9, -v9, v0, v10
; GFX9-NEXT: v_or_b32_e32 v2, 1, v2 ; GFX9-NEXT: v_or_b32_e32 v2, 1, v2
; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v8|, |v0| ; GFX9-NEXT: v_cmp_ge_f32_e64 s[2:3], |v9|, |v0|
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[2:3]
; GFX9-NEXT: v_add_u32_e32 v2, v9, v2 ; GFX9-NEXT: v_add_u32_e32 v2, v11, v2
; GFX9-NEXT: v_mul_lo_u32 v2, v2, s2 ; GFX9-NEXT: v_mul_lo_u32 v2, v2, s4
; GFX9-NEXT: v_add_u16_e32 v4, 1, v4 ; GFX9-NEXT: v_add_u16_e32 v4, 1, v4
; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, s3, v4 ; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, s5, v4
; GFX9-NEXT: v_mov_b32_e32 v8, s7
; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], s6, v5
; GFX9-NEXT: s_and_b64 vcc, exec, vcc ; GFX9-NEXT: s_and_b64 vcc, exec, vcc
; GFX9-NEXT: v_sub_u32_e32 v2, v7, v2 ; GFX9-NEXT: v_sub_u32_e32 v2, v7, v2
; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v8, v6, s[0:1]
; GFX9-NEXT: global_store_short v[5:6], v2, off ; GFX9-NEXT: global_store_short v[5:6], v2, off
; GFX9-NEXT: s_cbranch_vccz BB7_1 ; GFX9-NEXT: s_cbranch_vccz BB7_1
; GFX9-NEXT: ; %bb.2: ; %bb2 ; GFX9-NEXT: ; %bb.2: ; %bb2
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
bb: bb:
br label %bb3 br label %bb3
bb2: ; preds = %bb3 bb2: ; preds = %bb3
Show All 12 Lines

llvm/test/CodeGen/AMDGPU/idot2.ll

Show First 20 Lines • Show All 2,585 Lines • ▼ Show 20 Lines
; GFX7-NEXT: buffer_store_short v0, off, s[0:3], 0 ; GFX7-NEXT: buffer_store_short v0, off, s[0:3], 0
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX8-LABEL: udot2_acc16: ; GFX8-LABEL: udot2_acc16:
; GFX8: ; %bb.0: ; %entry ; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_load_ushort v2, v[0:1] ; GFX8-NEXT: flat_load_ushort v2, v[0:1]
; GFX8-NEXT: s_load_dword s1, s[6:7], 0x0 ; GFX8-NEXT: s_load_dword s1, s[4:5], 0x0
; GFX8-NEXT: s_load_dword s2, s[6:7], 0x0
; GFX8-NEXT: s_mov_b32 s0, 0xffff ; GFX8-NEXT: s_mov_b32 s0, 0xffff
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_and_b32 s3, s1, s0 ; GFX8-NEXT: s_and_b32 s3, s2, s0
; GFX8-NEXT: s_lshr_b32 s1, s1, 16
; GFX8-NEXT: s_and_b32 s0, s2, s0
; GFX8-NEXT: s_lshr_b32 s2, s2, 16 ; GFX8-NEXT: s_lshr_b32 s2, s2, 16
; GFX8-NEXT: v_mov_b32_e32 v3, s1 ; GFX8-NEXT: s_and_b32 s0, s1, s0
; GFX8-NEXT: s_lshr_b32 s1, s1, 16
; GFX8-NEXT: v_mov_b32_e32 v3, s2
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mad_u32_u24 v2, s2, v3, v2 ; GFX8-NEXT: v_mad_u32_u24 v2, s1, v3, v2
; GFX8-NEXT: v_mov_b32_e32 v3, s3 ; GFX8-NEXT: v_mov_b32_e32 v3, s3
; GFX8-NEXT: v_mad_u32_u24 v2, s0, v3, v2 ; GFX8-NEXT: v_mad_u32_u24 v2, s0, v3, v2
; GFX8-NEXT: flat_store_short v[0:1], v2 ; GFX8-NEXT: flat_store_short v[0:1], v2
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-NODL-LABEL: udot2_acc16: ; GFX9-NODL-LABEL: udot2_acc16:
; GFX9-NODL: ; %bb.0: ; %entry ; GFX9-NODL: ; %bb.0: ; %entry
; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NODL-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NODL-NEXT: global_load_ushort v2, v[0:1], off ; GFX9-NODL-NEXT: global_load_ushort v2, v[0:1], off
; GFX9-NODL-NEXT: s_load_dword s1, s[6:7], 0x0 ; GFX9-NODL-NEXT: s_load_dword s1, s[4:5], 0x0
; GFX9-NODL-NEXT: s_load_dword s2, s[6:7], 0x0
; GFX9-NODL-NEXT: s_mov_b32 s0, 0xffff ; GFX9-NODL-NEXT: s_mov_b32 s0, 0xffff
; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NODL-NEXT: s_and_b32 s3, s1, s0 ; GFX9-NODL-NEXT: s_and_b32 s3, s2, s0
; GFX9-NODL-NEXT: s_lshr_b32 s1, s1, 16
; GFX9-NODL-NEXT: s_and_b32 s0, s2, s0
; GFX9-NODL-NEXT: s_lshr_b32 s2, s2, 16 ; GFX9-NODL-NEXT: s_lshr_b32 s2, s2, 16
; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s1 ; GFX9-NODL-NEXT: s_and_b32 s0, s1, s0
; GFX9-NODL-NEXT: s_lshr_b32 s1, s1, 16
; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s2
; GFX9-NODL-NEXT: s_waitcnt vmcnt(0) ; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s2, v3, v2 ; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s1, v3, v2
; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s3 ; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s3
; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s0, v3, v2 ; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s0, v3, v2
; GFX9-NODL-NEXT: global_store_short v[0:1], v2, off ; GFX9-NODL-NEXT: global_store_short v[0:1], v2, off
; GFX9-NODL-NEXT: s_endpgm ; GFX9-NODL-NEXT: s_endpgm
; ;
; GFX9-DL-LABEL: udot2_acc16: ; GFX9-DL-LABEL: udot2_acc16:
; GFX9-DL: ; %bb.0: ; %entry ; GFX9-DL: ; %bb.0: ; %entry
; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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; GFX8: ; %bb.0: ; %entry ; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s4 ; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5 ; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: v_mov_b32_e32 v2, s6 ; GFX8-NEXT: v_mov_b32_e32 v2, s6
; GFX8-NEXT: v_mov_b32_e32 v3, s7 ; GFX8-NEXT: v_mov_b32_e32 v3, s7
; GFX8-NEXT: flat_load_ushort v2, v[2:3]
; GFX8-NEXT: flat_load_ushort v0, v[0:1] ; GFX8-NEXT: flat_load_ushort v0, v[0:1]
; GFX8-NEXT: flat_load_ushort v1, v[2:3]
; GFX8-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX8-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX8-NEXT: s_waitcnt vmcnt(1) lgkmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(1) lgkmcnt(0)
; GFX8-NEXT: v_bfe_i32 v3, v2, 0, 8 ; GFX8-NEXT: v_bfe_i32 v2, v0, 0, 8
; GFX8-NEXT: v_lshrrev_b16_e32 v2, 8, v2
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_bfe_i32 v1, v0, 0, 8
; GFX8-NEXT: v_lshrrev_b16_e32 v0, 8, v0 ; GFX8-NEXT: v_lshrrev_b16_e32 v0, 8, v0
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_bfe_i32 v3, v1, 0, 8
; GFX8-NEXT: v_lshrrev_b16_e32 v1, 8, v1
; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 8 ; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX8-NEXT: v_bfe_i32 v2, v2, 0, 8 ; GFX8-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX8-NEXT: v_mad_i32_i24 v0, v2, v0, s2 ; GFX8-NEXT: v_mad_i32_i24 v0, v1, v0, s2
; GFX8-NEXT: v_mad_i32_i24 v2, v3, v1, v0 ; GFX8-NEXT: v_mad_i32_i24 v2, v3, v2, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_store_dword v[0:1], v2 ; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-NODL-LABEL: notsdot2_sext8: ; GFX9-NODL-LABEL: notsdot2_sext8:
; GFX9-NODL: ; %bb.0: ; %entry ; GFX9-NODL: ; %bb.0: ; %entry
; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s5 ; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NODL-NEXT: v_mov_b32_e32 v2, s6 ; GFX9-NODL-NEXT: v_mov_b32_e32 v2, s6
; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s7 ; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s7
; GFX9-NODL-NEXT: global_load_ushort v2, v[2:3], off
; GFX9-NODL-NEXT: global_load_ushort v0, v[0:1], off ; GFX9-NODL-NEXT: global_load_ushort v0, v[0:1], off
; GFX9-NODL-NEXT: global_load_ushort v1, v[2:3], off
; GFX9-NODL-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX9-NODL-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX9-NODL-NEXT: s_waitcnt vmcnt(1) ; GFX9-NODL-NEXT: s_waitcnt vmcnt(1)
; GFX9-NODL-NEXT: v_bfe_i32 v3, v2, 0, 8 ; GFX9-NODL-NEXT: v_bfe_i32 v2, v0, 0, 8
; GFX9-NODL-NEXT: v_lshrrev_b16_e32 v2, 8, v2
; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
; GFX9-NODL-NEXT: v_bfe_i32 v1, v0, 0, 8
; GFX9-NODL-NEXT: v_lshrrev_b16_e32 v0, 8, v0 ; GFX9-NODL-NEXT: v_lshrrev_b16_e32 v0, 8, v0
; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
; GFX9-NODL-NEXT: v_bfe_i32 v3, v1, 0, 8
; GFX9-NODL-NEXT: v_lshrrev_b16_e32 v1, 8, v1
; GFX9-NODL-NEXT: v_bfe_i32 v0, v0, 0, 8 ; GFX9-NODL-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX9-NODL-NEXT: v_bfe_i32 v2, v2, 0, 8 ; GFX9-NODL-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NODL-NEXT: v_mad_i32_i24 v0, v2, v0, s2 ; GFX9-NODL-NEXT: v_mad_i32_i24 v0, v1, v0, s2
; GFX9-NODL-NEXT: v_mad_i32_i24 v2, v3, v1, v0 ; GFX9-NODL-NEXT: v_mad_i32_i24 v2, v3, v2, v0
; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NODL-NEXT: global_store_dword v[0:1], v2, off ; GFX9-NODL-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NODL-NEXT: s_endpgm ; GFX9-NODL-NEXT: s_endpgm
; ;
; GFX9-DL-LABEL: notsdot2_sext8: ; GFX9-DL-LABEL: notsdot2_sext8:
; GFX9-DL: ; %bb.0: ; %entry ; GFX9-DL: ; %bb.0: ; %entry
; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DL-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-DL-NEXT: v_mov_b32_e32 v0, s4
; GFX9-DL-NEXT: v_mov_b32_e32 v1, s5 ; GFX9-DL-NEXT: v_mov_b32_e32 v1, s5
; GFX9-DL-NEXT: v_mov_b32_e32 v2, s6 ; GFX9-DL-NEXT: v_mov_b32_e32 v2, s6
; GFX9-DL-NEXT: v_mov_b32_e32 v3, s7 ; GFX9-DL-NEXT: v_mov_b32_e32 v3, s7
; GFX9-DL-NEXT: global_load_ushort v2, v[2:3], off
; GFX9-DL-NEXT: global_load_ushort v0, v[0:1], off ; GFX9-DL-NEXT: global_load_ushort v0, v[0:1], off
; GFX9-DL-NEXT: global_load_ushort v1, v[2:3], off
; GFX9-DL-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX9-DL-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX9-DL-NEXT: s_waitcnt vmcnt(1) ; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
; GFX9-DL-NEXT: v_bfe_i32 v3, v2, 0, 8 ; GFX9-DL-NEXT: v_bfe_i32 v2, v0, 0, 8
; GFX9-DL-NEXT: v_lshrrev_b16_e32 v2, 8, v2
; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
; GFX9-DL-NEXT: v_bfe_i32 v1, v0, 0, 8
; GFX9-DL-NEXT: v_lshrrev_b16_e32 v0, 8, v0 ; GFX9-DL-NEXT: v_lshrrev_b16_e32 v0, 8, v0
; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
; GFX9-DL-NEXT: v_bfe_i32 v3, v1, 0, 8
; GFX9-DL-NEXT: v_lshrrev_b16_e32 v1, 8, v1
; GFX9-DL-NEXT: v_bfe_i32 v0, v0, 0, 8 ; GFX9-DL-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX9-DL-NEXT: v_bfe_i32 v2, v2, 0, 8 ; GFX9-DL-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DL-NEXT: v_mad_i32_i24 v0, v2, v0, s2 ; GFX9-DL-NEXT: v_mad_i32_i24 v0, v1, v0, s2
; GFX9-DL-NEXT: v_mad_i32_i24 v2, v3, v1, v0 ; GFX9-DL-NEXT: v_mad_i32_i24 v2, v3, v2, v0
; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX9-DL-NEXT: s_endpgm ; GFX9-DL-NEXT: s_endpgm
; ;
; GFX10-DL-LABEL: notsdot2_sext8: ; GFX10-DL-LABEL: notsdot2_sext8:
; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_clause 0x1 ; GFX10-DL-NEXT: s_clause 0x1
▲ Show 20 Lines • Show All 50 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/idot4s.ll

Show First 20 Lines • Show All 215 Lines • ▼ Show 20 Lines
; GFX7-NEXT: buffer_store_short v0, off, s[0:3], 0 ; GFX7-NEXT: buffer_store_short v0, off, s[0:3], 0
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX8-LABEL: idot4_acc16: ; GFX8-LABEL: idot4_acc16:
; GFX8: ; %bb.0: ; %entry ; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_load_dword s2, s[6:7], 0x0
; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_load_ushort v2, v[0:1] ; GFX8-NEXT: flat_load_ushort v2, v[0:1]
; GFX8-NEXT: s_load_dword s0, s[4:5], 0x0 ; GFX8-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX8-NEXT: s_load_dword s1, s[6:7], 0x0
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_sext_i32_i8 s3, s2 ; GFX8-NEXT: s_sext_i32_i8 s2, s0
; GFX8-NEXT: s_bfe_i32 s5, s2, 0x80008 ; GFX8-NEXT: s_sext_i32_i8 s3, s1
; GFX8-NEXT: s_bfe_i32 s5, s1, 0x80008
; GFX8-NEXT: v_mov_b32_e32 v3, s3 ; GFX8-NEXT: v_mov_b32_e32 v3, s3
; GFX8-NEXT: s_bfe_i32 s7, s2, 0x80010 ; GFX8-NEXT: s_bfe_i32 s7, s1, 0x80010
; GFX8-NEXT: s_sext_i32_i8 s1, s0
; GFX8-NEXT: s_bfe_i32 s4, s0, 0x80008 ; GFX8-NEXT: s_bfe_i32 s4, s0, 0x80008
; GFX8-NEXT: v_mov_b32_e32 v4, s5 ; GFX8-NEXT: v_mov_b32_e32 v4, s5
; GFX8-NEXT: s_bfe_i32 s6, s0, 0x80010 ; GFX8-NEXT: s_bfe_i32 s6, s0, 0x80010
; GFX8-NEXT: s_ashr_i32 s2, s2, 24 ; GFX8-NEXT: s_ashr_i32 s1, s1, 24
; GFX8-NEXT: v_mov_b32_e32 v5, s7 ; GFX8-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NEXT: s_ashr_i32 s0, s0, 24 ; GFX8-NEXT: s_ashr_i32 s0, s0, 24
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mad_i32_i24 v2, s1, v3, v2 ; GFX8-NEXT: v_mad_i32_i24 v2, s2, v3, v2
; GFX8-NEXT: v_mad_i32_i24 v2, s4, v4, v2 ; GFX8-NEXT: v_mad_i32_i24 v2, s4, v4, v2
; GFX8-NEXT: v_mad_i32_i24 v2, s6, v5, v2 ; GFX8-NEXT: v_mad_i32_i24 v2, s6, v5, v2
; GFX8-NEXT: v_mov_b32_e32 v3, s2 ; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mad_i32_i24 v2, s0, v3, v2 ; GFX8-NEXT: v_mad_i32_i24 v2, s0, v3, v2
; GFX8-NEXT: flat_store_short v[0:1], v2 ; GFX8-NEXT: flat_store_short v[0:1], v2
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-NODL-LABEL: idot4_acc16: ; GFX9-NODL-LABEL: idot4_acc16:
; GFX9-NODL: ; %bb.0: ; %entry ; GFX9-NODL: ; %bb.0: ; %entry
; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NODL-NEXT: s_load_dword s2, s[6:7], 0x0
; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NODL-NEXT: global_load_ushort v2, v[0:1], off ; GFX9-NODL-NEXT: global_load_ushort v2, v[0:1], off
; GFX9-NODL-NEXT: s_load_dword s0, s[4:5], 0x0 ; GFX9-NODL-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX9-NODL-NEXT: s_load_dword s1, s[6:7], 0x0
; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NODL-NEXT: s_sext_i32_i8 s3, s2 ; GFX9-NODL-NEXT: s_sext_i32_i8 s2, s0
; GFX9-NODL-NEXT: s_bfe_i32 s5, s2, 0x80008 ; GFX9-NODL-NEXT: s_sext_i32_i8 s3, s1
; GFX9-NODL-NEXT: s_bfe_i32 s5, s1, 0x80008
; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s3 ; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s3
; GFX9-NODL-NEXT: s_bfe_i32 s7, s2, 0x80010 ; GFX9-NODL-NEXT: s_bfe_i32 s7, s1, 0x80010
; GFX9-NODL-NEXT: s_sext_i32_i8 s1, s0
; GFX9-NODL-NEXT: s_bfe_i32 s4, s0, 0x80008 ; GFX9-NODL-NEXT: s_bfe_i32 s4, s0, 0x80008
; GFX9-NODL-NEXT: v_mov_b32_e32 v4, s5 ; GFX9-NODL-NEXT: v_mov_b32_e32 v4, s5
; GFX9-NODL-NEXT: s_bfe_i32 s6, s0, 0x80010 ; GFX9-NODL-NEXT: s_bfe_i32 s6, s0, 0x80010
; GFX9-NODL-NEXT: s_ashr_i32 s2, s2, 24 ; GFX9-NODL-NEXT: s_ashr_i32 s1, s1, 24
; GFX9-NODL-NEXT: v_mov_b32_e32 v5, s7 ; GFX9-NODL-NEXT: v_mov_b32_e32 v5, s7
; GFX9-NODL-NEXT: s_ashr_i32 s0, s0, 24 ; GFX9-NODL-NEXT: s_ashr_i32 s0, s0, 24
; GFX9-NODL-NEXT: s_waitcnt vmcnt(0) ; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
; GFX9-NODL-NEXT: v_mad_i32_i24 v2, s1, v3, v2 ; GFX9-NODL-NEXT: v_mad_i32_i24 v2, s2, v3, v2
; GFX9-NODL-NEXT: v_mad_i32_i24 v2, s4, v4, v2 ; GFX9-NODL-NEXT: v_mad_i32_i24 v2, s4, v4, v2
; GFX9-NODL-NEXT: v_mad_i32_i24 v2, s6, v5, v2 ; GFX9-NODL-NEXT: v_mad_i32_i24 v2, s6, v5, v2
; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s2 ; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NODL-NEXT: v_mad_i32_i24 v2, s0, v3, v2 ; GFX9-NODL-NEXT: v_mad_i32_i24 v2, s0, v3, v2
; GFX9-NODL-NEXT: global_store_short v[0:1], v2, off ; GFX9-NODL-NEXT: global_store_short v[0:1], v2, off
; GFX9-NODL-NEXT: s_endpgm ; GFX9-NODL-NEXT: s_endpgm
; ;
; GFX9-DL-LABEL: idot4_acc16: ; GFX9-DL-LABEL: idot4_acc16:
; GFX9-DL: ; %bb.0: ; %entry ; GFX9-DL: ; %bb.0: ; %entry
; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
define amdgpu_kernel void @idot4_acc8(<4 x i8> addrspace(1)* %src1, define amdgpu_kernel void @idot4_acc8(<4 x i8> addrspace(1)* %src1,
; GFX7-LABEL: idot4_acc8: ; GFX7-LABEL: idot4_acc8:
; GFX7: ; %bb.0: ; %entry ; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd ; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: s_mov_b32 s2, -1 ; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_movk_i32 s8, 0xff
; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_load_dword s6, s[6:7], 0x0
; GFX7-NEXT: buffer_load_ubyte v0, off, s[0:3], 0 ; GFX7-NEXT: buffer_load_ubyte v0, off, s[0:3], 0
; GFX7-NEXT: s_load_dword s4, s[4:5], 0x0 ; GFX7-NEXT: s_load_dword s4, s[4:5], 0x0
; GFX7-NEXT: s_movk_i32 s5, 0xff ; GFX7-NEXT: s_load_dword s5, s[6:7], 0x0
; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_and_b32 s7, s6, s5 ; GFX7-NEXT: s_and_b32 s7, s4, s8
; GFX7-NEXT: s_bfe_u32 s8, s6, 0x80008 ; GFX7-NEXT: s_and_b32 s6, s5, s8
; GFX7-NEXT: s_and_b32 s5, s4, s5 ; GFX7-NEXT: s_bfe_u32 s8, s5, 0x80008
; GFX7-NEXT: v_mov_b32_e32 v1, s7 ; GFX7-NEXT: v_mov_b32_e32 v1, s6
; GFX7-NEXT: s_bfe_u32 s10, s6, 0x80010 ; GFX7-NEXT: s_bfe_u32 s10, s5, 0x80010
; GFX7-NEXT: s_bfe_u32 s9, s4, 0x80008 ; GFX7-NEXT: s_bfe_u32 s9, s4, 0x80008
; GFX7-NEXT: v_mov_b32_e32 v2, s8 ; GFX7-NEXT: v_mov_b32_e32 v2, s8
; GFX7-NEXT: s_bfe_u32 s11, s4, 0x80010 ; GFX7-NEXT: s_bfe_u32 s11, s4, 0x80010
; GFX7-NEXT: s_lshr_b32 s6, s6, 24 ; GFX7-NEXT: s_lshr_b32 s5, s5, 24
; GFX7-NEXT: v_mov_b32_e32 v3, s10 ; GFX7-NEXT: v_mov_b32_e32 v3, s10
; GFX7-NEXT: s_lshr_b32 s4, s4, 24 ; GFX7-NEXT: s_lshr_b32 s4, s4, 24
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_mad_u32_u24 v0, s5, v1, v0 ; GFX7-NEXT: v_mad_u32_u24 v0, s7, v1, v0
; GFX7-NEXT: v_mad_u32_u24 v0, s9, v2, v0 ; GFX7-NEXT: v_mad_u32_u24 v0, s9, v2, v0
; GFX7-NEXT: v_mad_u32_u24 v0, s11, v3, v0 ; GFX7-NEXT: v_mad_u32_u24 v0, s11, v3, v0
; GFX7-NEXT: v_mov_b32_e32 v1, s6 ; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: v_mad_u32_u24 v0, s4, v1, v0 ; GFX7-NEXT: v_mad_u32_u24 v0, s4, v1, v0
; GFX7-NEXT: buffer_store_byte v0, off, s[0:3], 0 ; GFX7-NEXT: buffer_store_byte v0, off, s[0:3], 0
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX8-LABEL: idot4_acc8: ; GFX8-LABEL: idot4_acc8:
; GFX8: ; %bb.0: ; %entry ; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_load_ubyte v2, v[0:1] ; GFX8-NEXT: flat_load_ubyte v2, v[0:1]
; GFX8-NEXT: s_load_dword s1, s[6:7], 0x0 ; GFX8-NEXT: s_load_dword s1, s[4:5], 0x0
; GFX8-NEXT: s_load_dword s2, s[6:7], 0x0
; GFX8-NEXT: s_movk_i32 s0, 0xff ; GFX8-NEXT: s_movk_i32 s0, 0xff
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_bfe_u32 s5, s2, 0x80008 ; GFX8-NEXT: s_bfe_u32 s5, s1, 0x80008
; GFX8-NEXT: s_bfe_u32 s7, s2, 0x80010 ; GFX8-NEXT: s_and_b32 s3, s2, s0
; GFX8-NEXT: s_and_b32 s3, s1, s0 ; GFX8-NEXT: s_bfe_u32 s4, s2, 0x80008
; GFX8-NEXT: s_and_b32 s0, s2, s0 ; GFX8-NEXT: s_and_b32 s0, s1, s0
; GFX8-NEXT: s_bfe_u32 s4, s1, 0x80008
; GFX8-NEXT: v_mov_b32_e32 v3, s3 ; GFX8-NEXT: v_mov_b32_e32 v3, s3
; GFX8-NEXT: s_bfe_u32 s6, s1, 0x80010 ; GFX8-NEXT: s_bfe_u32 s6, s2, 0x80010
; GFX8-NEXT: v_mov_b32_e32 v4, s4 ; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: s_lshr_b32 s1, s1, 24 ; GFX8-NEXT: s_bfe_u32 s7, s1, 0x80010
; GFX8-NEXT: v_mov_b32_e32 v5, s6
; GFX8-NEXT: s_lshr_b32 s2, s2, 24 ; GFX8-NEXT: s_lshr_b32 s2, s2, 24
; GFX8-NEXT: v_mov_b32_e32 v5, s6
; GFX8-NEXT: s_lshr_b32 s1, s1, 24
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mad_u32_u24 v2, s0, v3, v2 ; GFX8-NEXT: v_mad_u32_u24 v2, s0, v3, v2
; GFX8-NEXT: v_mad_u32_u24 v2, s5, v4, v2 ; GFX8-NEXT: v_mad_u32_u24 v2, s5, v4, v2
; GFX8-NEXT: v_mad_u32_u24 v2, s7, v5, v2 ; GFX8-NEXT: v_mad_u32_u24 v2, s7, v5, v2
; GFX8-NEXT: v_mov_b32_e32 v3, s1 ; GFX8-NEXT: v_mov_b32_e32 v3, s2
; GFX8-NEXT: v_mad_u32_u24 v2, s2, v3, v2 ; GFX8-NEXT: v_mad_u32_u24 v2, s1, v3, v2
; GFX8-NEXT: flat_store_byte v[0:1], v2 ; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-NODL-LABEL: idot4_acc8: ; GFX9-NODL-LABEL: idot4_acc8:
; GFX9-NODL: ; %bb.0: ; %entry ; GFX9-NODL: ; %bb.0: ; %entry
; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NODL-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NODL-NEXT: global_load_ubyte v2, v[0:1], off ; GFX9-NODL-NEXT: global_load_ubyte v2, v[0:1], off
; GFX9-NODL-NEXT: s_load_dword s1, s[6:7], 0x0 ; GFX9-NODL-NEXT: s_load_dword s1, s[4:5], 0x0
; GFX9-NODL-NEXT: s_load_dword s2, s[6:7], 0x0
; GFX9-NODL-NEXT: s_movk_i32 s0, 0xff ; GFX9-NODL-NEXT: s_movk_i32 s0, 0xff
; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NODL-NEXT: s_bfe_u32 s5, s2, 0x80008 ; GFX9-NODL-NEXT: s_bfe_u32 s5, s1, 0x80008
; GFX9-NODL-NEXT: s_bfe_u32 s7, s2, 0x80010 ; GFX9-NODL-NEXT: s_and_b32 s3, s2, s0
; GFX9-NODL-NEXT: s_and_b32 s3, s1, s0 ; GFX9-NODL-NEXT: s_bfe_u32 s4, s2, 0x80008
; GFX9-NODL-NEXT: s_and_b32 s0, s2, s0 ; GFX9-NODL-NEXT: s_and_b32 s0, s1, s0
; GFX9-NODL-NEXT: s_bfe_u32 s4, s1, 0x80008
; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s3 ; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s3
; GFX9-NODL-NEXT: s_bfe_u32 s6, s1, 0x80010 ; GFX9-NODL-NEXT: s_bfe_u32 s6, s2, 0x80010
; GFX9-NODL-NEXT: v_mov_b32_e32 v4, s4 ; GFX9-NODL-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NODL-NEXT: s_lshr_b32 s1, s1, 24 ; GFX9-NODL-NEXT: s_bfe_u32 s7, s1, 0x80010
; GFX9-NODL-NEXT: v_mov_b32_e32 v5, s6
; GFX9-NODL-NEXT: s_lshr_b32 s2, s2, 24 ; GFX9-NODL-NEXT: s_lshr_b32 s2, s2, 24
; GFX9-NODL-NEXT: v_mov_b32_e32 v5, s6
; GFX9-NODL-NEXT: s_lshr_b32 s1, s1, 24
; GFX9-NODL-NEXT: s_waitcnt vmcnt(0) ; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s0, v3, v2 ; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s0, v3, v2
; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s5, v4, v2 ; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s5, v4, v2
; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s7, v5, v2 ; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s7, v5, v2
; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s1 ; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s2
; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s2, v3, v2 ; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s1, v3, v2
; GFX9-NODL-NEXT: global_store_byte v[0:1], v2, off ; GFX9-NODL-NEXT: global_store_byte v[0:1], v2, off
; GFX9-NODL-NEXT: s_endpgm ; GFX9-NODL-NEXT: s_endpgm
; ;
; GFX9-DL-LABEL: idot4_acc8: ; GFX9-DL-LABEL: idot4_acc8:
; GFX9-DL: ; %bb.0: ; %entry ; GFX9-DL: ; %bb.0: ; %entry
; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
▲ Show 20 Lines • Show All 651 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/idot4u.ll

Show First 20 Lines • Show All 178 Lines • ▼ Show 20 Lines
define amdgpu_kernel void @udot4_acc16(<4 x i8> addrspace(1)* %src1, define amdgpu_kernel void @udot4_acc16(<4 x i8> addrspace(1)* %src1,
; GFX7-LABEL: udot4_acc16: ; GFX7-LABEL: udot4_acc16:
; GFX7: ; %bb.0: ; %entry ; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd ; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: s_mov_b32 s2, -1 ; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_movk_i32 s8, 0xff
; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_load_dword s6, s[6:7], 0x0
; GFX7-NEXT: buffer_load_ushort v0, off, s[0:3], 0 ; GFX7-NEXT: buffer_load_ushort v0, off, s[0:3], 0
; GFX7-NEXT: s_load_dword s4, s[4:5], 0x0 ; GFX7-NEXT: s_load_dword s4, s[4:5], 0x0
; GFX7-NEXT: s_movk_i32 s5, 0xff ; GFX7-NEXT: s_load_dword s5, s[6:7], 0x0
; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_and_b32 s7, s6, s5 ; GFX7-NEXT: s_and_b32 s7, s4, s8
; GFX7-NEXT: s_bfe_u32 s8, s6, 0x80008 ; GFX7-NEXT: s_and_b32 s6, s5, s8
; GFX7-NEXT: s_and_b32 s5, s4, s5 ; GFX7-NEXT: s_bfe_u32 s8, s5, 0x80008
; GFX7-NEXT: v_mov_b32_e32 v1, s7 ; GFX7-NEXT: v_mov_b32_e32 v1, s6
; GFX7-NEXT: s_bfe_u32 s10, s6, 0x80010 ; GFX7-NEXT: s_bfe_u32 s10, s5, 0x80010
; GFX7-NEXT: s_bfe_u32 s9, s4, 0x80008 ; GFX7-NEXT: s_bfe_u32 s9, s4, 0x80008
; GFX7-NEXT: v_mov_b32_e32 v2, s8 ; GFX7-NEXT: v_mov_b32_e32 v2, s8
; GFX7-NEXT: s_bfe_u32 s11, s4, 0x80010 ; GFX7-NEXT: s_bfe_u32 s11, s4, 0x80010
; GFX7-NEXT: s_lshr_b32 s6, s6, 24 ; GFX7-NEXT: s_lshr_b32 s5, s5, 24
; GFX7-NEXT: v_mov_b32_e32 v3, s10 ; GFX7-NEXT: v_mov_b32_e32 v3, s10
; GFX7-NEXT: s_lshr_b32 s4, s4, 24 ; GFX7-NEXT: s_lshr_b32 s4, s4, 24
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_mad_u32_u24 v0, s5, v1, v0 ; GFX7-NEXT: v_mad_u32_u24 v0, s7, v1, v0
; GFX7-NEXT: v_mad_u32_u24 v0, s9, v2, v0 ; GFX7-NEXT: v_mad_u32_u24 v0, s9, v2, v0
; GFX7-NEXT: v_mad_u32_u24 v0, s11, v3, v0 ; GFX7-NEXT: v_mad_u32_u24 v0, s11, v3, v0
; GFX7-NEXT: v_mov_b32_e32 v1, s6 ; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: v_mad_u32_u24 v0, s4, v1, v0 ; GFX7-NEXT: v_mad_u32_u24 v0, s4, v1, v0
; GFX7-NEXT: buffer_store_short v0, off, s[0:3], 0 ; GFX7-NEXT: buffer_store_short v0, off, s[0:3], 0
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX8-LABEL: udot4_acc16: ; GFX8-LABEL: udot4_acc16:
; GFX8: ; %bb.0: ; %entry ; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_load_dword s2, s[6:7], 0x0
; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_load_ushort v2, v[0:1] ; GFX8-NEXT: flat_load_ushort v2, v[0:1]
; GFX8-NEXT: s_load_dword s1, s[4:5], 0x0 ; GFX8-NEXT: s_load_dword s1, s[4:5], 0x0
; GFX8-NEXT: s_load_dword s2, s[6:7], 0x0
; GFX8-NEXT: s_movk_i32 s0, 0xff ; GFX8-NEXT: s_movk_i32 s0, 0xff
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_bfe_u32 s5, s2, 0x80008
; GFX8-NEXT: s_bfe_u32 s7, s2, 0x80010
; GFX8-NEXT: v_mov_b32_e32 v4, s5
; GFX8-NEXT: s_and_b32 s3, s1, s0 ; GFX8-NEXT: s_and_b32 s3, s1, s0
; GFX8-NEXT: s_and_b32 s0, s2, s0 ; GFX8-NEXT: s_and_b32 s0, s2, s0
; GFX8-NEXT: s_bfe_u32 s5, s2, 0x80008
; GFX8-NEXT: v_mov_b32_e32 v3, s0 ; GFX8-NEXT: v_mov_b32_e32 v3, s0
; GFX8-NEXT: s_bfe_u32 s7, s2, 0x80010
; GFX8-NEXT: s_bfe_u32 s4, s1, 0x80008 ; GFX8-NEXT: s_bfe_u32 s4, s1, 0x80008
; GFX8-NEXT: v_mov_b32_e32 v4, s5
; GFX8-NEXT: s_bfe_u32 s6, s1, 0x80010 ; GFX8-NEXT: s_bfe_u32 s6, s1, 0x80010
; GFX8-NEXT: s_lshr_b32 s2, s2, 24 ; GFX8-NEXT: s_lshr_b32 s2, s2, 24
; GFX8-NEXT: v_mov_b32_e32 v5, s7 ; GFX8-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NEXT: s_lshr_b32 s1, s1, 24 ; GFX8-NEXT: s_lshr_b32 s1, s1, 24
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mad_u32_u24 v2, s3, v3, v2 ; GFX8-NEXT: v_mad_u32_u24 v2, s3, v3, v2
; GFX8-NEXT: v_mad_u32_u24 v2, s4, v4, v2 ; GFX8-NEXT: v_mad_u32_u24 v2, s4, v4, v2
; GFX8-NEXT: v_mad_u32_u24 v2, s6, v5, v2 ; GFX8-NEXT: v_mad_u32_u24 v2, s6, v5, v2
; GFX8-NEXT: v_mov_b32_e32 v3, s2 ; GFX8-NEXT: v_mov_b32_e32 v3, s2
; GFX8-NEXT: v_mad_u32_u24 v2, s1, v3, v2 ; GFX8-NEXT: v_mad_u32_u24 v2, s1, v3, v2
; GFX8-NEXT: flat_store_short v[0:1], v2 ; GFX8-NEXT: flat_store_short v[0:1], v2
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-NODL-LABEL: udot4_acc16: ; GFX9-NODL-LABEL: udot4_acc16:
; GFX9-NODL: ; %bb.0: ; %entry ; GFX9-NODL: ; %bb.0: ; %entry
; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NODL-NEXT: s_load_dword s2, s[6:7], 0x0
; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NODL-NEXT: global_load_ushort v2, v[0:1], off ; GFX9-NODL-NEXT: global_load_ushort v2, v[0:1], off
; GFX9-NODL-NEXT: s_load_dword s1, s[4:5], 0x0 ; GFX9-NODL-NEXT: s_load_dword s1, s[4:5], 0x0
; GFX9-NODL-NEXT: s_load_dword s2, s[6:7], 0x0
; GFX9-NODL-NEXT: s_movk_i32 s0, 0xff ; GFX9-NODL-NEXT: s_movk_i32 s0, 0xff
; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NODL-NEXT: s_bfe_u32 s5, s2, 0x80008
; GFX9-NODL-NEXT: s_bfe_u32 s7, s2, 0x80010
; GFX9-NODL-NEXT: v_mov_b32_e32 v4, s5
; GFX9-NODL-NEXT: s_and_b32 s3, s1, s0 ; GFX9-NODL-NEXT: s_and_b32 s3, s1, s0
; GFX9-NODL-NEXT: s_and_b32 s0, s2, s0 ; GFX9-NODL-NEXT: s_and_b32 s0, s2, s0
; GFX9-NODL-NEXT: s_bfe_u32 s5, s2, 0x80008
; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s0 ; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s0
; GFX9-NODL-NEXT: s_bfe_u32 s7, s2, 0x80010
; GFX9-NODL-NEXT: s_bfe_u32 s4, s1, 0x80008 ; GFX9-NODL-NEXT: s_bfe_u32 s4, s1, 0x80008
; GFX9-NODL-NEXT: v_mov_b32_e32 v4, s5
; GFX9-NODL-NEXT: s_bfe_u32 s6, s1, 0x80010 ; GFX9-NODL-NEXT: s_bfe_u32 s6, s1, 0x80010
; GFX9-NODL-NEXT: s_lshr_b32 s2, s2, 24 ; GFX9-NODL-NEXT: s_lshr_b32 s2, s2, 24
; GFX9-NODL-NEXT: v_mov_b32_e32 v5, s7 ; GFX9-NODL-NEXT: v_mov_b32_e32 v5, s7
; GFX9-NODL-NEXT: s_lshr_b32 s1, s1, 24 ; GFX9-NODL-NEXT: s_lshr_b32 s1, s1, 24
; GFX9-NODL-NEXT: s_waitcnt vmcnt(0) ; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s3, v3, v2 ; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s3, v3, v2
; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s4, v4, v2 ; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s4, v4, v2
; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s6, v5, v2 ; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s6, v5, v2
▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines
define amdgpu_kernel void @udot4_acc8(<4 x i8> addrspace(1)* %src1, define amdgpu_kernel void @udot4_acc8(<4 x i8> addrspace(1)* %src1,
; GFX7-LABEL: udot4_acc8: ; GFX7-LABEL: udot4_acc8:
; GFX7: ; %bb.0: ; %entry ; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd ; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: s_mov_b32 s2, -1 ; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_movk_i32 s8, 0xff
; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_load_dword s6, s[6:7], 0x0
; GFX7-NEXT: buffer_load_ubyte v0, off, s[0:3], 0 ; GFX7-NEXT: buffer_load_ubyte v0, off, s[0:3], 0
; GFX7-NEXT: s_load_dword s4, s[4:5], 0x0 ; GFX7-NEXT: s_load_dword s4, s[4:5], 0x0
; GFX7-NEXT: s_movk_i32 s5, 0xff ; GFX7-NEXT: s_load_dword s5, s[6:7], 0x0
; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_and_b32 s7, s6, s5 ; GFX7-NEXT: s_and_b32 s7, s4, s8
; GFX7-NEXT: s_bfe_u32 s8, s6, 0x80008 ; GFX7-NEXT: s_and_b32 s6, s5, s8
; GFX7-NEXT: s_and_b32 s5, s4, s5 ; GFX7-NEXT: s_bfe_u32 s8, s5, 0x80008
; GFX7-NEXT: v_mov_b32_e32 v1, s7 ; GFX7-NEXT: v_mov_b32_e32 v1, s6
; GFX7-NEXT: s_bfe_u32 s10, s6, 0x80010 ; GFX7-NEXT: s_bfe_u32 s10, s5, 0x80010
; GFX7-NEXT: s_bfe_u32 s9, s4, 0x80008 ; GFX7-NEXT: s_bfe_u32 s9, s4, 0x80008
; GFX7-NEXT: v_mov_b32_e32 v2, s8 ; GFX7-NEXT: v_mov_b32_e32 v2, s8
; GFX7-NEXT: s_bfe_u32 s11, s4, 0x80010 ; GFX7-NEXT: s_bfe_u32 s11, s4, 0x80010
; GFX7-NEXT: s_lshr_b32 s6, s6, 24 ; GFX7-NEXT: s_lshr_b32 s5, s5, 24
; GFX7-NEXT: v_mov_b32_e32 v3, s10 ; GFX7-NEXT: v_mov_b32_e32 v3, s10
; GFX7-NEXT: s_lshr_b32 s4, s4, 24 ; GFX7-NEXT: s_lshr_b32 s4, s4, 24
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_mad_u32_u24 v0, s5, v1, v0 ; GFX7-NEXT: v_mad_u32_u24 v0, s7, v1, v0
; GFX7-NEXT: v_mad_u32_u24 v0, s9, v2, v0 ; GFX7-NEXT: v_mad_u32_u24 v0, s9, v2, v0
; GFX7-NEXT: v_mad_u32_u24 v0, s11, v3, v0 ; GFX7-NEXT: v_mad_u32_u24 v0, s11, v3, v0
; GFX7-NEXT: v_mov_b32_e32 v1, s6 ; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: v_mad_u32_u24 v0, s4, v1, v0 ; GFX7-NEXT: v_mad_u32_u24 v0, s4, v1, v0
; GFX7-NEXT: buffer_store_byte v0, off, s[0:3], 0 ; GFX7-NEXT: buffer_store_byte v0, off, s[0:3], 0
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX8-LABEL: udot4_acc8: ; GFX8-LABEL: udot4_acc8:
; GFX8: ; %bb.0: ; %entry ; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_load_ubyte v2, v[0:1] ; GFX8-NEXT: flat_load_ubyte v2, v[0:1]
; GFX8-NEXT: s_load_dword s1, s[6:7], 0x0 ; GFX8-NEXT: s_load_dword s1, s[4:5], 0x0
; GFX8-NEXT: s_load_dword s2, s[6:7], 0x0
; GFX8-NEXT: s_movk_i32 s0, 0xff ; GFX8-NEXT: s_movk_i32 s0, 0xff
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_bfe_u32 s5, s2, 0x80008 ; GFX8-NEXT: s_bfe_u32 s5, s1, 0x80008
; GFX8-NEXT: s_bfe_u32 s7, s2, 0x80010 ; GFX8-NEXT: s_and_b32 s3, s2, s0
; GFX8-NEXT: s_and_b32 s3, s1, s0 ; GFX8-NEXT: s_bfe_u32 s4, s2, 0x80008
; GFX8-NEXT: s_and_b32 s0, s2, s0 ; GFX8-NEXT: s_and_b32 s0, s1, s0
; GFX8-NEXT: s_bfe_u32 s4, s1, 0x80008
; GFX8-NEXT: v_mov_b32_e32 v3, s3 ; GFX8-NEXT: v_mov_b32_e32 v3, s3
; GFX8-NEXT: s_bfe_u32 s6, s1, 0x80010 ; GFX8-NEXT: s_bfe_u32 s6, s2, 0x80010
; GFX8-NEXT: v_mov_b32_e32 v4, s4 ; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: s_lshr_b32 s1, s1, 24 ; GFX8-NEXT: s_bfe_u32 s7, s1, 0x80010
; GFX8-NEXT: v_mov_b32_e32 v5, s6
; GFX8-NEXT: s_lshr_b32 s2, s2, 24 ; GFX8-NEXT: s_lshr_b32 s2, s2, 24
; GFX8-NEXT: v_mov_b32_e32 v5, s6
; GFX8-NEXT: s_lshr_b32 s1, s1, 24
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mad_u32_u24 v2, s0, v3, v2 ; GFX8-NEXT: v_mad_u32_u24 v2, s0, v3, v2
; GFX8-NEXT: v_mad_u32_u24 v2, s5, v4, v2 ; GFX8-NEXT: v_mad_u32_u24 v2, s5, v4, v2
; GFX8-NEXT: v_mad_u32_u24 v2, s7, v5, v2 ; GFX8-NEXT: v_mad_u32_u24 v2, s7, v5, v2
; GFX8-NEXT: v_mov_b32_e32 v3, s1 ; GFX8-NEXT: v_mov_b32_e32 v3, s2
; GFX8-NEXT: v_mad_u32_u24 v2, s2, v3, v2 ; GFX8-NEXT: v_mad_u32_u24 v2, s1, v3, v2
; GFX8-NEXT: flat_store_byte v[0:1], v2 ; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-NODL-LABEL: udot4_acc8: ; GFX9-NODL-LABEL: udot4_acc8:
; GFX9-NODL: ; %bb.0: ; %entry ; GFX9-NODL: ; %bb.0: ; %entry
; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NODL-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NODL-NEXT: global_load_ubyte v2, v[0:1], off ; GFX9-NODL-NEXT: global_load_ubyte v2, v[0:1], off
; GFX9-NODL-NEXT: s_load_dword s1, s[6:7], 0x0 ; GFX9-NODL-NEXT: s_load_dword s1, s[4:5], 0x0
; GFX9-NODL-NEXT: s_load_dword s2, s[6:7], 0x0
; GFX9-NODL-NEXT: s_movk_i32 s0, 0xff ; GFX9-NODL-NEXT: s_movk_i32 s0, 0xff
; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NODL-NEXT: s_bfe_u32 s5, s2, 0x80008 ; GFX9-NODL-NEXT: s_bfe_u32 s5, s1, 0x80008
; GFX9-NODL-NEXT: s_bfe_u32 s7, s2, 0x80010 ; GFX9-NODL-NEXT: s_and_b32 s3, s2, s0
; GFX9-NODL-NEXT: s_and_b32 s3, s1, s0 ; GFX9-NODL-NEXT: s_bfe_u32 s4, s2, 0x80008
; GFX9-NODL-NEXT: s_and_b32 s0, s2, s0 ; GFX9-NODL-NEXT: s_and_b32 s0, s1, s0
; GFX9-NODL-NEXT: s_bfe_u32 s4, s1, 0x80008
; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s3 ; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s3
; GFX9-NODL-NEXT: s_bfe_u32 s6, s1, 0x80010 ; GFX9-NODL-NEXT: s_bfe_u32 s6, s2, 0x80010
; GFX9-NODL-NEXT: v_mov_b32_e32 v4, s4 ; GFX9-NODL-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NODL-NEXT: s_lshr_b32 s1, s1, 24 ; GFX9-NODL-NEXT: s_bfe_u32 s7, s1, 0x80010
; GFX9-NODL-NEXT: v_mov_b32_e32 v5, s6
; GFX9-NODL-NEXT: s_lshr_b32 s2, s2, 24 ; GFX9-NODL-NEXT: s_lshr_b32 s2, s2, 24
; GFX9-NODL-NEXT: v_mov_b32_e32 v5, s6
; GFX9-NODL-NEXT: s_lshr_b32 s1, s1, 24
; GFX9-NODL-NEXT: s_waitcnt vmcnt(0) ; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s0, v3, v2 ; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s0, v3, v2
; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s5, v4, v2 ; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s5, v4, v2
; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s7, v5, v2 ; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s7, v5, v2
; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s1 ; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s2
; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s2, v3, v2 ; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s1, v3, v2
; GFX9-NODL-NEXT: global_store_byte v[0:1], v2, off ; GFX9-NODL-NEXT: global_store_byte v[0:1], v2, off
; GFX9-NODL-NEXT: s_endpgm ; GFX9-NODL-NEXT: s_endpgm
; ;
; GFX9-DL-LABEL: udot4_acc8: ; GFX9-DL-LABEL: udot4_acc8:
; GFX9-DL: ; %bb.0: ; %entry ; GFX9-DL: ; %bb.0: ; %entry
; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
▲ Show 20 Lines • Show All 969 Lines • ▼ Show 20 Lines
; GFX7-LABEL: notdot4_mixedtypes: ; GFX7-LABEL: notdot4_mixedtypes:
; GFX7: ; %bb.0: ; %entry ; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd ; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: s_mov_b32 s2, -1 ; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_mov_b32 s8, 0xffff ; GFX7-NEXT: s_mov_b32 s8, 0xffff
; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_load_dword s6, s[6:7], 0x0
; GFX7-NEXT: buffer_load_ushort v0, off, s[0:3], 0 ; GFX7-NEXT: buffer_load_ushort v0, off, s[0:3], 0
; GFX7-NEXT: s_load_dword s4, s[4:5], 0x0 ; GFX7-NEXT: s_load_dword s4, s[4:5], 0x0
; GFX7-NEXT: s_load_dword s5, s[6:7], 0x0
; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_sext_i32_i8 s7, s6 ; GFX7-NEXT: s_sext_i32_i8 s6, s4
; GFX7-NEXT: s_bfe_u32 s9, s6, 0x80008 ; GFX7-NEXT: s_sext_i32_i8 s7, s5
; GFX7-NEXT: s_sext_i32_i8 s5, s4 ; GFX7-NEXT: s_bfe_u32 s9, s5, 0x80008
; GFX7-NEXT: s_and_b32 s7, s7, s8 ; GFX7-NEXT: s_and_b32 s7, s7, s8
; GFX7-NEXT: s_bfe_u32 s10, s4, 0x80008 ; GFX7-NEXT: s_bfe_u32 s10, s4, 0x80008
; GFX7-NEXT: v_mov_b32_e32 v1, s9 ; GFX7-NEXT: v_mov_b32_e32 v1, s9
; GFX7-NEXT: s_bfe_u32 s11, s6, 0x80010 ; GFX7-NEXT: s_bfe_u32 s11, s5, 0x80010
; GFX7-NEXT: s_and_b32 s5, s5, s8 ; GFX7-NEXT: s_and_b32 s6, s6, s8
; GFX7-NEXT: v_mov_b32_e32 v3, s7 ; GFX7-NEXT: v_mov_b32_e32 v3, s7
; GFX7-NEXT: s_bfe_u32 s12, s4, 0x80010 ; GFX7-NEXT: s_bfe_u32 s12, s4, 0x80010
; GFX7-NEXT: s_lshr_b32 s6, s6, 24 ; GFX7-NEXT: s_lshr_b32 s5, s5, 24
; GFX7-NEXT: v_mov_b32_e32 v2, s11 ; GFX7-NEXT: v_mov_b32_e32 v2, s11
; GFX7-NEXT: s_lshr_b32 s4, s4, 24 ; GFX7-NEXT: s_lshr_b32 s4, s4, 24
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_mad_u32_u24 v0, s10, v1, v0 ; GFX7-NEXT: v_mad_u32_u24 v0, s10, v1, v0
; GFX7-NEXT: v_mad_u32_u24 v0, s5, v3, v0 ; GFX7-NEXT: v_mad_u32_u24 v0, s6, v3, v0
; GFX7-NEXT: v_mad_u32_u24 v0, s12, v2, v0 ; GFX7-NEXT: v_mad_u32_u24 v0, s12, v2, v0
; GFX7-NEXT: v_mov_b32_e32 v1, s6 ; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: v_mad_u32_u24 v0, s4, v1, v0 ; GFX7-NEXT: v_mad_u32_u24 v0, s4, v1, v0
; GFX7-NEXT: buffer_store_short v0, off, s[0:3], 0 ; GFX7-NEXT: buffer_store_short v0, off, s[0:3], 0
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX8-LABEL: notdot4_mixedtypes: ; GFX8-LABEL: notdot4_mixedtypes:
; GFX8: ; %bb.0: ; %entry ; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_load_dword s2, s[6:7], 0x0
; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_load_ushort v2, v[0:1] ; GFX8-NEXT: flat_load_ushort v2, v[0:1]
; GFX8-NEXT: s_load_dword s0, s[4:5], 0x0 ; GFX8-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX8-NEXT: s_load_dword s1, s[6:7], 0x0
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_bfe_u32 s5, s2, 0x80008
; GFX8-NEXT: s_sext_i32_i8 s3, s2
; GFX8-NEXT: v_mov_b32_e32 v3, s5
; GFX8-NEXT: s_bfe_u32 s7, s2, 0x80010
; GFX8-NEXT: s_bfe_u32 s4, s0, 0x80008 ; GFX8-NEXT: s_bfe_u32 s4, s0, 0x80008
; GFX8-NEXT: s_sext_i32_i8 s1, s0 ; GFX8-NEXT: s_bfe_u32 s5, s1, 0x80008
; GFX8-NEXT: s_sext_i32_i8 s3, s1
; GFX8-NEXT: v_mov_b32_e32 v3, s5
; GFX8-NEXT: s_bfe_u32 s7, s1, 0x80010
; GFX8-NEXT: s_sext_i32_i8 s2, s0
; GFX8-NEXT: v_mov_b32_e32 v4, s3 ; GFX8-NEXT: v_mov_b32_e32 v4, s3
; GFX8-NEXT: s_bfe_u32 s6, s0, 0x80010 ; GFX8-NEXT: s_bfe_u32 s6, s0, 0x80010
; GFX8-NEXT: s_lshr_b32 s2, s2, 24 ; GFX8-NEXT: s_lshr_b32 s1, s1, 24
; GFX8-NEXT: v_mov_b32_e32 v5, s7 ; GFX8-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NEXT: s_lshr_b32 s0, s0, 24 ; GFX8-NEXT: s_lshr_b32 s0, s0, 24
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mad_u32_u24 v2, s4, v3, v2 ; GFX8-NEXT: v_mad_u32_u24 v2, s4, v3, v2
; GFX8-NEXT: v_mad_i32_i24 v2, s1, v4, v2 ; GFX8-NEXT: v_mad_i32_i24 v2, s2, v4, v2
; GFX8-NEXT: v_mad_u32_u24 v2, s6, v5, v2 ; GFX8-NEXT: v_mad_u32_u24 v2, s6, v5, v2
; GFX8-NEXT: v_mov_b32_e32 v3, s2 ; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mad_u32_u24 v2, s0, v3, v2 ; GFX8-NEXT: v_mad_u32_u24 v2, s0, v3, v2
; GFX8-NEXT: flat_store_short v[0:1], v2 ; GFX8-NEXT: flat_store_short v[0:1], v2
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-NODL-LABEL: notdot4_mixedtypes: ; GFX9-NODL-LABEL: notdot4_mixedtypes:
; GFX9-NODL: ; %bb.0: ; %entry ; GFX9-NODL: ; %bb.0: ; %entry
; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NODL-NEXT: s_load_dword s2, s[6:7], 0x0
; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NODL-NEXT: global_load_ushort v2, v[0:1], off ; GFX9-NODL-NEXT: global_load_ushort v2, v[0:1], off
; GFX9-NODL-NEXT: s_load_dword s0, s[4:5], 0x0 ; GFX9-NODL-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX9-NODL-NEXT: s_load_dword s1, s[6:7], 0x0
; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NODL-NEXT: s_bfe_u32 s5, s2, 0x80008
; GFX9-NODL-NEXT: s_sext_i32_i8 s3, s2
; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NODL-NEXT: s_bfe_u32 s7, s2, 0x80010
; GFX9-NODL-NEXT: s_bfe_u32 s4, s0, 0x80008 ; GFX9-NODL-NEXT: s_bfe_u32 s4, s0, 0x80008
; GFX9-NODL-NEXT: s_sext_i32_i8 s1, s0 ; GFX9-NODL-NEXT: s_bfe_u32 s5, s1, 0x80008
; GFX9-NODL-NEXT: s_sext_i32_i8 s3, s1
; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NODL-NEXT: s_bfe_u32 s7, s1, 0x80010
; GFX9-NODL-NEXT: s_sext_i32_i8 s2, s0
; GFX9-NODL-NEXT: v_mov_b32_e32 v4, s3 ; GFX9-NODL-NEXT: v_mov_b32_e32 v4, s3
; GFX9-NODL-NEXT: s_bfe_u32 s6, s0, 0x80010 ; GFX9-NODL-NEXT: s_bfe_u32 s6, s0, 0x80010
; GFX9-NODL-NEXT: s_lshr_b32 s2, s2, 24 ; GFX9-NODL-NEXT: s_lshr_b32 s1, s1, 24
; GFX9-NODL-NEXT: v_mov_b32_e32 v5, s7 ; GFX9-NODL-NEXT: v_mov_b32_e32 v5, s7
; GFX9-NODL-NEXT: s_lshr_b32 s0, s0, 24 ; GFX9-NODL-NEXT: s_lshr_b32 s0, s0, 24
; GFX9-NODL-NEXT: s_waitcnt vmcnt(0) ; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s4, v3, v2 ; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s4, v3, v2
; GFX9-NODL-NEXT: v_mad_i32_i24 v2, s1, v4, v2 ; GFX9-NODL-NEXT: v_mad_i32_i24 v2, s2, v4, v2
; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s6, v5, v2 ; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s6, v5, v2
; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s2 ; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s0, v3, v2 ; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s0, v3, v2
; GFX9-NODL-NEXT: global_store_short v[0:1], v2, off ; GFX9-NODL-NEXT: global_store_short v[0:1], v2, off
; GFX9-NODL-NEXT: s_endpgm ; GFX9-NODL-NEXT: s_endpgm
; ;
; GFX9-DL-LABEL: notdot4_mixedtypes: ; GFX9-DL-LABEL: notdot4_mixedtypes:
; GFX9-DL: ; %bb.0: ; %entry ; GFX9-DL: ; %bb.0: ; %entry
; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DL-NEXT: s_load_dword s2, s[6:7], 0x0
; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-DL-NEXT: global_load_ushort v2, v[0:1], off ; GFX9-DL-NEXT: global_load_ushort v2, v[0:1], off
; GFX9-DL-NEXT: s_load_dword s0, s[4:5], 0x0 ; GFX9-DL-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX9-DL-NEXT: s_load_dword s1, s[6:7], 0x0
; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DL-NEXT: s_bfe_u32 s5, s2, 0x80008
; GFX9-DL-NEXT: s_sext_i32_i8 s3, s2
; GFX9-DL-NEXT: v_mov_b32_e32 v3, s5
; GFX9-DL-NEXT: s_bfe_u32 s7, s2, 0x80010
; GFX9-DL-NEXT: s_bfe_u32 s4, s0, 0x80008 ; GFX9-DL-NEXT: s_bfe_u32 s4, s0, 0x80008
; GFX9-DL-NEXT: s_sext_i32_i8 s1, s0 ; GFX9-DL-NEXT: s_bfe_u32 s5, s1, 0x80008
; GFX9-DL-NEXT: s_sext_i32_i8 s3, s1
; GFX9-DL-NEXT: v_mov_b32_e32 v3, s5
; GFX9-DL-NEXT: s_bfe_u32 s7, s1, 0x80010
; GFX9-DL-NEXT: s_sext_i32_i8 s2, s0
; GFX9-DL-NEXT: v_mov_b32_e32 v4, s3 ; GFX9-DL-NEXT: v_mov_b32_e32 v4, s3
; GFX9-DL-NEXT: s_bfe_u32 s6, s0, 0x80010 ; GFX9-DL-NEXT: s_bfe_u32 s6, s0, 0x80010
; GFX9-DL-NEXT: s_lshr_b32 s2, s2, 24 ; GFX9-DL-NEXT: s_lshr_b32 s1, s1, 24
; GFX9-DL-NEXT: v_mov_b32_e32 v5, s7 ; GFX9-DL-NEXT: v_mov_b32_e32 v5, s7
; GFX9-DL-NEXT: s_lshr_b32 s0, s0, 24 ; GFX9-DL-NEXT: s_lshr_b32 s0, s0, 24
; GFX9-DL-NEXT: s_waitcnt vmcnt(0) ; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
; GFX9-DL-NEXT: v_mad_u32_u24 v2, s4, v3, v2 ; GFX9-DL-NEXT: v_mad_u32_u24 v2, s4, v3, v2
; GFX9-DL-NEXT: v_mad_i32_i24 v2, s1, v4, v2 ; GFX9-DL-NEXT: v_mad_i32_i24 v2, s2, v4, v2
; GFX9-DL-NEXT: v_mad_u32_u24 v2, s6, v5, v2 ; GFX9-DL-NEXT: v_mad_u32_u24 v2, s6, v5, v2
; GFX9-DL-NEXT: v_mov_b32_e32 v3, s2 ; GFX9-DL-NEXT: v_mov_b32_e32 v3, s1
; GFX9-DL-NEXT: v_mad_u32_u24 v2, s0, v3, v2 ; GFX9-DL-NEXT: v_mad_u32_u24 v2, s0, v3, v2
; GFX9-DL-NEXT: global_store_short v[0:1], v2, off ; GFX9-DL-NEXT: global_store_short v[0:1], v2, off
; GFX9-DL-NEXT: s_endpgm ; GFX9-DL-NEXT: s_endpgm
; ;
; GFX10-DL-LABEL: notdot4_mixedtypes: ; GFX10-DL-LABEL: notdot4_mixedtypes:
; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi
▲ Show 20 Lines • Show All 252 Lines • ▼ Show 20 Lines
; TODO: This pattern should be recognized. ; TODO: This pattern should be recognized.
define amdgpu_kernel void @udot4_acc16_vecMul(<4 x i8> addrspace(1)* %src1, define amdgpu_kernel void @udot4_acc16_vecMul(<4 x i8> addrspace(1)* %src1,
; GFX7-LABEL: udot4_acc16_vecMul: ; GFX7-LABEL: udot4_acc16_vecMul:
; GFX7: ; %bb.0: ; %entry ; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd ; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: s_mov_b32 s2, -1 ; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_movk_i32 s8, 0xff
; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_load_dword s6, s[6:7], 0x0
; GFX7-NEXT: buffer_load_ushort v0, off, s[0:3], 0 ; GFX7-NEXT: buffer_load_ushort v0, off, s[0:3], 0
; GFX7-NEXT: s_load_dword s4, s[4:5], 0x0 ; GFX7-NEXT: s_load_dword s4, s[4:5], 0x0
; GFX7-NEXT: s_movk_i32 s7, 0xff ; GFX7-NEXT: s_load_dword s5, s[6:7], 0x0
; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_bfe_u32 s10, s6, 0x80008 ; GFX7-NEXT: s_lshr_b32 s6, s4, 24
; GFX7-NEXT: s_bfe_u32 s12, s6, 0x80010 ; GFX7-NEXT: s_bfe_u32 s10, s5, 0x80008
; GFX7-NEXT: s_lshr_b32 s9, s6, 24 ; GFX7-NEXT: s_bfe_u32 s12, s5, 0x80010
; GFX7-NEXT: s_and_b32 s6, s6, s7 ; GFX7-NEXT: s_lshr_b32 s9, s5, 24
; GFX7-NEXT: s_lshr_b32 s5, s4, 24 ; GFX7-NEXT: s_and_b32 s5, s5, s8
; GFX7-NEXT: s_bfe_u32 s8, s4, 0x80008 ; GFX7-NEXT: s_bfe_u32 s7, s4, 0x80008
; GFX7-NEXT: s_bfe_u32 s11, s4, 0x80010 ; GFX7-NEXT: s_bfe_u32 s11, s4, 0x80010
; GFX7-NEXT: s_and_b32 s4, s4, s7 ; GFX7-NEXT: s_and_b32 s4, s4, s8
; GFX7-NEXT: v_mov_b32_e32 v1, s6 ; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: v_mov_b32_e32 v2, s10 ; GFX7-NEXT: v_mov_b32_e32 v2, s10
; GFX7-NEXT: v_mov_b32_e32 v3, s12 ; GFX7-NEXT: v_mov_b32_e32 v3, s12
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_mad_u32_u24 v0, s4, v1, v0 ; GFX7-NEXT: v_mad_u32_u24 v0, s4, v1, v0
; GFX7-NEXT: v_mad_u32_u24 v0, s8, v2, v0 ; GFX7-NEXT: v_mad_u32_u24 v0, s7, v2, v0
; GFX7-NEXT: v_mad_u32_u24 v0, s11, v3, v0 ; GFX7-NEXT: v_mad_u32_u24 v0, s11, v3, v0
; GFX7-NEXT: v_mov_b32_e32 v1, s9 ; GFX7-NEXT: v_mov_b32_e32 v1, s9
; GFX7-NEXT: v_mad_u32_u24 v0, s5, v1, v0 ; GFX7-NEXT: v_mad_u32_u24 v0, s6, v1, v0
; GFX7-NEXT: buffer_store_short v0, off, s[0:3], 0 ; GFX7-NEXT: buffer_store_short v0, off, s[0:3], 0
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX8-LABEL: udot4_acc16_vecMul: ; GFX8-LABEL: udot4_acc16_vecMul:
; GFX8: ; %bb.0: ; %entry ; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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llvm/test/CodeGen/AMDGPU/idot8s.ll

Show First 20 Lines • Show All 651 Lines • ▼ Show 20 Lines
; GFX7-NEXT: v_mad_u32_u24 v0, s4, v1, v0 ; GFX7-NEXT: v_mad_u32_u24 v0, s4, v1, v0
; GFX7-NEXT: buffer_store_byte v0, off, s[0:3], 0 ; GFX7-NEXT: buffer_store_byte v0, off, s[0:3], 0
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX8-LABEL: idot8_acc8: ; GFX8-LABEL: idot8_acc8:
; GFX8: ; %bb.0: ; %entry ; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX8-NEXT: s_movk_i32 s2, 0xff
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_load_dword s3, s[6:7], 0x0
; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_load_ubyte v2, v[0:1] ; GFX8-NEXT: flat_load_ubyte v2, v[0:1]
; GFX8-NEXT: s_load_dword s0, s[4:5], 0x0 ; GFX8-NEXT: s_load_dword s1, s[4:5], 0x0
; GFX8-NEXT: s_load_dword s2, s[6:7], 0x0
; GFX8-NEXT: s_movk_i32 s0, 0xff
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_bfe_i32 s6, s3, 0x40000 ; GFX8-NEXT: s_lshr_b32 s3, s1, 12
; GFX8-NEXT: s_lshr_b32 s4, s3, 12 ; GFX8-NEXT: s_bfe_i32 s6, s2, 0x40000
; GFX8-NEXT: s_bfe_i32 s8, s3, 0x40004 ; GFX8-NEXT: s_lshr_b32 s4, s2, 12
; GFX8-NEXT: s_bfe_i32 s10, s3, 0x40008 ; GFX8-NEXT: s_bfe_i32 s8, s2, 0x40004
; GFX8-NEXT: s_lshr_b32 s1, s0, 12 ; GFX8-NEXT: s_bfe_i32 s10, s2, 0x40008
; GFX8-NEXT: s_bfe_i32 s5, s0, 0x40000 ; GFX8-NEXT: s_bfe_i32 s5, s1, 0x40000
; GFX8-NEXT: v_mov_b32_e32 v6, s6 ; GFX8-NEXT: v_mov_b32_e32 v6, s6
; GFX8-NEXT: v_lshlrev_b16_e64 v4, 12, s1 ; GFX8-NEXT: v_lshlrev_b16_e64 v4, 12, s3
; GFX8-NEXT: v_lshlrev_b16_e64 v5, 12, s4 ; GFX8-NEXT: v_lshlrev_b16_e64 v5, 12, s4
; GFX8-NEXT: s_bfe_i32 s7, s0, 0x40004 ; GFX8-NEXT: s_bfe_i32 s7, s1, 0x40004
; GFX8-NEXT: s_bfe_i32 s9, s0, 0x40008 ; GFX8-NEXT: s_bfe_i32 s9, s1, 0x40008
; GFX8-NEXT: v_mov_b32_e32 v3, s10 ; GFX8-NEXT: v_mov_b32_e32 v3, s10
; GFX8-NEXT: v_mov_b32_e32 v7, s8 ; GFX8-NEXT: v_mov_b32_e32 v7, s8
; GFX8-NEXT: v_ashrrev_i16_e32 v4, 12, v4 ; GFX8-NEXT: v_ashrrev_i16_e32 v4, 12, v4
; GFX8-NEXT: v_ashrrev_i16_e32 v5, 12, v5 ; GFX8-NEXT: v_ashrrev_i16_e32 v5, 12, v5
; GFX8-NEXT: v_mul_i32_i24_e32 v3, s9, v3 ; GFX8-NEXT: v_mul_i32_i24_e32 v3, s9, v3
; GFX8-NEXT: s_bfe_i32 s12, s3, 0x40010 ; GFX8-NEXT: s_bfe_i32 s12, s2, 0x40010
; GFX8-NEXT: v_and_b32_e32 v4, s2, v4 ; GFX8-NEXT: v_and_b32_e32 v4, s0, v4
; GFX8-NEXT: v_and_b32_e32 v5, s2, v5 ; GFX8-NEXT: v_and_b32_e32 v5, s0, v5
; GFX8-NEXT: s_bfe_i32 s14, s3, 0x40014 ; GFX8-NEXT: s_bfe_i32 s14, s2, 0x40014
; GFX8-NEXT: s_bfe_i32 s11, s0, 0x40010 ; GFX8-NEXT: s_bfe_i32 s11, s1, 0x40010
; GFX8-NEXT: v_mov_b32_e32 v8, s12 ; GFX8-NEXT: v_mov_b32_e32 v8, s12
; GFX8-NEXT: s_bfe_i32 s16, s3, 0x40018 ; GFX8-NEXT: s_bfe_i32 s16, s2, 0x40018
; GFX8-NEXT: s_bfe_i32 s13, s0, 0x40014 ; GFX8-NEXT: s_bfe_i32 s13, s1, 0x40014
; GFX8-NEXT: v_mov_b32_e32 v9, s14 ; GFX8-NEXT: v_mov_b32_e32 v9, s14
; GFX8-NEXT: s_bfe_i32 s15, s0, 0x40018 ; GFX8-NEXT: s_bfe_i32 s15, s1, 0x40018
; GFX8-NEXT: s_ashr_i32 s3, s3, 28 ; GFX8-NEXT: s_ashr_i32 s2, s2, 28
; GFX8-NEXT: v_mov_b32_e32 v10, s16 ; GFX8-NEXT: v_mov_b32_e32 v10, s16
; GFX8-NEXT: s_ashr_i32 s0, s0, 28 ; GFX8-NEXT: s_ashr_i32 s1, s1, 28
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mad_i32_i24 v2, s5, v6, v2 ; GFX8-NEXT: v_mad_i32_i24 v2, s5, v6, v2
; GFX8-NEXT: v_mad_i32_i24 v2, s7, v7, v2 ; GFX8-NEXT: v_mad_i32_i24 v2, s7, v7, v2
; GFX8-NEXT: v_add_u32_sdwa v2, vcc, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 ; GFX8-NEXT: v_add_u32_sdwa v2, vcc, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
; GFX8-NEXT: v_mad_u32_u24 v2, v4, v5, v2 ; GFX8-NEXT: v_mad_u32_u24 v2, v4, v5, v2
; GFX8-NEXT: v_mad_i32_i24 v2, s11, v8, v2 ; GFX8-NEXT: v_mad_i32_i24 v2, s11, v8, v2
; GFX8-NEXT: v_mad_i32_i24 v2, s13, v9, v2 ; GFX8-NEXT: v_mad_i32_i24 v2, s13, v9, v2
; GFX8-NEXT: v_mad_i32_i24 v2, s15, v10, v2 ; GFX8-NEXT: v_mad_i32_i24 v2, s15, v10, v2
; GFX8-NEXT: v_mov_b32_e32 v3, s3 ; GFX8-NEXT: v_mov_b32_e32 v3, s2
; GFX8-NEXT: v_mad_i32_i24 v2, s0, v3, v2 ; GFX8-NEXT: v_mad_i32_i24 v2, s1, v3, v2
; GFX8-NEXT: flat_store_byte v[0:1], v2 ; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-LABEL: idot8_acc8: ; GFX9-LABEL: idot8_acc8:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-NEXT: s_movk_i32 s2, 0xff
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_load_dword s3, s[6:7], 0x0
; GFX9-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: global_load_ubyte v2, v[0:1], off ; GFX9-NEXT: global_load_ubyte v2, v[0:1], off
; GFX9-NEXT: s_load_dword s0, s[4:5], 0x0 ; GFX9-NEXT: s_load_dword s1, s[4:5], 0x0
; GFX9-NEXT: s_load_dword s2, s[6:7], 0x0
; GFX9-NEXT: s_movk_i32 s0, 0xff
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_bfe_i32 s6, s3, 0x40000 ; GFX9-NEXT: s_lshr_b32 s3, s1, 12
; GFX9-NEXT: s_lshr_b32 s4, s3, 12 ; GFX9-NEXT: s_bfe_i32 s6, s2, 0x40000
; GFX9-NEXT: s_bfe_i32 s8, s3, 0x40004 ; GFX9-NEXT: s_lshr_b32 s4, s2, 12
; GFX9-NEXT: s_bfe_i32 s10, s3, 0x40008 ; GFX9-NEXT: s_bfe_i32 s8, s2, 0x40004
; GFX9-NEXT: s_lshr_b32 s1, s0, 12 ; GFX9-NEXT: s_bfe_i32 s10, s2, 0x40008
; GFX9-NEXT: s_bfe_i32 s5, s0, 0x40000 ; GFX9-NEXT: s_bfe_i32 s5, s1, 0x40000
; GFX9-NEXT: v_mov_b32_e32 v6, s6 ; GFX9-NEXT: v_mov_b32_e32 v6, s6
; GFX9-NEXT: v_lshlrev_b16_e64 v4, 12, s1 ; GFX9-NEXT: v_lshlrev_b16_e64 v4, 12, s3
; GFX9-NEXT: v_lshlrev_b16_e64 v5, 12, s4 ; GFX9-NEXT: v_lshlrev_b16_e64 v5, 12, s4
; GFX9-NEXT: s_bfe_i32 s7, s0, 0x40004 ; GFX9-NEXT: s_bfe_i32 s7, s1, 0x40004
; GFX9-NEXT: s_bfe_i32 s9, s0, 0x40008 ; GFX9-NEXT: s_bfe_i32 s9, s1, 0x40008
; GFX9-NEXT: v_mov_b32_e32 v3, s10 ; GFX9-NEXT: v_mov_b32_e32 v3, s10
; GFX9-NEXT: v_mov_b32_e32 v7, s8 ; GFX9-NEXT: v_mov_b32_e32 v7, s8
; GFX9-NEXT: v_ashrrev_i16_e32 v4, 12, v4 ; GFX9-NEXT: v_ashrrev_i16_e32 v4, 12, v4
; GFX9-NEXT: v_ashrrev_i16_e32 v5, 12, v5 ; GFX9-NEXT: v_ashrrev_i16_e32 v5, 12, v5
; GFX9-NEXT: v_mul_i32_i24_e32 v3, s9, v3 ; GFX9-NEXT: v_mul_i32_i24_e32 v3, s9, v3
; GFX9-NEXT: s_bfe_i32 s12, s3, 0x40010 ; GFX9-NEXT: s_bfe_i32 s12, s2, 0x40010
; GFX9-NEXT: v_and_b32_e32 v4, s2, v4 ; GFX9-NEXT: v_and_b32_e32 v4, s0, v4
; GFX9-NEXT: v_and_b32_e32 v5, s2, v5 ; GFX9-NEXT: v_and_b32_e32 v5, s0, v5
; GFX9-NEXT: s_bfe_i32 s14, s3, 0x40014 ; GFX9-NEXT: s_bfe_i32 s14, s2, 0x40014
; GFX9-NEXT: s_bfe_i32 s11, s0, 0x40010 ; GFX9-NEXT: s_bfe_i32 s11, s1, 0x40010
; GFX9-NEXT: v_mov_b32_e32 v8, s12 ; GFX9-NEXT: v_mov_b32_e32 v8, s12
; GFX9-NEXT: s_bfe_i32 s16, s3, 0x40018 ; GFX9-NEXT: s_bfe_i32 s16, s2, 0x40018
; GFX9-NEXT: s_bfe_i32 s13, s0, 0x40014 ; GFX9-NEXT: s_bfe_i32 s13, s1, 0x40014
; GFX9-NEXT: v_mov_b32_e32 v9, s14 ; GFX9-NEXT: v_mov_b32_e32 v9, s14
; GFX9-NEXT: s_bfe_i32 s15, s0, 0x40018 ; GFX9-NEXT: s_bfe_i32 s15, s1, 0x40018
; GFX9-NEXT: s_ashr_i32 s3, s3, 28 ; GFX9-NEXT: s_ashr_i32 s2, s2, 28
; GFX9-NEXT: v_mov_b32_e32 v10, s16 ; GFX9-NEXT: v_mov_b32_e32 v10, s16
; GFX9-NEXT: s_ashr_i32 s0, s0, 28 ; GFX9-NEXT: s_ashr_i32 s1, s1, 28
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mad_i32_i24 v2, s5, v6, v2 ; GFX9-NEXT: v_mad_i32_i24 v2, s5, v6, v2
; GFX9-NEXT: v_mad_i32_i24 v2, s7, v7, v2 ; GFX9-NEXT: v_mad_i32_i24 v2, s7, v7, v2
; GFX9-NEXT: v_add_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 ; GFX9-NEXT: v_add_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
; GFX9-NEXT: v_mad_u32_u24 v2, v4, v5, v2 ; GFX9-NEXT: v_mad_u32_u24 v2, v4, v5, v2
; GFX9-NEXT: v_mad_i32_i24 v2, s11, v8, v2 ; GFX9-NEXT: v_mad_i32_i24 v2, s11, v8, v2
; GFX9-NEXT: v_mad_i32_i24 v2, s13, v9, v2 ; GFX9-NEXT: v_mad_i32_i24 v2, s13, v9, v2
; GFX9-NEXT: v_mad_i32_i24 v2, s15, v10, v2 ; GFX9-NEXT: v_mad_i32_i24 v2, s15, v10, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s3 ; GFX9-NEXT: v_mov_b32_e32 v3, s2
; GFX9-NEXT: v_mad_i32_i24 v2, s0, v3, v2 ; GFX9-NEXT: v_mad_i32_i24 v2, s1, v3, v2
; GFX9-NEXT: global_store_byte v[0:1], v2, off ; GFX9-NEXT: global_store_byte v[0:1], v2, off
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX9-DL-LABEL: idot8_acc8: ; GFX9-DL-LABEL: idot8_acc8:
; GFX9-DL: ; %bb.0: ; %entry ; GFX9-DL: ; %bb.0: ; %entry
; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-DL-NEXT: s_movk_i32 s2, 0xff
; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DL-NEXT: s_load_dword s3, s[6:7], 0x0
; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-DL-NEXT: global_load_ubyte v2, v[0:1], off ; GFX9-DL-NEXT: global_load_ubyte v2, v[0:1], off
; GFX9-DL-NEXT: s_load_dword s0, s[4:5], 0x0 ; GFX9-DL-NEXT: s_load_dword s1, s[4:5], 0x0
; GFX9-DL-NEXT: s_load_dword s2, s[6:7], 0x0
; GFX9-DL-NEXT: s_movk_i32 s0, 0xff
; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DL-NEXT: s_bfe_i32 s6, s3, 0x40000 ; GFX9-DL-NEXT: s_lshr_b32 s3, s1, 12
; GFX9-DL-NEXT: s_lshr_b32 s4, s3, 12 ; GFX9-DL-NEXT: s_bfe_i32 s6, s2, 0x40000
; GFX9-DL-NEXT: s_bfe_i32 s8, s3, 0x40004 ; GFX9-DL-NEXT: s_lshr_b32 s4, s2, 12
; GFX9-DL-NEXT: s_bfe_i32 s10, s3, 0x40008 ; GFX9-DL-NEXT: s_bfe_i32 s8, s2, 0x40004
; GFX9-DL-NEXT: s_lshr_b32 s1, s0, 12 ; GFX9-DL-NEXT: s_bfe_i32 s10, s2, 0x40008
; GFX9-DL-NEXT: s_bfe_i32 s5, s0, 0x40000 ; GFX9-DL-NEXT: s_bfe_i32 s5, s1, 0x40000
; GFX9-DL-NEXT: v_mov_b32_e32 v6, s6 ; GFX9-DL-NEXT: v_mov_b32_e32 v6, s6
; GFX9-DL-NEXT: v_lshlrev_b16_e64 v4, 12, s1 ; GFX9-DL-NEXT: v_lshlrev_b16_e64 v4, 12, s3
; GFX9-DL-NEXT: v_lshlrev_b16_e64 v5, 12, s4 ; GFX9-DL-NEXT: v_lshlrev_b16_e64 v5, 12, s4
; GFX9-DL-NEXT: s_bfe_i32 s7, s0, 0x40004 ; GFX9-DL-NEXT: s_bfe_i32 s7, s1, 0x40004
; GFX9-DL-NEXT: s_bfe_i32 s9, s0, 0x40008 ; GFX9-DL-NEXT: s_bfe_i32 s9, s1, 0x40008
; GFX9-DL-NEXT: v_mov_b32_e32 v3, s10 ; GFX9-DL-NEXT: v_mov_b32_e32 v3, s10
; GFX9-DL-NEXT: v_mov_b32_e32 v7, s8 ; GFX9-DL-NEXT: v_mov_b32_e32 v7, s8
; GFX9-DL-NEXT: v_ashrrev_i16_e32 v4, 12, v4 ; GFX9-DL-NEXT: v_ashrrev_i16_e32 v4, 12, v4
; GFX9-DL-NEXT: v_ashrrev_i16_e32 v5, 12, v5 ; GFX9-DL-NEXT: v_ashrrev_i16_e32 v5, 12, v5
; GFX9-DL-NEXT: v_mul_i32_i24_e32 v3, s9, v3 ; GFX9-DL-NEXT: v_mul_i32_i24_e32 v3, s9, v3
; GFX9-DL-NEXT: s_bfe_i32 s12, s3, 0x40010 ; GFX9-DL-NEXT: s_bfe_i32 s12, s2, 0x40010
; GFX9-DL-NEXT: v_and_b32_e32 v4, s2, v4 ; GFX9-DL-NEXT: v_and_b32_e32 v4, s0, v4
; GFX9-DL-NEXT: v_and_b32_e32 v5, s2, v5 ; GFX9-DL-NEXT: v_and_b32_e32 v5, s0, v5
; GFX9-DL-NEXT: s_bfe_i32 s14, s3, 0x40014 ; GFX9-DL-NEXT: s_bfe_i32 s14, s2, 0x40014
; GFX9-DL-NEXT: s_bfe_i32 s11, s0, 0x40010 ; GFX9-DL-NEXT: s_bfe_i32 s11, s1, 0x40010
; GFX9-DL-NEXT: v_mov_b32_e32 v8, s12 ; GFX9-DL-NEXT: v_mov_b32_e32 v8, s12
; GFX9-DL-NEXT: s_bfe_i32 s16, s3, 0x40018 ; GFX9-DL-NEXT: s_bfe_i32 s16, s2, 0x40018
; GFX9-DL-NEXT: s_bfe_i32 s13, s0, 0x40014 ; GFX9-DL-NEXT: s_bfe_i32 s13, s1, 0x40014
; GFX9-DL-NEXT: v_mov_b32_e32 v9, s14 ; GFX9-DL-NEXT: v_mov_b32_e32 v9, s14
; GFX9-DL-NEXT: s_bfe_i32 s15, s0, 0x40018 ; GFX9-DL-NEXT: s_bfe_i32 s15, s1, 0x40018
; GFX9-DL-NEXT: s_ashr_i32 s3, s3, 28 ; GFX9-DL-NEXT: s_ashr_i32 s2, s2, 28
; GFX9-DL-NEXT: v_mov_b32_e32 v10, s16 ; GFX9-DL-NEXT: v_mov_b32_e32 v10, s16
; GFX9-DL-NEXT: s_ashr_i32 s0, s0, 28 ; GFX9-DL-NEXT: s_ashr_i32 s1, s1, 28
; GFX9-DL-NEXT: s_waitcnt vmcnt(0) ; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
; GFX9-DL-NEXT: v_mad_i32_i24 v2, s5, v6, v2 ; GFX9-DL-NEXT: v_mad_i32_i24 v2, s5, v6, v2
; GFX9-DL-NEXT: v_mad_i32_i24 v2, s7, v7, v2 ; GFX9-DL-NEXT: v_mad_i32_i24 v2, s7, v7, v2
; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 ; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
; GFX9-DL-NEXT: v_mad_u32_u24 v2, v4, v5, v2 ; GFX9-DL-NEXT: v_mad_u32_u24 v2, v4, v5, v2
; GFX9-DL-NEXT: v_mad_i32_i24 v2, s11, v8, v2 ; GFX9-DL-NEXT: v_mad_i32_i24 v2, s11, v8, v2
; GFX9-DL-NEXT: v_mad_i32_i24 v2, s13, v9, v2 ; GFX9-DL-NEXT: v_mad_i32_i24 v2, s13, v9, v2
; GFX9-DL-NEXT: v_mad_i32_i24 v2, s15, v10, v2 ; GFX9-DL-NEXT: v_mad_i32_i24 v2, s15, v10, v2
; GFX9-DL-NEXT: v_mov_b32_e32 v3, s3 ; GFX9-DL-NEXT: v_mov_b32_e32 v3, s2
; GFX9-DL-NEXT: v_mad_i32_i24 v2, s0, v3, v2 ; GFX9-DL-NEXT: v_mad_i32_i24 v2, s1, v3, v2
; GFX9-DL-NEXT: global_store_byte v[0:1], v2, off ; GFX9-DL-NEXT: global_store_byte v[0:1], v2, off
; GFX9-DL-NEXT: s_endpgm ; GFX9-DL-NEXT: s_endpgm
; ;
; GFX10-DL-LABEL: idot8_acc8: ; GFX10-DL-LABEL: idot8_acc8:
; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
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; GFX7-LABEL: idot8_acc16_vecMul: ; GFX7-LABEL: idot8_acc16_vecMul:
; GFX7: ; %bb.0: ; %entry ; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd ; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: s_mov_b32 s2, -1 ; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_mov_b32 s8, 0xffff ; GFX7-NEXT: s_mov_b32 s8, 0xffff
; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_load_dword s6, s[6:7], 0x0
; GFX7-NEXT: buffer_load_ushort v0, off, s[0:3], 0 ; GFX7-NEXT: buffer_load_ushort v0, off, s[0:3], 0
; GFX7-NEXT: s_load_dword s4, s[4:5], 0x0 ; GFX7-NEXT: s_load_dword s4, s[4:5], 0x0
; GFX7-NEXT: s_load_dword s5, s[6:7], 0x0
; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_bfe_i32 s15, s6, 0x40018 ; GFX7-NEXT: s_ashr_i32 s6, s4, 28
; GFX7-NEXT: s_bfe_i32 s16, s6, 0x40014 ; GFX7-NEXT: s_bfe_i32 s15, s5, 0x40018
; GFX7-NEXT: s_bfe_i32 s17, s6, 0x40010 ; GFX7-NEXT: s_bfe_i32 s16, s5, 0x40014
; GFX7-NEXT: s_bfe_i32 s18, s6, 0x40000 ; GFX7-NEXT: s_bfe_i32 s17, s5, 0x40010
; GFX7-NEXT: s_bfe_i32 s19, s6, 0x40004 ; GFX7-NEXT: s_bfe_i32 s18, s5, 0x40000
; GFX7-NEXT: s_bfe_i32 s20, s6, 0x40008 ; GFX7-NEXT: s_bfe_i32 s19, s5, 0x40004
; GFX7-NEXT: s_ashr_i32 s14, s6, 28 ; GFX7-NEXT: s_bfe_i32 s20, s5, 0x40008
; GFX7-NEXT: s_bfe_i32 s6, s6, 0x4000c ; GFX7-NEXT: s_ashr_i32 s14, s5, 28
; GFX7-NEXT: s_ashr_i32 s5, s4, 28 ; GFX7-NEXT: s_bfe_i32 s5, s5, 0x4000c
; GFX7-NEXT: s_bfe_i32 s7, s4, 0x40018 ; GFX7-NEXT: s_bfe_i32 s7, s4, 0x40018
; GFX7-NEXT: s_bfe_i32 s9, s4, 0x40014 ; GFX7-NEXT: s_bfe_i32 s9, s4, 0x40014
; GFX7-NEXT: s_bfe_i32 s10, s4, 0x40010 ; GFX7-NEXT: s_bfe_i32 s10, s4, 0x40010
; GFX7-NEXT: s_bfe_i32 s11, s4, 0x40000 ; GFX7-NEXT: s_bfe_i32 s11, s4, 0x40000
; GFX7-NEXT: v_mov_b32_e32 v4, s18 ; GFX7-NEXT: v_mov_b32_e32 v4, s18
; GFX7-NEXT: s_bfe_i32 s12, s4, 0x40004 ; GFX7-NEXT: s_bfe_i32 s12, s4, 0x40004
; GFX7-NEXT: v_mov_b32_e32 v3, s19 ; GFX7-NEXT: v_mov_b32_e32 v3, s19
; GFX7-NEXT: s_bfe_i32 s13, s4, 0x40008 ; GFX7-NEXT: s_bfe_i32 s13, s4, 0x40008
; GFX7-NEXT: v_mov_b32_e32 v2, s20 ; GFX7-NEXT: v_mov_b32_e32 v2, s20
; GFX7-NEXT: s_bfe_i32 s4, s4, 0x4000c ; GFX7-NEXT: s_bfe_i32 s4, s4, 0x4000c
; GFX7-NEXT: v_mov_b32_e32 v1, s6 ; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: v_mul_i32_i24_e32 v1, s4, v1 ; GFX7-NEXT: v_mul_i32_i24_e32 v1, s4, v1
; GFX7-NEXT: v_mul_i32_i24_e32 v2, s13, v2 ; GFX7-NEXT: v_mul_i32_i24_e32 v2, s13, v2
; GFX7-NEXT: v_mul_i32_i24_e32 v3, s12, v3 ; GFX7-NEXT: v_mul_i32_i24_e32 v3, s12, v3
; GFX7-NEXT: v_mul_i32_i24_e32 v4, s11, v4 ; GFX7-NEXT: v_mul_i32_i24_e32 v4, s11, v4
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX7-NEXT: v_and_b32_e32 v2, s8, v2 ; GFX7-NEXT: v_and_b32_e32 v2, s8, v2
; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX7-NEXT: v_and_b32_e32 v4, s8, v4 ; GFX7-NEXT: v_and_b32_e32 v4, s8, v4
; GFX7-NEXT: v_or_b32_e32 v1, v2, v1 ; GFX7-NEXT: v_or_b32_e32 v1, v2, v1
; GFX7-NEXT: v_or_b32_e32 v2, v4, v3 ; GFX7-NEXT: v_or_b32_e32 v2, v4, v3
; GFX7-NEXT: v_alignbit_b32 v3, v1, v2, 16 ; GFX7-NEXT: v_alignbit_b32 v3, v1, v2, 16
; GFX7-NEXT: v_lshrrev_b32_e32 v4, 16, v1 ; GFX7-NEXT: v_lshrrev_b32_e32 v4, 16, v1
; GFX7-NEXT: v_mov_b32_e32 v5, s17 ; GFX7-NEXT: v_mov_b32_e32 v5, s17
; GFX7-NEXT: v_mov_b32_e32 v6, s16 ; GFX7-NEXT: v_mov_b32_e32 v6, s16
; GFX7-NEXT: v_mov_b32_e32 v7, s15 ; GFX7-NEXT: v_mov_b32_e32 v7, s15
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX7-NEXT: v_add_i32_e32 v0, vcc, v3, v0 ; GFX7-NEXT: v_add_i32_e32 v0, vcc, v3, v0
; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX7-NEXT: v_add_i32_e32 v0, vcc, v4, v0 ; GFX7-NEXT: v_add_i32_e32 v0, vcc, v4, v0
; GFX7-NEXT: v_mad_i32_i24 v0, s10, v5, v0 ; GFX7-NEXT: v_mad_i32_i24 v0, s10, v5, v0
; GFX7-NEXT: v_mad_i32_i24 v0, s9, v6, v0 ; GFX7-NEXT: v_mad_i32_i24 v0, s9, v6, v0
; GFX7-NEXT: v_mad_i32_i24 v0, s7, v7, v0 ; GFX7-NEXT: v_mad_i32_i24 v0, s7, v7, v0
; GFX7-NEXT: v_mov_b32_e32 v1, s14 ; GFX7-NEXT: v_mov_b32_e32 v1, s14
; GFX7-NEXT: v_mad_i32_i24 v0, s5, v1, v0 ; GFX7-NEXT: v_mad_i32_i24 v0, s6, v1, v0
; GFX7-NEXT: buffer_store_short v0, off, s[0:3], 0 ; GFX7-NEXT: buffer_store_short v0, off, s[0:3], 0
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX8-LABEL: idot8_acc16_vecMul: ; GFX8-LABEL: idot8_acc16_vecMul:
; GFX8: ; %bb.0: ; %entry ; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: v_add_u32_sdwa v2, vcc, v6, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD ; GFX8-NEXT: v_add_u32_sdwa v2, vcc, v6, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
; GFX8-NEXT: flat_store_byte v[0:1], v2 ; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-LABEL: idot8_acc8_vecMul: ; GFX9-LABEL: idot8_acc8_vecMul:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-NEXT: s_mov_b32 s2, 0xffff
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: global_load_ubyte v2, v[0:1], off ; GFX9-NEXT: global_load_ubyte v2, v[0:1], off
; GFX9-NEXT: s_load_dword s0, s[4:5], 0x0 ; GFX9-NEXT: s_load_dword s1, s[4:5], 0x0
; GFX9-NEXT: s_load_dword s1, s[6:7], 0x0 ; GFX9-NEXT: s_load_dword s2, s[6:7], 0x0
; GFX9-NEXT: s_mov_b32 s0, 0xffff
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshr_b32 s7, s0, 4 ; GFX9-NEXT: s_lshr_b32 s7, s1, 4
; GFX9-NEXT: s_lshr_b32 s14, s1, 4 ; GFX9-NEXT: s_lshr_b32 s14, s2, 4
; GFX9-NEXT: v_lshlrev_b16_e64 v3, 12, s0 ; GFX9-NEXT: v_lshlrev_b16_e64 v3, 12, s1
; GFX9-NEXT: v_lshlrev_b16_e64 v4, 12, s1 ; GFX9-NEXT: v_lshlrev_b16_e64 v4, 12, s2
; GFX9-NEXT: v_lshlrev_b16_e64 v7, 12, s7 ; GFX9-NEXT: v_lshlrev_b16_e64 v7, 12, s7
; GFX9-NEXT: v_lshlrev_b16_e64 v14, 12, s14 ; GFX9-NEXT: v_lshlrev_b16_e64 v14, 12, s14
; GFX9-NEXT: s_lshr_b32 s8, s0, 12 ; GFX9-NEXT: s_lshr_b32 s8, s1, 12
; GFX9-NEXT: s_lshr_b32 s9, s0, 8 ; GFX9-NEXT: s_lshr_b32 s9, s1, 8
; GFX9-NEXT: s_lshr_b32 s15, s1, 12 ; GFX9-NEXT: s_lshr_b32 s15, s2, 12
; GFX9-NEXT: s_lshr_b32 s16, s1, 8 ; GFX9-NEXT: s_lshr_b32 s16, s2, 8
; GFX9-NEXT: v_lshlrev_b16_e64 v5, 12, s9 ; GFX9-NEXT: v_lshlrev_b16_e64 v5, 12, s9
; GFX9-NEXT: v_lshlrev_b16_e64 v6, 12, s8 ; GFX9-NEXT: v_lshlrev_b16_e64 v6, 12, s8
; GFX9-NEXT: v_lshlrev_b16_e64 v12, 12, s16 ; GFX9-NEXT: v_lshlrev_b16_e64 v12, 12, s16
; GFX9-NEXT: v_lshlrev_b16_e64 v13, 12, s15 ; GFX9-NEXT: v_lshlrev_b16_e64 v13, 12, s15
; GFX9-NEXT: v_ashrrev_i16_e32 v3, 12, v3 ; GFX9-NEXT: v_ashrrev_i16_e32 v3, 12, v3
; GFX9-NEXT: v_ashrrev_i16_e32 v4, 12, v4 ; GFX9-NEXT: v_ashrrev_i16_e32 v4, 12, v4
; GFX9-NEXT: v_ashrrev_i16_e32 v7, 12, v7 ; GFX9-NEXT: v_ashrrev_i16_e32 v7, 12, v7
; GFX9-NEXT: v_ashrrev_i16_e32 v14, 12, v14 ; GFX9-NEXT: v_ashrrev_i16_e32 v14, 12, v14
; GFX9-NEXT: v_ashrrev_i16_e32 v5, 12, v5 ; GFX9-NEXT: v_ashrrev_i16_e32 v5, 12, v5
; GFX9-NEXT: v_ashrrev_i16_e32 v12, 12, v12 ; GFX9-NEXT: v_ashrrev_i16_e32 v12, 12, v12
; GFX9-NEXT: v_ashrrev_i16_e32 v6, 12, v6 ; GFX9-NEXT: v_ashrrev_i16_e32 v6, 12, v6
; GFX9-NEXT: v_ashrrev_i16_e32 v13, 12, v13 ; GFX9-NEXT: v_ashrrev_i16_e32 v13, 12, v13
; GFX9-NEXT: v_mul_lo_u16_e32 v3, v3, v4 ; GFX9-NEXT: v_mul_lo_u16_e32 v3, v3, v4
; GFX9-NEXT: v_mul_lo_u16_sdwa v7, v7, v14 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-NEXT: v_mul_lo_u16_sdwa v7, v7, v14 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v3, v3, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX9-NEXT: v_or_b32_sdwa v3, v3, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: s_lshr_b32 s3, s0, 20 ; GFX9-NEXT: s_lshr_b32 s3, s1, 20
; GFX9-NEXT: s_lshr_b32 s4, s0, 16 ; GFX9-NEXT: s_lshr_b32 s4, s1, 16
; GFX9-NEXT: s_lshr_b32 s10, s1, 20 ; GFX9-NEXT: s_lshr_b32 s10, s2, 20
; GFX9-NEXT: s_lshr_b32 s11, s1, 16 ; GFX9-NEXT: s_lshr_b32 s11, s2, 16
; GFX9-NEXT: v_mul_lo_u16_sdwa v6, v6, v13 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-NEXT: v_mul_lo_u16_sdwa v6, v6, v13 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_mul_lo_u16_e32 v5, v5, v12 ; GFX9-NEXT: v_mul_lo_u16_e32 v5, v5, v12
; GFX9-NEXT: v_lshlrev_b16_e64 v10, 12, s4 ; GFX9-NEXT: v_lshlrev_b16_e64 v10, 12, s4
; GFX9-NEXT: v_lshlrev_b16_e64 v11, 12, s3 ; GFX9-NEXT: v_lshlrev_b16_e64 v11, 12, s3
; GFX9-NEXT: v_lshlrev_b16_e64 v17, 12, s11 ; GFX9-NEXT: v_lshlrev_b16_e64 v17, 12, s11
; GFX9-NEXT: v_lshlrev_b16_e64 v18, 12, s10 ; GFX9-NEXT: v_lshlrev_b16_e64 v18, 12, s10
; GFX9-NEXT: s_lshr_b32 s5, s0, 28 ; GFX9-NEXT: s_lshr_b32 s5, s1, 28
; GFX9-NEXT: s_lshr_b32 s6, s0, 24 ; GFX9-NEXT: s_lshr_b32 s6, s1, 24
; GFX9-NEXT: s_lshr_b32 s12, s1, 28 ; GFX9-NEXT: s_lshr_b32 s12, s2, 28
; GFX9-NEXT: s_lshr_b32 s13, s1, 24 ; GFX9-NEXT: s_lshr_b32 s13, s2, 24
; GFX9-NEXT: v_and_b32_e32 v3, s2, v3 ; GFX9-NEXT: v_and_b32_e32 v3, s0, v3
; GFX9-NEXT: v_or_b32_sdwa v5, v5, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX9-NEXT: v_or_b32_sdwa v5, v5, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_lshlrev_b16_e64 v8, 12, s6 ; GFX9-NEXT: v_lshlrev_b16_e64 v8, 12, s6
; GFX9-NEXT: v_lshlrev_b16_e64 v9, 12, s5 ; GFX9-NEXT: v_lshlrev_b16_e64 v9, 12, s5
; GFX9-NEXT: v_lshlrev_b16_e64 v15, 12, s13 ; GFX9-NEXT: v_lshlrev_b16_e64 v15, 12, s13
; GFX9-NEXT: v_lshlrev_b16_e64 v16, 12, s12 ; GFX9-NEXT: v_lshlrev_b16_e64 v16, 12, s12
; GFX9-NEXT: v_or_b32_e32 v5, v3, v5 ; GFX9-NEXT: v_or_b32_e32 v5, v3, v5
; GFX9-NEXT: v_ashrrev_i16_e32 v10, 12, v10 ; GFX9-NEXT: v_ashrrev_i16_e32 v10, 12, v10
; GFX9-NEXT: v_ashrrev_i16_e32 v17, 12, v17 ; GFX9-NEXT: v_ashrrev_i16_e32 v17, 12, v17
; GFX9-NEXT: v_ashrrev_i16_e32 v11, 12, v11 ; GFX9-NEXT: v_ashrrev_i16_e32 v11, 12, v11
; GFX9-NEXT: v_ashrrev_i16_e32 v18, 12, v18 ; GFX9-NEXT: v_ashrrev_i16_e32 v18, 12, v18
; GFX9-NEXT: v_ashrrev_i16_e32 v8, 12, v8 ; GFX9-NEXT: v_ashrrev_i16_e32 v8, 12, v8
; GFX9-NEXT: v_ashrrev_i16_e32 v15, 12, v15 ; GFX9-NEXT: v_ashrrev_i16_e32 v15, 12, v15
; GFX9-NEXT: v_ashrrev_i16_e32 v9, 12, v9 ; GFX9-NEXT: v_ashrrev_i16_e32 v9, 12, v9
; GFX9-NEXT: v_ashrrev_i16_e32 v16, 12, v16 ; GFX9-NEXT: v_ashrrev_i16_e32 v16, 12, v16
; GFX9-NEXT: v_mul_lo_u16_sdwa v4, v11, v18 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-NEXT: v_mul_lo_u16_sdwa v4, v11, v18 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_mul_lo_u16_e32 v10, v10, v17 ; GFX9-NEXT: v_mul_lo_u16_e32 v10, v10, v17
; GFX9-NEXT: v_lshrrev_b32_e32 v7, 8, v5 ; GFX9-NEXT: v_lshrrev_b32_e32 v7, 8, v5
; GFX9-NEXT: v_or_b32_sdwa v4, v10, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX9-NEXT: v_or_b32_sdwa v4, v10, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_mul_lo_u16_sdwa v9, v9, v16 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-NEXT: v_mul_lo_u16_sdwa v9, v9, v16 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_mul_lo_u16_e32 v8, v8, v15 ; GFX9-NEXT: v_mul_lo_u16_e32 v8, v8, v15
; GFX9-NEXT: v_or_b32_sdwa v8, v8, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX9-NEXT: v_or_b32_sdwa v8, v8, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_and_b32_e32 v4, s2, v4 ; GFX9-NEXT: v_and_b32_e32 v4, s0, v4
; GFX9-NEXT: v_or_b32_e32 v6, v4, v8 ; GFX9-NEXT: v_or_b32_e32 v6, v4, v8
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
; GFX9-NEXT: v_add_u32_e32 v2, v2, v7 ; GFX9-NEXT: v_add_u32_e32 v2, v2, v7
; GFX9-NEXT: v_add_u32_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_2 ; GFX9-NEXT: v_add_u32_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_2
; GFX9-NEXT: v_add_u32_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3 ; GFX9-NEXT: v_add_u32_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
; GFX9-NEXT: v_add_u32_e32 v2, v2, v4 ; GFX9-NEXT: v_add_u32_e32 v2, v2, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 8, v6 ; GFX9-NEXT: v_lshrrev_b32_e32 v3, 8, v6
; GFX9-NEXT: v_add_u32_e32 v2, v2, v3 ; GFX9-NEXT: v_add_u32_e32 v2, v2, v3
; GFX9-NEXT: v_add_u32_sdwa v2, v2, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX9-NEXT: v_add_u32_sdwa v2, v2, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9-NEXT: v_add_u32_sdwa v2, v2, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3 ; GFX9-NEXT: v_add_u32_sdwa v2, v2, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
; GFX9-NEXT: global_store_byte v[0:1], v2, off ; GFX9-NEXT: global_store_byte v[0:1], v2, off
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX9-DL-LABEL: idot8_acc8_vecMul: ; GFX9-DL-LABEL: idot8_acc8_vecMul:
; GFX9-DL: ; %bb.0: ; %entry ; GFX9-DL: ; %bb.0: ; %entry
; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-DL-NEXT: s_mov_b32 s2, 0xffff
; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-DL-NEXT: global_load_ubyte v2, v[0:1], off ; GFX9-DL-NEXT: global_load_ubyte v2, v[0:1], off
; GFX9-DL-NEXT: s_load_dword s0, s[4:5], 0x0 ; GFX9-DL-NEXT: s_load_dword s1, s[4:5], 0x0
; GFX9-DL-NEXT: s_load_dword s1, s[6:7], 0x0 ; GFX9-DL-NEXT: s_load_dword s2, s[6:7], 0x0
; GFX9-DL-NEXT: s_mov_b32 s0, 0xffff
; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DL-NEXT: s_lshr_b32 s7, s0, 4 ; GFX9-DL-NEXT: s_lshr_b32 s7, s1, 4
; GFX9-DL-NEXT: s_lshr_b32 s14, s1, 4 ; GFX9-DL-NEXT: s_lshr_b32 s14, s2, 4
; GFX9-DL-NEXT: v_lshlrev_b16_e64 v3, 12, s0 ; GFX9-DL-NEXT: v_lshlrev_b16_e64 v3, 12, s1
; GFX9-DL-NEXT: v_lshlrev_b16_e64 v4, 12, s1 ; GFX9-DL-NEXT: v_lshlrev_b16_e64 v4, 12, s2
; GFX9-DL-NEXT: v_lshlrev_b16_e64 v7, 12, s7 ; GFX9-DL-NEXT: v_lshlrev_b16_e64 v7, 12, s7
; GFX9-DL-NEXT: v_lshlrev_b16_e64 v14, 12, s14 ; GFX9-DL-NEXT: v_lshlrev_b16_e64 v14, 12, s14
; GFX9-DL-NEXT: s_lshr_b32 s8, s0, 12 ; GFX9-DL-NEXT: s_lshr_b32 s8, s1, 12
; GFX9-DL-NEXT: s_lshr_b32 s9, s0, 8 ; GFX9-DL-NEXT: s_lshr_b32 s9, s1, 8
; GFX9-DL-NEXT: s_lshr_b32 s15, s1, 12 ; GFX9-DL-NEXT: s_lshr_b32 s15, s2, 12
; GFX9-DL-NEXT: s_lshr_b32 s16, s1, 8 ; GFX9-DL-NEXT: s_lshr_b32 s16, s2, 8
; GFX9-DL-NEXT: v_lshlrev_b16_e64 v5, 12, s9 ; GFX9-DL-NEXT: v_lshlrev_b16_e64 v5, 12, s9
; GFX9-DL-NEXT: v_lshlrev_b16_e64 v6, 12, s8 ; GFX9-DL-NEXT: v_lshlrev_b16_e64 v6, 12, s8
; GFX9-DL-NEXT: v_lshlrev_b16_e64 v12, 12, s16 ; GFX9-DL-NEXT: v_lshlrev_b16_e64 v12, 12, s16
; GFX9-DL-NEXT: v_lshlrev_b16_e64 v13, 12, s15 ; GFX9-DL-NEXT: v_lshlrev_b16_e64 v13, 12, s15
; GFX9-DL-NEXT: v_ashrrev_i16_e32 v3, 12, v3 ; GFX9-DL-NEXT: v_ashrrev_i16_e32 v3, 12, v3
; GFX9-DL-NEXT: v_ashrrev_i16_e32 v4, 12, v4 ; GFX9-DL-NEXT: v_ashrrev_i16_e32 v4, 12, v4
; GFX9-DL-NEXT: v_ashrrev_i16_e32 v7, 12, v7 ; GFX9-DL-NEXT: v_ashrrev_i16_e32 v7, 12, v7
; GFX9-DL-NEXT: v_ashrrev_i16_e32 v14, 12, v14 ; GFX9-DL-NEXT: v_ashrrev_i16_e32 v14, 12, v14
; GFX9-DL-NEXT: v_ashrrev_i16_e32 v5, 12, v5 ; GFX9-DL-NEXT: v_ashrrev_i16_e32 v5, 12, v5
; GFX9-DL-NEXT: v_ashrrev_i16_e32 v12, 12, v12 ; GFX9-DL-NEXT: v_ashrrev_i16_e32 v12, 12, v12
; GFX9-DL-NEXT: v_ashrrev_i16_e32 v6, 12, v6 ; GFX9-DL-NEXT: v_ashrrev_i16_e32 v6, 12, v6
; GFX9-DL-NEXT: v_ashrrev_i16_e32 v13, 12, v13 ; GFX9-DL-NEXT: v_ashrrev_i16_e32 v13, 12, v13
; GFX9-DL-NEXT: v_mul_lo_u16_e32 v3, v3, v4 ; GFX9-DL-NEXT: v_mul_lo_u16_e32 v3, v3, v4
; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v7, v7, v14 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v7, v7, v14 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-DL-NEXT: v_or_b32_sdwa v3, v3, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX9-DL-NEXT: v_or_b32_sdwa v3, v3, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-DL-NEXT: s_lshr_b32 s3, s0, 20 ; GFX9-DL-NEXT: s_lshr_b32 s3, s1, 20
; GFX9-DL-NEXT: s_lshr_b32 s4, s0, 16 ; GFX9-DL-NEXT: s_lshr_b32 s4, s1, 16
; GFX9-DL-NEXT: s_lshr_b32 s10, s1, 20 ; GFX9-DL-NEXT: s_lshr_b32 s10, s2, 20
; GFX9-DL-NEXT: s_lshr_b32 s11, s1, 16 ; GFX9-DL-NEXT: s_lshr_b32 s11, s2, 16
; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v6, v6, v13 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v6, v6, v13 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-DL-NEXT: v_mul_lo_u16_e32 v5, v5, v12 ; GFX9-DL-NEXT: v_mul_lo_u16_e32 v5, v5, v12
; GFX9-DL-NEXT: v_lshlrev_b16_e64 v10, 12, s4 ; GFX9-DL-NEXT: v_lshlrev_b16_e64 v10, 12, s4
; GFX9-DL-NEXT: v_lshlrev_b16_e64 v11, 12, s3 ; GFX9-DL-NEXT: v_lshlrev_b16_e64 v11, 12, s3
; GFX9-DL-NEXT: v_lshlrev_b16_e64 v17, 12, s11 ; GFX9-DL-NEXT: v_lshlrev_b16_e64 v17, 12, s11
; GFX9-DL-NEXT: v_lshlrev_b16_e64 v18, 12, s10 ; GFX9-DL-NEXT: v_lshlrev_b16_e64 v18, 12, s10
; GFX9-DL-NEXT: s_lshr_b32 s5, s0, 28 ; GFX9-DL-NEXT: s_lshr_b32 s5, s1, 28
; GFX9-DL-NEXT: s_lshr_b32 s6, s0, 24 ; GFX9-DL-NEXT: s_lshr_b32 s6, s1, 24
; GFX9-DL-NEXT: s_lshr_b32 s12, s1, 28 ; GFX9-DL-NEXT: s_lshr_b32 s12, s2, 28
; GFX9-DL-NEXT: s_lshr_b32 s13, s1, 24 ; GFX9-DL-NEXT: s_lshr_b32 s13, s2, 24
; GFX9-DL-NEXT: v_and_b32_e32 v3, s2, v3 ; GFX9-DL-NEXT: v_and_b32_e32 v3, s0, v3
; GFX9-DL-NEXT: v_or_b32_sdwa v5, v5, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX9-DL-NEXT: v_or_b32_sdwa v5, v5, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-DL-NEXT: v_lshlrev_b16_e64 v8, 12, s6 ; GFX9-DL-NEXT: v_lshlrev_b16_e64 v8, 12, s6
; GFX9-DL-NEXT: v_lshlrev_b16_e64 v9, 12, s5 ; GFX9-DL-NEXT: v_lshlrev_b16_e64 v9, 12, s5
; GFX9-DL-NEXT: v_lshlrev_b16_e64 v15, 12, s13 ; GFX9-DL-NEXT: v_lshlrev_b16_e64 v15, 12, s13
; GFX9-DL-NEXT: v_lshlrev_b16_e64 v16, 12, s12 ; GFX9-DL-NEXT: v_lshlrev_b16_e64 v16, 12, s12
; GFX9-DL-NEXT: v_or_b32_e32 v5, v3, v5 ; GFX9-DL-NEXT: v_or_b32_e32 v5, v3, v5
; GFX9-DL-NEXT: v_ashrrev_i16_e32 v10, 12, v10 ; GFX9-DL-NEXT: v_ashrrev_i16_e32 v10, 12, v10
; GFX9-DL-NEXT: v_ashrrev_i16_e32 v17, 12, v17 ; GFX9-DL-NEXT: v_ashrrev_i16_e32 v17, 12, v17
; GFX9-DL-NEXT: v_ashrrev_i16_e32 v11, 12, v11 ; GFX9-DL-NEXT: v_ashrrev_i16_e32 v11, 12, v11
; GFX9-DL-NEXT: v_ashrrev_i16_e32 v18, 12, v18 ; GFX9-DL-NEXT: v_ashrrev_i16_e32 v18, 12, v18
; GFX9-DL-NEXT: v_ashrrev_i16_e32 v8, 12, v8 ; GFX9-DL-NEXT: v_ashrrev_i16_e32 v8, 12, v8
; GFX9-DL-NEXT: v_ashrrev_i16_e32 v15, 12, v15 ; GFX9-DL-NEXT: v_ashrrev_i16_e32 v15, 12, v15
; GFX9-DL-NEXT: v_ashrrev_i16_e32 v9, 12, v9 ; GFX9-DL-NEXT: v_ashrrev_i16_e32 v9, 12, v9
; GFX9-DL-NEXT: v_ashrrev_i16_e32 v16, 12, v16 ; GFX9-DL-NEXT: v_ashrrev_i16_e32 v16, 12, v16
; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v4, v11, v18 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v4, v11, v18 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-DL-NEXT: v_mul_lo_u16_e32 v10, v10, v17 ; GFX9-DL-NEXT: v_mul_lo_u16_e32 v10, v10, v17
; GFX9-DL-NEXT: v_lshrrev_b32_e32 v7, 8, v5 ; GFX9-DL-NEXT: v_lshrrev_b32_e32 v7, 8, v5
; GFX9-DL-NEXT: v_or_b32_sdwa v4, v10, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX9-DL-NEXT: v_or_b32_sdwa v4, v10, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v9, v9, v16 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v9, v9, v16 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-DL-NEXT: v_mul_lo_u16_e32 v8, v8, v15 ; GFX9-DL-NEXT: v_mul_lo_u16_e32 v8, v8, v15
; GFX9-DL-NEXT: v_or_b32_sdwa v8, v8, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX9-DL-NEXT: v_or_b32_sdwa v8, v8, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-DL-NEXT: v_and_b32_e32 v4, s2, v4 ; GFX9-DL-NEXT: v_and_b32_e32 v4, s0, v4
; GFX9-DL-NEXT: v_or_b32_e32 v6, v4, v8 ; GFX9-DL-NEXT: v_or_b32_e32 v6, v4, v8
; GFX9-DL-NEXT: s_waitcnt vmcnt(0) ; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
; GFX9-DL-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-DL-NEXT: v_add_u32_e32 v2, v3, v2
; GFX9-DL-NEXT: v_add_u32_e32 v2, v2, v7 ; GFX9-DL-NEXT: v_add_u32_e32 v2, v2, v7
; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_2 ; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_2
; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3 ; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
; GFX9-DL-NEXT: v_add_u32_e32 v2, v2, v4 ; GFX9-DL-NEXT: v_add_u32_e32 v2, v2, v4
; GFX9-DL-NEXT: v_lshrrev_b32_e32 v3, 8, v6 ; GFX9-DL-NEXT: v_lshrrev_b32_e32 v3, 8, v6
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llvm/test/CodeGen/AMDGPU/idot8u.ll

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; GFX8-NEXT: v_add_u32_sdwa v2, vcc, v6, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD ; GFX8-NEXT: v_add_u32_sdwa v2, vcc, v6, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
; GFX8-NEXT: flat_store_byte v[0:1], v2 ; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-LABEL: udot8_acc8_vecMul: ; GFX9-LABEL: udot8_acc8_vecMul:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-NEXT: s_mov_b32 s2, 0xffff
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: global_load_ubyte v2, v[0:1], off ; GFX9-NEXT: global_load_ubyte v2, v[0:1], off
; GFX9-NEXT: s_load_dword s0, s[4:5], 0x0 ; GFX9-NEXT: s_load_dword s1, s[4:5], 0x0
; GFX9-NEXT: s_load_dword s1, s[6:7], 0x0 ; GFX9-NEXT: s_load_dword s2, s[6:7], 0x0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_mov_b32 s0, 0xffff
; GFX9-NEXT: s_bfe_u32 s3, s0, 0x40010 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_bfe_u32 s10, s1, 0x40010 ; GFX9-NEXT: s_bfe_u32 s3, s1, 0x40010
; GFX9-NEXT: s_bfe_u32 s11, s1, 0x40014 ; GFX9-NEXT: s_bfe_u32 s10, s2, 0x40010
; GFX9-NEXT: s_bfe_u32 s12, s1, 0x40018 ; GFX9-NEXT: s_bfe_u32 s11, s2, 0x40014
; GFX9-NEXT: s_lshr_b32 s13, s1, 28 ; GFX9-NEXT: s_bfe_u32 s12, s2, 0x40018
; GFX9-NEXT: s_and_b32 s14, s1, 15 ; GFX9-NEXT: s_lshr_b32 s13, s2, 28
; GFX9-NEXT: s_bfe_u32 s15, s1, 0x40004 ; GFX9-NEXT: s_and_b32 s14, s2, 15
; GFX9-NEXT: s_bfe_u32 s16, s1, 0x40008 ; GFX9-NEXT: s_bfe_u32 s15, s2, 0x40004
; GFX9-NEXT: s_bfe_u32 s16, s2, 0x40008
; GFX9-NEXT: v_mov_b32_e32 v3, s10 ; GFX9-NEXT: v_mov_b32_e32 v3, s10
; GFX9-NEXT: s_bfe_u32 s1, s1, 0x4000c ; GFX9-NEXT: s_bfe_u32 s2, s2, 0x4000c
; GFX9-NEXT: s_bfe_u32 s4, s0, 0x40014 ; GFX9-NEXT: s_bfe_u32 s4, s1, 0x40014
; GFX9-NEXT: v_mov_b32_e32 v4, s11 ; GFX9-NEXT: v_mov_b32_e32 v4, s11
; GFX9-NEXT: s_bfe_u32 s5, s0, 0x40018 ; GFX9-NEXT: s_bfe_u32 s5, s1, 0x40018
; GFX9-NEXT: v_mov_b32_e32 v5, s12 ; GFX9-NEXT: v_mov_b32_e32 v5, s12
; GFX9-NEXT: s_lshr_b32 s6, s0, 28 ; GFX9-NEXT: s_lshr_b32 s6, s1, 28
; GFX9-NEXT: v_mov_b32_e32 v6, s13 ; GFX9-NEXT: v_mov_b32_e32 v6, s13
; GFX9-NEXT: s_and_b32 s7, s0, 15 ; GFX9-NEXT: s_and_b32 s7, s1, 15
; GFX9-NEXT: v_mov_b32_e32 v7, s14 ; GFX9-NEXT: v_mov_b32_e32 v7, s14
; GFX9-NEXT: s_bfe_u32 s8, s0, 0x40004 ; GFX9-NEXT: s_bfe_u32 s8, s1, 0x40004
; GFX9-NEXT: v_mov_b32_e32 v8, s15 ; GFX9-NEXT: v_mov_b32_e32 v8, s15
; GFX9-NEXT: s_bfe_u32 s9, s0, 0x40008 ; GFX9-NEXT: s_bfe_u32 s9, s1, 0x40008
; GFX9-NEXT: v_mov_b32_e32 v9, s16 ; GFX9-NEXT: v_mov_b32_e32 v9, s16
; GFX9-NEXT: s_bfe_u32 s0, s0, 0x4000c ; GFX9-NEXT: s_bfe_u32 s1, s1, 0x4000c
; GFX9-NEXT: v_mov_b32_e32 v10, s1 ; GFX9-NEXT: v_mov_b32_e32 v10, s2
; GFX9-NEXT: v_mul_lo_u16_e32 v3, s3, v3 ; GFX9-NEXT: v_mul_lo_u16_e32 v3, s3, v3
; GFX9-NEXT: v_mul_lo_u16_sdwa v4, s4, v4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-NEXT: v_mul_lo_u16_sdwa v4, s4, v4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_mul_lo_u16_e32 v5, s5, v5 ; GFX9-NEXT: v_mul_lo_u16_e32 v5, s5, v5
; GFX9-NEXT: v_mul_lo_u16_sdwa v6, s6, v6 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-NEXT: v_mul_lo_u16_sdwa v6, s6, v6 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_mul_lo_u16_e32 v7, s7, v7 ; GFX9-NEXT: v_mul_lo_u16_e32 v7, s7, v7
; GFX9-NEXT: v_mul_lo_u16_sdwa v8, s8, v8 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-NEXT: v_mul_lo_u16_sdwa v8, s8, v8 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4 ; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-NEXT: v_or_b32_sdwa v4, v5, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v5, v7, v8 ; GFX9-NEXT: v_or_b32_e32 v5, v7, v8
; GFX9-NEXT: v_mul_lo_u16_e32 v9, s9, v9 ; GFX9-NEXT: v_mul_lo_u16_e32 v9, s9, v9
; GFX9-NEXT: v_mul_lo_u16_sdwa v10, s0, v10 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-NEXT: v_mul_lo_u16_sdwa v10, s1, v10 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_and_b32_e32 v5, s2, v5 ; GFX9-NEXT: v_and_b32_e32 v5, s0, v5
; GFX9-NEXT: v_or_b32_sdwa v6, v9, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-NEXT: v_or_b32_sdwa v6, v9, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v6, v5, v6 ; GFX9-NEXT: v_or_b32_e32 v6, v5, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v7, 8, v6 ; GFX9-NEXT: v_lshrrev_b32_e32 v7, 8, v6
; GFX9-NEXT: v_and_b32_e32 v3, s2, v3 ; GFX9-NEXT: v_and_b32_e32 v3, s0, v3
; GFX9-NEXT: v_or_b32_e32 v4, v3, v4 ; GFX9-NEXT: v_or_b32_e32 v4, v3, v4
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v2, v5, v2 ; GFX9-NEXT: v_add_u32_e32 v2, v5, v2
; GFX9-NEXT: v_add_u32_e32 v2, v2, v7 ; GFX9-NEXT: v_add_u32_e32 v2, v2, v7
; GFX9-NEXT: v_add_u32_sdwa v2, v2, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_2 ; GFX9-NEXT: v_add_u32_sdwa v2, v2, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_2
; GFX9-NEXT: v_add_u32_sdwa v2, v2, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3 ; GFX9-NEXT: v_add_u32_sdwa v2, v2, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
; GFX9-NEXT: v_add_u32_e32 v2, v2, v3 ; GFX9-NEXT: v_add_u32_e32 v2, v2, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 8, v4 ; GFX9-NEXT: v_lshrrev_b32_e32 v3, 8, v4
; GFX9-NEXT: v_add_u32_e32 v2, v2, v3 ; GFX9-NEXT: v_add_u32_e32 v2, v2, v3
; GFX9-NEXT: v_add_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX9-NEXT: v_add_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9-NEXT: v_add_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3 ; GFX9-NEXT: v_add_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
; GFX9-NEXT: global_store_byte v[0:1], v2, off ; GFX9-NEXT: global_store_byte v[0:1], v2, off
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX9-DL-LABEL: udot8_acc8_vecMul: ; GFX9-DL-LABEL: udot8_acc8_vecMul:
; GFX9-DL: ; %bb.0: ; %entry ; GFX9-DL: ; %bb.0: ; %entry
; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-DL-NEXT: s_mov_b32 s2, 0xffff
; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-DL-NEXT: global_load_ubyte v2, v[0:1], off ; GFX9-DL-NEXT: global_load_ubyte v2, v[0:1], off
; GFX9-DL-NEXT: s_load_dword s0, s[4:5], 0x0 ; GFX9-DL-NEXT: s_load_dword s1, s[4:5], 0x0
; GFX9-DL-NEXT: s_load_dword s1, s[6:7], 0x0 ; GFX9-DL-NEXT: s_load_dword s2, s[6:7], 0x0
; GFX9-DL-NEXT: s_mov_b32 s0, 0xffff
; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DL-NEXT: s_bfe_u32 s3, s0, 0x40010 ; GFX9-DL-NEXT: s_bfe_u32 s3, s1, 0x40010
; GFX9-DL-NEXT: s_bfe_u32 s10, s1, 0x40010 ; GFX9-DL-NEXT: s_bfe_u32 s10, s2, 0x40010
; GFX9-DL-NEXT: s_bfe_u32 s11, s1, 0x40014 ; GFX9-DL-NEXT: s_bfe_u32 s11, s2, 0x40014
; GFX9-DL-NEXT: s_bfe_u32 s12, s1, 0x40018 ; GFX9-DL-NEXT: s_bfe_u32 s12, s2, 0x40018
; GFX9-DL-NEXT: s_lshr_b32 s13, s1, 28 ; GFX9-DL-NEXT: s_lshr_b32 s13, s2, 28
; GFX9-DL-NEXT: s_and_b32 s14, s1, 15 ; GFX9-DL-NEXT: s_and_b32 s14, s2, 15
; GFX9-DL-NEXT: s_bfe_u32 s15, s1, 0x40004 ; GFX9-DL-NEXT: s_bfe_u32 s15, s2, 0x40004
; GFX9-DL-NEXT: s_bfe_u32 s16, s1, 0x40008 ; GFX9-DL-NEXT: s_bfe_u32 s16, s2, 0x40008
; GFX9-DL-NEXT: v_mov_b32_e32 v3, s10 ; GFX9-DL-NEXT: v_mov_b32_e32 v3, s10
; GFX9-DL-NEXT: s_bfe_u32 s1, s1, 0x4000c ; GFX9-DL-NEXT: s_bfe_u32 s2, s2, 0x4000c
; GFX9-DL-NEXT: s_bfe_u32 s4, s0, 0x40014 ; GFX9-DL-NEXT: s_bfe_u32 s4, s1, 0x40014
; GFX9-DL-NEXT: v_mov_b32_e32 v4, s11 ; GFX9-DL-NEXT: v_mov_b32_e32 v4, s11
; GFX9-DL-NEXT: s_bfe_u32 s5, s0, 0x40018 ; GFX9-DL-NEXT: s_bfe_u32 s5, s1, 0x40018
; GFX9-DL-NEXT: v_mov_b32_e32 v5, s12 ; GFX9-DL-NEXT: v_mov_b32_e32 v5, s12
; GFX9-DL-NEXT: s_lshr_b32 s6, s0, 28 ; GFX9-DL-NEXT: s_lshr_b32 s6, s1, 28
; GFX9-DL-NEXT: v_mov_b32_e32 v6, s13 ; GFX9-DL-NEXT: v_mov_b32_e32 v6, s13
; GFX9-DL-NEXT: s_and_b32 s7, s0, 15 ; GFX9-DL-NEXT: s_and_b32 s7, s1, 15
; GFX9-DL-NEXT: v_mov_b32_e32 v7, s14 ; GFX9-DL-NEXT: v_mov_b32_e32 v7, s14
; GFX9-DL-NEXT: s_bfe_u32 s8, s0, 0x40004 ; GFX9-DL-NEXT: s_bfe_u32 s8, s1, 0x40004
; GFX9-DL-NEXT: v_mov_b32_e32 v8, s15 ; GFX9-DL-NEXT: v_mov_b32_e32 v8, s15
; GFX9-DL-NEXT: s_bfe_u32 s9, s0, 0x40008 ; GFX9-DL-NEXT: s_bfe_u32 s9, s1, 0x40008
; GFX9-DL-NEXT: v_mov_b32_e32 v9, s16 ; GFX9-DL-NEXT: v_mov_b32_e32 v9, s16
; GFX9-DL-NEXT: s_bfe_u32 s0, s0, 0x4000c ; GFX9-DL-NEXT: s_bfe_u32 s1, s1, 0x4000c
; GFX9-DL-NEXT: v_mov_b32_e32 v10, s1 ; GFX9-DL-NEXT: v_mov_b32_e32 v10, s2
; GFX9-DL-NEXT: v_mul_lo_u16_e32 v3, s3, v3 ; GFX9-DL-NEXT: v_mul_lo_u16_e32 v3, s3, v3
; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v4, s4, v4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v4, s4, v4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-DL-NEXT: v_mul_lo_u16_e32 v5, s5, v5 ; GFX9-DL-NEXT: v_mul_lo_u16_e32 v5, s5, v5
; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v6, s6, v6 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v6, s6, v6 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-DL-NEXT: v_mul_lo_u16_e32 v7, s7, v7 ; GFX9-DL-NEXT: v_mul_lo_u16_e32 v7, s7, v7
; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v8, s8, v8 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v8, s8, v8 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-DL-NEXT: v_or_b32_e32 v3, v3, v4 ; GFX9-DL-NEXT: v_or_b32_e32 v3, v3, v4
; GFX9-DL-NEXT: v_or_b32_sdwa v4, v5, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-DL-NEXT: v_or_b32_sdwa v4, v5, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-DL-NEXT: v_or_b32_e32 v5, v7, v8 ; GFX9-DL-NEXT: v_or_b32_e32 v5, v7, v8
; GFX9-DL-NEXT: v_mul_lo_u16_e32 v9, s9, v9 ; GFX9-DL-NEXT: v_mul_lo_u16_e32 v9, s9, v9
; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v10, s0, v10 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v10, s1, v10 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-DL-NEXT: v_and_b32_e32 v5, s2, v5 ; GFX9-DL-NEXT: v_and_b32_e32 v5, s0, v5
; GFX9-DL-NEXT: v_or_b32_sdwa v6, v9, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-DL-NEXT: v_or_b32_sdwa v6, v9, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-DL-NEXT: v_or_b32_e32 v6, v5, v6 ; GFX9-DL-NEXT: v_or_b32_e32 v6, v5, v6
; GFX9-DL-NEXT: v_lshrrev_b32_e32 v7, 8, v6 ; GFX9-DL-NEXT: v_lshrrev_b32_e32 v7, 8, v6
; GFX9-DL-NEXT: v_and_b32_e32 v3, s2, v3 ; GFX9-DL-NEXT: v_and_b32_e32 v3, s0, v3
; GFX9-DL-NEXT: v_or_b32_e32 v4, v3, v4 ; GFX9-DL-NEXT: v_or_b32_e32 v4, v3, v4
; GFX9-DL-NEXT: s_waitcnt vmcnt(0) ; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
; GFX9-DL-NEXT: v_add_u32_e32 v2, v5, v2 ; GFX9-DL-NEXT: v_add_u32_e32 v2, v5, v2
; GFX9-DL-NEXT: v_add_u32_e32 v2, v2, v7 ; GFX9-DL-NEXT: v_add_u32_e32 v2, v2, v7
; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_2 ; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_2
; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3 ; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
; GFX9-DL-NEXT: v_add_u32_e32 v2, v2, v3 ; GFX9-DL-NEXT: v_add_u32_e32 v2, v2, v3
; GFX9-DL-NEXT: v_lshrrev_b32_e32 v3, 8, v4 ; GFX9-DL-NEXT: v_lshrrev_b32_e32 v3, 8, v4
▲ Show 20 Lines • Show All 616 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll

Show First 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
; VI-NEXT: flat_store_dword v[0:1], v2 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; CI-LABEL: s_insertelement_v2i16_0_reg: ; CI-LABEL: s_insertelement_v2i16_0_reg:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; CI-NEXT: s_load_dword s4, s[4:5], 0xc ; CI-NEXT: s_load_dword s4, s[4:5], 0xc
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_load_dword s2, s[2:3], 0x0
; CI-NEXT: v_mov_b32_e32 v0, s0 ; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: s_load_dword s0, s[2:3], 0x0
; CI-NEXT: v_mov_b32_e32 v1, s1 ; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: s_and_b32 s1, s4, 0xffff ; CI-NEXT: s_and_b32 s1, s4, 0xffff
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_and_b32 s0, s0, 0xffff0000 ; CI-NEXT: s_and_b32 s0, s2, 0xffff0000
; CI-NEXT: s_or_b32 s0, s1, s0 ; CI-NEXT: s_or_b32 s0, s1, s0
; CI-NEXT: v_mov_b32_e32 v2, s0 ; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_store_dword v[0:1], v2 ; CI-NEXT: flat_store_dword v[0:1], v2
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
%vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr %vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr
%vecins = insertelement <2 x i16> %vec, i16 %elt, i32 0 %vecins = insertelement <2 x i16> %vec, i16 %elt, i32 0
store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @s_insertelement_v2i16_0_multi_use_hi_reg(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(4)* %vec.ptr, [8 x i32], i16 %elt) #0 { define amdgpu_kernel void @s_insertelement_v2i16_0_multi_use_hi_reg(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(4)* %vec.ptr, [8 x i32], i16 %elt) #0 {
; GFX9-LABEL: s_insertelement_v2i16_0_multi_use_hi_reg: ; GFX9-LABEL: s_insertelement_v2i16_0_multi_use_hi_reg:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX9-NEXT: s_load_dword s4, s[4:5], 0x30 ; GFX9-NEXT: s_load_dword s4, s[4:5], 0x30
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_load_dword s2, s[2:3], 0x0
; GFX9-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: s_load_dword s0, s[2:3], 0x0
; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshr_b32 s0, s0, 16 ; GFX9-NEXT: s_lshr_b32 s0, s2, 16
; GFX9-NEXT: s_pack_ll_b32_b16 s1, s4, s0 ; GFX9-NEXT: s_pack_ll_b32_b16 s1, s4, s0
; GFX9-NEXT: v_mov_b32_e32 v2, s1 ; GFX9-NEXT: v_mov_b32_e32 v2, s1
; GFX9-NEXT: global_store_dword v[0:1], v2, off ; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: ;;#ASMSTART ; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s0 ; GFX9-NEXT: ; use s0
; GFX9-NEXT: ;;#ASMEND ; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
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; VI-NEXT: ;;#ASMEND ; VI-NEXT: ;;#ASMEND
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; CI-LABEL: s_insertelement_v2i16_0_multi_use_hi_reg: ; CI-LABEL: s_insertelement_v2i16_0_multi_use_hi_reg:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; CI-NEXT: s_load_dword s4, s[4:5], 0xc ; CI-NEXT: s_load_dword s4, s[4:5], 0xc
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s0 ; CI-NEXT: s_load_dword s2, s[2:3], 0x0
; CI-NEXT: s_load_dword s0, s[2:3], 0x0
; CI-NEXT: v_mov_b32_e32 v1, s1 ; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: s_and_b32 s1, s4, 0xffff ; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: s_and_b32 s0, s4, 0xffff
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_lshr_b32 s0, s0, 16 ; CI-NEXT: s_lshr_b32 s1, s2, 16
; CI-NEXT: s_lshl_b32 s2, s0, 16 ; CI-NEXT: s_lshl_b32 s2, s1, 16
; CI-NEXT: s_or_b32 s1, s1, s2 ; CI-NEXT: s_or_b32 s0, s0, s2
; CI-NEXT: v_mov_b32_e32 v2, s1 ; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_store_dword v[0:1], v2 ; CI-NEXT: flat_store_dword v[0:1], v2
; CI-NEXT: ;;#ASMSTART ; CI-NEXT: ;;#ASMSTART
; CI-NEXT: ; use s0 ; CI-NEXT: ; use s1
; CI-NEXT: ;;#ASMEND ; CI-NEXT: ;;#ASMEND
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
%vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr %vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr
%elt1 = extractelement <2 x i16> %vec, i32 1 %elt1 = extractelement <2 x i16> %vec, i32 1
%vecins = insertelement <2 x i16> %vec, i16 %elt, i32 0 %vecins = insertelement <2 x i16> %vec, i16 %elt, i32 0
store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out
%use1 = zext i16 %elt1 to i32 %use1 = zext i16 %elt1 to i32
call void asm sideeffect "; use $0", "s"(i32 %use1) #0 call void asm sideeffect "; use $0", "s"(i32 %use1) #0
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; VI-NEXT: flat_store_dword v[0:1], v2 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; CI-LABEL: s_insertelement_v2i16_0_reghi: ; CI-LABEL: s_insertelement_v2i16_0_reghi:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; CI-NEXT: s_load_dword s4, s[4:5], 0xc ; CI-NEXT: s_load_dword s4, s[4:5], 0xc
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_load_dword s2, s[2:3], 0x0
; CI-NEXT: v_mov_b32_e32 v0, s0 ; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: s_load_dword s0, s[2:3], 0x0
; CI-NEXT: v_mov_b32_e32 v1, s1 ; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: s_lshr_b32 s1, s4, 16 ; CI-NEXT: s_lshr_b32 s1, s4, 16
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_and_b32 s0, s0, 0xffff0000 ; CI-NEXT: s_and_b32 s0, s2, 0xffff0000
; CI-NEXT: s_or_b32 s0, s1, s0 ; CI-NEXT: s_or_b32 s0, s1, s0
; CI-NEXT: v_mov_b32_e32 v2, s0 ; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_store_dword v[0:1], v2 ; CI-NEXT: flat_store_dword v[0:1], v2
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
%vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr %vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr
%elt.hi = lshr i32 %elt.arg, 16 %elt.hi = lshr i32 %elt.arg, 16
%elt = trunc i32 %elt.hi to i16 %elt = trunc i32 %elt.hi to i16
%vecins = insertelement <2 x i16> %vec, i16 %elt, i32 0 %vecins = insertelement <2 x i16> %vec, i16 %elt, i32 0
store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @s_insertelement_v2i16_0_reghi_multi_use_1(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(4)* %vec.ptr, i32 %elt.arg) #0 { define amdgpu_kernel void @s_insertelement_v2i16_0_reghi_multi_use_1(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(4)* %vec.ptr, i32 %elt.arg) #0 {
; GFX9-LABEL: s_insertelement_v2i16_0_reghi_multi_use_1: ; GFX9-LABEL: s_insertelement_v2i16_0_reghi_multi_use_1:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX9-NEXT: s_load_dword s4, s[4:5], 0x10 ; GFX9-NEXT: s_load_dword s4, s[4:5], 0x10
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_load_dword s2, s[2:3], 0x0
; GFX9-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: s_load_dword s0, s[2:3], 0x0 ; GFX9-NEXT: s_lshr_b32 s0, s4, 16
; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: s_lshr_b32 s1, s4, 16
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_pack_lh_b32_b16 s0, s1, s0 ; GFX9-NEXT: s_pack_lh_b32_b16 s1, s0, s2
; GFX9-NEXT: v_mov_b32_e32 v2, s0 ; GFX9-NEXT: v_mov_b32_e32 v2, s1
; GFX9-NEXT: global_store_dword v[0:1], v2, off ; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: ;;#ASMSTART ; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s1 ; GFX9-NEXT: ; use s0
; GFX9-NEXT: ;;#ASMEND ; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: s_insertelement_v2i16_0_reghi_multi_use_1: ; VI-LABEL: s_insertelement_v2i16_0_reghi_multi_use_1:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; VI-NEXT: s_load_dword s4, s[4:5], 0x10 ; VI-NEXT: s_load_dword s4, s[4:5], 0x10
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_load_dword s2, s[2:3], 0x0
; VI-NEXT: v_mov_b32_e32 v0, s0 ; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: s_load_dword s0, s[2:3], 0x0
; VI-NEXT: v_mov_b32_e32 v1, s1 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: s_lshr_b32 s1, s4, 16 ; VI-NEXT: s_lshr_b32 s0, s4, 16
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_and_b32 s0, s0, 0xffff0000 ; VI-NEXT: s_and_b32 s1, s2, 0xffff0000
; VI-NEXT: s_or_b32 s0, s1, s0 ; VI-NEXT: s_or_b32 s1, s0, s1
; VI-NEXT: v_mov_b32_e32 v2, s0 ; VI-NEXT: v_mov_b32_e32 v2, s1
; VI-NEXT: flat_store_dword v[0:1], v2 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: ;;#ASMSTART ; VI-NEXT: ;;#ASMSTART
; VI-NEXT: ; use s1 ; VI-NEXT: ; use s0
; VI-NEXT: ;;#ASMEND ; VI-NEXT: ;;#ASMEND
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; CI-LABEL: s_insertelement_v2i16_0_reghi_multi_use_1: ; CI-LABEL: s_insertelement_v2i16_0_reghi_multi_use_1:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; CI-NEXT: s_load_dword s4, s[4:5], 0x4 ; CI-NEXT: s_load_dword s4, s[4:5], 0x4
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_load_dword s2, s[2:3], 0x0
; CI-NEXT: v_mov_b32_e32 v0, s0 ; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: s_load_dword s0, s[2:3], 0x0
; CI-NEXT: v_mov_b32_e32 v1, s1 ; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: s_lshr_b32 s1, s4, 16 ; CI-NEXT: s_lshr_b32 s0, s4, 16
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_and_b32 s0, s0, 0xffff0000 ; CI-NEXT: s_and_b32 s1, s2, 0xffff0000
; CI-NEXT: s_or_b32 s0, s1, s0 ; CI-NEXT: s_or_b32 s1, s0, s1
; CI-NEXT: v_mov_b32_e32 v2, s0 ; CI-NEXT: v_mov_b32_e32 v2, s1
; CI-NEXT: flat_store_dword v[0:1], v2 ; CI-NEXT: flat_store_dword v[0:1], v2
; CI-NEXT: ;;#ASMSTART ; CI-NEXT: ;;#ASMSTART
; CI-NEXT: ; use s1 ; CI-NEXT: ; use s0
; CI-NEXT: ;;#ASMEND ; CI-NEXT: ;;#ASMEND
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
%vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr %vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr
%elt.hi = lshr i32 %elt.arg, 16 %elt.hi = lshr i32 %elt.arg, 16
%elt = trunc i32 %elt.hi to i16 %elt = trunc i32 %elt.hi to i16
%vecins = insertelement <2 x i16> %vec, i16 %elt, i32 0 %vecins = insertelement <2 x i16> %vec, i16 %elt, i32 0
store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out
%use1 = zext i16 %elt to i32 %use1 = zext i16 %elt to i32
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; VI-NEXT: flat_store_dword v[0:1], v2 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; CI-LABEL: s_insertelement_v2i16_1_reg: ; CI-LABEL: s_insertelement_v2i16_1_reg:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; CI-NEXT: s_load_dword s4, s[4:5], 0xc ; CI-NEXT: s_load_dword s4, s[4:5], 0xc
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_load_dword s2, s[2:3], 0x0
; CI-NEXT: v_mov_b32_e32 v0, s0 ; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: s_load_dword s0, s[2:3], 0x0
; CI-NEXT: v_mov_b32_e32 v1, s1 ; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: s_lshl_b32 s1, s4, 16 ; CI-NEXT: s_lshl_b32 s1, s4, 16
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_and_b32 s0, s0, 0xffff ; CI-NEXT: s_and_b32 s0, s2, 0xffff
; CI-NEXT: s_or_b32 s0, s0, s1 ; CI-NEXT: s_or_b32 s0, s0, s1
; CI-NEXT: v_mov_b32_e32 v2, s0 ; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_store_dword v[0:1], v2 ; CI-NEXT: flat_store_dword v[0:1], v2
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
%vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr %vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr
%vecins = insertelement <2 x i16> %vec, i16 %elt, i32 1 %vecins = insertelement <2 x i16> %vec, i16 %elt, i32 1
store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out
ret void ret void
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; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; CI-NEXT: s_load_dword s4, s[4:5], 0x4 ; CI-NEXT: s_load_dword s4, s[4:5], 0x4
; CI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; CI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v1, s3 ; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: v_add_i32_e32 v0, vcc, s2, v2 ; CI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; CI-NEXT: flat_load_dword v0, v[0:1] ; CI-NEXT: flat_load_dword v3, v[0:1]
; CI-NEXT: v_add_i32_e32 v2, vcc, s0, v2 ; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v2
; CI-NEXT: v_mov_b32_e32 v3, s1 ; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: s_lshr_b32 s0, s4, 16 ; CI-NEXT: s_lshr_b32 s0, s4, 16
; CI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 ; CI-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
; CI-NEXT: v_or_b32_e32 v0, s0, v0 ; CI-NEXT: v_or_b32_e32 v2, s0, v2
; CI-NEXT: flat_store_dword v[2:3], v0 ; CI-NEXT: flat_store_dword v[0:1], v2
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
%out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
%vec = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep %vec = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
%elt.hi = lshr i32 %elt.arg, 16 %elt.hi = lshr i32 %elt.arg, 16
%elt = trunc i32 %elt.hi to i16 %elt = trunc i32 %elt.hi to i16
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; GFX9-LABEL: v_insertelement_v2f16_0: ; GFX9-LABEL: v_insertelement_v2f16_0:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: global_load_dword v0, v[0:1], off ; GFX9-NEXT: global_load_dword v3, v[0:1], off
; GFX9-NEXT: v_mov_b32_e32 v3, s1 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_mov_b32_e32 v1, 0x4500 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v3
; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v1 ; GFX9-NEXT: v_mov_b32_e32 v3, 0x4500
; GFX9-NEXT: global_store_dword v[2:3], v0, off ; GFX9-NEXT: v_lshl_or_b32 v2, v2, 16, v3
; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: v_insertelement_v2f16_0: ; VI-LABEL: v_insertelement_v2f16_0:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
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define amdgpu_kernel void @s_insertelement_v2i16_dynamic(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(4)* %vec.ptr, i32 addrspace(4)* %idx.ptr) #0 { define amdgpu_kernel void @s_insertelement_v2i16_dynamic(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(4)* %vec.ptr, i32 addrspace(4)* %idx.ptr) #0 {
; GFX9-LABEL: s_insertelement_v2i16_dynamic: ; GFX9-LABEL: s_insertelement_v2i16_dynamic:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x10 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x10
; GFX9-NEXT: v_mov_b32_e32 v2, 0x3e703e7 ; GFX9-NEXT: v_mov_b32_e32 v2, 0x3e703e7
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: s_load_dword s4, s[4:5], 0x0
; GFX9-NEXT: s_load_dword s2, s[2:3], 0x0
; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX9-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshl_b32 s0, s0, 4 ; GFX9-NEXT: s_lshl_b32 s0, s4, 4
; GFX9-NEXT: s_lshl_b32 s0, 0xffff, s0 ; GFX9-NEXT: s_lshl_b32 s0, 0xffff, s0
; GFX9-NEXT: v_mov_b32_e32 v3, s1 ; GFX9-NEXT: v_mov_b32_e32 v3, s2
; GFX9-NEXT: v_bfi_b32 v2, s0, v2, v3 ; GFX9-NEXT: v_bfi_b32 v2, s0, v2, v3
; GFX9-NEXT: global_store_dword v[0:1], v2, off ; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: s_insertelement_v2i16_dynamic: ; VI-LABEL: s_insertelement_v2i16_dynamic:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; VI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x10 ; VI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x10
; VI-NEXT: v_mov_b32_e32 v2, 0x3e703e7 ; VI-NEXT: v_mov_b32_e32 v2, 0x3e703e7
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s0 ; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: s_load_dword s4, s[4:5], 0x0
; VI-NEXT: s_load_dword s2, s[2:3], 0x0
; VI-NEXT: v_mov_b32_e32 v1, s1 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: s_load_dword s0, s[4:5], 0x0
; VI-NEXT: s_load_dword s1, s[2:3], 0x0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_lshl_b32 s0, s0, 4 ; VI-NEXT: s_lshl_b32 s0, s4, 4
; VI-NEXT: s_lshl_b32 s0, 0xffff, s0 ; VI-NEXT: s_lshl_b32 s0, 0xffff, s0
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_mov_b32_e32 v3, s2
; VI-NEXT: v_bfi_b32 v2, s0, v2, v3 ; VI-NEXT: v_bfi_b32 v2, s0, v2, v3
; VI-NEXT: flat_store_dword v[0:1], v2 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; CI-LABEL: s_insertelement_v2i16_dynamic: ; CI-LABEL: s_insertelement_v2i16_dynamic:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; CI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x4 ; CI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x4
; CI-NEXT: v_mov_b32_e32 v2, 0x3e703e7 ; CI-NEXT: v_mov_b32_e32 v2, 0x3e703e7
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s0 ; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: s_load_dword s4, s[4:5], 0x0
; CI-NEXT: s_load_dword s2, s[2:3], 0x0
; CI-NEXT: v_mov_b32_e32 v1, s1 ; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: s_load_dword s0, s[4:5], 0x0
; CI-NEXT: s_load_dword s1, s[2:3], 0x0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_lshl_b32 s0, s0, 4 ; CI-NEXT: s_lshl_b32 s0, s4, 4
; CI-NEXT: s_lshl_b32 s0, 0xffff, s0 ; CI-NEXT: s_lshl_b32 s0, 0xffff, s0
; CI-NEXT: v_mov_b32_e32 v3, s1 ; CI-NEXT: v_mov_b32_e32 v3, s2
; CI-NEXT: v_bfi_b32 v2, s0, v2, v3 ; CI-NEXT: v_bfi_b32 v2, s0, v2, v3
; CI-NEXT: flat_store_dword v[0:1], v2 ; CI-NEXT: flat_store_dword v[0:1], v2
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
%idx = load volatile i32, i32 addrspace(4)* %idx.ptr %idx = load volatile i32, i32 addrspace(4)* %idx.ptr
%vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr %vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr
%vecins = insertelement <2 x i16> %vec, i16 999, i32 %idx %vecins = insertelement <2 x i16> %vec, i16 999, i32 %idx
store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out
ret void ret void
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define amdgpu_kernel void @v_insertelement_v2f16_dynamic_vgpr(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in, i32 addrspace(1)* %idx.ptr) #0 { define amdgpu_kernel void @v_insertelement_v2f16_dynamic_vgpr(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in, i32 addrspace(1)* %idx.ptr) #0 {
; GFX9-LABEL: v_insertelement_v2f16_dynamic_vgpr: ; GFX9-LABEL: v_insertelement_v2f16_dynamic_vgpr:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x10 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x10
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v4, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v4 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v4
; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: v_mov_b32_e32 v3, s5 ; GFX9-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s4, v4 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s4, v4
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: global_load_dword v0, v[0:1], off ; GFX9-NEXT: global_load_dword v2, v[2:3], off
; GFX9-NEXT: global_load_dword v1, v[2:3], off ; GFX9-NEXT: global_load_dword v3, v[0:1], off
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, s0, v4 ; GFX9-NEXT: s_mov_b32 s2, 0xffff
; GFX9-NEXT: s_mov_b32 s0, 0xffff ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s1 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 4, v1
; GFX9-NEXT: v_lshlrev_b32_e64 v1, v1, s0
; GFX9-NEXT: s_mov_b32 s0, 0x12341234 ; GFX9-NEXT: s_mov_b32 s0, 0x12341234
; GFX9-NEXT: v_bfi_b32 v0, v1, s0, v0 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: global_store_dword v[4:5], v0, off ; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 4, v2
; GFX9-NEXT: v_lshlrev_b32_e64 v2, v2, s2
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_bfi_b32 v2, v2, s0, v3
; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: v_insertelement_v2f16_dynamic_vgpr: ; VI-LABEL: v_insertelement_v2f16_dynamic_vgpr:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; VI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x10 ; VI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x10
; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v3, s5 ; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v4 ; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v4
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v2, v[2:3]
; VI-NEXT: flat_load_dword v1, v[2:3] ; VI-NEXT: flat_load_dword v3, v[0:1]
; VI-NEXT: v_add_u32_e32 v4, vcc, s0, v4 ; VI-NEXT: s_mov_b32 s2, 0xffff
; VI-NEXT: s_mov_b32 s0, 0xffff ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v4
; VI-NEXT: v_mov_b32_e32 v5, s1 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_lshlrev_b32_e32 v1, 4, v1
; VI-NEXT: v_lshlrev_b32_e64 v1, v1, s0
; VI-NEXT: s_mov_b32 s0, 0x12341234 ; VI-NEXT: s_mov_b32 s0, 0x12341234
; VI-NEXT: v_bfi_b32 v0, v1, s0, v0 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_store_dword v[4:5], v0 ; VI-NEXT: s_waitcnt vmcnt(1) lgkmcnt(1)
; VI-NEXT: v_lshlrev_b32_e32 v2, 4, v2
; VI-NEXT: v_lshlrev_b32_e64 v2, v2, s2
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_bfi_b32 v2, v2, s0, v3
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; CI-LABEL: v_insertelement_v2f16_dynamic_vgpr: ; CI-LABEL: v_insertelement_v2f16_dynamic_vgpr:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; CI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x4 ; CI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x4
; CI-NEXT: v_lshlrev_b32_e32 v4, 2, v0 ; CI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v1, s3 ; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: v_add_i32_e32 v0, vcc, s2, v4 ; CI-NEXT: v_add_i32_e32 v0, vcc, s2, v4
; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; CI-NEXT: v_mov_b32_e32 v3, s5 ; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: v_add_i32_e32 v2, vcc, s4, v4 ; CI-NEXT: v_add_i32_e32 v2, vcc, s4, v4
; CI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; CI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; CI-NEXT: flat_load_dword v2, v[2:3] ; CI-NEXT: flat_load_dword v2, v[2:3]
; CI-NEXT: flat_load_dword v0, v[0:1] ; CI-NEXT: flat_load_dword v3, v[0:1]
; CI-NEXT: v_add_i32_e32 v4, vcc, s0, v4 ; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v4
; CI-NEXT: v_mov_b32_e32 v5, s1 ; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: s_mov_b32 s0, 0x12341234 ; CI-NEXT: s_mov_b32 s0, 0x12341234
; CI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; CI-NEXT: s_waitcnt vmcnt(1) lgkmcnt(1) ; CI-NEXT: s_waitcnt vmcnt(1) lgkmcnt(1)
; CI-NEXT: v_lshlrev_b32_e32 v1, 4, v2 ; CI-NEXT: v_lshlrev_b32_e32 v2, 4, v2
; CI-NEXT: v_lshl_b32_e32 v1, 0xffff, v1 ; CI-NEXT: v_lshl_b32_e32 v2, 0xffff, v2
; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CI-NEXT: v_bfi_b32 v0, v1, s0, v0 ; CI-NEXT: v_bfi_b32 v2, v2, s0, v3
; CI-NEXT: flat_store_dword v[4:5], v0 ; CI-NEXT: flat_store_dword v[0:1], v2
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%in.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %in, i64 %tid.ext %in.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %in, i64 %tid.ext
%idx.gep = getelementptr inbounds i32, i32 addrspace(1)* %idx.ptr, i64 %tid.ext %idx.gep = getelementptr inbounds i32, i32 addrspace(1)* %idx.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %out, i64 %tid.ext
%idx = load i32, i32 addrspace(1)* %idx.gep %idx = load i32, i32 addrspace(1)* %idx.gep
%vec = load <2 x half>, <2 x half> addrspace(1)* %in.gep %vec = load <2 x half>, <2 x half> addrspace(1)* %in.gep
▲ Show 20 Lines • Show All 358 Lines • ▼ Show 20 Lines
} }
; FIXME: Better code on CI? ; FIXME: Better code on CI?
define amdgpu_kernel void @v_insertelement_v4i16_dynamic_vgpr(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in, i32 %val) #0 { define amdgpu_kernel void @v_insertelement_v4i16_dynamic_vgpr(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in, i32 %val) #0 {
; GFX9-LABEL: v_insertelement_v4i16_dynamic_vgpr: ; GFX9-LABEL: v_insertelement_v4i16_dynamic_vgpr:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX9-NEXT: s_load_dword s4, s[4:5], 0x10 ; GFX9-NEXT: s_load_dword s4, s[4:5], 0x10
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 3, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v4, 3, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v4
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: global_load_dword v4, v[0:1], off ; GFX9-NEXT: global_load_dword v2, v[0:1], off
; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off ; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX9-NEXT: v_mov_b32_e32 v3, s1 ; GFX9-NEXT: s_mov_b32 s3, 0
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2 ; GFX9-NEXT: s_mov_b32 s2, 0xffff
; GFX9-NEXT: s_mov_b32 s1, 0 ; GFX9-NEXT: v_mov_b32_e32 v5, s1
; GFX9-NEXT: s_mov_b32 s0, 0xffff ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, s0, v4
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX9-NEXT: s_pack_ll_b32_b16 s1, s4, s4
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX9-NEXT: s_waitcnt vmcnt(1) ; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 4, v4 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 4, v2
; GFX9-NEXT: v_lshlrev_b64 v[4:5], v4, s[0:1] ; GFX9-NEXT: v_lshlrev_b64 v[2:3], v2, s[2:3]
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s4, s4
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_bfi_b32 v1, v5, s0, v1 ; GFX9-NEXT: v_bfi_b32 v1, v3, s1, v1
; GFX9-NEXT: v_bfi_b32 v0, v4, s0, v0 ; GFX9-NEXT: v_bfi_b32 v0, v2, s1, v0
; GFX9-NEXT: global_store_dwordx2 v[2:3], v[0:1], off ; GFX9-NEXT: global_store_dwordx2 v[4:5], v[0:1], off
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: v_insertelement_v4i16_dynamic_vgpr: ; VI-LABEL: v_insertelement_v4i16_dynamic_vgpr:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; VI-NEXT: s_load_dword s4, s[4:5], 0x10 ; VI-NEXT: s_load_dword s4, s[4:5], 0x10
; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v4, v[0:1] ; VI-NEXT: flat_load_dword v4, v[0:1]
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] ; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2 ; VI-NEXT: s_mov_b32 s2, 0xffff
; VI-NEXT: s_mov_b32 s0, 0xffff
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: s_and_b32 s2, s4, s0 ; VI-NEXT: s_mov_b32 s3, 0
; VI-NEXT: s_mov_b32 s1, 0 ; VI-NEXT: s_and_b32 s1, s4, s2
; VI-NEXT: s_lshl_b32 s3, s2, 16 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
; VI-NEXT: s_lshl_b32 s0, s1, 16
; VI-NEXT: s_or_b32 s0, s1, s0
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: s_waitcnt vmcnt(1) lgkmcnt(1) ; VI-NEXT: s_waitcnt vmcnt(1) lgkmcnt(1)
; VI-NEXT: v_lshlrev_b32_e32 v4, 4, v4 ; VI-NEXT: v_lshlrev_b32_e32 v4, 4, v4
; VI-NEXT: v_lshlrev_b64 v[4:5], v4, s[0:1] ; VI-NEXT: v_lshlrev_b64 v[4:5], v4, s[2:3]
; VI-NEXT: s_or_b32 s0, s2, s3
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_bfi_b32 v1, v5, s0, v1 ; VI-NEXT: v_bfi_b32 v1, v5, s0, v1
; VI-NEXT: v_bfi_b32 v0, v4, s0, v0 ; VI-NEXT: v_bfi_b32 v0, v4, s0, v0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; CI-LABEL: v_insertelement_v4i16_dynamic_vgpr: ; CI-LABEL: v_insertelement_v4i16_dynamic_vgpr:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: flat_load_dword v4, v[0:1]
; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; CI-NEXT: s_load_dword s4, s[4:5], 0x4 ; CI-NEXT: s_load_dword s4, s[4:5], 0x4
; CI-NEXT: v_lshlrev_b32_e32 v2, 3, v0 ; CI-NEXT: v_lshlrev_b32_e32 v2, 3, v0
; CI-NEXT: s_mov_b32 s6, 0xffff
; CI-NEXT: s_mov_b32 s7, 0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v1, s3 ; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: v_add_i32_e32 v0, vcc, s2, v2 ; CI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; CI-NEXT: flat_load_dword v4, v[0:1]
; CI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] ; CI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; CI-NEXT: s_mov_b32 s2, 0xffff
; CI-NEXT: s_mov_b32 s3, 0
; CI-NEXT: v_mov_b32_e32 v3, s1 ; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: s_lshl_b32 s1, s4, 16 ; CI-NEXT: s_lshl_b32 s1, s4, 16
; CI-NEXT: s_and_b32 s3, s4, s6 ; CI-NEXT: s_and_b32 s4, s4, s2
; CI-NEXT: v_add_i32_e32 v2, vcc, s0, v2 ; CI-NEXT: v_add_i32_e32 v2, vcc, s0, v2
; CI-NEXT: s_or_b32 s0, s3, s1 ; CI-NEXT: s_or_b32 s0, s4, s1
; CI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; CI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; CI-NEXT: s_waitcnt vmcnt(1) ; CI-NEXT: s_waitcnt vmcnt(1) lgkmcnt(1)
; CI-NEXT: v_lshlrev_b32_e32 v4, 4, v4 ; CI-NEXT: v_lshlrev_b32_e32 v4, 4, v4
; CI-NEXT: v_lshl_b64 v[4:5], s[6:7], v4 ; CI-NEXT: v_lshl_b64 v[4:5], s[2:3], v4
; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CI-NEXT: v_bfi_b32 v1, v5, s0, v1 ; CI-NEXT: v_bfi_b32 v1, v5, s0, v1
; CI-NEXT: v_bfi_b32 v0, v4, s0, v0 ; CI-NEXT: v_bfi_b32 v0, v4, s0, v0
; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%in.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %in, i64 %tid.ext %in.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %in, i64 %tid.ext
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; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x10 ; GFX9-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x10
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 3, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 3, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off ; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX9-NEXT: s_pack_ll_b32_b16 s2, s4, s4 ; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s4
; GFX9-NEXT: v_mov_b32_e32 v3, s1 ; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: s_mov_b32 s3, 0
; GFX9-NEXT: s_mov_b32 s2, 0xffff
; GFX9-NEXT: s_lshl_b32 s1, s5, 4
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2
; GFX9-NEXT: s_mov_b32 s1, 0 ; GFX9-NEXT: s_lshl_b64 s[0:1], s[2:3], s1
; GFX9-NEXT: s_mov_b32 s0, 0xffff ; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: s_lshl_b32 s3, s5, 4 ; GFX9-NEXT: v_mov_b32_e32 v5, s4
; GFX9-NEXT: v_mov_b32_e32 v4, s2
; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], s3
; GFX9-NEXT: v_mov_b32_e32 v5, s2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_bfi_b32 v1, s1, v5, v1 ; GFX9-NEXT: v_bfi_b32 v1, s1, v4, v1
; GFX9-NEXT: v_bfi_b32 v0, s0, v4, v0 ; GFX9-NEXT: v_bfi_b32 v0, s0, v5, v0
; GFX9-NEXT: global_store_dwordx2 v[2:3], v[0:1], off ; GFX9-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: v_insertelement_v4f16_dynamic_sgpr: ; VI-LABEL: v_insertelement_v4f16_dynamic_sgpr:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x10 ; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x10
; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] ; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2 ; VI-NEXT: s_mov_b32 s2, 0xffff
; VI-NEXT: s_mov_b32 s0, 0xffff
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: s_mov_b32 s1, 0 ; VI-NEXT: s_mov_b32 s3, 0
; VI-NEXT: s_lshl_b32 s2, s5, 4 ; VI-NEXT: s_lshl_b32 s1, s5, 4
; VI-NEXT: s_and_b32 s3, s4, s0 ; VI-NEXT: s_and_b32 s4, s4, s2
; VI-NEXT: s_lshl_b64 s[0:1], s[0:1], s2 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
; VI-NEXT: s_lshl_b32 s2, s3, 16 ; VI-NEXT: s_lshl_b64 s[0:1], s[2:3], s1
; VI-NEXT: s_or_b32 s2, s3, s2 ; VI-NEXT: s_lshl_b32 s2, s4, 16
; VI-NEXT: s_or_b32 s2, s4, s2
; VI-NEXT: v_mov_b32_e32 v4, s2 ; VI-NEXT: v_mov_b32_e32 v4, s2
; VI-NEXT: v_mov_b32_e32 v5, s2 ; VI-NEXT: v_mov_b32_e32 v5, s2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_bfi_b32 v1, s1, v4, v1 ; VI-NEXT: v_bfi_b32 v1, s1, v4, v1
; VI-NEXT: v_bfi_b32 v0, s0, v5, v0 ; VI-NEXT: v_bfi_b32 v0, s0, v5, v0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; CI-LABEL: v_insertelement_v4f16_dynamic_sgpr: ; CI-LABEL: v_insertelement_v4f16_dynamic_sgpr:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x4 ; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x4
; CI-NEXT: v_lshlrev_b32_e32 v2, 3, v0 ; CI-NEXT: v_lshlrev_b32_e32 v2, 3, v0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v1, s3 ; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: v_add_i32_e32 v0, vcc, s2, v2 ; CI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; CI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] ; CI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; CI-NEXT: v_add_i32_e32 v2, vcc, s0, v2 ; CI-NEXT: s_mov_b32 s2, 0xffff
; CI-NEXT: s_mov_b32 s0, 0xffff
; CI-NEXT: s_and_b32 s2, s4, s0
; CI-NEXT: s_lshl_b32 s4, s4, 16
; CI-NEXT: v_mov_b32_e32 v3, s1 ; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: s_or_b32 s2, s2, s4 ; CI-NEXT: s_and_b32 s6, s4, s2
; CI-NEXT: s_mov_b32 s1, 0 ; CI-NEXT: s_mov_b32 s3, 0
; CI-NEXT: s_lshl_b32 s3, s5, 4 ; CI-NEXT: s_lshl_b32 s1, s5, 4
; CI-NEXT: s_lshl_b64 s[0:1], s[0:1], s3 ; CI-NEXT: s_lshl_b32 s4, s4, 16
; CI-NEXT: v_add_i32_e32 v2, vcc, s0, v2
; CI-NEXT: s_lshl_b64 s[0:1], s[2:3], s1
; CI-NEXT: s_or_b32 s2, s6, s4
; CI-NEXT: v_mov_b32_e32 v4, s2 ; CI-NEXT: v_mov_b32_e32 v4, s2
; CI-NEXT: v_mov_b32_e32 v5, s2 ; CI-NEXT: v_mov_b32_e32 v5, s2
; CI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; CI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CI-NEXT: v_bfi_b32 v1, s1, v4, v1 ; CI-NEXT: v_bfi_b32 v1, s1, v4, v1
; CI-NEXT: v_bfi_b32 v0, s0, v5, v0 ; CI-NEXT: v_bfi_b32 v0, s0, v5, v0
; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
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llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.atomic.ll

;RUN: llc < %s -march=amdgcn -mcpu=verde -amdgpu-atomic-optimizations=false -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=SICI ;RUN: llc < %s -march=amdgcn -mcpu=verde -amdgpu-atomic-optimizations=false -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=SICI
;RUN: llc < %s -march=amdgcn -mcpu=tonga -amdgpu-atomic-optimizations=false -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=VI ;RUN: llc < %s -march=amdgcn -mcpu=tonga -amdgpu-atomic-optimizations=false -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=VI
;CHECK-LABEL: {{^}}test1: ;CHECK-LABEL: {{^}}test1:
;CHECK-NOT: s_waitcnt ;CHECK-NOT: s_waitcnt
;CHECK: buffer_atomic_swap v0, off, s[0:3], 0 glc ;CHECK: buffer_atomic_swap v0, off, s[0:3], 0 glc
;VI: s_movk_i32 [[SOFS:s[0-9]+]], 0x1ffc ;VI: s_movk_i32 [[SOFS:s[0-9]+]], 0x1ffc
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
;CHECK: buffer_atomic_swap v0, v1, s[0:3], 0 idxen glc ;CHECK: buffer_atomic_swap v0, v1, s[0:3], 0 idxen glc
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
;CHECK: buffer_atomic_swap v0, v2, s[0:3], 0 offen glc ;CHECK: buffer_atomic_swap v0, v2, s[0:3], 0 offen glc
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
;CHECK: buffer_atomic_swap v0, v[1:2], s[0:3], 0 idxen offen glc ;CHECK: buffer_atomic_swap v0, v[1:2], s[0:3], 0 idxen offen glc
;SICI: v_mov_b32_e32 v1, 0x2000
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
;CHECK: buffer_atomic_swap v0, v2, s[0:3], 0 offen offset:42 glc ;CHECK: buffer_atomic_swap v0, v2, s[0:3], 0 offen offset:42 glc
;CHECK-DAG: s_waitcnt vmcnt(0) ;CHECK-DAG: s_waitcnt vmcnt(0)
;SICI: buffer_atomic_swap v0, v1, s[0:3], 0 offen glc ;SICI: buffer_atomic_swap v0, v1, s[0:3], 0 offen glc
;VI: buffer_atomic_swap v0, off, s[0:3], [[SOFS]] offset:4 glc ;VI: buffer_atomic_swap v0, off, s[0:3], [[SOFS]] offset:4 glc
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
;CHECK: buffer_atomic_swap v0, off, s[0:3], 0{{$}} ;CHECK: buffer_atomic_swap v0, off, s[0:3], 0{{$}}
define amdgpu_ps float @test1(<4 x i32> inreg %rsrc, i32 %data, i32 %vindex, i32 %voffset) { define amdgpu_ps float @test1(<4 x i32> inreg %rsrc, i32 %data, i32 %vindex, i32 %voffset) {
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llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.ll

Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
; Ideally, we would teach tablegen & friends that cmpswap only modifies the ; Ideally, we would teach tablegen & friends that cmpswap only modifies the
; first vgpr. Since we don't do that yet, the register allocator will have to ; first vgpr. Since we don't do that yet, the register allocator will have to
; create copies which we don't bother to track here. ; create copies which we don't bother to track here.
; ;
;CHECK-LABEL: {{^}}test3: ;CHECK-LABEL: {{^}}test3:
;CHECK-NOT: s_waitcnt ;CHECK-NOT: s_waitcnt
;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, s[0:3], 0 idxen glc ;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, s[0:3], 0 idxen glc
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, v2, s[0:3], 0 idxen glc ;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, s[0:3], 0 idxen glc
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
;CHECK: s_movk_i32 [[SOFS:s[0-9]+]], 0x1ffc ;CHECK: s_movk_i32 [[SOFS:s[0-9]+]], 0x1ffc
;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, s[0:3], 0 idxen offen glc ;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, s[0:3], 0 idxen offen glc
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, s[0:3], 0 idxen offen glc ;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, s[0:3], 0 idxen offen glc
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, s[0:3], 0 idxen offen offset:44 glc ;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, s[0:3], 0 idxen offen offset:44 glc
;CHECK-DAG: s_waitcnt vmcnt(0) ;CHECK-DAG: s_waitcnt vmcnt(0)
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llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll

Show First 20 Lines • Show All 1,553 Lines • ▼ Show 20 Lines
; SI-NEXT: v_bfe_u32 v1, v0, 2, 2 ; SI-NEXT: v_bfe_u32 v1, v0, 2, 2
; SI-NEXT: buffer_store_dword v1, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v1, off, s[0:3], 0
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: simplify_bfe_u32_multi_use_arg: ; VI-LABEL: simplify_bfe_u32_multi_use_arg:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s11, 0xf000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s10, -1
; VI-NEXT: s_mov_b32 s10, s2 ; VI-NEXT: s_mov_b32 s2, s10
; VI-NEXT: s_mov_b32 s11, s3 ; VI-NEXT: s_mov_b32 s3, s11
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0 ; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: s_mov_b32 s8, s4
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s9, s5
; VI-NEXT: s_mov_b32 s4, s6 ; VI-NEXT: s_mov_b32 s0, s6
; VI-NEXT: s_mov_b32 s5, s7 ; VI-NEXT: s_mov_b32 s1, s7
; VI-NEXT: s_mov_b32 s6, s2
; VI-NEXT: s_mov_b32 s7, s3
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_and_b32_e32 v0, 63, v0 ; VI-NEXT: v_and_b32_e32 v0, 63, v0
; VI-NEXT: v_bfe_u32 v1, v0, 2, 2 ; VI-NEXT: v_bfe_u32 v1, v0, 2, 2
; VI-NEXT: buffer_store_dword v1, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v1, off, s[8:11], 0
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
i32 addrspace(1)* %out1, i32 addrspace(1)* %out1,
i32 addrspace(1)* %in) #0 { i32 addrspace(1)* %in) #0 {
%src = load i32, i32 addrspace(1)* %in, align 4 %src = load i32, i32 addrspace(1)* %in, align 4
%and = and i32 %src, 63 %and = and i32 %src, 63
%bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 %and, i32 2, i32 2) %bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 %and, i32 2, i32 2)
store i32 %bfe_u32, i32 addrspace(1)* %out0, align 4 store i32 %bfe_u32, i32 addrspace(1)* %out0, align 4
store i32 %and, i32 addrspace(1)* %out1, align 4 store i32 %and, i32 addrspace(1)* %out1, align 4
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llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll

Show First 20 Lines • Show All 112 Lines • ▼ Show 20 Lines
; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_or_b32_e32 v2, v3, v2 ; GFX8-NEXT: v_or_b32_e32 v2, v3, v2
; GFX8-NEXT: flat_store_dword v[0:1], v2 ; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-LABEL: cos_v2f16: ; GFX9-LABEL: cos_v2f16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: v_mov_b32_e32 v2, 0x3118
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s2 ; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: global_load_dword v0, v[0:1], off ; GFX9-NEXT: global_load_dword v0, v[0:1], off
; GFX9-NEXT: v_mov_b32_e32 v1, 0x3118
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mul_f16_e32 v1, 0.15915494, v0 ; GFX9-NEXT: v_mul_f16_e32 v2, 0.15915494, v0
; GFX9-NEXT: v_cos_f16_e32 v3, v1 ; GFX9-NEXT: v_cos_f16_e32 v2, v2
; GFX9-NEXT: v_mul_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX9-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_cos_f16_e32 v2, v0 ; GFX9-NEXT: v_cos_f16_e32 v3, v0
; GFX9-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_and_b32_e32 v3, 0xffff, v3 ; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_lshl_or_b32 v2, v2, 16, v3 ; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: global_store_dword v[0:1], v2, off ; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%a.val = load <2 x half>, <2 x half> addrspace(1)* %a %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
%r.val = call <2 x half> @llvm.cos.v2f16(<2 x half> %a.val) %r.val = call <2 x half> @llvm.cos.v2f16(<2 x half> %a.val)
store <2 x half> %r.val, <2 x half> addrspace(1)* %r store <2 x half> %r.val, <2 x half> addrspace(1)* %r
ret void ret void
} }
declare half @llvm.cos.f16(half %a) declare half @llvm.cos.f16(half %a)
declare <2 x half> @llvm.cos.v2f16(<2 x half> %a) declare <2 x half> @llvm.cos.v2f16(<2 x half> %a)

llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll

Show First 20 Lines • Show All 167 Lines • ▼ Show 20 Lines
; SI: v_cvt_f32_f16_e32 v[[C_F32_0:[0-9]+]], v[[C_V2_F16]] ; SI: v_cvt_f32_f16_e32 v[[C_F32_0:[0-9]+]], v[[C_V2_F16]]
; SI: v_cvt_f32_f16_e32 v[[B_F32_0:[0-9]+]], v[[B_V2_F16]] ; SI: v_cvt_f32_f16_e32 v[[B_F32_0:[0-9]+]], v[[B_V2_F16]]
; SI: v_fma_f32 v[[R_F32_1:[0-9]+]], v[[B_F32_1]], s[[A_F32]], v[[C_F32_1]] ; SI: v_fma_f32 v[[R_F32_1:[0-9]+]], v[[B_F32_1]], s[[A_F32]], v[[C_F32_1]]
; SI-DAG: v_fma_f32 v[[R_F32_0:[0-9]+]], v[[B_F32_0]], s[[A_F32]], v[[C_F32_0]] ; SI-DAG: v_fma_f32 v[[R_F32_0:[0-9]+]], v[[B_F32_0]], s[[A_F32]], v[[C_F32_0]]
; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]] ; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]]
; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]] ; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]]
; VI-DAG: v_fma_f16 v[[R_F16_1:[0-9]+]], v[[C_F16_1]], s[[A_F16]], v[[B_F16_1]] ; VI-DAG: v_fma_f16 v[[R_F16_1:[0-9]+]], v[[B_F16_1]], s[[A_F16]], v[[C_F16_1]]
; VI-DAG: v_fma_f16 v[[R_F16_0:[0-9]+]], v[[C_V2_F16]], s[[A_F16]], v[[B_V2_F16]] ; VI-DAG: v_fma_f16 v[[R_F16_0:[0-9]+]], v[[B_V2_F16]], s[[A_F16]], v[[C_V2_F16]]
; GFX9: v_pk_fma_f16 v[[R_V2_F16:[0-9]+]], v[[C_V2_F16]], s[[A_F16]], v[[B_V2_F16]] ; GFX9: v_pk_fma_f16 v[[R_V2_F16:[0-9]+]], v[[C_V2_F16]], s[[A_F16]], v[[B_V2_F16]]
; SIVI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] ; SIVI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]]
; GCN-NOT: and ; GCN-NOT: and
; SIVI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]] ; SIVI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]]
; GCN: buffer_store_dword v[[R_V2_F16]] ; GCN: buffer_store_dword v[[R_V2_F16]]
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @fma_v2f16_imm_a( define amdgpu_kernel void @fma_v2f16_imm_a(
<2 x half> addrspace(1)* %r, <2 x half> addrspace(1)* %r,
<2 x half> addrspace(1)* %b, <2 x half> addrspace(1)* %b,
<2 x half> addrspace(1)* %c) { <2 x half> addrspace(1)* %c) {
%b.val = load <2 x half>, <2 x half> addrspace(1)* %b %b.val = load <2 x half>, <2 x half> addrspace(1)* %b
%c.val = load <2 x half>, <2 x half> addrspace(1)* %c %c.val = load <2 x half>, <2 x half> addrspace(1)* %c
%r.val = call <2 x half> @llvm.fma.v2f16(<2 x half> <half 3.0, half 3.0>, <2 x half> %b.val, <2 x half> %c.val) %r.val = call <2 x half> @llvm.fma.v2f16(<2 x half> <half 3.0, half 3.0>, <2 x half> %b.val, <2 x half> %c.val)
store <2 x half> %r.val, <2 x half> addrspace(1)* %r store <2 x half> %r.val, <2 x half> addrspace(1)* %r
ret void ret void
} }
; GCN-LABEL: {{^}}fma_v2f16_imm_b: ; GCN-LABEL: {{^}}fma_v2f16_imm_b:
; SI: buffer_load_dword v[[C_V2_F16:[0-9]+]] ; SI: buffer_load_dword v[[C_V2_F16:[0-9]+]]
; SI: buffer_load_dword v[[A_V2_F16:[0-9]+]] ; SI: buffer_load_dword v[[A_V2_F16:[0-9]+]]
; VI: buffer_load_dword v[[C_V2_F16:[0-9]+]]
; VIGFX9: buffer_load_dword v[[A_V2_F16:[0-9]+]] ; VIGFX9: buffer_load_dword v[[A_V2_F16:[0-9]+]]
; VIGFX9: buffer_load_dword v[[C_V2_F16:[0-9]+]] ; GFX9: buffer_load_dword v[[C_V2_F16:[0-9]+]]
; SI: s_mov_b32 s[[B_F32:[0-9]+]], 0x40400000{{$}} ; SI: s_mov_b32 s[[B_F32:[0-9]+]], 0x40400000{{$}}
; VIGFX9: s_movk_i32 s[[B_F16:[0-9]+]], 0x4200{{$}} ; VIGFX9: s_movk_i32 s[[B_F16:[0-9]+]], 0x4200{{$}}
; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]] ; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]]
; SI-DAG: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]] ; SI-DAG: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
; SI-DAG: v_cvt_f32_f16_e32 v[[C_F32_0:[0-9]+]], v[[C_V2_F16]] ; SI-DAG: v_cvt_f32_f16_e32 v[[C_F32_0:[0-9]+]], v[[C_V2_F16]]
; SI-DAG: v_lshrrev_b32_e32 v[[C_F16_1:[0-9]+]], 16, v[[C_V2_F16]] ; SI-DAG: v_lshrrev_b32_e32 v[[C_F16_1:[0-9]+]], 16, v[[C_V2_F16]]
Show All 27 Linesdefine amdgpu_kernel void @fma_v2f16_imm_b(
store <2 x half> %r.val, <2 x half> addrspace(1)* %r store <2 x half> %r.val, <2 x half> addrspace(1)* %r
ret void ret void
} }
; GCN-LABEL: {{^}}fma_v2f16_imm_c: ; GCN-LABEL: {{^}}fma_v2f16_imm_c:
; SI: buffer_load_dword v[[B_V2_F16:[0-9]+]] ; SI: buffer_load_dword v[[B_V2_F16:[0-9]+]]
; SI: buffer_load_dword v[[A_V2_F16:[0-9]+]] ; SI: buffer_load_dword v[[A_V2_F16:[0-9]+]]
; VIGFX9: buffer_load_dword v[[A_V2_F16:[0-9]+]] ; GFX9: buffer_load_dword v[[A_V2_F16:[0-9]+]]
; VIGFX9: buffer_load_dword v[[B_V2_F16:[0-9]+]] ; VIGFX9: buffer_load_dword v[[B_V2_F16:[0-9]+]]
; VI: buffer_load_dword v[[A_V2_F16:[0-9]+]]
; SI: s_mov_b32 s[[C_F32:[0-9]+]], 0x40400000{{$}} ; SI: s_mov_b32 s[[C_F32:[0-9]+]], 0x40400000{{$}}
; VIGFX9: s_movk_i32 s[[C_F16:[0-9]+]], 0x4200{{$}} ; VIGFX9: s_movk_i32 s[[C_F16:[0-9]+]], 0x4200{{$}}
; SI: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]] ; SI: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]]
; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]] ; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]] ; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]]
▲ Show 20 Lines • Show All 105 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll

Show All 37 Lines
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: maxnum_f16: ; VI-LABEL: maxnum_f16:
; VI: ; %bb.0: ; %entry ; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34 ; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_mov_b32 s10, s2 ; VI-NEXT: s_mov_b32 s14, s2
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: s_mov_b32 s12, s6
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s13, s7
; VI-NEXT: s_mov_b32 s4, s6 ; VI-NEXT: s_mov_b32 s15, s3
; VI-NEXT: s_mov_b32 s5, s7 ; VI-NEXT: s_mov_b32 s10, s2
; VI-NEXT: s_mov_b32 s6, s2
; VI-NEXT: s_mov_b32 s7, s3
; VI-NEXT: s_mov_b32 s11, s3 ; VI-NEXT: s_mov_b32 s11, s3
; VI-NEXT: buffer_load_ushort v0, off, s[4:7], 0 ; VI-NEXT: buffer_load_ushort v0, off, s[12:15], 0
; VI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 ; VI-NEXT: buffer_load_ushort v1, off, s[8:11], 0
; VI-NEXT: s_mov_b32 s0, s4
; VI-NEXT: s_mov_b32 s1, s5
; VI-NEXT: s_waitcnt vmcnt(1) ; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_max_f16_e32 v0, v0, v0 ; VI-NEXT: v_max_f16_e32 v0, v0, v0
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_max_f16_e32 v1, v1, v1 ; VI-NEXT: v_max_f16_e32 v1, v1, v1
; VI-NEXT: v_max_f16_e32 v0, v0, v1 ; VI-NEXT: v_max_f16_e32 v0, v0, v1
; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: maxnum_f16: ; GFX9-LABEL: maxnum_f16:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_mov_b32 s10, s2 ; GFX9-NEXT: s_mov_b32 s14, s2
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s0, s4 ; GFX9-NEXT: s_mov_b32 s12, s6
; GFX9-NEXT: s_mov_b32 s1, s5 ; GFX9-NEXT: s_mov_b32 s13, s7
; GFX9-NEXT: s_mov_b32 s4, s6 ; GFX9-NEXT: s_mov_b32 s15, s3
; GFX9-NEXT: s_mov_b32 s5, s7 ; GFX9-NEXT: s_mov_b32 s10, s2
; GFX9-NEXT: s_mov_b32 s6, s2
; GFX9-NEXT: s_mov_b32 s7, s3
; GFX9-NEXT: s_mov_b32 s11, s3 ; GFX9-NEXT: s_mov_b32 s11, s3
; GFX9-NEXT: buffer_load_ushort v0, off, s[4:7], 0 ; GFX9-NEXT: buffer_load_ushort v0, off, s[12:15], 0
; GFX9-NEXT: buffer_load_ushort v1, off, s[8:11], 0 ; GFX9-NEXT: buffer_load_ushort v1, off, s[8:11], 0
; GFX9-NEXT: s_mov_b32 s0, s4
; GFX9-NEXT: s_mov_b32 s1, s5
; GFX9-NEXT: s_waitcnt vmcnt(1) ; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_max_f16_e32 v0, v0, v0 ; GFX9-NEXT: v_max_f16_e32 v0, v0, v0
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_max_f16_e32 v1, v1, v1 ; GFX9-NEXT: v_max_f16_e32 v1, v1, v1
; GFX9-NEXT: v_max_f16_e32 v0, v0, v1 ; GFX9-NEXT: v_max_f16_e32 v0, v0, v1
; GFX9-NEXT: buffer_store_short v0, off, s[0:3], 0 ; GFX9-NEXT: buffer_store_short v0, off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
half addrspace(1)* %r, half addrspace(1)* %r,
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; VI-NEXT: v_max_f16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI-NEXT: v_max_f16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: maxnum_v2f16: ; GFX9-LABEL: maxnum_v2f16:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_load_dword s6, s[6:7], 0x0
; GFX9-NEXT: s_load_dword s7, s[0:1], 0x0
; GFX9-NEXT: s_mov_b32 s0, s4 ; GFX9-NEXT: s_mov_b32 s0, s4
; GFX9-NEXT: s_mov_b32 s1, s5 ; GFX9-NEXT: s_mov_b32 s1, s5
; GFX9-NEXT: s_load_dword s4, s[6:7], 0x0
; GFX9-NEXT: s_load_dword s5, s[8:9], 0x0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_pk_max_f16 v1, s4, s4 ; GFX9-NEXT: v_pk_max_f16 v1, s6, s6
; GFX9-NEXT: v_pk_max_f16 v0, s5, s5 ; GFX9-NEXT: v_pk_max_f16 v0, s7, s7
; GFX9-NEXT: v_pk_max_f16 v0, v1, v0 ; GFX9-NEXT: v_pk_max_f16 v0, v1, v0
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
<2 x half> addrspace(1)* %r, <2 x half> addrspace(1)* %r,
<2 x half> addrspace(1)* %a, <2 x half> addrspace(1)* %a,
<2 x half> addrspace(1)* %b) #0 { <2 x half> addrspace(1)* %b) #0 {
entry: entry:
%a.val = load <2 x half>, <2 x half> addrspace(1)* %a %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
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; VI-NEXT: v_max_f16_e32 v0, 0x4200, v0 ; VI-NEXT: v_max_f16_e32 v0, 0x4200, v0
; VI-NEXT: v_max_f16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI-NEXT: v_max_f16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: maxnum_v2f16_imm_a: ; GFX9-LABEL: maxnum_v2f16_imm_a:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s7, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s6, -1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s0, s4 ; GFX9-NEXT: s_load_dword s2, s[2:3], 0x0
; GFX9-NEXT: s_load_dword s4, s[6:7], 0x0 ; GFX9-NEXT: s_mov_b32 s4, s0
; GFX9-NEXT: s_mov_b32 s1, s5 ; GFX9-NEXT: s_mov_b32 s0, 0x44004200
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_mov_b32 s5, s1
; GFX9-NEXT: v_pk_max_f16 v0, s4, s4 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 0x44004200 ; GFX9-NEXT: v_pk_max_f16 v0, s2, s2
; GFX9-NEXT: v_pk_max_f16 v0, v0, s4 ; GFX9-NEXT: v_pk_max_f16 v0, v0, s0
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
<2 x half> addrspace(1)* %r, <2 x half> addrspace(1)* %r,
<2 x half> addrspace(1)* %b) #0 { <2 x half> addrspace(1)* %b) #0 {
entry: entry:
%b.val = load <2 x half>, <2 x half> addrspace(1)* %b %b.val = load <2 x half>, <2 x half> addrspace(1)* %b
%r.val = call <2 x half> @llvm.maxnum.v2f16(<2 x half> <half 3.0, half 4.0>, <2 x half> %b.val) %r.val = call <2 x half> @llvm.maxnum.v2f16(<2 x half> <half 3.0, half 4.0>, <2 x half> %b.val)
store <2 x half> %r.val, <2 x half> addrspace(1)* %r store <2 x half> %r.val, <2 x half> addrspace(1)* %r
ret void ret void
Show All 39 Lines
; VI-NEXT: v_max_f16_e32 v0, 4.0, v0 ; VI-NEXT: v_max_f16_e32 v0, 4.0, v0
; VI-NEXT: v_max_f16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI-NEXT: v_max_f16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: maxnum_v2f16_imm_b: ; GFX9-LABEL: maxnum_v2f16_imm_b:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s7, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s6, -1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s0, s4 ; GFX9-NEXT: s_load_dword s2, s[2:3], 0x0
; GFX9-NEXT: s_load_dword s4, s[6:7], 0x0 ; GFX9-NEXT: s_mov_b32 s4, s0
; GFX9-NEXT: s_mov_b32 s1, s5 ; GFX9-NEXT: s_mov_b32 s0, 0x42004400
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_mov_b32 s5, s1
; GFX9-NEXT: v_pk_max_f16 v0, s4, s4 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 0x42004400 ; GFX9-NEXT: v_pk_max_f16 v0, s2, s2
; GFX9-NEXT: v_pk_max_f16 v0, v0, s4 ; GFX9-NEXT: v_pk_max_f16 v0, v0, s0
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
<2 x half> addrspace(1)* %r, <2 x half> addrspace(1)* %r,
<2 x half> addrspace(1)* %a) #0 { <2 x half> addrspace(1)* %a) #0 {
entry: entry:
%a.val = load <2 x half>, <2 x half> addrspace(1)* %a %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
%r.val = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %a.val, <2 x half> <half 4.0, half 3.0>) %r.val = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %a.val, <2 x half> <half 4.0, half 3.0>)
store <2 x half> %r.val, <2 x half> addrspace(1)* %r store <2 x half> %r.val, <2 x half> addrspace(1)* %r
ret void ret void
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; GFX9-LABEL: fmax_v4f16_imm_a: ; GFX9-LABEL: fmax_v4f16_imm_a:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_mov_b32 s8, 0x44004200 ; GFX9-NEXT: s_mov_b32 s8, 0x44004200
; GFX9-NEXT: s_mov_b32 s9, 0x40004800 ; GFX9-NEXT: s_mov_b32 s9, 0x40004800
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[6:7], 0x0
; GFX9-NEXT: s_mov_b32 s0, s4 ; GFX9-NEXT: s_mov_b32 s0, s4
; GFX9-NEXT: s_mov_b32 s1, s5 ; GFX9-NEXT: s_mov_b32 s1, s5
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[6:7], 0x0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_pk_max_f16 v0, s5, s5 ; GFX9-NEXT: v_pk_max_f16 v0, s7, s7
; GFX9-NEXT: v_pk_max_f16 v2, s4, s4 ; GFX9-NEXT: v_pk_max_f16 v2, s6, s6
; GFX9-NEXT: v_pk_max_f16 v1, v0, s8 ; GFX9-NEXT: v_pk_max_f16 v1, v0, s8
; GFX9-NEXT: v_pk_max_f16 v0, v2, s9 ; GFX9-NEXT: v_pk_max_f16 v0, v2, s9
; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
<4 x half> addrspace(1)* %r, <4 x half> addrspace(1)* %r,
<4 x half> addrspace(1)* %b) #0 { <4 x half> addrspace(1)* %b) #0 {
entry: entry:
%b.val = load <4 x half>, <4 x half> addrspace(1)* %b %b.val = load <4 x half>, <4 x half> addrspace(1)* %b
%r.val = call <4 x half> @llvm.maxnum.v4f16(<4 x half> <half 8.0, half 2.0, half 3.0, half 4.0>, <4 x half> %b.val) %r.val = call <4 x half> @llvm.maxnum.v4f16(<4 x half> <half 8.0, half 2.0, half 3.0, half 4.0>, <4 x half> %b.val)
store <4 x half> %r.val, <4 x half> addrspace(1)* %r store <4 x half> %r.val, <4 x half> addrspace(1)* %r
ret void ret void
} }
attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" } attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" }

llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll

Show All 37 Lines
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: minnum_f16_ieee: ; VI-LABEL: minnum_f16_ieee:
; VI: ; %bb.0: ; %entry ; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34 ; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_mov_b32 s10, s2 ; VI-NEXT: s_mov_b32 s14, s2
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: s_mov_b32 s12, s6
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s13, s7
; VI-NEXT: s_mov_b32 s4, s6 ; VI-NEXT: s_mov_b32 s15, s3
; VI-NEXT: s_mov_b32 s5, s7 ; VI-NEXT: s_mov_b32 s10, s2
; VI-NEXT: s_mov_b32 s6, s2
; VI-NEXT: s_mov_b32 s7, s3
; VI-NEXT: s_mov_b32 s11, s3 ; VI-NEXT: s_mov_b32 s11, s3
; VI-NEXT: buffer_load_ushort v0, off, s[4:7], 0 ; VI-NEXT: buffer_load_ushort v0, off, s[12:15], 0
; VI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 ; VI-NEXT: buffer_load_ushort v1, off, s[8:11], 0
; VI-NEXT: s_mov_b32 s0, s4
; VI-NEXT: s_mov_b32 s1, s5
; VI-NEXT: s_waitcnt vmcnt(1) ; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_max_f16_e32 v0, v0, v0 ; VI-NEXT: v_max_f16_e32 v0, v0, v0
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_max_f16_e32 v1, v1, v1 ; VI-NEXT: v_max_f16_e32 v1, v1, v1
; VI-NEXT: v_min_f16_e32 v0, v0, v1 ; VI-NEXT: v_min_f16_e32 v0, v0, v1
; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: minnum_f16_ieee: ; GFX9-LABEL: minnum_f16_ieee:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_mov_b32 s10, s2 ; GFX9-NEXT: s_mov_b32 s14, s2
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s0, s4 ; GFX9-NEXT: s_mov_b32 s12, s6
; GFX9-NEXT: s_mov_b32 s1, s5 ; GFX9-NEXT: s_mov_b32 s13, s7
; GFX9-NEXT: s_mov_b32 s4, s6 ; GFX9-NEXT: s_mov_b32 s15, s3
; GFX9-NEXT: s_mov_b32 s5, s7 ; GFX9-NEXT: s_mov_b32 s10, s2
; GFX9-NEXT: s_mov_b32 s6, s2
; GFX9-NEXT: s_mov_b32 s7, s3
; GFX9-NEXT: s_mov_b32 s11, s3 ; GFX9-NEXT: s_mov_b32 s11, s3
; GFX9-NEXT: buffer_load_ushort v0, off, s[4:7], 0 ; GFX9-NEXT: buffer_load_ushort v0, off, s[12:15], 0
; GFX9-NEXT: buffer_load_ushort v1, off, s[8:11], 0 ; GFX9-NEXT: buffer_load_ushort v1, off, s[8:11], 0
; GFX9-NEXT: s_mov_b32 s0, s4
; GFX9-NEXT: s_mov_b32 s1, s5
; GFX9-NEXT: s_waitcnt vmcnt(1) ; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_max_f16_e32 v0, v0, v0 ; GFX9-NEXT: v_max_f16_e32 v0, v0, v0
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_max_f16_e32 v1, v1, v1 ; GFX9-NEXT: v_max_f16_e32 v1, v1, v1
; GFX9-NEXT: v_min_f16_e32 v0, v0, v1 ; GFX9-NEXT: v_min_f16_e32 v0, v0, v1
; GFX9-NEXT: buffer_store_short v0, off, s[0:3], 0 ; GFX9-NEXT: buffer_store_short v0, off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
half addrspace(1)* %r, half addrspace(1)* %r,
▲ Show 20 Lines • Show All 220 Lines • ▼ Show 20 Lines
; VI-NEXT: v_min_f16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI-NEXT: v_min_f16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: minnum_v2f16_ieee: ; GFX9-LABEL: minnum_v2f16_ieee:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_load_dword s6, s[6:7], 0x0
; GFX9-NEXT: s_load_dword s7, s[0:1], 0x0
; GFX9-NEXT: s_mov_b32 s0, s4 ; GFX9-NEXT: s_mov_b32 s0, s4
; GFX9-NEXT: s_mov_b32 s1, s5 ; GFX9-NEXT: s_mov_b32 s1, s5
; GFX9-NEXT: s_load_dword s4, s[6:7], 0x0
; GFX9-NEXT: s_load_dword s5, s[8:9], 0x0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_pk_max_f16 v1, s4, s4 ; GFX9-NEXT: v_pk_max_f16 v1, s6, s6
; GFX9-NEXT: v_pk_max_f16 v0, s5, s5 ; GFX9-NEXT: v_pk_max_f16 v0, s7, s7
; GFX9-NEXT: v_pk_min_f16 v0, v1, v0 ; GFX9-NEXT: v_pk_min_f16 v0, v1, v0
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
<2 x half> addrspace(1)* %r, <2 x half> addrspace(1)* %r,
<2 x half> addrspace(1)* %a, <2 x half> addrspace(1)* %a,
<2 x half> addrspace(1)* %b) #0 { <2 x half> addrspace(1)* %b) #0 {
entry: entry:
%a.val = load <2 x half>, <2 x half> addrspace(1)* %a %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
; VI-NEXT: v_min_f16_e32 v0, 0x4200, v0 ; VI-NEXT: v_min_f16_e32 v0, 0x4200, v0
; VI-NEXT: v_min_f16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI-NEXT: v_min_f16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: minnum_v2f16_imm_a: ; GFX9-LABEL: minnum_v2f16_imm_a:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s7, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s6, -1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s0, s4 ; GFX9-NEXT: s_load_dword s2, s[2:3], 0x0
; GFX9-NEXT: s_load_dword s4, s[6:7], 0x0 ; GFX9-NEXT: s_mov_b32 s4, s0
; GFX9-NEXT: s_mov_b32 s1, s5 ; GFX9-NEXT: s_mov_b32 s0, 0x44004200
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_mov_b32 s5, s1
; GFX9-NEXT: v_pk_max_f16 v0, s4, s4 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 0x44004200 ; GFX9-NEXT: v_pk_max_f16 v0, s2, s2
; GFX9-NEXT: v_pk_min_f16 v0, v0, s4 ; GFX9-NEXT: v_pk_min_f16 v0, v0, s0
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
<2 x half> addrspace(1)* %r, <2 x half> addrspace(1)* %r,
<2 x half> addrspace(1)* %b) #0 { <2 x half> addrspace(1)* %b) #0 {
entry: entry:
%b.val = load <2 x half>, <2 x half> addrspace(1)* %b %b.val = load <2 x half>, <2 x half> addrspace(1)* %b
%r.val = call <2 x half> @llvm.minnum.v2f16(<2 x half> <half 3.0, half 4.0>, <2 x half> %b.val) %r.val = call <2 x half> @llvm.minnum.v2f16(<2 x half> <half 3.0, half 4.0>, <2 x half> %b.val)
store <2 x half> %r.val, <2 x half> addrspace(1)* %r store <2 x half> %r.val, <2 x half> addrspace(1)* %r
ret void ret void
Show All 39 Lines
; VI-NEXT: v_min_f16_e32 v0, 4.0, v0 ; VI-NEXT: v_min_f16_e32 v0, 4.0, v0
; VI-NEXT: v_min_f16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI-NEXT: v_min_f16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: minnum_v2f16_imm_b: ; GFX9-LABEL: minnum_v2f16_imm_b:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s7, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s6, -1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s0, s4 ; GFX9-NEXT: s_load_dword s2, s[2:3], 0x0
; GFX9-NEXT: s_load_dword s4, s[6:7], 0x0 ; GFX9-NEXT: s_mov_b32 s4, s0
; GFX9-NEXT: s_mov_b32 s1, s5 ; GFX9-NEXT: s_mov_b32 s0, 0x42004400
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_mov_b32 s5, s1
; GFX9-NEXT: v_pk_max_f16 v0, s4, s4 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 0x42004400 ; GFX9-NEXT: v_pk_max_f16 v0, s2, s2
; GFX9-NEXT: v_pk_min_f16 v0, v0, s4 ; GFX9-NEXT: v_pk_min_f16 v0, v0, s0
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
<2 x half> addrspace(1)* %r, <2 x half> addrspace(1)* %r,
<2 x half> addrspace(1)* %a) #0 { <2 x half> addrspace(1)* %a) #0 {
entry: entry:
%a.val = load <2 x half>, <2 x half> addrspace(1)* %a %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
%r.val = call <2 x half> @llvm.minnum.v2f16(<2 x half> %a.val, <2 x half> <half 4.0, half 3.0>) %r.val = call <2 x half> @llvm.minnum.v2f16(<2 x half> %a.val, <2 x half> <half 4.0, half 3.0>)
store <2 x half> %r.val, <2 x half> addrspace(1)* %r store <2 x half> %r.val, <2 x half> addrspace(1)* %r
ret void ret void
▲ Show 20 Lines • Show All 278 Lines • ▼ Show 20 Lines
; GFX9-LABEL: fmin_v4f16_imm_a: ; GFX9-LABEL: fmin_v4f16_imm_a:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_mov_b32 s8, 0x44004200 ; GFX9-NEXT: s_mov_b32 s8, 0x44004200
; GFX9-NEXT: s_mov_b32 s9, 0x40004800 ; GFX9-NEXT: s_mov_b32 s9, 0x40004800
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[6:7], 0x0
; GFX9-NEXT: s_mov_b32 s0, s4 ; GFX9-NEXT: s_mov_b32 s0, s4
; GFX9-NEXT: s_mov_b32 s1, s5 ; GFX9-NEXT: s_mov_b32 s1, s5
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[6:7], 0x0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_pk_max_f16 v0, s5, s5 ; GFX9-NEXT: v_pk_max_f16 v0, s7, s7
; GFX9-NEXT: v_pk_max_f16 v2, s4, s4 ; GFX9-NEXT: v_pk_max_f16 v2, s6, s6
; GFX9-NEXT: v_pk_min_f16 v1, v0, s8 ; GFX9-NEXT: v_pk_min_f16 v1, v0, s8
; GFX9-NEXT: v_pk_min_f16 v0, v2, s9 ; GFX9-NEXT: v_pk_min_f16 v0, v2, s9
; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
<4 x half> addrspace(1)* %r, <4 x half> addrspace(1)* %r,
<4 x half> addrspace(1)* %b) #0 { <4 x half> addrspace(1)* %b) #0 {
entry: entry:
%b.val = load <4 x half>, <4 x half> addrspace(1)* %b %b.val = load <4 x half>, <4 x half> addrspace(1)* %b
%r.val = call <4 x half> @llvm.minnum.v4f16(<4 x half> <half 8.0, half 2.0, half 3.0, half 4.0>, <4 x half> %b.val) %r.val = call <4 x half> @llvm.minnum.v4f16(<4 x half> <half 8.0, half 2.0, half 3.0, half 4.0>, <4 x half> %b.val)
store <4 x half> %r.val, <4 x half> addrspace(1)* %r store <4 x half> %r.val, <4 x half> addrspace(1)* %r
ret void ret void
} }
attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" } attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" }

llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll

Show First 20 Lines • Show All 71 Lines • ▼ Show 20 Lines
; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, 0 ; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; SI-NEXT: v_mov_b32_e32 v1, 0 ; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b64 s[0:1], s[6:7] ; SI-NEXT: s_mov_b64 s[0:1], s[6:7]
; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 ; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_movk_i32 s9, 0xfc01 ; SI-NEXT: s_movk_i32 s7, 0xfc01
; SI-NEXT: s_mov_b32 s7, 0xfffff ; SI-NEXT: s_mov_b32 s1, 0xfffff
; SI-NEXT: s_mov_b32 s6, -1 ; SI-NEXT: s_mov_b32 s0, -1
; SI-NEXT: s_brev_b32 s8, -2 ; SI-NEXT: s_brev_b32 s6, -2
; SI-NEXT: v_mov_b32_e32 v8, 0x3ff00000 ; SI-NEXT: v_mov_b32_e32 v8, 0x3ff00000
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_bfe_u32 v4, v3, 20, 11 ; SI-NEXT: v_bfe_u32 v4, v3, 20, 11
; SI-NEXT: v_add_i32_e32 v6, vcc, s9, v4 ; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v4
; SI-NEXT: v_lshr_b64 v[4:5], s[6:7], v6 ; SI-NEXT: v_lshr_b64 v[4:5], s[0:1], v6
; SI-NEXT: v_and_b32_e32 v7, 0x80000000, v3 ; SI-NEXT: v_and_b32_e32 v7, 0x80000000, v3
; SI-NEXT: v_not_b32_e32 v4, v4 ; SI-NEXT: v_not_b32_e32 v4, v4
; SI-NEXT: v_not_b32_e32 v5, v5 ; SI-NEXT: v_not_b32_e32 v5, v5
; SI-NEXT: v_and_b32_e32 v5, v3, v5 ; SI-NEXT: v_and_b32_e32 v5, v3, v5
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v6 ; SI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v6
; SI-NEXT: v_and_b32_e32 v4, v2, v4 ; SI-NEXT: v_and_b32_e32 v4, v2, v4
; SI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc ; SI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; SI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc ; SI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
; SI-NEXT: v_cmp_lt_i32_e32 vcc, 51, v6 ; SI-NEXT: v_cmp_lt_i32_e32 vcc, 51, v6
; SI-NEXT: v_cndmask_b32_e32 v5, v5, v3, vcc ; SI-NEXT: v_cndmask_b32_e32 v5, v5, v3, vcc
; SI-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc ; SI-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc
; SI-NEXT: v_add_f64 v[6:7], v[2:3], -v[4:5] ; SI-NEXT: v_add_f64 v[6:7], v[2:3], -v[4:5]
; SI-NEXT: v_bfi_b32 v2, s8, v8, v3 ; SI-NEXT: v_bfi_b32 v2, s6, v8, v3
; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[6:7]|, 0.5 ; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[6:7]|, 0.5
; SI-NEXT: s_mov_b64 s[6:7], s[2:3] ; SI-NEXT: s_mov_b64 s[6:7], s[2:3]
; SI-NEXT: v_cndmask_b32_e32 v3, 0, v2, vcc ; SI-NEXT: v_cndmask_b32_e32 v3, 0, v2, vcc
; SI-NEXT: v_mov_b32_e32 v2, 0 ; SI-NEXT: v_mov_b32_e32 v2, 0
; SI-NEXT: v_add_f64 v[2:3], v[4:5], v[2:3] ; SI-NEXT: v_add_f64 v[2:3], v[4:5], v[2:3]
; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 ; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; CI-LABEL: v_round_f64: ; CI-LABEL: v_round_f64:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; CI-NEXT: s_mov_b32 s3, 0xf000 ; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0 ; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 ; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; CI-NEXT: v_mov_b32_e32 v1, 0 ; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_mov_b64 s[0:1], s[6:7] ; CI-NEXT: s_mov_b64 s[0:1], s[6:7]
; CI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 ; CI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
; CI-NEXT: s_brev_b32 s6, -2 ; CI-NEXT: s_brev_b32 s0, -2
; CI-NEXT: v_mov_b32_e32 v8, 0x3ff00000 ; CI-NEXT: v_mov_b32_e32 v8, 0x3ff00000
; CI-NEXT: s_mov_b64 s[6:7], s[2:3]
; CI-NEXT: s_waitcnt vmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_trunc_f64_e32 v[4:5], v[2:3] ; CI-NEXT: v_trunc_f64_e32 v[4:5], v[2:3]
; CI-NEXT: v_add_f64 v[6:7], v[2:3], -v[4:5] ; CI-NEXT: v_add_f64 v[6:7], v[2:3], -v[4:5]
; CI-NEXT: v_bfi_b32 v2, s6, v8, v3 ; CI-NEXT: v_bfi_b32 v2, s0, v8, v3
; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[6:7]|, 0.5 ; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[6:7]|, 0.5
; CI-NEXT: s_mov_b64 s[6:7], s[2:3]
; CI-NEXT: v_cndmask_b32_e32 v3, 0, v2, vcc ; CI-NEXT: v_cndmask_b32_e32 v3, 0, v2, vcc
; CI-NEXT: v_mov_b32_e32 v2, 0 ; CI-NEXT: v_mov_b32_e32 v2, 0
; CI-NEXT: v_add_f64 v[2:3], v[4:5], v[2:3] ; CI-NEXT: v_add_f64 v[2:3], v[4:5], v[2:3]
; CI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 ; CI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
%gep = getelementptr double, double addrspace(1)* %in, i32 %tid %gep = getelementptr double, double addrspace(1)* %in, i32 %tid
%out.gep = getelementptr double, double addrspace(1)* %out, i32 %tid %out.gep = getelementptr double, double addrspace(1)* %out, i32 %tid
▲ Show 20 Lines • Show All 557 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll

Show First 20 Lines • Show All 112 Lines • ▼ Show 20 Lines
; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_or_b32_e32 v2, v3, v2 ; GFX8-NEXT: v_or_b32_e32 v2, v3, v2
; GFX8-NEXT: flat_store_dword v[0:1], v2 ; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-LABEL: sin_v2f16: ; GFX9-LABEL: sin_v2f16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: v_mov_b32_e32 v2, 0x3118
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s2 ; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: global_load_dword v0, v[0:1], off ; GFX9-NEXT: global_load_dword v0, v[0:1], off
; GFX9-NEXT: v_mov_b32_e32 v1, 0x3118
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mul_f16_e32 v1, 0.15915494, v0 ; GFX9-NEXT: v_mul_f16_e32 v2, 0.15915494, v0
; GFX9-NEXT: v_sin_f16_e32 v3, v1 ; GFX9-NEXT: v_sin_f16_e32 v2, v2
; GFX9-NEXT: v_mul_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX9-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_sin_f16_e32 v2, v0 ; GFX9-NEXT: v_sin_f16_e32 v3, v0
; GFX9-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_and_b32_e32 v3, 0xffff, v3 ; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_lshl_or_b32 v2, v2, 16, v3 ; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: global_store_dword v[0:1], v2, off ; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%a.val = load <2 x half>, <2 x half> addrspace(1)* %a %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
%r.val = call <2 x half> @llvm.sin.v2f16(<2 x half> %a.val) %r.val = call <2 x half> @llvm.sin.v2f16(<2 x half> %a.val)
store <2 x half> %r.val, <2 x half> addrspace(1)* %r store <2 x half> %r.val, <2 x half> addrspace(1)* %r
ret void ret void
} }
declare half @llvm.sin.f16(half %a) declare half @llvm.sin.f16(half %a)
declare <2 x half> @llvm.sin.v2f16(<2 x half> %a) declare <2 x half> @llvm.sin.v2f16(<2 x half> %a)

llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll

Show First 20 Lines • Show All 113 Lines • ▼ Show 20 Lines
; GCN: ; %bb.0: ; %bb ; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-NEXT: v_mov_b32_e32 v2, 0 ; GCN-NEXT: v_mov_b32_e32 v2, 0
; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_mov_b32 s2, 0 ; GCN-NEXT: s_mov_b32 s2, 0
; GCN-NEXT: v_lshlrev_b32_e32 v1, 2, v0 ; GCN-NEXT: v_lshlrev_b32_e32 v1, 2, v0
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b64 s[0:1], s[6:7] ; GCN-NEXT: s_mov_b64 s[0:1], s[6:7]
; GCN-NEXT: buffer_load_dword v1, v[1:2], s[0:3], 0 addr64
; GCN-NEXT: v_lshlrev_b32_e32 v3, 3, v0 ; GCN-NEXT: v_lshlrev_b32_e32 v3, 3, v0
; GCN-NEXT: buffer_load_dword v0, v[1:2], s[0:3], 0 addr64
; GCN-NEXT: s_mov_b64 s[6:7], s[2:3] ; GCN-NEXT: s_mov_b64 s[6:7], s[2:3]
; GCN-NEXT: v_mov_b32_e32 v4, v2 ; GCN-NEXT: v_mov_b32_e32 v4, v2
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_or_b32_e32 v0, 0x800000, v0 ; GCN-NEXT: v_or_b32_e32 v0, 0x800000, v1
; GCN-NEXT: v_mul_i32_i24_e32 v0, -7, v0 ; GCN-NEXT: v_mul_i32_i24_e32 v0, -7, v0
; GCN-NEXT: v_lshlrev_b32_e32 v1, 3, v0 ; GCN-NEXT: v_lshlrev_b32_e32 v1, 3, v0
; GCN-NEXT: buffer_store_dwordx2 v[1:2], v[3:4], s[4:7], 0 addr64 ; GCN-NEXT: buffer_store_dwordx2 v[1:2], v[3:4], s[4:7], 0 addr64
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
bb: bb:
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x() %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
%tmp2 = sext i32 %tmp to i64 %tmp2 = sext i32 %tmp to i64
%tmp3 = getelementptr inbounds i32, i32 addrspace(1)* %arg1, i64 %tmp2 %tmp3 = getelementptr inbounds i32, i32 addrspace(1)* %arg1, i64 %tmp2
Show All 11 Lines

llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll

Show First 20 Lines • Show All 81 Lines • ▼ Show 20 Lines
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_pk_lshrrev_b16 v0, v0, v4 ; GFX9-NEXT: v_pk_lshrrev_b16 v0, v0, v4
; GFX9-NEXT: global_store_dword v[2:3], v0, off ; GFX9-NEXT: global_store_dword v[2:3], v0, off
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: v_lshr_v2i16: ; VI-LABEL: v_lshr_v2i16:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v5, v[0:1]
; VI-NEXT: flat_load_dword v2, v[2:3]
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v4
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v4, vcc, 4, v0
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1]
; VI-NEXT: flat_load_dword v1, v[4:5]
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_lshrrev_b16_e32 v4, v1, v0 ; VI-NEXT: v_lshrrev_b16_e32 v3, v2, v5
; VI-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-NEXT: v_lshrrev_b16_sdwa v2, v2, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-NEXT: v_or_b32_e32 v0, v4, v0 ; VI-NEXT: v_or_b32_e32 v2, v3, v2
; VI-NEXT: flat_store_dword v[2:3], v0 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; CI-LABEL: v_lshr_v2i16: ; CI-LABEL: v_lshr_v2i16:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; CI-NEXT: s_mov_b32 s3, 0xf000 ; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0 ; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; CI-NEXT: v_mov_b32_e32 v1, 0 ; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_mov_b64 s[0:1], s[6:7] ; CI-NEXT: s_mov_b64 s[0:1], s[6:7]
; CI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 ; CI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64
; CI-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 ; CI-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4
; CI-NEXT: s_mov_b32 s8, 0xffff ; CI-NEXT: s_mov_b32 s0, 0xffff
; CI-NEXT: s_mov_b64 s[6:7], s[2:3] ; CI-NEXT: s_mov_b64 s[6:7], s[2:3]
; CI-NEXT: s_waitcnt vmcnt(1) ; CI-NEXT: s_waitcnt vmcnt(1)
; CI-NEXT: v_lshrrev_b32_e32 v4, 16, v2 ; CI-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; CI-NEXT: s_waitcnt vmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_lshrrev_b32_e32 v5, 16, v3 ; CI-NEXT: v_lshrrev_b32_e32 v5, 16, v3
; CI-NEXT: v_and_b32_e32 v2, s8, v2 ; CI-NEXT: v_and_b32_e32 v2, s0, v2
; CI-NEXT: v_and_b32_e32 v3, s8, v3 ; CI-NEXT: v_and_b32_e32 v3, s0, v3
; CI-NEXT: v_lshr_b32_e32 v2, v2, v3 ; CI-NEXT: v_lshr_b32_e32 v2, v2, v3
; CI-NEXT: v_lshr_b32_e32 v3, v4, v5 ; CI-NEXT: v_lshr_b32_e32 v3, v4, v5
; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; CI-NEXT: v_or_b32_e32 v2, v2, v3 ; CI-NEXT: v_or_b32_e32 v2, v2, v3
; CI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64 ; CI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
Show All 30 Lines
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_load_dword s0, s[0:1], 0x34 ; VI-NEXT: s_load_dword s0, s[0:1], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s7 ; VI-NEXT: v_mov_b32_e32 v1, s7
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v3, v[0:1]
; VI-NEXT: s_lshr_b32 s1, s0, 16 ; VI-NEXT: s_lshr_b32 s1, s0, 16
; VI-NEXT: v_mov_b32_e32 v4, s1 ; VI-NEXT: v_add_u32_e32 v0, vcc, s4, v2
; VI-NEXT: v_mov_b32_e32 v3, s5 ; VI-NEXT: v_mov_b32_e32 v2, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v2 ; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_lshrrev_b16_e32 v1, s0, v0 ; VI-NEXT: v_lshrrev_b16_e32 v4, s0, v3
; VI-NEXT: v_lshrrev_b16_sdwa v0, v4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; VI-NEXT: v_lshrrev_b16_sdwa v2, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_or_b32_e32 v0, v1, v0 ; VI-NEXT: v_or_b32_e32 v2, v4, v2
; VI-NEXT: flat_store_dword v[2:3], v0 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; CI-LABEL: lshr_v_s_v2i16: ; CI-LABEL: lshr_v_s_v2i16:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; CI-NEXT: s_load_dword s0, s[0:1], 0xd ; CI-NEXT: s_load_dword s8, s[0:1], 0xd
; CI-NEXT: s_mov_b32 s8, 0xffff
; CI-NEXT: s_mov_b32 s3, 0xf000 ; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0 ; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_lshr_b32 s9, s0, 16
; CI-NEXT: s_and_b32 s10, s0, s8
; CI-NEXT: s_mov_b64 s[0:1], s[6:7] ; CI-NEXT: s_mov_b64 s[0:1], s[6:7]
; CI-NEXT: v_mov_b32_e32 v1, 0 ; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 ; CI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64
; CI-NEXT: s_mov_b32 s0, 0xffff
; CI-NEXT: s_lshr_b32 s1, s8, 16
; CI-NEXT: s_and_b32 s8, s8, s0
; CI-NEXT: s_mov_b64 s[6:7], s[2:3] ; CI-NEXT: s_mov_b64 s[6:7], s[2:3]
; CI-NEXT: s_waitcnt vmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_lshrrev_b32_e32 v3, 16, v2 ; CI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
; CI-NEXT: v_and_b32_e32 v2, s8, v2 ; CI-NEXT: v_and_b32_e32 v2, s0, v2
; CI-NEXT: v_lshrrev_b32_e32 v3, s9, v3 ; CI-NEXT: v_lshrrev_b32_e32 v3, s1, v3
; CI-NEXT: v_lshrrev_b32_e32 v2, s10, v2 ; CI-NEXT: v_lshrrev_b32_e32 v2, s8, v2
; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; CI-NEXT: v_or_b32_e32 v2, v2, v3 ; CI-NEXT: v_or_b32_e32 v2, v2, v3
; CI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64 ; CI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
%out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
Show All 26 Lines
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_load_dword s0, s[0:1], 0x34 ; VI-NEXT: s_load_dword s0, s[0:1], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s7 ; VI-NEXT: v_mov_b32_e32 v1, s7
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v3, v[0:1]
; VI-NEXT: s_lshr_b32 s1, s0, 16 ; VI-NEXT: s_lshr_b32 s1, s0, 16
; VI-NEXT: v_mov_b32_e32 v4, s1 ; VI-NEXT: v_add_u32_e32 v0, vcc, s4, v2
; VI-NEXT: v_mov_b32_e32 v3, s5 ; VI-NEXT: v_mov_b32_e32 v2, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v2 ; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_lshrrev_b16_e64 v1, v0, s0 ; VI-NEXT: v_lshrrev_b16_e64 v4, v3, s0
; VI-NEXT: v_lshrrev_b16_sdwa v0, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; VI-NEXT: v_lshrrev_b16_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v1, v0 ; VI-NEXT: v_or_b32_e32 v2, v4, v2
; VI-NEXT: flat_store_dword v[2:3], v0 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; CI-LABEL: lshr_s_v_v2i16: ; CI-LABEL: lshr_s_v_v2i16:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; CI-NEXT: s_load_dword s0, s[0:1], 0xd ; CI-NEXT: s_load_dword s8, s[0:1], 0xd
; CI-NEXT: s_mov_b32 s8, 0xffff
; CI-NEXT: s_mov_b32 s3, 0xf000 ; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0 ; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_lshr_b32 s9, s0, 16
; CI-NEXT: s_and_b32 s10, s0, s8
; CI-NEXT: s_mov_b64 s[0:1], s[6:7] ; CI-NEXT: s_mov_b64 s[0:1], s[6:7]
; CI-NEXT: v_mov_b32_e32 v1, 0 ; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 ; CI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64
; CI-NEXT: s_mov_b32 s0, 0xffff
; CI-NEXT: s_lshr_b32 s1, s8, 16
; CI-NEXT: s_and_b32 s8, s8, s0
; CI-NEXT: s_mov_b64 s[6:7], s[2:3] ; CI-NEXT: s_mov_b64 s[6:7], s[2:3]
; CI-NEXT: s_waitcnt vmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_lshrrev_b32_e32 v3, 16, v2 ; CI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
; CI-NEXT: v_and_b32_e32 v2, s8, v2 ; CI-NEXT: v_and_b32_e32 v2, s0, v2
; CI-NEXT: v_lshr_b32_e32 v3, s9, v3 ; CI-NEXT: v_lshr_b32_e32 v3, s1, v3
; CI-NEXT: v_lshr_b32_e32 v2, s10, v2 ; CI-NEXT: v_lshr_b32_e32 v2, s8, v2
; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; CI-NEXT: v_or_b32_e32 v2, v2, v3 ; CI-NEXT: v_or_b32_e32 v2, v2, v3
; CI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64 ; CI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
%out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
Show All 25 Lines
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: v_mov_b32_e32 v4, 8 ; VI-NEXT: v_mov_b32_e32 v4, 8
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v3, v[0:1]
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_lshrrev_b16_e64 v1, v0, 8 ; VI-NEXT: v_lshrrev_b16_e64 v2, v3, 8
; VI-NEXT: v_lshrrev_b16_sdwa v0, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; VI-NEXT: v_lshrrev_b16_sdwa v3, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v1, v0 ; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: flat_store_dword v[2:3], v0 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; CI-LABEL: lshr_imm_v_v2i16: ; CI-LABEL: lshr_imm_v_v2i16:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; CI-NEXT: s_mov_b32 s3, 0xf000 ; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0 ; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
▲ Show 20 Lines • Show All 83 Lines • ▼ Show 20 Lines; CI-NEXT: s_endpgm
store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep
ret void ret void
} }
define amdgpu_kernel void @v_lshr_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) #0 { define amdgpu_kernel void @v_lshr_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) #0 {
; GFX9-LABEL: v_lshr_v4i16: ; GFX9-LABEL: v_lshr_v4i16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 3, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v4, 3, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v4
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: global_load_dwordx2 v[4:5], v[0:1], off ; GFX9-NEXT: global_load_dwordx2 v[2:3], v[0:1], off
; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off offset:8 ; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off offset:8
; GFX9-NEXT: v_mov_b32_e32 v3, s1 ; GFX9-NEXT: v_mov_b32_e32 v5, s1
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, s0, v4
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_pk_lshrrev_b16 v1, v1, v5 ; GFX9-NEXT: v_pk_lshrrev_b16 v1, v1, v3
; GFX9-NEXT: v_pk_lshrrev_b16 v0, v0, v4 ; GFX9-NEXT: v_pk_lshrrev_b16 v0, v0, v2
; GFX9-NEXT: global_store_dwordx2 v[2:3], v[0:1], off ; GFX9-NEXT: global_store_dwordx2 v[4:5], v[0:1], off
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: v_lshr_v4i16: ; VI-LABEL: v_lshr_v4i16:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v0 ; VI-NEXT: v_lshlrev_b32_e32 v4, 3, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2 ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v4, vcc, 8, v0
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] ; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; VI-NEXT: flat_load_dwordx2 v[4:5], v[4:5] ; VI-NEXT: flat_load_dwordx2 v[2:3], v[2:3]
; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_add_u32_e32 v4, vcc, s0, v4
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_lshrrev_b16_e32 v6, v5, v1 ; VI-NEXT: v_lshrrev_b16_e32 v6, v3, v1
; VI-NEXT: v_lshrrev_b16_sdwa v1, v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-NEXT: v_lshrrev_b16_sdwa v1, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-NEXT: v_lshrrev_b16_e32 v5, v4, v0 ; VI-NEXT: v_lshrrev_b16_e32 v3, v2, v0
; VI-NEXT: v_lshrrev_b16_sdwa v0, v4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-NEXT: v_lshrrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-NEXT: v_or_b32_e32 v1, v6, v1 ; VI-NEXT: v_or_b32_e32 v1, v6, v1
; VI-NEXT: v_or_b32_e32 v0, v5, v0 ; VI-NEXT: v_or_b32_e32 v0, v3, v0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; CI-LABEL: v_lshr_v4i16: ; CI-LABEL: v_lshr_v4i16:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; CI-NEXT: s_mov_b32 s3, 0xf000 ; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0 ; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 ; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; CI-NEXT: v_mov_b32_e32 v1, 0 ; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_mov_b64 s[0:1], s[6:7] ; CI-NEXT: s_mov_b64 s[0:1], s[6:7]
; CI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 ; CI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
; CI-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[0:3], 0 addr64 offset:8 ; CI-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[0:3], 0 addr64 offset:8
; CI-NEXT: s_mov_b32 s8, 0xffff ; CI-NEXT: s_mov_b32 s0, 0xffff
; CI-NEXT: s_mov_b64 s[6:7], s[2:3] ; CI-NEXT: s_mov_b64 s[6:7], s[2:3]
; CI-NEXT: s_waitcnt vmcnt(1) ; CI-NEXT: s_waitcnt vmcnt(1)
; CI-NEXT: v_lshrrev_b32_e32 v6, 16, v2 ; CI-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; CI-NEXT: v_lshrrev_b32_e32 v7, 16, v3 ; CI-NEXT: v_lshrrev_b32_e32 v7, 16, v3
; CI-NEXT: s_waitcnt vmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_lshrrev_b32_e32 v8, 16, v4 ; CI-NEXT: v_lshrrev_b32_e32 v8, 16, v4
; CI-NEXT: v_lshrrev_b32_e32 v9, 16, v5 ; CI-NEXT: v_lshrrev_b32_e32 v9, 16, v5
; CI-NEXT: v_and_b32_e32 v2, s8, v2 ; CI-NEXT: v_and_b32_e32 v2, s0, v2
; CI-NEXT: v_and_b32_e32 v4, s8, v4 ; CI-NEXT: v_and_b32_e32 v4, s0, v4
; CI-NEXT: v_and_b32_e32 v3, s8, v3 ; CI-NEXT: v_and_b32_e32 v3, s0, v3
; CI-NEXT: v_and_b32_e32 v5, s8, v5 ; CI-NEXT: v_and_b32_e32 v5, s0, v5
; CI-NEXT: v_lshr_b32_e32 v3, v3, v5 ; CI-NEXT: v_lshr_b32_e32 v3, v3, v5
; CI-NEXT: v_lshr_b32_e32 v5, v7, v9 ; CI-NEXT: v_lshr_b32_e32 v5, v7, v9
; CI-NEXT: v_lshr_b32_e32 v2, v2, v4 ; CI-NEXT: v_lshr_b32_e32 v2, v2, v4
; CI-NEXT: v_lshr_b32_e32 v4, v6, v8 ; CI-NEXT: v_lshr_b32_e32 v4, v6, v8
; CI-NEXT: v_lshlrev_b32_e32 v5, 16, v5 ; CI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; CI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; CI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; CI-NEXT: v_or_b32_e32 v3, v3, v5 ; CI-NEXT: v_or_b32_e32 v3, v3, v5
; CI-NEXT: v_or_b32_e32 v2, v2, v4 ; CI-NEXT: v_or_b32_e32 v2, v2, v4
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; CI-NEXT: s_mov_b32 s3, 0xf000 ; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0 ; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 ; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; CI-NEXT: v_mov_b32_e32 v1, 0 ; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_mov_b64 s[0:1], s[6:7] ; CI-NEXT: s_mov_b64 s[0:1], s[6:7]
; CI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 ; CI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
; CI-NEXT: s_mov_b32 s8, 0xff00ff ; CI-NEXT: s_mov_b32 s0, 0xff00ff
; CI-NEXT: s_mov_b64 s[6:7], s[2:3] ; CI-NEXT: s_mov_b64 s[6:7], s[2:3]
; CI-NEXT: s_waitcnt vmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_lshrrev_b32_e32 v3, 8, v3 ; CI-NEXT: v_lshrrev_b32_e32 v3, 8, v3
; CI-NEXT: v_lshrrev_b32_e32 v2, 8, v2 ; CI-NEXT: v_lshrrev_b32_e32 v2, 8, v2
; CI-NEXT: v_and_b32_e32 v3, s8, v3 ; CI-NEXT: v_and_b32_e32 v3, s0, v3
; CI-NEXT: v_and_b32_e32 v2, s8, v2 ; CI-NEXT: v_and_b32_e32 v2, s0, v2
; CI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 ; CI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%in.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %in, i64 %tid.ext %in.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %in, i64 %tid.ext
%out.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %out, i64 %tid.ext
%vgpr = load <4 x i16>, <4 x i16> addrspace(1)* %in.gep %vgpr = load <4 x i16>, <4 x i16> addrspace(1)* %in.gep
%result = lshr <4 x i16> %vgpr, <i16 8, i16 8, i16 8, i16 8> %result = lshr <4 x i16> %vgpr, <i16 8, i16 8, i16 8, i16 8>
store <4 x i16> %result, <4 x i16> addrspace(1)* %out.gep store <4 x i16> %result, <4 x i16> addrspace(1)* %out.gep
ret void ret void
} }
declare i32 @llvm.amdgcn.workitem.id.x() #1 declare i32 @llvm.amdgcn.workitem.id.x() #1
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }

llvm/test/CodeGen/AMDGPU/madak.ll

Show All 33 Linesdefine amdgpu_kernel void @madak_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b) #0 {
ret void ret void
} }
; Make sure this is only folded with one use. This is a code size ; Make sure this is only folded with one use. This is a code size
; optimization and if we fold the immediate multiple times, we'll undo ; optimization and if we fold the immediate multiple times, we'll undo
; it. ; it.
; GCN-LABEL: {{^}}madak_2_use_f32: ; GCN-LABEL: {{^}}madak_2_use_f32:
; GFX8_9_10: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000 ; GFX9: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000
; GFX10: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000
; GFX6-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; GFX6-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
; GFX6-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 ; GFX6-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
; GFX6-DAG: buffer_load_dword [[VC:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 ; GFX6-DAG: buffer_load_dword [[VC:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
; GFX8_9_10: {{flat|global}}_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}} ; GFX8_9_10: {{flat|global}}_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}
; GFX8_9_10: {{flat|global}}_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}} ; GFX8_9_10: {{flat|global}}_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}
; GFX8_9_10: {{flat|global}}_load_dword [[VC:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}} ; GFX8_9_10: {{flat|global}}_load_dword [[VC:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}
; GFX6-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000 ; GFX6-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000
; GFX8-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000
; GFX6_8_9-DAG: v_madak_f32 {{v[0-9]+}}, [[VA]], [[VB]], 0x41200000 ; GFX6_8_9-DAG: v_madak_f32 {{v[0-9]+}}, [[VA]], [[VB]], 0x41200000
; GFX10-MAD-DAG:v_madak_f32 {{v[0-9]+}}, [[VA]], [[VB]], 0x41200000 ; GFX10-MAD-DAG:v_madak_f32 {{v[0-9]+}}, [[VA]], [[VB]], 0x41200000
; FMA-DAG: v_fmaak_f32 {{v[0-9]+}}, [[VA]], [[VB]], 0x41200000 ; FMA-DAG: v_fmaak_f32 {{v[0-9]+}}, [[VA]], [[VB]], 0x41200000
; MAD-DAG: v_mac_f32_e32 [[VK]], [[VA]], [[VC]] ; MAD-DAG: v_mac_f32_e32 [[VK]], [[VA]], [[VC]]
; FMA-DAG: v_fmac_f32_e32 [[VK]], [[VA]], [[VC]] ; FMA-DAG: v_fmac_f32_e32 [[VK]], [[VA]], [[VC]]
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @madak_2_use_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #0 { define amdgpu_kernel void @madak_2_use_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #0 {
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
▲ Show 20 Lines • Show All 211 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/max.i16.ll

Show First 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s7 ; VI-NEXT: v_mov_b32_e32 v1, s7
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v5, v[0:1]
; VI-NEXT: flat_load_dword v1, v[2:3] ; VI-NEXT: flat_load_dword v2, v[2:3]
; VI-NEXT: v_mov_b32_e32 v5, s5 ; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_add_u32_e32 v4, vcc, s4, v4 ; VI-NEXT: v_add_u32_e32 v0, vcc, s4, v4
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_max_i16_e32 v2, v0, v1 ; VI-NEXT: v_max_i16_e32 v3, v5, v2
; VI-NEXT: v_max_i16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-NEXT: v_max_i16_sdwa v2, v5, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-NEXT: v_or_b32_e32 v0, v2, v0 ; VI-NEXT: v_or_b32_e32 v2, v3, v2
; VI-NEXT: flat_store_dword v[4:5], v0 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_test_imax_sge_v2i16: ; GFX9-LABEL: v_test_imax_sge_v2i16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v4, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
Show All 25 Lines
} }
; FIXME: Need to handle non-uniform case for function below (load without gep). ; FIXME: Need to handle non-uniform case for function below (load without gep).
define amdgpu_kernel void @v_test_imax_sge_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> addrspace(1)* %aptr, <3 x i16> addrspace(1)* %bptr) nounwind { define amdgpu_kernel void @v_test_imax_sge_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> addrspace(1)* %aptr, <3 x i16> addrspace(1)* %bptr) nounwind {
; VI-LABEL: v_test_imax_sge_v3i16: ; VI-LABEL: v_test_imax_sge_v3i16:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v4, 3, v0 ; VI-NEXT: v_lshlrev_b32_e32 v6, 3, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s7 ; VI-NEXT: v_mov_b32_e32 v1, s7
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v6
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v6
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_mov_b32_e32 v5, s5 ; VI-NEXT: v_add_u32_e32 v4, vcc, 4, v0
; VI-NEXT: v_add_u32_e32 v4, vcc, s4, v4 ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc ; VI-NEXT: flat_load_ushort v4, v[4:5]
; VI-NEXT: v_add_u32_e32 v6, vcc, 4, v0 ; VI-NEXT: flat_load_dword v5, v[0:1]
; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc
; VI-NEXT: flat_load_ushort v6, v[6:7]
; VI-NEXT: flat_load_dword v7, v[0:1]
; VI-NEXT: v_add_u32_e32 v0, vcc, 4, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, 4, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
; VI-NEXT: flat_load_ushort v0, v[0:1] ; VI-NEXT: flat_load_dword v7, v[2:3]
; VI-NEXT: flat_load_dword v8, v[2:3] ; VI-NEXT: flat_load_ushort v8, v[0:1]
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v4 ; VI-NEXT: v_add_u32_e32 v0, vcc, s4, v6
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc ; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; VI-NEXT: s_waitcnt vmcnt(1) lgkmcnt(1) ; VI-NEXT: s_waitcnt vmcnt(1) lgkmcnt(1)
; VI-NEXT: v_max_i16_e32 v0, v6, v0 ; VI-NEXT: v_max_i16_e32 v6, v5, v7
; VI-NEXT: v_max_i16_sdwa v5, v5, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_max_i16_e32 v1, v7, v8 ; VI-NEXT: v_max_i16_e32 v4, v4, v8
; VI-NEXT: v_max_i16_sdwa v7, v7, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-NEXT: v_or_b32_e32 v5, v6, v5
; VI-NEXT: v_or_b32_e32 v1, v1, v7 ; VI-NEXT: flat_store_short v[2:3], v4
; VI-NEXT: flat_store_short v[2:3], v0 ; VI-NEXT: flat_store_dword v[0:1], v5
; VI-NEXT: flat_store_dword v[4:5], v1
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_test_imax_sge_v3i16: ; GFX9-LABEL: v_test_imax_sge_v3i16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 3, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v5, 3, v0
; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: v_mov_b32_e32 v6, 0 ; GFX9-NEXT: v_mov_b32_e32 v6, 0
; GFX9-NEXT: v_mov_b32_e32 v7, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, s7 ; GFX9-NEXT: v_mov_b32_e32 v1, s7
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s6, v4 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s6, v5
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: v_mov_b32_e32 v3, s1 ; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v4 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v5
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: global_load_short_d16 v7, v[0:1], off offset:4 ; GFX9-NEXT: global_load_short_d16 v6, v[0:1], off offset:4
; GFX9-NEXT: global_load_dword v0, v[0:1], off ; GFX9-NEXT: global_load_dword v7, v[0:1], off
; GFX9-NEXT: global_load_short_d16 v6, v[2:3], off offset:4 ; GFX9-NEXT: global_load_short_d16 v4, v[2:3], off offset:4
; GFX9-NEXT: global_load_dword v1, v[2:3], off ; GFX9-NEXT: global_load_dword v2, v[2:3], off
; GFX9-NEXT: v_mov_b32_e32 v5, s5 ; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, s4, v4 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s4, v5
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_pk_max_i16 v3, v6, v4
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_pk_max_i16 v0, v0, v1 ; GFX9-NEXT: v_pk_max_i16 v2, v7, v2
; GFX9-NEXT: v_pk_max_i16 v1, v7, v6 ; GFX9-NEXT: global_store_short v[0:1], v3, off offset:4
; GFX9-NEXT: global_store_short v[4:5], v1, off offset:4 ; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: global_store_dword v[4:5], v0, off
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
%gep0 = getelementptr <3 x i16>, <3 x i16> addrspace(1)* %aptr, i32 %tid %gep0 = getelementptr <3 x i16>, <3 x i16> addrspace(1)* %aptr, i32 %tid
%gep1 = getelementptr <3 x i16>, <3 x i16> addrspace(1)* %bptr, i32 %tid %gep1 = getelementptr <3 x i16>, <3 x i16> addrspace(1)* %bptr, i32 %tid
%outgep = getelementptr <3 x i16>, <3 x i16> addrspace(1)* %out, i32 %tid %outgep = getelementptr <3 x i16>, <3 x i16> addrspace(1)* %out, i32 %tid
%a = load <3 x i16>, <3 x i16> addrspace(1)* %gep0, align 4 %a = load <3 x i16>, <3 x i16> addrspace(1)* %gep0, align 4
%b = load <3 x i16>, <3 x i16> addrspace(1)* %gep1, align 4 %b = load <3 x i16>, <3 x i16> addrspace(1)* %gep1, align 4
%cmp = icmp sge <3 x i16> %a, %b %cmp = icmp sge <3 x i16> %a, %b
▲ Show 20 Lines • Show All 244 Lines • ▼ Show 20 Lines
; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s7 ; VI-NEXT: v_mov_b32_e32 v1, s7
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v5, v[0:1]
; VI-NEXT: flat_load_dword v1, v[2:3] ; VI-NEXT: flat_load_dword v2, v[2:3]
; VI-NEXT: v_mov_b32_e32 v5, s5 ; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_add_u32_e32 v4, vcc, s4, v4 ; VI-NEXT: v_add_u32_e32 v0, vcc, s4, v4
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_max_u16_e32 v2, v0, v1 ; VI-NEXT: v_max_u16_e32 v3, v5, v2
; VI-NEXT: v_max_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-NEXT: v_max_u16_sdwa v2, v5, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-NEXT: v_or_b32_e32 v0, v2, v0 ; VI-NEXT: v_or_b32_e32 v2, v3, v2
; VI-NEXT: flat_store_dword v[4:5], v0 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_test_umax_ugt_v2i16: ; GFX9-LABEL: v_test_umax_ugt_v2i16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v4, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
Show All 28 Lines

llvm/test/CodeGen/AMDGPU/memory_clause.ll

Show First 20 Lines • Show All 102 Lines • ▼ Show 20 Lines
define void @mubuf_clause(<4 x i32> addrspace(5)* noalias nocapture readonly %arg, <4 x i32> addrspace(5)* noalias nocapture %arg1) { define void @mubuf_clause(<4 x i32> addrspace(5)* noalias nocapture readonly %arg, <4 x i32> addrspace(5)* noalias nocapture %arg1) {
; GCN-LABEL: mubuf_clause: ; GCN-LABEL: mubuf_clause:
; GCN: ; %bb.0: ; %bb ; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_and_b32_e32 v2, 0x3ff, v2 ; GCN-NEXT: v_and_b32_e32 v2, 0x3ff, v2
; GCN-NEXT: v_lshlrev_b32_e32 v2, 4, v2 ; GCN-NEXT: v_lshlrev_b32_e32 v2, 4, v2
; GCN-NEXT: v_add_u32_e32 v0, v0, v2 ; GCN-NEXT: v_add_u32_e32 v0, v0, v2
; GCN-NEXT: buffer_load_dword v3, v0, s[0:3], 0 offen
; GCN-NEXT: buffer_load_dword v4, v0, s[0:3], 0 offen offset:4
; GCN-NEXT: buffer_load_dword v5, v0, s[0:3], 0 offen offset:8
; GCN-NEXT: buffer_load_dword v6, v0, s[0:3], 0 offen offset:12
; GCN-NEXT: buffer_load_dword v7, v0, s[0:3], 0 offen offset:16
; GCN-NEXT: buffer_load_dword v8, v0, s[0:3], 0 offen offset:20
; GCN-NEXT: buffer_load_dword v9, v0, s[0:3], 0 offen offset:24
; GCN-NEXT: buffer_load_dword v10, v0, s[0:3], 0 offen offset:28
; GCN-NEXT: buffer_load_dword v11, v0, s[0:3], 0 offen offset:32
; GCN-NEXT: buffer_load_dword v12, v0, s[0:3], 0 offen offset:36
; GCN-NEXT: buffer_load_dword v13, v0, s[0:3], 0 offen offset:40
; GCN-NEXT: buffer_load_dword v14, v0, s[0:3], 0 offen offset:44
; GCN-NEXT: buffer_load_dword v15, v0, s[0:3], 0 offen offset:48
; GCN-NEXT: buffer_load_dword v16, v0, s[0:3], 0 offen offset:52
; GCN-NEXT: buffer_load_dword v17, v0, s[0:3], 0 offen offset:56
; GCN-NEXT: v_add_u32_e32 v1, v1, v2 ; GCN-NEXT: v_add_u32_e32 v1, v1, v2
; GCN-NEXT: buffer_load_dword v6, v0, s[0:3], 0 offen offset:20 ; GCN-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen offset:60
; GCN-NEXT: buffer_load_dword v7, v0, s[0:3], 0 offen offset:24
; GCN-NEXT: buffer_load_dword v8, v0, s[0:3], 0 offen offset:28
; GCN-NEXT: buffer_load_dword v9, v0, s[0:3], 0 offen offset:32
; GCN-NEXT: buffer_load_dword v10, v0, s[0:3], 0 offen offset:36
; GCN-NEXT: buffer_load_dword v11, v0, s[0:3], 0 offen offset:40
; GCN-NEXT: buffer_load_dword v12, v0, s[0:3], 0 offen offset:44
; GCN-NEXT: buffer_load_dword v13, v0, s[0:3], 0 offen offset:48
; GCN-NEXT: buffer_load_dword v14, v0, s[0:3], 0 offen offset:52
; GCN-NEXT: buffer_load_dword v15, v0, s[0:3], 0 offen offset:56
; GCN-NEXT: buffer_load_dword v16, v0, s[0:3], 0 offen offset:60
; GCN-NEXT: buffer_load_dword v2, v0, s[0:3], 0 offen
; GCN-NEXT: buffer_load_dword v3, v0, s[0:3], 0 offen offset:4
; GCN-NEXT: buffer_load_dword v4, v0, s[0:3], 0 offen offset:8
; GCN-NEXT: buffer_load_dword v5, v0, s[0:3], 0 offen offset:12
; GCN-NEXT: s_nop 0 ; GCN-NEXT: s_nop 0
; GCN-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen offset:16 ; GCN-NEXT: s_waitcnt vmcnt(15)
; GCN-NEXT: s_nop 0 ; GCN-NEXT: buffer_store_dword v3, v1, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(4) ; GCN-NEXT: s_waitcnt vmcnt(15)
; GCN-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; GCN-NEXT: buffer_store_dword v4, v1, s[0:3], 0 offen offset:4
; GCN-NEXT: s_waitcnt vmcnt(4) ; GCN-NEXT: s_waitcnt vmcnt(15)
; GCN-NEXT: buffer_store_dword v3, v1, s[0:3], 0 offen offset:4 ; GCN-NEXT: buffer_store_dword v5, v1, s[0:3], 0 offen offset:8
; GCN-NEXT: s_waitcnt vmcnt(4) ; GCN-NEXT: s_waitcnt vmcnt(15)
; GCN-NEXT: buffer_store_dword v4, v1, s[0:3], 0 offen offset:8 ; GCN-NEXT: buffer_store_dword v6, v1, s[0:3], 0 offen offset:12
; GCN-NEXT: s_waitcnt vmcnt(4) ; GCN-NEXT: s_waitcnt vmcnt(15)
; GCN-NEXT: buffer_store_dword v5, v1, s[0:3], 0 offen offset:12 ; GCN-NEXT: buffer_store_dword v7, v1, s[0:3], 0 offen offset:16
; GCN-NEXT: s_waitcnt vmcnt(4) ; GCN-NEXT: s_waitcnt vmcnt(15)
; GCN-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:16 ; GCN-NEXT: buffer_store_dword v8, v1, s[0:3], 0 offen offset:20
; GCN-NEXT: buffer_store_dword v6, v1, s[0:3], 0 offen offset:20 ; GCN-NEXT: s_waitcnt vmcnt(15)
; GCN-NEXT: buffer_store_dword v7, v1, s[0:3], 0 offen offset:24 ; GCN-NEXT: buffer_store_dword v9, v1, s[0:3], 0 offen offset:24
; GCN-NEXT: buffer_store_dword v8, v1, s[0:3], 0 offen offset:28 ; GCN-NEXT: s_waitcnt vmcnt(15)
; GCN-NEXT: buffer_store_dword v9, v1, s[0:3], 0 offen offset:32 ; GCN-NEXT: buffer_store_dword v10, v1, s[0:3], 0 offen offset:28
; GCN-NEXT: buffer_store_dword v10, v1, s[0:3], 0 offen offset:36 ; GCN-NEXT: s_waitcnt vmcnt(15)
; GCN-NEXT: buffer_store_dword v11, v1, s[0:3], 0 offen offset:40 ; GCN-NEXT: buffer_store_dword v11, v1, s[0:3], 0 offen offset:32
; GCN-NEXT: buffer_store_dword v12, v1, s[0:3], 0 offen offset:44 ; GCN-NEXT: s_waitcnt vmcnt(15)
; GCN-NEXT: buffer_store_dword v13, v1, s[0:3], 0 offen offset:48 ; GCN-NEXT: buffer_store_dword v12, v1, s[0:3], 0 offen offset:36
; GCN-NEXT: buffer_store_dword v14, v1, s[0:3], 0 offen offset:52 ; GCN-NEXT: s_waitcnt vmcnt(15)
; GCN-NEXT: buffer_store_dword v15, v1, s[0:3], 0 offen offset:56 ; GCN-NEXT: buffer_store_dword v13, v1, s[0:3], 0 offen offset:40
; GCN-NEXT: buffer_store_dword v16, v1, s[0:3], 0 offen offset:60 ; GCN-NEXT: s_waitcnt vmcnt(15)
; GCN-NEXT: buffer_store_dword v14, v1, s[0:3], 0 offen offset:44
; GCN-NEXT: s_waitcnt vmcnt(15)
; GCN-NEXT: buffer_store_dword v15, v1, s[0:3], 0 offen offset:48
; GCN-NEXT: s_waitcnt vmcnt(15)
; GCN-NEXT: buffer_store_dword v16, v1, s[0:3], 0 offen offset:52
; GCN-NEXT: s_waitcnt vmcnt(15)
; GCN-NEXT: buffer_store_dword v17, v1, s[0:3], 0 offen offset:56
; GCN-NEXT: s_waitcnt vmcnt(15)
; GCN-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:60
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
bb: bb:
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x() %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
%tmp2 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(5)* %arg, i32 %tmp %tmp2 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(5)* %arg, i32 %tmp
%tmp3 = load <4 x i32>, <4 x i32> addrspace(5)* %tmp2, align 16 %tmp3 = load <4 x i32>, <4 x i32> addrspace(5)* %tmp2, align 16
%tmp4 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(5)* %arg1, i32 %tmp %tmp4 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(5)* %arg1, i32 %tmp
%tmp5 = add nuw nsw i32 %tmp, 1 %tmp5 = add nuw nsw i32 %tmp, 1
▲ Show 20 Lines • Show All 112 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll

Show First 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
define void @lsr_order_mul24_1(i32 %arg, i32 %arg1, i32 %arg2, float addrspace(3)* nocapture %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, float addrspace(1)* nocapture readonly %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15, i32 %arg16, i1 zeroext %arg17, i1 zeroext %arg18) #0 { define void @lsr_order_mul24_1(i32 %arg, i32 %arg1, i32 %arg2, float addrspace(3)* nocapture %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, float addrspace(1)* nocapture readonly %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15, i32 %arg16, i1 zeroext %arg17, i1 zeroext %arg18) #0 {
; GFX9-LABEL: lsr_order_mul24_1: ; GFX9-LABEL: lsr_order_mul24_1:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_and_b32_e32 v5, 1, v18 ; GFX9-NEXT: v_and_b32_e32 v5, 1, v18
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v5 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v5
; GFX9-NEXT: v_cmp_lt_u32_e64 s[4:5], v0, v1 ; GFX9-NEXT: v_cmp_lt_u32_e64 s[4:5], v0, v1
; GFX9-NEXT: s_and_saveexec_b64 s[10:11], s[4:5] ; GFX9-NEXT: s_and_saveexec_b64 s[8:9], s[4:5]
; GFX9-NEXT: s_cbranch_execz BB1_3 ; GFX9-NEXT: s_cbranch_execz BB1_3
; GFX9-NEXT: ; %bb.1: ; %bb19 ; GFX9-NEXT: ; %bb.1: ; %bb19
; GFX9-NEXT: v_cvt_f32_u32_e32 v7, v6 ; GFX9-NEXT: v_cvt_f32_u32_e32 v7, v6
; GFX9-NEXT: v_and_b32_e32 v5, 0xffffff, v6 ; GFX9-NEXT: v_and_b32_e32 v5, 0xffffff, v6
; GFX9-NEXT: v_add_u32_e32 v6, v4, v0 ; GFX9-NEXT: v_add_u32_e32 v6, v4, v0
; GFX9-NEXT: v_lshl_add_u32 v3, v6, 2, v3 ; GFX9-NEXT: v_lshl_add_u32 v3, v6, 2, v3
; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v7 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v7
; GFX9-NEXT: v_lshlrev_b32_e32 v6, 2, v2 ; GFX9-NEXT: v_lshlrev_b32_e32 v6, 2, v2
; GFX9-NEXT: v_add_u32_e32 v7, v17, v12 ; GFX9-NEXT: v_add_u32_e32 v7, v17, v12
; GFX9-NEXT: s_mov_b64 s[12:13], 0 ; GFX9-NEXT: s_mov_b64 s[10:11], 0
; GFX9-NEXT: BB1_2: ; %bb23 ; GFX9-NEXT: BB1_2: ; %bb23
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_cvt_f32_u32_e32 v8, v0 ; GFX9-NEXT: v_cvt_f32_u32_e32 v8, v0
; GFX9-NEXT: v_add_u32_e32 v9, v17, v0 ; GFX9-NEXT: v_add_u32_e32 v9, v17, v0
; GFX9-NEXT: v_add_u32_e32 v12, v7, v0 ; GFX9-NEXT: v_add_u32_e32 v12, v7, v0
; GFX9-NEXT: v_add_u32_e32 v0, v0, v2 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
; GFX9-NEXT: v_madak_f32 v8, v8, v4, 0x3727c5ac ; GFX9-NEXT: v_madak_f32 v8, v8, v4, 0x3727c5ac
; GFX9-NEXT: v_cvt_u32_f32_e32 v8, v8 ; GFX9-NEXT: v_cvt_u32_f32_e32 v8, v8
; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v1
; GFX9-NEXT: v_mul_u32_u24_e32 v18, v8, v5 ; GFX9-NEXT: v_mul_u32_u24_e32 v18, v8, v5
; GFX9-NEXT: v_add_u32_e32 v8, v8, v16 ; GFX9-NEXT: v_add_u32_e32 v8, v8, v16
; GFX9-NEXT: v_cmp_lt_u32_e64 s[6:7], v8, v13 ; GFX9-NEXT: v_cmp_lt_u32_e64 s[4:5], v8, v13
; GFX9-NEXT: v_mul_lo_u32 v8, v8, v15 ; GFX9-NEXT: v_mul_lo_u32 v8, v8, v15
; GFX9-NEXT: v_sub_u32_e32 v19, v9, v18 ; GFX9-NEXT: v_sub_u32_e32 v19, v9, v18
; GFX9-NEXT: v_cmp_lt_u32_e64 s[8:9], v19, v14 ; GFX9-NEXT: v_cmp_lt_u32_e64 s[6:7], v19, v14
; GFX9-NEXT: s_and_b64 s[6:7], s[6:7], s[8:9] ; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], s[6:7]
; GFX9-NEXT: v_sub_u32_e32 v12, v12, v18 ; GFX9-NEXT: v_sub_u32_e32 v12, v12, v18
; GFX9-NEXT: s_and_b64 s[6:7], s[6:7], vcc
; GFX9-NEXT: v_add_u32_e32 v8, v12, v8 ; GFX9-NEXT: v_add_u32_e32 v8, v12, v8
; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], vcc
; GFX9-NEXT: v_mov_b32_e32 v9, 0 ; GFX9-NEXT: v_mov_b32_e32 v9, 0
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, v8, s[6:7] ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, v8, s[4:5]
; GFX9-NEXT: v_lshlrev_b64 v[8:9], 2, v[8:9] ; GFX9-NEXT: v_lshlrev_b64 v[8:9], 2, v[8:9]
; GFX9-NEXT: s_or_b64 s[12:13], s[4:5], s[12:13] ; GFX9-NEXT: v_add_co_u32_e64 v8, s[6:7], v10, v8
; GFX9-NEXT: v_add_co_u32_e64 v8, s[4:5], v10, v8 ; GFX9-NEXT: v_addc_co_u32_e64 v9, s[6:7], v11, v9, s[6:7]
; GFX9-NEXT: v_addc_co_u32_e64 v9, s[4:5], v11, v9, s[4:5]
; GFX9-NEXT: global_load_dword v8, v[8:9], off ; GFX9-NEXT: global_load_dword v8, v[8:9], off
; GFX9-NEXT: v_cmp_ge_u32_e64 s[6:7], v0, v1
; GFX9-NEXT: s_or_b64 s[10:11], s[6:7], s[10:11]
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, v8, s[6:7] ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, v8, s[4:5]
; GFX9-NEXT: ds_write_b32 v3, v8 ; GFX9-NEXT: ds_write_b32 v3, v8
; GFX9-NEXT: v_add_u32_e32 v3, v3, v6 ; GFX9-NEXT: v_add_u32_e32 v3, v3, v6
; GFX9-NEXT: s_andn2_b64 exec, exec, s[12:13] ; GFX9-NEXT: s_andn2_b64 exec, exec, s[10:11]
; GFX9-NEXT: s_cbranch_execnz BB1_2 ; GFX9-NEXT: s_cbranch_execnz BB1_2
; GFX9-NEXT: BB1_3: ; %Flow3 ; GFX9-NEXT: BB1_3: ; %Flow3
; GFX9-NEXT: s_or_b64 exec, exec, s[10:11] ; GFX9-NEXT: s_or_b64 exec, exec, s[8:9]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
bb: bb:
%tmp = icmp ult i32 %arg, %arg1 %tmp = icmp ult i32 %arg, %arg1
br i1 %tmp, label %bb19, label %.loopexit br i1 %tmp, label %bb19, label %.loopexit
bb19: ; preds = %bb bb19: ; preds = %bb
%tmp20 = uitofp i32 %arg6 to float %tmp20 = uitofp i32 %arg6 to float
▲ Show 20 Lines • Show All 148 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll

Show First 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:2048 ; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:2048
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-4096 ; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-4096
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048 ; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}} ; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:2048 ; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:2048
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-4096 ; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-4096
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off ; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off
; ;
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}} ; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}} ; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048 ; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}} ; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048 ; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}} ; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048 ; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off ; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048 ; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off ; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
entry: entry:
%call = tail call i64 @_Z13get_global_idj(i32 0) %call = tail call i64 @_Z13get_global_idj(i32 0)
%conv = and i64 %call, 255 %conv = and i64 %call, 255
%a0 = shl i64 %call, 17 %a0 = shl i64 %call, 17
%idx.ext11 = and i64 %a0, 4261412864 %idx.ext11 = and i64 %a0, 4261412864
%add.ptr12 = getelementptr inbounds i8, i8 addrspace(1)* %buffer, i64 %idx.ext11 %add.ptr12 = getelementptr inbounds i8, i8 addrspace(1)* %buffer, i64 %idx.ext11
%a1 = bitcast i8 addrspace(1)* %add.ptr12 to i64 addrspace(1)* %a1 = bitcast i8 addrspace(1)* %add.ptr12 to i64 addrspace(1)*
%add.ptr6 = getelementptr inbounds i64, i64 addrspace(1)* %a1, i64 %conv %add.ptr6 = getelementptr inbounds i64, i64 addrspace(1)* %a1, i64 %conv
▲ Show 20 Lines • Show All 429 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/saddo.ll

Show First 20 Lines • Show All 160 Lines • ▼ Show 20 Lines
; SI-LABEL: v_saddo_i32: ; SI-LABEL: v_saddo_i32:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s11, 0xf000 ; SI-NEXT: s_mov_b32 s11, 0xf000
; SI-NEXT: s_mov_b32 s10, -1 ; SI-NEXT: s_mov_b32 s10, -1
; SI-NEXT: s_mov_b32 s14, s10 ; SI-NEXT: s_mov_b32 s14, s10
; SI-NEXT: s_mov_b32 s15, s11 ; SI-NEXT: s_mov_b32 s15, s11
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s8, s0 ; SI-NEXT: s_mov_b32 s12, s4
; SI-NEXT: s_mov_b32 s9, s1 ; SI-NEXT: s_mov_b32 s13, s5
; SI-NEXT: s_mov_b32 s12, s2
; SI-NEXT: s_mov_b32 s13, s3
; SI-NEXT: s_mov_b32 s0, s4
; SI-NEXT: s_mov_b32 s1, s5
; SI-NEXT: s_mov_b32 s2, s10
; SI-NEXT: s_mov_b32 s3, s11
; SI-NEXT: s_mov_b32 s4, s6 ; SI-NEXT: s_mov_b32 s4, s6
; SI-NEXT: s_mov_b32 s5, s7 ; SI-NEXT: s_mov_b32 s5, s7
; SI-NEXT: s_mov_b32 s6, s10 ; SI-NEXT: s_mov_b32 s6, s10
; SI-NEXT: s_mov_b32 s7, s11 ; SI-NEXT: s_mov_b32 s7, s11
; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 ; SI-NEXT: buffer_load_dword v0, off, s[12:15], 0
; SI-NEXT: buffer_load_dword v1, off, s[4:7], 0 ; SI-NEXT: buffer_load_dword v1, off, s[4:7], 0
; SI-NEXT: s_mov_b32 s8, s0
; SI-NEXT: s_mov_b32 s9, s1
; SI-NEXT: s_mov_b32 s4, s2
; SI-NEXT: s_mov_b32 s5, s3
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v2, vcc, v1, v0 ; SI-NEXT: v_add_i32_e32 v2, vcc, v1, v0
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1 ; SI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1
; SI-NEXT: v_cmp_lt_i32_e64 s[0:1], v2, v0 ; SI-NEXT: v_cmp_lt_i32_e64 s[0:1], v2, v0
; SI-NEXT: s_xor_b64 s[0:1], vcc, s[0:1] ; SI-NEXT: s_xor_b64 s[0:1], vcc, s[0:1]
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] ; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; SI-NEXT: buffer_store_dword v2, off, s[8:11], 0 ; SI-NEXT: buffer_store_dword v2, off, s[8:11], 0
; SI-NEXT: buffer_store_byte v0, off, s[12:15], 0 ; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: v_saddo_i32: ; VI-LABEL: v_saddo_i32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v4, s4 ; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v5, s5 ; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_mov_b32_e32 v6, s6 ; VI-NEXT: v_mov_b32_e32 v2, s6
; VI-NEXT: v_mov_b32_e32 v7, s7 ; VI-NEXT: v_mov_b32_e32 v3, s7
; VI-NEXT: flat_load_dword v4, v[4:5] ; VI-NEXT: flat_load_dword v4, v[0:1]
; VI-NEXT: flat_load_dword v5, v[6:7] ; VI-NEXT: flat_load_dword v5, v[2:3]
; VI-NEXT: v_mov_b32_e32 v0, s0 ; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v2, s2 ; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3 ; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_add_u32_e32 v6, vcc, v5, v4 ; VI-NEXT: v_add_u32_e32 v6, vcc, v5, v4
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v5 ; VI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v5
; VI-NEXT: v_cmp_lt_i32_e64 s[0:1], v6, v4 ; VI-NEXT: v_cmp_lt_i32_e64 s[0:1], v6, v4
; VI-NEXT: s_xor_b64 s[0:1], vcc, s[0:1] ; VI-NEXT: s_xor_b64 s[0:1], vcc, s[0:1]
; VI-NEXT: flat_store_dword v[0:1], v6 ; VI-NEXT: flat_store_dword v[0:1], v6
; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] ; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; VI-NEXT: flat_store_byte v[2:3], v0 ; VI-NEXT: flat_store_byte v[2:3], v0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_saddo_i32: ; GFX9-LABEL: v_saddo_i32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v4, s4 ; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v5, s5 ; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: v_mov_b32_e32 v6, s6 ; GFX9-NEXT: v_mov_b32_e32 v2, s6
; GFX9-NEXT: v_mov_b32_e32 v7, s7 ; GFX9-NEXT: v_mov_b32_e32 v3, s7
; GFX9-NEXT: global_load_dword v4, v[4:5], off ; GFX9-NEXT: global_load_dword v4, v[0:1], off
; GFX9-NEXT: global_load_dword v5, v[6:7], off ; GFX9-NEXT: global_load_dword v5, v[2:3], off
; GFX9-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_mov_b32_e32 v2, s2 ; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: v_mov_b32_e32 v3, s3 ; GFX9-NEXT: v_mov_b32_e32 v3, s3
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v6, v4, v5 ; GFX9-NEXT: v_add_u32_e32 v6, v4, v5
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 0, v5 ; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 0, v5
; GFX9-NEXT: v_cmp_lt_i32_e64 s[0:1], v6, v4 ; GFX9-NEXT: v_cmp_lt_i32_e64 s[0:1], v6, v4
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
; SI-LABEL: v_saddo_i64: ; SI-LABEL: v_saddo_i64:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s11, 0xf000 ; SI-NEXT: s_mov_b32 s11, 0xf000
; SI-NEXT: s_mov_b32 s10, -1 ; SI-NEXT: s_mov_b32 s10, -1
; SI-NEXT: s_mov_b32 s14, s10 ; SI-NEXT: s_mov_b32 s14, s10
; SI-NEXT: s_mov_b32 s15, s11 ; SI-NEXT: s_mov_b32 s15, s11
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s8, s0 ; SI-NEXT: s_mov_b32 s12, s4
; SI-NEXT: s_mov_b32 s9, s1 ; SI-NEXT: s_mov_b32 s13, s5
; SI-NEXT: s_mov_b32 s12, s2
; SI-NEXT: s_mov_b32 s13, s3
; SI-NEXT: s_mov_b32 s0, s4
; SI-NEXT: s_mov_b32 s1, s5
; SI-NEXT: s_mov_b32 s2, s10
; SI-NEXT: s_mov_b32 s3, s11
; SI-NEXT: s_mov_b32 s4, s6 ; SI-NEXT: s_mov_b32 s4, s6
; SI-NEXT: s_mov_b32 s5, s7 ; SI-NEXT: s_mov_b32 s5, s7
; SI-NEXT: s_mov_b32 s6, s10 ; SI-NEXT: s_mov_b32 s6, s10
; SI-NEXT: s_mov_b32 s7, s11 ; SI-NEXT: s_mov_b32 s7, s11
; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[0:3], 0 ; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[12:15], 0
; SI-NEXT: buffer_load_dwordx2 v[2:3], off, s[4:7], 0 ; SI-NEXT: buffer_load_dwordx2 v[2:3], off, s[4:7], 0
; SI-NEXT: s_mov_b32 s8, s0
; SI-NEXT: s_mov_b32 s9, s1
; SI-NEXT: s_mov_b32 s4, s2
; SI-NEXT: s_mov_b32 s5, s3
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v4, vcc, v0, v2 ; SI-NEXT: v_add_i32_e32 v4, vcc, v0, v2
; SI-NEXT: v_addc_u32_e32 v5, vcc, v1, v3, vcc ; SI-NEXT: v_addc_u32_e32 v5, vcc, v1, v3, vcc
; SI-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[2:3] ; SI-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[2:3]
; SI-NEXT: v_cmp_lt_i64_e64 s[0:1], v[4:5], v[0:1] ; SI-NEXT: v_cmp_lt_i64_e64 s[0:1], v[4:5], v[0:1]
; SI-NEXT: buffer_store_dwordx2 v[4:5], off, s[8:11], 0 ; SI-NEXT: buffer_store_dwordx2 v[4:5], off, s[8:11], 0
; SI-NEXT: s_xor_b64 s[0:1], vcc, s[0:1] ; SI-NEXT: s_xor_b64 s[0:1], vcc, s[0:1]
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] ; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; SI-NEXT: buffer_store_byte v0, off, s[12:15], 0 ; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: v_saddo_i64: ; VI-LABEL: v_saddo_i64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v4, s4 ; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v5, s5 ; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_mov_b32_e32 v6, s6 ; VI-NEXT: v_mov_b32_e32 v2, s6
; VI-NEXT: v_mov_b32_e32 v7, s7 ; VI-NEXT: v_mov_b32_e32 v3, s7
; VI-NEXT: flat_load_dwordx2 v[4:5], v[4:5] ; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; VI-NEXT: flat_load_dwordx2 v[6:7], v[6:7] ; VI-NEXT: flat_load_dwordx2 v[2:3], v[2:3]
; VI-NEXT: v_mov_b32_e32 v0, s0 ; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: v_mov_b32_e32 v1, s1 ; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v2, s2 ; VI-NEXT: v_mov_b32_e32 v6, s2
; VI-NEXT: v_mov_b32_e32 v3, s3 ; VI-NEXT: v_mov_b32_e32 v7, s3
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_add_u32_e32 v8, vcc, v4, v6 ; VI-NEXT: v_add_u32_e32 v8, vcc, v0, v2
; VI-NEXT: v_addc_u32_e32 v9, vcc, v5, v7, vcc ; VI-NEXT: v_addc_u32_e32 v9, vcc, v1, v3, vcc
; VI-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[6:7] ; VI-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[2:3]
; VI-NEXT: v_cmp_lt_i64_e64 s[0:1], v[8:9], v[4:5] ; VI-NEXT: v_cmp_lt_i64_e64 s[0:1], v[8:9], v[0:1]
; VI-NEXT: flat_store_dwordx2 v[0:1], v[8:9] ; VI-NEXT: flat_store_dwordx2 v[4:5], v[8:9]
; VI-NEXT: s_xor_b64 s[0:1], vcc, s[0:1] ; VI-NEXT: s_xor_b64 s[0:1], vcc, s[0:1]
; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] ; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; VI-NEXT: flat_store_byte v[2:3], v0 ; VI-NEXT: flat_store_byte v[6:7], v0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_saddo_i64: ; GFX9-LABEL: v_saddo_i64:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v4, s4 ; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v5, s5 ; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: v_mov_b32_e32 v6, s6 ; GFX9-NEXT: v_mov_b32_e32 v2, s6
; GFX9-NEXT: v_mov_b32_e32 v7, s7 ; GFX9-NEXT: v_mov_b32_e32 v3, s7
; GFX9-NEXT: global_load_dwordx2 v[4:5], v[4:5], off ; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX9-NEXT: global_load_dwordx2 v[6:7], v[6:7], off ; GFX9-NEXT: global_load_dwordx2 v[2:3], v[2:3], off
; GFX9-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NEXT: v_mov_b32_e32 v4, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: v_mov_b32_e32 v5, s1
; GFX9-NEXT: v_mov_b32_e32 v2, s2 ; GFX9-NEXT: v_mov_b32_e32 v6, s2
; GFX9-NEXT: v_mov_b32_e32 v3, s3 ; GFX9-NEXT: v_mov_b32_e32 v7, s3
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v4, v6 ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v5, v7, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v1, v3, vcc
; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[6:7] ; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[2:3]
; GFX9-NEXT: v_cmp_lt_i64_e64 s[0:1], v[8:9], v[4:5] ; GFX9-NEXT: v_cmp_lt_i64_e64 s[0:1], v[8:9], v[0:1]
; GFX9-NEXT: global_store_dwordx2 v[0:1], v[8:9], off ; GFX9-NEXT: global_store_dwordx2 v[4:5], v[8:9], off
; GFX9-NEXT: s_xor_b64 s[0:1], vcc, s[0:1] ; GFX9-NEXT: s_xor_b64 s[0:1], vcc, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; GFX9-NEXT: global_store_byte v[2:3], v0, off ; GFX9-NEXT: global_store_byte v[6:7], v0, off
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%a = load i64, i64 addrspace(1)* %aptr, align 4 %a = load i64, i64 addrspace(1)* %aptr, align 4
%b = load i64, i64 addrspace(1)* %bptr, align 4 %b = load i64, i64 addrspace(1)* %bptr, align 4
%sadd = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %a, i64 %b) nounwind %sadd = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %a, i64 %b) nounwind
%val = extractvalue { i64, i1 } %sadd, 0 %val = extractvalue { i64, i1 } %sadd, 0
%carry = extractvalue { i64, i1 } %sadd, 1 %carry = extractvalue { i64, i1 } %sadd, 1
store i64 %val, i64 addrspace(1)* %out, align 8 store i64 %val, i64 addrspace(1)* %out, align 8
store i1 %carry, i1 addrspace(1)* %carryout store i1 %carry, i1 addrspace(1)* %carryout
ret void ret void
} }
define amdgpu_kernel void @v_saddo_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %carryout, <2 x i32> addrspace(1)* %aptr, <2 x i32> addrspace(1)* %bptr) nounwind { define amdgpu_kernel void @v_saddo_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %carryout, <2 x i32> addrspace(1)* %aptr, <2 x i32> addrspace(1)* %bptr) nounwind {
; SI-LABEL: v_saddo_v2i32: ; SI-LABEL: v_saddo_v2i32:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s11, 0xf000 ; SI-NEXT: s_mov_b32 s11, 0xf000
; SI-NEXT: s_mov_b32 s10, -1 ; SI-NEXT: s_mov_b32 s10, -1
; SI-NEXT: s_mov_b32 s14, s10 ; SI-NEXT: s_mov_b32 s14, s10
; SI-NEXT: s_mov_b32 s15, s11 ; SI-NEXT: s_mov_b32 s15, s11
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s8, s0 ; SI-NEXT: s_mov_b32 s12, s4
; SI-NEXT: s_mov_b32 s9, s1 ; SI-NEXT: s_mov_b32 s13, s5
; SI-NEXT: s_mov_b32 s12, s2
; SI-NEXT: s_mov_b32 s13, s3
; SI-NEXT: s_mov_b32 s0, s4
; SI-NEXT: s_mov_b32 s1, s5
; SI-NEXT: s_mov_b32 s2, s10
; SI-NEXT: s_mov_b32 s3, s11
; SI-NEXT: s_mov_b32 s4, s6 ; SI-NEXT: s_mov_b32 s4, s6
; SI-NEXT: s_mov_b32 s5, s7 ; SI-NEXT: s_mov_b32 s5, s7
; SI-NEXT: s_mov_b32 s6, s10 ; SI-NEXT: s_mov_b32 s6, s10
; SI-NEXT: s_mov_b32 s7, s11 ; SI-NEXT: s_mov_b32 s7, s11
; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[0:3], 0 ; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[12:15], 0
; SI-NEXT: buffer_load_dwordx2 v[2:3], off, s[4:7], 0 ; SI-NEXT: buffer_load_dwordx2 v[2:3], off, s[4:7], 0
; SI-NEXT: s_mov_b32 s8, s0
; SI-NEXT: s_mov_b32 s9, s1
; SI-NEXT: s_mov_b32 s12, s2
; SI-NEXT: s_mov_b32 s13, s3
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v5, vcc, v1, v3 ; SI-NEXT: v_add_i32_e32 v5, vcc, v1, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, v0, v2 ; SI-NEXT: v_add_i32_e32 v4, vcc, v0, v2
; SI-NEXT: v_cmp_gt_i32_e64 s[0:1], 0, v3 ; SI-NEXT: v_cmp_gt_i32_e64 s[0:1], 0, v3
; SI-NEXT: v_cmp_lt_i32_e64 s[4:5], v5, v1 ; SI-NEXT: v_cmp_lt_i32_e64 s[4:5], v5, v1
; SI-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5] ; SI-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v2 ; SI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v2
; SI-NEXT: v_cmp_lt_i32_e64 s[2:3], v4, v0 ; SI-NEXT: v_cmp_lt_i32_e64 s[2:3], v4, v0
; SI-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] ; SI-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; SI-NEXT: s_xor_b64 s[0:1], vcc, s[2:3] ; SI-NEXT: s_xor_b64 s[0:1], vcc, s[2:3]
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] ; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; SI-NEXT: buffer_store_dwordx2 v[4:5], off, s[8:11], 0 ; SI-NEXT: buffer_store_dwordx2 v[4:5], off, s[8:11], 0
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[12:15], 0 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[12:15], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: v_saddo_v2i32: ; VI-LABEL: v_saddo_v2i32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v4, s4 ; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v5, s5 ; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_mov_b32_e32 v6, s6 ; VI-NEXT: v_mov_b32_e32 v2, s6
; VI-NEXT: v_mov_b32_e32 v7, s7 ; VI-NEXT: v_mov_b32_e32 v3, s7
; VI-NEXT: flat_load_dwordx2 v[4:5], v[4:5] ; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; VI-NEXT: flat_load_dwordx2 v[6:7], v[6:7] ; VI-NEXT: flat_load_dwordx2 v[2:3], v[2:3]
; VI-NEXT: v_mov_b32_e32 v0, s0 ; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: v_mov_b32_e32 v1, s1 ; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v2, s2 ; VI-NEXT: v_mov_b32_e32 v6, s2
; VI-NEXT: v_mov_b32_e32 v3, s3 ; VI-NEXT: v_mov_b32_e32 v7, s3
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_add_u32_e32 v9, vcc, v5, v7 ; VI-NEXT: v_add_u32_e32 v9, vcc, v1, v3
; VI-NEXT: v_add_u32_e32 v8, vcc, v4, v6 ; VI-NEXT: v_add_u32_e32 v8, vcc, v0, v2
; VI-NEXT: v_cmp_gt_i32_e64 s[0:1], 0, v7 ; VI-NEXT: v_cmp_gt_i32_e64 s[0:1], 0, v3
; VI-NEXT: v_cmp_lt_i32_e64 s[4:5], v9, v5 ; VI-NEXT: v_cmp_lt_i32_e64 s[4:5], v9, v1
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v6
; VI-NEXT: v_cmp_lt_i32_e64 s[2:3], v8, v4
; VI-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5] ; VI-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]
; VI-NEXT: flat_store_dwordx2 v[0:1], v[8:9] ; VI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v2
; VI-NEXT: v_cmp_lt_i32_e64 s[2:3], v8, v0
; VI-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] ; VI-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; VI-NEXT: s_xor_b64 s[0:1], vcc, s[2:3] ; VI-NEXT: s_xor_b64 s[0:1], vcc, s[2:3]
; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] ; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; VI-NEXT: flat_store_dwordx2 v[4:5], v[8:9]
; VI-NEXT: flat_store_dwordx2 v[6:7], v[0:1]
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_saddo_v2i32: ; GFX9-LABEL: v_saddo_v2i32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v4, s4 ; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v5, s5 ; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: v_mov_b32_e32 v6, s6 ; GFX9-NEXT: v_mov_b32_e32 v2, s6
; GFX9-NEXT: v_mov_b32_e32 v7, s7 ; GFX9-NEXT: v_mov_b32_e32 v3, s7
; GFX9-NEXT: global_load_dwordx2 v[4:5], v[4:5], off ; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX9-NEXT: global_load_dwordx2 v[6:7], v[6:7], off ; GFX9-NEXT: global_load_dwordx2 v[2:3], v[2:3], off
; GFX9-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NEXT: v_mov_b32_e32 v4, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: v_mov_b32_e32 v5, s1
; GFX9-NEXT: v_mov_b32_e32 v2, s2 ; GFX9-NEXT: v_mov_b32_e32 v6, s2
; GFX9-NEXT: v_mov_b32_e32 v3, s3 ; GFX9-NEXT: v_mov_b32_e32 v7, s3
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v9, v5, v7 ; GFX9-NEXT: v_add_u32_e32 v9, v1, v3
; GFX9-NEXT: v_add_u32_e32 v8, v4, v6 ; GFX9-NEXT: v_add_u32_e32 v8, v0, v2
; GFX9-NEXT: v_cmp_gt_i32_e64 s[0:1], 0, v7 ; GFX9-NEXT: v_cmp_gt_i32_e64 s[0:1], 0, v3
; GFX9-NEXT: v_cmp_lt_i32_e64 s[4:5], v9, v5 ; GFX9-NEXT: v_cmp_lt_i32_e64 s[4:5], v9, v1
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 0, v6
; GFX9-NEXT: v_cmp_lt_i32_e64 s[2:3], v8, v4
; GFX9-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5] ; GFX9-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]
; GFX9-NEXT: global_store_dwordx2 v[0:1], v[8:9], off ; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 0, v2
; GFX9-NEXT: v_cmp_lt_i32_e64 s[2:3], v8, v0
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX9-NEXT: s_xor_b64 s[0:1], vcc, s[2:3] ; GFX9-NEXT: s_xor_b64 s[0:1], vcc, s[2:3]
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; GFX9-NEXT: global_store_dwordx2 v[2:3], v[0:1], off ; GFX9-NEXT: global_store_dwordx2 v[4:5], v[8:9], off
; GFX9-NEXT: global_store_dwordx2 v[6:7], v[0:1], off
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%a = load <2 x i32>, <2 x i32> addrspace(1)* %aptr, align 4 %a = load <2 x i32>, <2 x i32> addrspace(1)* %aptr, align 4
%b = load <2 x i32>, <2 x i32> addrspace(1)* %bptr, align 4 %b = load <2 x i32>, <2 x i32> addrspace(1)* %bptr, align 4
%sadd = call { <2 x i32>, <2 x i1> } @llvm.sadd.with.overflow.v2i32(<2 x i32> %a, <2 x i32> %b) nounwind %sadd = call { <2 x i32>, <2 x i1> } @llvm.sadd.with.overflow.v2i32(<2 x i32> %a, <2 x i32> %b) nounwind
%val = extractvalue { <2 x i32>, <2 x i1> } %sadd, 0 %val = extractvalue { <2 x i32>, <2 x i1> } %sadd, 0
%carry = extractvalue { <2 x i32>, <2 x i1> } %sadd, 1 %carry = extractvalue { <2 x i32>, <2 x i1> } %sadd, 1
store <2 x i32> %val, <2 x i32> addrspace(1)* %out, align 4 store <2 x i32> %val, <2 x i32> addrspace(1)* %out, align 4
%carry.ext = zext <2 x i1> %carry to <2 x i32> %carry.ext = zext <2 x i1> %carry to <2 x i32>
store <2 x i32> %carry.ext, <2 x i32> addrspace(1)* %carryout store <2 x i32> %carry.ext, <2 x i32> addrspace(1)* %carryout
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/salu-to-valu.ll

Show First 20 Lines • Show All 167 Lines • ▼ Show 20 Lines
; Original scalar load uses SGPR offset on SI and 32-bit literal on ; Original scalar load uses SGPR offset on SI and 32-bit literal on
; CI. ; CI.
; GCN-LABEL: {{^}}smrd_valu_ci_offset_x8: ; GCN-LABEL: {{^}}smrd_valu_ci_offset_x8:
; GCN-NOHSA-DAG: s_mov_b32 [[OFFSET0:s[0-9]+]], 0x9a40{{$}} ; GCN-NOHSA-DAG: s_mov_b32 [[OFFSET0:s[0-9]+]], 0x9a40{{$}}
; CI-NOHSA-DAG: s_mov_b32 [[OFFSET1:s[0-9]+]], 0x9a50{{$}} ; CI-NOHSA-DAG: s_mov_b32 [[OFFSET1:s[0-9]+]], 0x9a50{{$}}
; CI-NOHSA-NOT: v_add ; CI-NOHSA-NOT: v_add
; SI: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:16
; CI-NOHSA: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET1]] addr64{{$}} ; CI-NOHSA: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET1]] addr64{{$}}
; GCN-NOHSA: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET0]] addr64{{$}} ; GCN-NOHSA: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET0]] addr64{{$}}
; SI: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:16
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
Show All 13 Linesentry:
ret void ret void
} }
; GCN-LABEL: {{^}}smrd_valu_ci_offset_x16: ; GCN-LABEL: {{^}}smrd_valu_ci_offset_x16:
; SI: s_mov_b32 {{s[0-9]+}}, 0x13480 ; SI: s_mov_b32 {{s[0-9]+}}, 0x13480
; SI: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:16 ; SI: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:16
; SI: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:32 ; SI: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:32
; SI: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:48
; SI: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], {{s[0-9]+}} addr64 ; SI: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], {{s[0-9]+}} addr64
; SI: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:48
; CI-NOHSA-DAG: s_mov_b32 [[OFFSET0:s[0-9]+]], 0x13480{{$}} ; CI-NOHSA-DAG: s_mov_b32 [[OFFSET0:s[0-9]+]], 0x13480{{$}}
; CI-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET0]] addr64{{$}} ; CI-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET0]] addr64{{$}}
; CI-NOHSA-DAG: s_mov_b32 [[OFFSET1:s[0-9]+]], 0x13490{{$}} ; CI-NOHSA-DAG: s_mov_b32 [[OFFSET1:s[0-9]+]], 0x13490{{$}}
; CI-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET1]] addr64{{$}} ; CI-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET1]] addr64{{$}}
; CI-NOHSA-DAG: s_mov_b32 [[OFFSET2:s[0-9]+]], 0x134a0{{$}} ; CI-NOHSA-DAG: s_mov_b32 [[OFFSET2:s[0-9]+]], 0x134a0{{$}}
; CI-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET2]] addr64{{$}} ; CI-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET2]] addr64{{$}}
; CI-NOHSA-DAG: s_mov_b32 [[OFFSET3:s[0-9]+]], 0x134b0{{$}} ; CI-NOHSA-DAG: s_mov_b32 [[OFFSET3:s[0-9]+]], 0x134b0{{$}}
; CI-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET3]] addr64{{$}} ; CI-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET3]] addr64{{$}}
▲ Show 20 Lines • Show All 296 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir

Show All 30 Linesbody: |
; CHECK: dead %6:vgpr_32 = DS_READ_B32_gfx9 undef %7:vgpr_32, 0, 0, implicit $exec ; CHECK: dead %6:vgpr_32 = DS_READ_B32_gfx9 undef %7:vgpr_32, 0, 0, implicit $exec
; CHECK: dead %8:vreg_64 = DS_READ_B64_gfx9 [[V_MOV_B32_e32_]], 0, 0, implicit $exec ; CHECK: dead %8:vreg_64 = DS_READ_B64_gfx9 [[V_MOV_B32_e32_]], 0, 0, implicit $exec
; CHECK: dead %9:vreg_128 = DS_READ_B128_gfx9 [[V_ADD_U32_e32_]], 0, 0, implicit $exec ; CHECK: dead %9:vreg_128 = DS_READ_B128_gfx9 [[V_ADD_U32_e32_]], 0, 0, implicit $exec
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; CHECK: undef %11.sub1:vreg_512 = COPY [[COPY]].sub1 ; CHECK: undef %11.sub1:vreg_512 = COPY [[COPY]].sub1
; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VGPR_LO16 */, def dead [[COPY1]], 851978 /* regdef:VGPR_LO16 */, def dead [[COPY]].sub1, 2147483657 /* reguse tiedto:$0 */, [[COPY1]], 2147549193 /* reguse tiedto:$1 */, [[COPY]].sub1 ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VGPR_LO16 */, def dead [[COPY1]], 851978 /* regdef:VGPR_LO16 */, def dead [[COPY]].sub1, 2147483657 /* reguse tiedto:$0 */, [[COPY1]], 2147549193 /* reguse tiedto:$1 */, [[COPY]].sub1
; CHECK: %11.sub0:vreg_512 = COPY [[COPY]].sub0 ; CHECK: %11.sub0:vreg_512 = COPY [[COPY]].sub0
; CHECK: %11.sub3:vreg_512 = COPY [[COPY]].sub3 ; CHECK: %11.sub3:vreg_512 = COPY [[COPY]].sub3
; CHECK: dead %10:vgpr_32 = V_ADD_CO_U32_e32 4, [[V_MOV_B32_e32_1]], implicit-def dead $vcc, implicit $exec
; CHECK: %11.sub2:vreg_512 = COPY undef [[V_MOV_B32_e32_]] ; CHECK: %11.sub2:vreg_512 = COPY undef [[V_MOV_B32_e32_]]
; CHECK: %11.sub5:vreg_512 = COPY undef [[V_MOV_B32_e32_]] ; CHECK: %11.sub5:vreg_512 = COPY undef [[V_MOV_B32_e32_]]
; CHECK: [[COPY2:%[0-9]+]]:vreg_512 = COPY %11 ; CHECK: [[COPY2:%[0-9]+]]:vreg_512 = COPY %11
; CHECK: dead %10:vgpr_32 = V_ADD_CO_U32_e32 4, [[V_MOV_B32_e32_1]], implicit-def dead $vcc, implicit $exec
; CHECK: S_BRANCH %bb.1 ; CHECK: S_BRANCH %bb.1
bb.0: bb.0:
liveins: $sgpr6_sgpr7 liveins: $sgpr6_sgpr7
undef %0.sub3:vreg_512 = V_MOV_B32_e32 0, implicit $exec undef %0.sub3:vreg_512 = V_MOV_B32_e32 0, implicit $exec
%1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
%2:vgpr_32 = V_ADD_U32_e32 0, %1, implicit $exec %2:vgpr_32 = V_ADD_U32_e32 0, %1, implicit $exec
%3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec %3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
Show All 19 Lines

llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir

Show All 19 Linesbody: |
; CHECK-LABEL: name: only_dbg_value_sched_region ; CHECK-LABEL: name: only_dbg_value_sched_region
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $vgpr0 ; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; CHECK: [[GLOBAL_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2 [[DEF]], 0, 0, 0, 0, implicit $exec ; CHECK: [[GLOBAL_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2 [[DEF]], 0, 0, 0, 0, implicit $exec
; CHECK: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF]], 8, 0, 0, 0, implicit $exec ; CHECK: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF]], 8, 0, 0, 0, implicit $exec
; CHECK: [[COPY1:%[0-9]+]]:vreg_64 = COPY [[GLOBAL_LOAD_DWORDX2_]]
; CHECK: undef %6.sub0:vreg_64 = V_ADD_F32_e32 [[DEF]].sub0, [[COPY1]].sub0, implicit $mode, implicit $exec
; CHECK: dead undef %6.sub1:vreg_64 = V_ADD_F32_e32 [[DEF]].sub1, [[COPY1]].sub0, implicit $mode, implicit $exec
; CHECK: [[GLOBAL_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[COPY1]], 0, 0, 0, 0, implicit $exec
; CHECK: undef %4.sub0:vreg_64 = V_MOV_B32_e32 111, implicit $exec ; CHECK: undef %4.sub0:vreg_64 = V_MOV_B32_e32 111, implicit $exec
; CHECK: [[DEF1:%[0-9]+]]:vreg_64 = IMPLICIT_DEF ; CHECK: [[DEF1:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; CHECK: [[DEF2:%[0-9]+]]:vreg_64 = IMPLICIT_DEF ; CHECK: [[DEF2:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; CHECK: [[DEF3:%[0-9]+]]:vreg_64 = IMPLICIT_DEF ; CHECK: [[DEF3:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; CHECK: undef %11.sub1:vreg_64 = IMPLICIT_DEF ; CHECK: undef %11.sub1:vreg_64 = IMPLICIT_DEF
; CHECK: [[DEF4:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; CHECK: [[DEF4:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; CHECK: [[DEF5:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; CHECK: [[DEF5:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; CHECK: [[COPY1:%[0-9]+]]:vreg_64 = COPY [[GLOBAL_LOAD_DWORDX2_]]
; CHECK: undef %6.sub0:vreg_64 = V_ADD_F32_e32 [[DEF]].sub0, [[COPY1]].sub0, implicit $mode, implicit $exec
; CHECK: dead undef %6.sub1:vreg_64 = V_ADD_F32_e32 [[DEF]].sub1, [[COPY1]].sub0, implicit $mode, implicit $exec
; CHECK: [[DEF6:%[0-9]+]]:vreg_64 = IMPLICIT_DEF ; CHECK: [[DEF6:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; CHECK: [[GLOBAL_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[COPY1]], 0, 0, 0, 0, implicit $exec
; CHECK: undef %19.sub0:vreg_64 = V_ADD_F32_e32 [[GLOBAL_LOAD_DWORD1]], [[GLOBAL_LOAD_DWORDX2_]].sub0, implicit $mode, implicit $exec ; CHECK: undef %19.sub0:vreg_64 = V_ADD_F32_e32 [[GLOBAL_LOAD_DWORD1]], [[GLOBAL_LOAD_DWORDX2_]].sub0, implicit $mode, implicit $exec
; CHECK: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF ; CHECK: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; CHECK: %19.sub1:vreg_64 = V_ADD_F32_e32 [[GLOBAL_LOAD_DWORD]], [[GLOBAL_LOAD_DWORD]], implicit $mode, implicit $exec ; CHECK: %19.sub1:vreg_64 = V_ADD_F32_e32 [[GLOBAL_LOAD_DWORD]], [[GLOBAL_LOAD_DWORD]], implicit $mode, implicit $exec
; CHECK: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; CHECK: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; CHECK: %4.sub1:vreg_64 = V_ADD_U32_e32 [[COPY]], [[COPY]], implicit $exec ; CHECK: %4.sub1:vreg_64 = V_ADD_U32_e32 [[COPY]], [[COPY]], implicit $exec
; CHECK: GLOBAL_STORE_DWORDX2 %19, %4, 32, 0, 0, 0, implicit $exec ; CHECK: GLOBAL_STORE_DWORDX2 %19, %4, 32, 0, 0, 0, implicit $exec
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; CHECK: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec ; CHECK: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
▲ Show 20 Lines • Show All 68 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/sdiv.ll

Show First 20 Lines • Show All 197 Lines • ▼ Show 20 Lines
} }
define amdgpu_kernel void @sdiv_i32_4(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { define amdgpu_kernel void @sdiv_i32_4(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
; GCN-LABEL: sdiv_i32_4: ; GCN-LABEL: sdiv_i32_4:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_mov_b32 s10, s2
; GCN-NEXT: s_mov_b32 s11, s3
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s8, s6
; GCN-NEXT: s_mov_b32 s9, s7
; GCN-NEXT: buffer_load_dword v0, off, s[8:11], 0
; GCN-NEXT: s_mov_b32 s0, s4 ; GCN-NEXT: s_mov_b32 s0, s4
; GCN-NEXT: s_mov_b32 s1, s5 ; GCN-NEXT: s_mov_b32 s1, s5
; GCN-NEXT: s_mov_b32 s4, s6
; GCN-NEXT: s_mov_b32 s5, s7
; GCN-NEXT: s_mov_b32 s6, s2
; GCN-NEXT: s_mov_b32 s7, s3
; GCN-NEXT: buffer_load_dword v0, off, s[4:7], 0
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-NEXT: v_lshrrev_b32_e32 v1, 30, v1 ; GCN-NEXT: v_lshrrev_b32_e32 v1, 30, v1
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GCN-NEXT: v_ashrrev_i32_e32 v0, 2, v0 ; GCN-NEXT: v_ashrrev_i32_e32 v0, 2, v0
; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; TONGA-LABEL: sdiv_i32_4: ; TONGA-LABEL: sdiv_i32_4:
; TONGA: ; %bb.0: ; TONGA: ; %bb.0:
; TONGA-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; TONGA-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; TONGA-NEXT: s_mov_b32 s3, 0xf000 ; TONGA-NEXT: s_mov_b32 s3, 0xf000
; TONGA-NEXT: s_mov_b32 s2, -1 ; TONGA-NEXT: s_mov_b32 s2, -1
; TONGA-NEXT: s_mov_b32 s10, s2
; TONGA-NEXT: s_mov_b32 s11, s3
; TONGA-NEXT: s_waitcnt lgkmcnt(0) ; TONGA-NEXT: s_waitcnt lgkmcnt(0)
; TONGA-NEXT: s_mov_b32 s8, s6
; TONGA-NEXT: s_mov_b32 s9, s7
; TONGA-NEXT: buffer_load_dword v0, off, s[8:11], 0
; TONGA-NEXT: s_mov_b32 s0, s4 ; TONGA-NEXT: s_mov_b32 s0, s4
; TONGA-NEXT: s_mov_b32 s1, s5 ; TONGA-NEXT: s_mov_b32 s1, s5
; TONGA-NEXT: s_mov_b32 s4, s6
; TONGA-NEXT: s_mov_b32 s5, s7
; TONGA-NEXT: s_mov_b32 s6, s2
; TONGA-NEXT: s_mov_b32 s7, s3
; TONGA-NEXT: buffer_load_dword v0, off, s[4:7], 0
; TONGA-NEXT: s_waitcnt vmcnt(0) ; TONGA-NEXT: s_waitcnt vmcnt(0)
; TONGA-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; TONGA-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; TONGA-NEXT: v_lshrrev_b32_e32 v1, 30, v1 ; TONGA-NEXT: v_lshrrev_b32_e32 v1, 30, v1
; TONGA-NEXT: v_add_u32_e32 v0, vcc, v0, v1 ; TONGA-NEXT: v_add_u32_e32 v0, vcc, v0, v1
; TONGA-NEXT: v_ashrrev_i32_e32 v0, 2, v0 ; TONGA-NEXT: v_ashrrev_i32_e32 v0, 2, v0
; TONGA-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; TONGA-NEXT: buffer_store_dword v0, off, s[0:3], 0
; TONGA-NEXT: s_endpgm ; TONGA-NEXT: s_endpgm
; ;
▲ Show 20 Lines • Show All 446 Lines • ▼ Show 20 Lines
} }
define amdgpu_kernel void @sdiv_v2i32_4(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { define amdgpu_kernel void @sdiv_v2i32_4(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
; GCN-LABEL: sdiv_v2i32_4: ; GCN-LABEL: sdiv_v2i32_4:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_mov_b32 s10, s2
; GCN-NEXT: s_mov_b32 s11, s3
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s8, s6
; GCN-NEXT: s_mov_b32 s9, s7
; GCN-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
; GCN-NEXT: s_mov_b32 s0, s4 ; GCN-NEXT: s_mov_b32 s0, s4
; GCN-NEXT: s_mov_b32 s1, s5 ; GCN-NEXT: s_mov_b32 s1, s5
; GCN-NEXT: s_mov_b32 s4, s6
; GCN-NEXT: s_mov_b32 s5, s7
; GCN-NEXT: s_mov_b32 s6, s2
; GCN-NEXT: s_mov_b32 s7, s3
; GCN-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_ashrrev_i32_e32 v2, 31, v0 ; GCN-NEXT: v_ashrrev_i32_e32 v2, 31, v0
; GCN-NEXT: v_ashrrev_i32_e32 v3, 31, v1 ; GCN-NEXT: v_ashrrev_i32_e32 v3, 31, v1
; GCN-NEXT: v_lshrrev_b32_e32 v2, 30, v2 ; GCN-NEXT: v_lshrrev_b32_e32 v2, 30, v2
; GCN-NEXT: v_lshrrev_b32_e32 v3, 30, v3 ; GCN-NEXT: v_lshrrev_b32_e32 v3, 30, v3
; GCN-NEXT: v_add_i32_e32 v0, vcc, v2, v0 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v2, v0
; GCN-NEXT: v_add_i32_e32 v1, vcc, v3, v1 ; GCN-NEXT: v_add_i32_e32 v1, vcc, v3, v1
; GCN-NEXT: v_ashrrev_i32_e32 v0, 2, v0 ; GCN-NEXT: v_ashrrev_i32_e32 v0, 2, v0
; GCN-NEXT: v_ashrrev_i32_e32 v1, 2, v1 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 2, v1
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; TONGA-LABEL: sdiv_v2i32_4: ; TONGA-LABEL: sdiv_v2i32_4:
; TONGA: ; %bb.0: ; TONGA: ; %bb.0:
; TONGA-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; TONGA-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; TONGA-NEXT: s_mov_b32 s3, 0xf000 ; TONGA-NEXT: s_mov_b32 s3, 0xf000
; TONGA-NEXT: s_mov_b32 s2, -1 ; TONGA-NEXT: s_mov_b32 s2, -1
; TONGA-NEXT: s_mov_b32 s10, s2
; TONGA-NEXT: s_mov_b32 s11, s3
; TONGA-NEXT: s_waitcnt lgkmcnt(0) ; TONGA-NEXT: s_waitcnt lgkmcnt(0)
; TONGA-NEXT: s_mov_b32 s8, s6
; TONGA-NEXT: s_mov_b32 s9, s7
; TONGA-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
; TONGA-NEXT: s_mov_b32 s0, s4 ; TONGA-NEXT: s_mov_b32 s0, s4
; TONGA-NEXT: s_mov_b32 s1, s5 ; TONGA-NEXT: s_mov_b32 s1, s5
; TONGA-NEXT: s_mov_b32 s4, s6
; TONGA-NEXT: s_mov_b32 s5, s7
; TONGA-NEXT: s_mov_b32 s6, s2
; TONGA-NEXT: s_mov_b32 s7, s3
; TONGA-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 0
; TONGA-NEXT: s_waitcnt vmcnt(0) ; TONGA-NEXT: s_waitcnt vmcnt(0)
; TONGA-NEXT: v_ashrrev_i32_e32 v2, 31, v0 ; TONGA-NEXT: v_ashrrev_i32_e32 v2, 31, v0
; TONGA-NEXT: v_ashrrev_i32_e32 v3, 31, v1 ; TONGA-NEXT: v_ashrrev_i32_e32 v3, 31, v1
; TONGA-NEXT: v_lshrrev_b32_e32 v2, 30, v2 ; TONGA-NEXT: v_lshrrev_b32_e32 v2, 30, v2
; TONGA-NEXT: v_lshrrev_b32_e32 v3, 30, v3 ; TONGA-NEXT: v_lshrrev_b32_e32 v3, 30, v3
; TONGA-NEXT: v_add_u32_e32 v0, vcc, v2, v0 ; TONGA-NEXT: v_add_u32_e32 v0, vcc, v2, v0
; TONGA-NEXT: v_add_u32_e32 v1, vcc, v3, v1 ; TONGA-NEXT: v_add_u32_e32 v1, vcc, v3, v1
; TONGA-NEXT: v_ashrrev_i32_e32 v0, 2, v0 ; TONGA-NEXT: v_ashrrev_i32_e32 v0, 2, v0
; TONGA-NEXT: v_ashrrev_i32_e32 v1, 2, v1 ; TONGA-NEXT: v_ashrrev_i32_e32 v1, 2, v1
; TONGA-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; TONGA-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; TONGA-NEXT: s_endpgm ; TONGA-NEXT: s_endpgm
; ;
; GFX9-LABEL: sdiv_v2i32_4: ; GFX9-LABEL: sdiv_v2i32_4:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_mov_b32 s10, s2
; GFX9-NEXT: s_mov_b32 s11, s3
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s8, s6
; GFX9-NEXT: s_mov_b32 s9, s7
; GFX9-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
; GFX9-NEXT: s_mov_b32 s0, s4 ; GFX9-NEXT: s_mov_b32 s0, s4
; GFX9-NEXT: s_mov_b32 s1, s5 ; GFX9-NEXT: s_mov_b32 s1, s5
; GFX9-NEXT: s_mov_b32 s4, s6
; GFX9-NEXT: s_mov_b32 s5, s7
; GFX9-NEXT: s_mov_b32 s6, s2
; GFX9-NEXT: s_mov_b32 s7, s3
; GFX9-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 0
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v0 ; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v0
; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v1 ; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 30, v2 ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 30, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 30, v3 ; GFX9-NEXT: v_lshrrev_b32_e32 v3, 30, v3
; GFX9-NEXT: v_add_u32_e32 v0, v0, v2 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 2, v0 ; GFX9-NEXT: v_ashrrev_i32_e32 v0, 2, v0
▲ Show 20 Lines • Show All 305 Lines • ▼ Show 20 Lines
; TONGA-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; TONGA-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; TONGA-NEXT: s_endpgm ; TONGA-NEXT: s_endpgm
; ;
; GFX9-LABEL: sdiv_v4i32: ; GFX9-LABEL: sdiv_v4i32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: s_mov_b32 s11, 0xf000 ; GFX9-NEXT: s_mov_b32 s11, 0xf000
; GFX9-NEXT: s_mov_b32 s10, -1 ; GFX9-NEXT: s_mov_b32 s10, -1
; GFX9-NEXT: s_mov_b32 s4, 0x4f7ffffe ; GFX9-NEXT: s_mov_b32 s6, s10
; GFX9-NEXT: s_mov_b32 s7, s11
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, s2
; GFX9-NEXT: s_mov_b32 s5, s3
; GFX9-NEXT: buffer_load_dwordx4 v[0:3], off, s[4:7], 0
; GFX9-NEXT: buffer_load_dwordx4 v[4:7], off, s[4:7], 0 offset:16
; GFX9-NEXT: s_mov_b32 s2, 0x4f7ffffe
; GFX9-NEXT: s_mov_b32 s8, s0 ; GFX9-NEXT: s_mov_b32 s8, s0
; GFX9-NEXT: s_mov_b32 s9, s1 ; GFX9-NEXT: s_mov_b32 s9, s1
; GFX9-NEXT: s_mov_b32 s0, s2
; GFX9-NEXT: s_mov_b32 s1, s3
; GFX9-NEXT: s_mov_b32 s2, s10
; GFX9-NEXT: s_mov_b32 s3, s11
; GFX9-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
; GFX9-NEXT: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 offset:16
; GFX9-NEXT: s_waitcnt vmcnt(1) ; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_ashrrev_i32_e32 v8, 31, v0 ; GFX9-NEXT: v_ashrrev_i32_e32 v8, 31, v0
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_ashrrev_i32_e32 v9, 31, v4 ; GFX9-NEXT: v_ashrrev_i32_e32 v9, 31, v4
; GFX9-NEXT: v_add_u32_e32 v4, v4, v9 ; GFX9-NEXT: v_add_u32_e32 v4, v4, v9
; GFX9-NEXT: v_ashrrev_i32_e32 v11, 31, v5 ; GFX9-NEXT: v_ashrrev_i32_e32 v11, 31, v5
; GFX9-NEXT: v_add_u32_e32 v0, v0, v8 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v8
; GFX9-NEXT: v_xor_b32_e32 v4, v4, v9 ; GFX9-NEXT: v_xor_b32_e32 v4, v4, v9
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; GFX9-NEXT: v_cvt_f32_u32_e32 v12, v6 ; GFX9-NEXT: v_cvt_f32_u32_e32 v12, v6
; GFX9-NEXT: v_xor_b32_e32 v7, v7, v15 ; GFX9-NEXT: v_xor_b32_e32 v7, v7, v15
; GFX9-NEXT: v_rcp_iflag_f32_e32 v8, v8 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v8, v8
; GFX9-NEXT: v_xor_b32_e32 v19, v14, v15 ; GFX9-NEXT: v_xor_b32_e32 v19, v14, v15
; GFX9-NEXT: v_xor_b32_e32 v3, v3, v14 ; GFX9-NEXT: v_xor_b32_e32 v3, v3, v14
; GFX9-NEXT: v_cvt_f32_u32_e32 v14, v7 ; GFX9-NEXT: v_cvt_f32_u32_e32 v14, v7
; GFX9-NEXT: v_rcp_iflag_f32_e32 v10, v10 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v10, v10
; GFX9-NEXT: v_rcp_iflag_f32_e32 v12, v12 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v12, v12
; GFX9-NEXT: v_mul_f32_e32 v8, s4, v8 ; GFX9-NEXT: v_mul_f32_e32 v8, s2, v8
; GFX9-NEXT: v_rcp_iflag_f32_e32 v14, v14 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v14, v14
; GFX9-NEXT: v_cvt_u32_f32_e32 v8, v8 ; GFX9-NEXT: v_cvt_u32_f32_e32 v8, v8
; GFX9-NEXT: v_mul_f32_e32 v10, s4, v10 ; GFX9-NEXT: v_mul_f32_e32 v10, s2, v10
; GFX9-NEXT: v_mul_f32_e32 v12, s4, v12 ; GFX9-NEXT: v_mul_f32_e32 v12, s2, v12
; GFX9-NEXT: v_cvt_u32_f32_e32 v10, v10 ; GFX9-NEXT: v_cvt_u32_f32_e32 v10, v10
; GFX9-NEXT: v_sub_u32_e32 v9, 0, v4 ; GFX9-NEXT: v_sub_u32_e32 v9, 0, v4
; GFX9-NEXT: v_mul_f32_e32 v14, s4, v14 ; GFX9-NEXT: v_mul_f32_e32 v14, s2, v14
; GFX9-NEXT: v_cvt_u32_f32_e32 v12, v12 ; GFX9-NEXT: v_cvt_u32_f32_e32 v12, v12
; GFX9-NEXT: v_mul_lo_u32 v9, v9, v8 ; GFX9-NEXT: v_mul_lo_u32 v9, v9, v8
; GFX9-NEXT: v_cvt_u32_f32_e32 v14, v14 ; GFX9-NEXT: v_cvt_u32_f32_e32 v14, v14
; GFX9-NEXT: v_sub_u32_e32 v11, 0, v5 ; GFX9-NEXT: v_sub_u32_e32 v11, 0, v5
; GFX9-NEXT: v_sub_u32_e32 v13, 0, v6 ; GFX9-NEXT: v_sub_u32_e32 v13, 0, v6
; GFX9-NEXT: v_mul_lo_u32 v11, v11, v10 ; GFX9-NEXT: v_mul_lo_u32 v11, v11, v10
; GFX9-NEXT: v_sub_u32_e32 v15, 0, v7 ; GFX9-NEXT: v_sub_u32_e32 v15, 0, v7
; GFX9-NEXT: v_mul_lo_u32 v13, v13, v12 ; GFX9-NEXT: v_mul_lo_u32 v13, v13, v12
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} }
define amdgpu_kernel void @sdiv_v4i32_4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { define amdgpu_kernel void @sdiv_v4i32_4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
; GCN-LABEL: sdiv_v4i32_4: ; GCN-LABEL: sdiv_v4i32_4:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_mov_b32 s10, s2
; GCN-NEXT: s_mov_b32 s11, s3
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s8, s6
; GCN-NEXT: s_mov_b32 s9, s7
; GCN-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
; GCN-NEXT: s_mov_b32 s0, s4 ; GCN-NEXT: s_mov_b32 s0, s4
; GCN-NEXT: s_mov_b32 s1, s5 ; GCN-NEXT: s_mov_b32 s1, s5
; GCN-NEXT: s_mov_b32 s4, s6
; GCN-NEXT: s_mov_b32 s5, s7
; GCN-NEXT: s_mov_b32 s6, s2
; GCN-NEXT: s_mov_b32 s7, s3
; GCN-NEXT: buffer_load_dwordx4 v[0:3], off, s[4:7], 0
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_ashrrev_i32_e32 v4, 31, v0 ; GCN-NEXT: v_ashrrev_i32_e32 v4, 31, v0
; GCN-NEXT: v_ashrrev_i32_e32 v5, 31, v1 ; GCN-NEXT: v_ashrrev_i32_e32 v5, 31, v1
; GCN-NEXT: v_ashrrev_i32_e32 v6, 31, v2 ; GCN-NEXT: v_ashrrev_i32_e32 v6, 31, v2
; GCN-NEXT: v_ashrrev_i32_e32 v7, 31, v3 ; GCN-NEXT: v_ashrrev_i32_e32 v7, 31, v3
; GCN-NEXT: v_lshrrev_b32_e32 v4, 30, v4 ; GCN-NEXT: v_lshrrev_b32_e32 v4, 30, v4
; GCN-NEXT: v_lshrrev_b32_e32 v5, 30, v5 ; GCN-NEXT: v_lshrrev_b32_e32 v5, 30, v5
; GCN-NEXT: v_lshrrev_b32_e32 v6, 30, v6 ; GCN-NEXT: v_lshrrev_b32_e32 v6, 30, v6
Show All 9 Lines
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; TONGA-LABEL: sdiv_v4i32_4: ; TONGA-LABEL: sdiv_v4i32_4:
; TONGA: ; %bb.0: ; TONGA: ; %bb.0:
; TONGA-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; TONGA-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; TONGA-NEXT: s_mov_b32 s3, 0xf000 ; TONGA-NEXT: s_mov_b32 s3, 0xf000
; TONGA-NEXT: s_mov_b32 s2, -1 ; TONGA-NEXT: s_mov_b32 s2, -1
; TONGA-NEXT: s_mov_b32 s10, s2
; TONGA-NEXT: s_mov_b32 s11, s3
; TONGA-NEXT: s_waitcnt lgkmcnt(0) ; TONGA-NEXT: s_waitcnt lgkmcnt(0)
; TONGA-NEXT: s_mov_b32 s8, s6
; TONGA-NEXT: s_mov_b32 s9, s7
; TONGA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
; TONGA-NEXT: s_mov_b32 s0, s4 ; TONGA-NEXT: s_mov_b32 s0, s4
; TONGA-NEXT: s_mov_b32 s1, s5 ; TONGA-NEXT: s_mov_b32 s1, s5
; TONGA-NEXT: s_mov_b32 s4, s6
; TONGA-NEXT: s_mov_b32 s5, s7
; TONGA-NEXT: s_mov_b32 s6, s2
; TONGA-NEXT: s_mov_b32 s7, s3
; TONGA-NEXT: buffer_load_dwordx4 v[0:3], off, s[4:7], 0
; TONGA-NEXT: s_waitcnt vmcnt(0) ; TONGA-NEXT: s_waitcnt vmcnt(0)
; TONGA-NEXT: v_ashrrev_i32_e32 v4, 31, v0 ; TONGA-NEXT: v_ashrrev_i32_e32 v4, 31, v0
; TONGA-NEXT: v_ashrrev_i32_e32 v5, 31, v1 ; TONGA-NEXT: v_ashrrev_i32_e32 v5, 31, v1
; TONGA-NEXT: v_ashrrev_i32_e32 v6, 31, v2 ; TONGA-NEXT: v_ashrrev_i32_e32 v6, 31, v2
; TONGA-NEXT: v_ashrrev_i32_e32 v7, 31, v3 ; TONGA-NEXT: v_ashrrev_i32_e32 v7, 31, v3
; TONGA-NEXT: v_lshrrev_b32_e32 v4, 30, v4 ; TONGA-NEXT: v_lshrrev_b32_e32 v4, 30, v4
; TONGA-NEXT: v_lshrrev_b32_e32 v5, 30, v5 ; TONGA-NEXT: v_lshrrev_b32_e32 v5, 30, v5
; TONGA-NEXT: v_lshrrev_b32_e32 v6, 30, v6 ; TONGA-NEXT: v_lshrrev_b32_e32 v6, 30, v6
Show All 9 Lines
; TONGA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; TONGA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; TONGA-NEXT: s_endpgm ; TONGA-NEXT: s_endpgm
; ;
; GFX9-LABEL: sdiv_v4i32_4: ; GFX9-LABEL: sdiv_v4i32_4:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_mov_b32 s10, s2
; GFX9-NEXT: s_mov_b32 s11, s3
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s8, s6
; GFX9-NEXT: s_mov_b32 s9, s7
; GFX9-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
; GFX9-NEXT: s_mov_b32 s0, s4 ; GFX9-NEXT: s_mov_b32 s0, s4
; GFX9-NEXT: s_mov_b32 s1, s5 ; GFX9-NEXT: s_mov_b32 s1, s5
; GFX9-NEXT: s_mov_b32 s4, s6
; GFX9-NEXT: s_mov_b32 s5, s7
; GFX9-NEXT: s_mov_b32 s6, s2
; GFX9-NEXT: s_mov_b32 s7, s3
; GFX9-NEXT: buffer_load_dwordx4 v[0:3], off, s[4:7], 0
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_ashrrev_i32_e32 v4, 31, v0 ; GFX9-NEXT: v_ashrrev_i32_e32 v4, 31, v0
; GFX9-NEXT: v_ashrrev_i32_e32 v5, 31, v1 ; GFX9-NEXT: v_ashrrev_i32_e32 v5, 31, v1
; GFX9-NEXT: v_ashrrev_i32_e32 v6, 31, v2 ; GFX9-NEXT: v_ashrrev_i32_e32 v6, 31, v2
; GFX9-NEXT: v_ashrrev_i32_e32 v7, 31, v3 ; GFX9-NEXT: v_ashrrev_i32_e32 v7, 31, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 30, v4 ; GFX9-NEXT: v_lshrrev_b32_e32 v4, 30, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 30, v5 ; GFX9-NEXT: v_lshrrev_b32_e32 v5, 30, v5
; GFX9-NEXT: v_lshrrev_b32_e32 v6, 30, v6 ; GFX9-NEXT: v_lshrrev_b32_e32 v6, 30, v6
▲ Show 20 Lines • Show All 199 Lines • ▼ Show 20 Lines
} }
define amdgpu_kernel void @v_sdiv_i23(i32 addrspace(1)* %out, i23 addrspace(1)* %in) { define amdgpu_kernel void @v_sdiv_i23(i32 addrspace(1)* %out, i23 addrspace(1)* %in) {
; GCN-LABEL: v_sdiv_i23: ; GCN-LABEL: v_sdiv_i23:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_mov_b32 s10, s2
; GCN-NEXT: s_mov_b32 s11, s3
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s8, s6
; GCN-NEXT: s_mov_b32 s9, s7
; GCN-NEXT: buffer_load_ushort v0, off, s[8:11], 0
; GCN-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 offset:2
; GCN-NEXT: buffer_load_ushort v2, off, s[8:11], 0 offset:4
; GCN-NEXT: buffer_load_ubyte v3, off, s[8:11], 0 offset:6
; GCN-NEXT: s_mov_b32 s0, s4 ; GCN-NEXT: s_mov_b32 s0, s4
; GCN-NEXT: s_mov_b32 s1, s5 ; GCN-NEXT: s_mov_b32 s1, s5
; GCN-NEXT: s_mov_b32 s4, s6
; GCN-NEXT: s_mov_b32 s5, s7
; GCN-NEXT: s_mov_b32 s6, s2
; GCN-NEXT: s_mov_b32 s7, s3
; GCN-NEXT: buffer_load_ushort v0, off, s[4:7], 0
; GCN-NEXT: buffer_load_ubyte v1, off, s[4:7], 0 offset:2
; GCN-NEXT: buffer_load_ushort v2, off, s[4:7], 0 offset:4
; GCN-NEXT: buffer_load_ubyte v3, off, s[4:7], 0 offset:6
; GCN-NEXT: s_waitcnt vmcnt(2) ; GCN-NEXT: s_waitcnt vmcnt(2)
; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GCN-NEXT: v_or_b32_e32 v0, v0, v1 ; GCN-NEXT: v_or_b32_e32 v0, v0, v1
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GCN-NEXT: v_or_b32_e32 v2, v2, v3 ; GCN-NEXT: v_or_b32_e32 v2, v2, v3
; GCN-NEXT: v_bfe_i32 v2, v2, 0, 23 ; GCN-NEXT: v_bfe_i32 v2, v2, 0, 23
; GCN-NEXT: v_cvt_f32_i32_e32 v3, v2 ; GCN-NEXT: v_cvt_f32_i32_e32 v3, v2
Show All 14 Lines
; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; TONGA-LABEL: v_sdiv_i23: ; TONGA-LABEL: v_sdiv_i23:
; TONGA: ; %bb.0: ; TONGA: ; %bb.0:
; TONGA-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; TONGA-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; TONGA-NEXT: s_mov_b32 s3, 0xf000 ; TONGA-NEXT: s_mov_b32 s3, 0xf000
; TONGA-NEXT: s_mov_b32 s2, -1 ; TONGA-NEXT: s_mov_b32 s2, -1
; TONGA-NEXT: s_mov_b32 s10, s2
; TONGA-NEXT: s_mov_b32 s11, s3
; TONGA-NEXT: s_waitcnt lgkmcnt(0) ; TONGA-NEXT: s_waitcnt lgkmcnt(0)
; TONGA-NEXT: s_mov_b32 s8, s6
; TONGA-NEXT: s_mov_b32 s9, s7
; TONGA-NEXT: buffer_load_ushort v0, off, s[8:11], 0
; TONGA-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 offset:2
; TONGA-NEXT: buffer_load_ushort v2, off, s[8:11], 0 offset:4
; TONGA-NEXT: buffer_load_ubyte v3, off, s[8:11], 0 offset:6
; TONGA-NEXT: s_mov_b32 s0, s4 ; TONGA-NEXT: s_mov_b32 s0, s4
; TONGA-NEXT: s_mov_b32 s1, s5 ; TONGA-NEXT: s_mov_b32 s1, s5
; TONGA-NEXT: s_mov_b32 s4, s6
; TONGA-NEXT: s_mov_b32 s5, s7
; TONGA-NEXT: s_mov_b32 s6, s2
; TONGA-NEXT: s_mov_b32 s7, s3
; TONGA-NEXT: buffer_load_ushort v0, off, s[4:7], 0
; TONGA-NEXT: buffer_load_ubyte v1, off, s[4:7], 0 offset:2
; TONGA-NEXT: buffer_load_ushort v2, off, s[4:7], 0 offset:4
; TONGA-NEXT: buffer_load_ubyte v3, off, s[4:7], 0 offset:6
; TONGA-NEXT: s_waitcnt vmcnt(2) ; TONGA-NEXT: s_waitcnt vmcnt(2)
; TONGA-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; TONGA-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; TONGA-NEXT: v_or_b32_e32 v0, v0, v1 ; TONGA-NEXT: v_or_b32_e32 v0, v0, v1
; TONGA-NEXT: s_waitcnt vmcnt(0) ; TONGA-NEXT: s_waitcnt vmcnt(0)
; TONGA-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; TONGA-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; TONGA-NEXT: v_or_b32_e32 v2, v2, v3 ; TONGA-NEXT: v_or_b32_e32 v2, v2, v3
; TONGA-NEXT: v_bfe_i32 v2, v2, 0, 23 ; TONGA-NEXT: v_bfe_i32 v2, v2, 0, 23
; TONGA-NEXT: v_cvt_f32_i32_e32 v3, v2 ; TONGA-NEXT: v_cvt_f32_i32_e32 v3, v2
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; TONGA-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; TONGA-NEXT: buffer_store_dword v0, off, s[0:3], 0
; TONGA-NEXT: s_endpgm ; TONGA-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_sdiv_i23: ; GFX9-LABEL: v_sdiv_i23:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_mov_b32 s10, s2
; GFX9-NEXT: s_mov_b32 s11, s3
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s8, s6
; GFX9-NEXT: s_mov_b32 s9, s7
; GFX9-NEXT: buffer_load_ushort v0, off, s[8:11], 0
; GFX9-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 offset:2
; GFX9-NEXT: buffer_load_ushort v2, off, s[8:11], 0 offset:4
; GFX9-NEXT: buffer_load_ubyte v3, off, s[8:11], 0 offset:6
; GFX9-NEXT: s_mov_b32 s0, s4 ; GFX9-NEXT: s_mov_b32 s0, s4
; GFX9-NEXT: s_mov_b32 s1, s5 ; GFX9-NEXT: s_mov_b32 s1, s5
; GFX9-NEXT: s_mov_b32 s4, s6
; GFX9-NEXT: s_mov_b32 s5, s7
; GFX9-NEXT: s_mov_b32 s6, s2
; GFX9-NEXT: s_mov_b32 s7, s3
; GFX9-NEXT: buffer_load_ushort v0, off, s[4:7], 0
; GFX9-NEXT: buffer_load_ubyte v1, off, s[4:7], 0 offset:2
; GFX9-NEXT: buffer_load_ushort v2, off, s[4:7], 0 offset:4
; GFX9-NEXT: buffer_load_ubyte v3, off, s[4:7], 0 offset:6
; GFX9-NEXT: s_waitcnt vmcnt(2) ; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT: v_or_b32_e32 v2, v2, v3 ; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_bfe_i32 v2, v2, 0, 23 ; GFX9-NEXT: v_bfe_i32 v2, v2, 0, 23
; GFX9-NEXT: v_cvt_f32_i32_e32 v3, v2 ; GFX9-NEXT: v_cvt_f32_i32_e32 v3, v2
▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Lines
} }
define amdgpu_kernel void @v_sdiv_i24(i32 addrspace(1)* %out, i24 addrspace(1)* %in) { define amdgpu_kernel void @v_sdiv_i24(i32 addrspace(1)* %out, i24 addrspace(1)* %in) {
; GCN-LABEL: v_sdiv_i24: ; GCN-LABEL: v_sdiv_i24:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_mov_b32 s10, s2
; GCN-NEXT: s_mov_b32 s11, s3
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s8, s6
; GCN-NEXT: s_mov_b32 s9, s7
; GCN-NEXT: buffer_load_ushort v0, off, s[8:11], 0
; GCN-NEXT: buffer_load_sbyte v1, off, s[8:11], 0 offset:2
; GCN-NEXT: buffer_load_ushort v2, off, s[8:11], 0 offset:4
; GCN-NEXT: buffer_load_sbyte v3, off, s[8:11], 0 offset:6
; GCN-NEXT: s_mov_b32 s0, s4 ; GCN-NEXT: s_mov_b32 s0, s4
; GCN-NEXT: s_mov_b32 s1, s5 ; GCN-NEXT: s_mov_b32 s1, s5
; GCN-NEXT: s_mov_b32 s4, s6
; GCN-NEXT: s_mov_b32 s5, s7
; GCN-NEXT: s_mov_b32 s6, s2
; GCN-NEXT: s_mov_b32 s7, s3
; GCN-NEXT: buffer_load_ushort v0, off, s[4:7], 0
; GCN-NEXT: buffer_load_sbyte v1, off, s[4:7], 0 offset:2
; GCN-NEXT: buffer_load_ushort v2, off, s[4:7], 0 offset:4
; GCN-NEXT: buffer_load_sbyte v3, off, s[4:7], 0 offset:6
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v3 ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v3
; GCN-NEXT: v_or_b32_e32 v2, v2, v4 ; GCN-NEXT: v_or_b32_e32 v2, v2, v4
; GCN-NEXT: v_cvt_f32_i32_e32 v2, v2 ; GCN-NEXT: v_cvt_f32_i32_e32 v2, v2
; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v1 ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v1
; GCN-NEXT: v_or_b32_e32 v0, v0, v4 ; GCN-NEXT: v_or_b32_e32 v0, v0, v4
; GCN-NEXT: v_cvt_f32_i32_e32 v0, v0 ; GCN-NEXT: v_cvt_f32_i32_e32 v0, v0
; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v2 ; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v2
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; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; TONGA-LABEL: v_sdiv_i24: ; TONGA-LABEL: v_sdiv_i24:
; TONGA: ; %bb.0: ; TONGA: ; %bb.0:
; TONGA-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; TONGA-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; TONGA-NEXT: s_mov_b32 s3, 0xf000 ; TONGA-NEXT: s_mov_b32 s3, 0xf000
; TONGA-NEXT: s_mov_b32 s2, -1 ; TONGA-NEXT: s_mov_b32 s2, -1
; TONGA-NEXT: s_mov_b32 s10, s2
; TONGA-NEXT: s_mov_b32 s11, s3
; TONGA-NEXT: s_waitcnt lgkmcnt(0) ; TONGA-NEXT: s_waitcnt lgkmcnt(0)
; TONGA-NEXT: s_mov_b32 s8, s6
; TONGA-NEXT: s_mov_b32 s9, s7
; TONGA-NEXT: buffer_load_ushort v0, off, s[8:11], 0
; TONGA-NEXT: buffer_load_sbyte v1, off, s[8:11], 0 offset:2
; TONGA-NEXT: buffer_load_ushort v2, off, s[8:11], 0 offset:4
; TONGA-NEXT: buffer_load_sbyte v3, off, s[8:11], 0 offset:6
; TONGA-NEXT: s_mov_b32 s0, s4 ; TONGA-NEXT: s_mov_b32 s0, s4
; TONGA-NEXT: s_mov_b32 s1, s5 ; TONGA-NEXT: s_mov_b32 s1, s5
; TONGA-NEXT: s_mov_b32 s4, s6
; TONGA-NEXT: s_mov_b32 s5, s7
; TONGA-NEXT: s_mov_b32 s6, s2
; TONGA-NEXT: s_mov_b32 s7, s3
; TONGA-NEXT: buffer_load_ushort v0, off, s[4:7], 0
; TONGA-NEXT: buffer_load_sbyte v1, off, s[4:7], 0 offset:2
; TONGA-NEXT: buffer_load_ushort v2, off, s[4:7], 0 offset:4
; TONGA-NEXT: buffer_load_sbyte v3, off, s[4:7], 0 offset:6
; TONGA-NEXT: s_waitcnt vmcnt(0) ; TONGA-NEXT: s_waitcnt vmcnt(0)
; TONGA-NEXT: v_lshlrev_b32_e32 v4, 16, v3 ; TONGA-NEXT: v_lshlrev_b32_e32 v4, 16, v3
; TONGA-NEXT: v_or_b32_e32 v2, v2, v4 ; TONGA-NEXT: v_or_b32_e32 v2, v2, v4
; TONGA-NEXT: v_cvt_f32_i32_e32 v2, v2 ; TONGA-NEXT: v_cvt_f32_i32_e32 v2, v2
; TONGA-NEXT: v_lshlrev_b32_e32 v4, 16, v1 ; TONGA-NEXT: v_lshlrev_b32_e32 v4, 16, v1
; TONGA-NEXT: v_or_b32_e32 v0, v0, v4 ; TONGA-NEXT: v_or_b32_e32 v0, v0, v4
; TONGA-NEXT: v_cvt_f32_i32_e32 v0, v0 ; TONGA-NEXT: v_cvt_f32_i32_e32 v0, v0
; TONGA-NEXT: v_rcp_iflag_f32_e32 v4, v2 ; TONGA-NEXT: v_rcp_iflag_f32_e32 v4, v2
▲ Show 20 Lines • Show All 347 Lines • ▼ Show 20 Lines
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s0, s4 ; GCN-NEXT: s_mov_b32 s0, s4
; GCN-NEXT: s_mov_b32 s1, s5 ; GCN-NEXT: s_mov_b32 s1, s5
; GCN-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 ; GCN-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
; GCN-NEXT: s_mov_b32 s0, 0x1389c755 ; GCN-NEXT: s_mov_b32 s4, 0x1389c755
; GCN-NEXT: s_mov_b32 s4, s6 ; GCN-NEXT: s_mov_b32 s0, s6
; GCN-NEXT: s_mov_b32 s5, s7 ; GCN-NEXT: s_mov_b32 s1, s7
; GCN-NEXT: s_mov_b32 s6, s2
; GCN-NEXT: s_mov_b32 s7, s3
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_mul_hi_i32 v0, v0, s0 ; GCN-NEXT: v_mul_hi_i32 v0, v0, s4
; GCN-NEXT: v_mul_hi_i32 v1, v1, s0 ; GCN-NEXT: v_mul_hi_i32 v1, v1, s4
; GCN-NEXT: v_mul_hi_i32 v2, v2, s0 ; GCN-NEXT: v_mul_hi_i32 v2, v2, s4
; GCN-NEXT: v_mul_hi_i32 v3, v3, s0 ; GCN-NEXT: v_mul_hi_i32 v3, v3, s4
; GCN-NEXT: v_lshrrev_b32_e32 v4, 31, v0 ; GCN-NEXT: v_lshrrev_b32_e32 v4, 31, v0
; GCN-NEXT: v_ashrrev_i32_e32 v0, 12, v0 ; GCN-NEXT: v_ashrrev_i32_e32 v0, 12, v0
; GCN-NEXT: v_lshrrev_b32_e32 v5, 31, v1 ; GCN-NEXT: v_lshrrev_b32_e32 v5, 31, v1
; GCN-NEXT: v_ashrrev_i32_e32 v1, 12, v1 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 12, v1
; GCN-NEXT: v_lshrrev_b32_e32 v6, 31, v2 ; GCN-NEXT: v_lshrrev_b32_e32 v6, 31, v2
; GCN-NEXT: v_ashrrev_i32_e32 v2, 12, v2 ; GCN-NEXT: v_ashrrev_i32_e32 v2, 12, v2
; GCN-NEXT: v_lshrrev_b32_e32 v7, 31, v3 ; GCN-NEXT: v_lshrrev_b32_e32 v7, 31, v3
; GCN-NEXT: v_ashrrev_i32_e32 v3, 12, v3 ; GCN-NEXT: v_ashrrev_i32_e32 v3, 12, v3
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v5 ; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v5
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v7 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v7
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; TONGA-LABEL: scalarize_mulhs_4xi32: ; TONGA-LABEL: scalarize_mulhs_4xi32:
; TONGA: ; %bb.0: ; TONGA: ; %bb.0:
; TONGA-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; TONGA-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; TONGA-NEXT: s_mov_b32 s3, 0xf000 ; TONGA-NEXT: s_mov_b32 s3, 0xf000
; TONGA-NEXT: s_mov_b32 s2, -1 ; TONGA-NEXT: s_mov_b32 s2, -1
; TONGA-NEXT: s_waitcnt lgkmcnt(0) ; TONGA-NEXT: s_waitcnt lgkmcnt(0)
; TONGA-NEXT: s_mov_b32 s0, s4 ; TONGA-NEXT: s_mov_b32 s0, s4
; TONGA-NEXT: s_mov_b32 s1, s5 ; TONGA-NEXT: s_mov_b32 s1, s5
; TONGA-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 ; TONGA-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
; TONGA-NEXT: s_mov_b32 s0, 0x1389c755 ; TONGA-NEXT: s_mov_b32 s4, 0x1389c755
; TONGA-NEXT: s_mov_b32 s4, s6 ; TONGA-NEXT: s_mov_b32 s0, s6
; TONGA-NEXT: s_mov_b32 s5, s7 ; TONGA-NEXT: s_mov_b32 s1, s7
; TONGA-NEXT: s_mov_b32 s6, s2
; TONGA-NEXT: s_mov_b32 s7, s3
; TONGA-NEXT: s_waitcnt vmcnt(0) ; TONGA-NEXT: s_waitcnt vmcnt(0)
; TONGA-NEXT: v_mul_hi_i32 v0, v0, s0 ; TONGA-NEXT: v_mul_hi_i32 v0, v0, s4
; TONGA-NEXT: v_mul_hi_i32 v1, v1, s0 ; TONGA-NEXT: v_mul_hi_i32 v1, v1, s4
; TONGA-NEXT: v_mul_hi_i32 v2, v2, s0 ; TONGA-NEXT: v_mul_hi_i32 v2, v2, s4
; TONGA-NEXT: v_mul_hi_i32 v3, v3, s0 ; TONGA-NEXT: v_mul_hi_i32 v3, v3, s4
; TONGA-NEXT: v_lshrrev_b32_e32 v4, 31, v0 ; TONGA-NEXT: v_lshrrev_b32_e32 v4, 31, v0
; TONGA-NEXT: v_ashrrev_i32_e32 v0, 12, v0 ; TONGA-NEXT: v_ashrrev_i32_e32 v0, 12, v0
; TONGA-NEXT: v_lshrrev_b32_e32 v5, 31, v1 ; TONGA-NEXT: v_lshrrev_b32_e32 v5, 31, v1
; TONGA-NEXT: v_ashrrev_i32_e32 v1, 12, v1 ; TONGA-NEXT: v_ashrrev_i32_e32 v1, 12, v1
; TONGA-NEXT: v_lshrrev_b32_e32 v6, 31, v2 ; TONGA-NEXT: v_lshrrev_b32_e32 v6, 31, v2
; TONGA-NEXT: v_ashrrev_i32_e32 v2, 12, v2 ; TONGA-NEXT: v_ashrrev_i32_e32 v2, 12, v2
; TONGA-NEXT: v_lshrrev_b32_e32 v7, 31, v3 ; TONGA-NEXT: v_lshrrev_b32_e32 v7, 31, v3
; TONGA-NEXT: v_ashrrev_i32_e32 v3, 12, v3 ; TONGA-NEXT: v_ashrrev_i32_e32 v3, 12, v3
; TONGA-NEXT: v_add_u32_e32 v0, vcc, v0, v4 ; TONGA-NEXT: v_add_u32_e32 v0, vcc, v0, v4
; TONGA-NEXT: v_add_u32_e32 v1, vcc, v1, v5 ; TONGA-NEXT: v_add_u32_e32 v1, vcc, v1, v5
; TONGA-NEXT: v_add_u32_e32 v2, vcc, v2, v6 ; TONGA-NEXT: v_add_u32_e32 v2, vcc, v2, v6
; TONGA-NEXT: v_add_u32_e32 v3, vcc, v3, v7 ; TONGA-NEXT: v_add_u32_e32 v3, vcc, v3, v7
; TONGA-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; TONGA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; TONGA-NEXT: s_endpgm ; TONGA-NEXT: s_endpgm
; ;
; GFX9-LABEL: scalarize_mulhs_4xi32: ; GFX9-LABEL: scalarize_mulhs_4xi32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s0, s4 ; GFX9-NEXT: s_mov_b32 s0, s4
; GFX9-NEXT: s_mov_b32 s1, s5 ; GFX9-NEXT: s_mov_b32 s1, s5
; GFX9-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 ; GFX9-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
; GFX9-NEXT: s_mov_b32 s0, 0x1389c755 ; GFX9-NEXT: s_mov_b32 s4, 0x1389c755
; GFX9-NEXT: s_mov_b32 s4, s6 ; GFX9-NEXT: s_mov_b32 s0, s6
; GFX9-NEXT: s_mov_b32 s5, s7 ; GFX9-NEXT: s_mov_b32 s1, s7
; GFX9-NEXT: s_mov_b32 s6, s2
; GFX9-NEXT: s_mov_b32 s7, s3
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mul_hi_i32 v0, v0, s0 ; GFX9-NEXT: v_mul_hi_i32 v0, v0, s4
; GFX9-NEXT: v_mul_hi_i32 v1, v1, s0 ; GFX9-NEXT: v_mul_hi_i32 v1, v1, s4
; GFX9-NEXT: v_mul_hi_i32 v2, v2, s0 ; GFX9-NEXT: v_mul_hi_i32 v2, v2, s4
; GFX9-NEXT: v_mul_hi_i32 v3, v3, s0 ; GFX9-NEXT: v_mul_hi_i32 v3, v3, s4
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 31, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v4, 31, v0
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 12, v0 ; GFX9-NEXT: v_ashrrev_i32_e32 v0, 12, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 31, v1 ; GFX9-NEXT: v_lshrrev_b32_e32 v5, 31, v1
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 12, v1 ; GFX9-NEXT: v_ashrrev_i32_e32 v1, 12, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v6, 31, v2 ; GFX9-NEXT: v_lshrrev_b32_e32 v6, 31, v2
; GFX9-NEXT: v_ashrrev_i32_e32 v2, 12, v2 ; GFX9-NEXT: v_ashrrev_i32_e32 v2, 12, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v7, 31, v3 ; GFX9-NEXT: v_lshrrev_b32_e32 v7, 31, v3
; GFX9-NEXT: v_ashrrev_i32_e32 v3, 12, v3 ; GFX9-NEXT: v_ashrrev_i32_e32 v3, 12, v3
; GFX9-NEXT: v_add_u32_e32 v0, v0, v4 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v4
; GFX9-NEXT: v_add_u32_e32 v1, v1, v5 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v5
; GFX9-NEXT: v_add_u32_e32 v2, v2, v6 ; GFX9-NEXT: v_add_u32_e32 v2, v2, v6
; GFX9-NEXT: v_add_u32_e32 v3, v3, v7 ; GFX9-NEXT: v_add_u32_e32 v3, v3, v7
; GFX9-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; GFX9-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; EG-LABEL: scalarize_mulhs_4xi32: ; EG-LABEL: scalarize_mulhs_4xi32:
; EG: ; %bb.0: ; EG: ; %bb.0:
; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6 ; EG-NEXT: TEX 0 @6
; EG-NEXT: ALU 25, @9, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 25, @9, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
Show All 38 Lines

llvm/test/CodeGen/AMDGPU/sdiv64.ll

Show First 20 Lines • Show All 1,861 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: s_setpc_b64 s[30:31] ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = sdiv i64 %x, 32768 %result = sdiv i64 %x, 32768
ret i64 %result ret i64 %result
} }
define amdgpu_kernel void @s_test_sdiv24_k_num_i64(i64 addrspace(1)* %out, i64 %x) { define amdgpu_kernel void @s_test_sdiv24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
; GCN-LABEL: s_test_sdiv24_k_num_i64: ; GCN-LABEL: s_test_sdiv24_k_num_i64:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_ashr_i64 s[6:7], s[6:7], 40 ; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 40
; GCN-NEXT: v_cvt_f32_i32_e32 v0, s6 ; GCN-NEXT: v_cvt_f32_i32_e32 v0, s2
; GCN-NEXT: s_mov_b32 s7, 0x41c00000 ; GCN-NEXT: s_mov_b32 s3, 0x41c00000
; GCN-NEXT: s_mov_b32 s0, s4 ; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: s_ashr_i32 s4, s6, 30 ; GCN-NEXT: s_ashr_i32 s0, s2, 30
; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0 ; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0
; GCN-NEXT: s_mov_b32 s1, s5 ; GCN-NEXT: s_mov_b32 s5, s1
; GCN-NEXT: s_or_b32 s6, s4, 1 ; GCN-NEXT: s_or_b32 s2, s0, 1
; GCN-NEXT: v_mul_f32_e32 v1, s7, v1 ; GCN-NEXT: v_mul_f32_e32 v1, s3, v1
; GCN-NEXT: v_trunc_f32_e32 v1, v1 ; GCN-NEXT: v_trunc_f32_e32 v1, v1
; GCN-NEXT: v_mad_f32 v2, -v1, v0, s7 ; GCN-NEXT: v_mad_f32 v2, -v1, v0, s3
; GCN-NEXT: v_cvt_i32_f32_e32 v1, v1 ; GCN-NEXT: v_cvt_i32_f32_e32 v1, v1
; GCN-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, |v0| ; GCN-NEXT: v_cmp_ge_f32_e64 s[0:1], |v2|, |v0|
; GCN-NEXT: s_cmp_lg_u32 s4, 0 ; GCN-NEXT: s_cmp_lg_u32 s0, 0
; GCN-NEXT: s_cselect_b32 s4, s6, 0 ; GCN-NEXT: s_cselect_b32 s0, s2, 0
; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v1 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s0, v1
; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GCN-IR-LABEL: s_test_sdiv24_k_num_i64: ; GCN-IR-LABEL: s_test_sdiv24_k_num_i64:
; GCN-IR: ; %bb.0: ; GCN-IR: ; %bb.0:
; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: s_mov_b32 s6, -1
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[6:7], 40 ; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 40
; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s6 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s2
; GCN-IR-NEXT: s_mov_b32 s7, 0x41c00000 ; GCN-IR-NEXT: s_mov_b32 s3, 0x41c00000
; GCN-IR-NEXT: s_mov_b32 s0, s4 ; GCN-IR-NEXT: s_mov_b32 s4, s0
; GCN-IR-NEXT: s_ashr_i32 s4, s6, 30 ; GCN-IR-NEXT: s_ashr_i32 s0, s2, 30
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v1, v0 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v1, v0
; GCN-IR-NEXT: s_mov_b32 s1, s5 ; GCN-IR-NEXT: s_mov_b32 s5, s1
; GCN-IR-NEXT: s_or_b32 s6, s4, 1 ; GCN-IR-NEXT: s_or_b32 s2, s0, 1
; GCN-IR-NEXT: v_mul_f32_e32 v1, s7, v1 ; GCN-IR-NEXT: v_mul_f32_e32 v1, s3, v1
; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1 ; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1
; GCN-IR-NEXT: v_mad_f32 v2, -v1, v0, s7 ; GCN-IR-NEXT: v_mad_f32 v2, -v1, v0, s3
; GCN-IR-NEXT: v_cvt_i32_f32_e32 v1, v1 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v1, v1
; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, |v0| ; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[0:1], |v2|, |v0|
; GCN-IR-NEXT: s_cmp_lg_u32 s4, 0 ; GCN-IR-NEXT: s_cmp_lg_u32 s0, 0
; GCN-IR-NEXT: s_cselect_b32 s4, s6, 0 ; GCN-IR-NEXT: s_cselect_b32 s0, s2, 0
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s4, v1 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s0, v1
; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24
; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-IR-NEXT: s_endpgm ; GCN-IR-NEXT: s_endpgm
%x.shr = ashr i64 %x, 40 %x.shr = ashr i64 %x, 40
%result = sdiv i64 24, %x.shr %result = sdiv i64 24, %x.shr
store i64 %result, i64 addrspace(1)* %out store i64 %result, i64 addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @s_test_sdiv24_k_den_i64(i64 addrspace(1)* %out, i64 %x) { define amdgpu_kernel void @s_test_sdiv24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
▲ Show 20 Lines • Show All 180 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll

Show First 20 Lines • Show All 67 Lines • ▼ Show 20 Linesentry:
%mul = mul i16 %a, %b %mul = mul i16 %a, %b
store i16 %mul, i16 addrspace(1)* %out, align 4 store i16 %mul, i16 addrspace(1)* %out, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}mul_v2i16: ; GCN-LABEL: {{^}}mul_v2i16:
; NOSDWA: v_lshrrev_b32_e32 v[[DST0:[0-9]+]], 16, v{{[0-9]+}} ; NOSDWA: v_lshrrev_b32_e32 v[[DST0:[0-9]+]], 16, v{{[0-9]+}}
; NOSDWA: v_lshrrev_b32_e32 v[[DST1:[0-9]+]], 16, v{{[0-9]+}} ; NOSDWA: v_lshrrev_b32_e32 v[[DST1:[0-9]+]], 16, v{{[0-9]+}}
; NOSDWA: v_mul_u32_u24_e32 v[[DST_MUL:[0-9]+]], v[[DST1]], v[[DST0]] ; NOSDWA: v_mul_u32_u24_e32 v[[DST_MUL:[0-9]+]], v[[DST0]], v[[DST1]]
; NOSDWA: v_lshlrev_b32_e32 v[[DST_SHL:[0-9]+]], 16, v[[DST_MUL]] ; NOSDWA: v_lshlrev_b32_e32 v[[DST_SHL:[0-9]+]], 16, v[[DST_MUL]]
; NOSDWA: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[DST_SHL]] ; NOSDWA: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[DST_SHL]]
; NOSDWA-NOT: v_mul_u32_u24_sdwa ; NOSDWA-NOT: v_mul_u32_u24_sdwa
; VI-DAG: v_mul_u32_u24_sdwa v[[DST_MUL_LO:[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0 ; VI-DAG: v_mul_u32_u24_sdwa v[[DST_MUL_LO:[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0
; VI-DAG: v_mul_u32_u24_sdwa v[[DST_MUL_HI:[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-DAG: v_mul_u32_u24_sdwa v[[DST_MUL_HI:[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI: v_or_b32_sdwa v{{[0-9]+}}, v[[DST_MUL_LO]], v[[DST_MUL_HI]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI: v_or_b32_sdwa v{{[0-9]+}}, v[[DST_MUL_LO]], v[[DST_MUL_HI]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
▲ Show 20 Lines • Show All 484 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/select.f16.ll

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; VI-LABEL: select_f16: ; VI-LABEL: select_f16:
; VI: ; %bb.0: ; %entry ; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x44 ; VI-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x44
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_mov_b32 s18, s2 ; VI-NEXT: s_mov_b32 s18, s2
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: s_mov_b32 s16, s6
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s17, s7
; VI-NEXT: s_mov_b32 s4, s6 ; VI-NEXT: s_mov_b32 s19, s3
; VI-NEXT: s_mov_b32 s5, s7 ; VI-NEXT: s_mov_b32 s20, s8
; VI-NEXT: s_mov_b32 s6, s2 ; VI-NEXT: s_mov_b32 s21, s9
; VI-NEXT: s_mov_b32 s7, s3
; VI-NEXT: s_mov_b32 s16, s8
; VI-NEXT: s_mov_b32 s17, s9
; VI-NEXT: s_mov_b32 s8, s10 ; VI-NEXT: s_mov_b32 s8, s10
; VI-NEXT: s_mov_b32 s9, s11 ; VI-NEXT: s_mov_b32 s9, s11
; VI-NEXT: s_mov_b32 s19, s3 ; VI-NEXT: s_mov_b32 s22, s2
; VI-NEXT: s_mov_b32 s23, s3
; VI-NEXT: s_mov_b32 s10, s2 ; VI-NEXT: s_mov_b32 s10, s2
; VI-NEXT: s_mov_b32 s11, s3 ; VI-NEXT: s_mov_b32 s11, s3
; VI-NEXT: s_mov_b32 s14, s2 ; VI-NEXT: s_mov_b32 s14, s2
; VI-NEXT: s_mov_b32 s15, s3 ; VI-NEXT: s_mov_b32 s15, s3
; VI-NEXT: buffer_load_ushort v0, off, s[4:7], 0 ; VI-NEXT: buffer_load_ushort v0, off, s[16:19], 0
; VI-NEXT: buffer_load_ushort v1, off, s[16:19], 0 ; VI-NEXT: buffer_load_ushort v1, off, s[20:23], 0
; VI-NEXT: buffer_load_ushort v2, off, s[8:11], 0 ; VI-NEXT: buffer_load_ushort v2, off, s[8:11], 0
; VI-NEXT: buffer_load_ushort v3, off, s[12:15], 0 ; VI-NEXT: buffer_load_ushort v3, off, s[12:15], 0
; VI-NEXT: s_mov_b32 s0, s4
; VI-NEXT: s_mov_b32 s1, s5
; VI-NEXT: s_waitcnt vmcnt(2) ; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_cmp_lt_f16_e32 vcc, v0, v1 ; VI-NEXT: v_cmp_lt_f16_e32 vcc, v0, v1
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; VI-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
half addrspace(1)* %r, half addrspace(1)* %r,
half addrspace(1)* %a, half addrspace(1)* %a,
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; VI-LABEL: select_f16_imm_a: ; VI-LABEL: select_f16_imm_a:
; VI: ; %bb.0: ; %entry ; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; VI-NEXT: s_mov_b32 s11, 0xf000 ; VI-NEXT: s_mov_b32 s11, 0xf000
; VI-NEXT: s_mov_b32 s10, -1 ; VI-NEXT: s_mov_b32 s10, -1
; VI-NEXT: s_mov_b32 s14, s10 ; VI-NEXT: s_mov_b32 s14, s10
; VI-NEXT: s_mov_b32 s15, s11 ; VI-NEXT: s_mov_b32 s15, s11
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s8, s0 ; VI-NEXT: s_mov_b32 s12, s2
; VI-NEXT: s_mov_b32 s9, s1 ; VI-NEXT: s_mov_b32 s13, s3
; VI-NEXT: s_mov_b32 s0, s2 ; VI-NEXT: s_mov_b32 s16, s4
; VI-NEXT: s_mov_b32 s1, s3 ; VI-NEXT: s_mov_b32 s17, s5
; VI-NEXT: s_mov_b32 s2, s10
; VI-NEXT: s_mov_b32 s3, s11
; VI-NEXT: s_mov_b32 s12, s4
; VI-NEXT: s_mov_b32 s13, s5
; VI-NEXT: s_mov_b32 s4, s6 ; VI-NEXT: s_mov_b32 s4, s6
; VI-NEXT: s_mov_b32 s5, s7 ; VI-NEXT: s_mov_b32 s5, s7
; VI-NEXT: s_mov_b32 s18, s10
; VI-NEXT: s_mov_b32 s19, s11
; VI-NEXT: s_mov_b32 s6, s10 ; VI-NEXT: s_mov_b32 s6, s10
; VI-NEXT: s_mov_b32 s7, s11 ; VI-NEXT: s_mov_b32 s7, s11
; VI-NEXT: buffer_load_ushort v0, off, s[0:3], 0 ; VI-NEXT: buffer_load_ushort v0, off, s[12:15], 0
; VI-NEXT: buffer_load_ushort v1, off, s[12:15], 0 ; VI-NEXT: buffer_load_ushort v1, off, s[16:19], 0
; VI-NEXT: buffer_load_ushort v2, off, s[4:7], 0 ; VI-NEXT: buffer_load_ushort v2, off, s[4:7], 0
; VI-NEXT: s_mov_b32 s8, s0
; VI-NEXT: s_mov_b32 s9, s1
; VI-NEXT: s_waitcnt vmcnt(2) ; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_cmp_lt_f16_e32 vcc, 0.5, v0 ; VI-NEXT: v_cmp_lt_f16_e32 vcc, 0.5, v0
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc ; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; VI-NEXT: buffer_store_short v0, off, s[8:11], 0 ; VI-NEXT: buffer_store_short v0, off, s[8:11], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
half addrspace(1)* %r, half addrspace(1)* %r,
half addrspace(1)* %b, half addrspace(1)* %b,
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; VI-LABEL: select_f16_imm_b: ; VI-LABEL: select_f16_imm_b:
; VI: ; %bb.0: ; %entry ; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; VI-NEXT: s_mov_b32 s11, 0xf000 ; VI-NEXT: s_mov_b32 s11, 0xf000
; VI-NEXT: s_mov_b32 s10, -1 ; VI-NEXT: s_mov_b32 s10, -1
; VI-NEXT: s_mov_b32 s14, s10 ; VI-NEXT: s_mov_b32 s14, s10
; VI-NEXT: s_mov_b32 s15, s11 ; VI-NEXT: s_mov_b32 s15, s11
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s8, s0 ; VI-NEXT: s_mov_b32 s12, s2
; VI-NEXT: s_mov_b32 s9, s1 ; VI-NEXT: s_mov_b32 s13, s3
; VI-NEXT: s_mov_b32 s0, s2 ; VI-NEXT: s_mov_b32 s16, s4
; VI-NEXT: s_mov_b32 s1, s3 ; VI-NEXT: s_mov_b32 s17, s5
; VI-NEXT: s_mov_b32 s2, s10
; VI-NEXT: s_mov_b32 s3, s11
; VI-NEXT: s_mov_b32 s12, s4
; VI-NEXT: s_mov_b32 s13, s5
; VI-NEXT: s_mov_b32 s4, s6 ; VI-NEXT: s_mov_b32 s4, s6
; VI-NEXT: s_mov_b32 s5, s7 ; VI-NEXT: s_mov_b32 s5, s7
; VI-NEXT: s_mov_b32 s18, s10
; VI-NEXT: s_mov_b32 s19, s11
; VI-NEXT: s_mov_b32 s6, s10 ; VI-NEXT: s_mov_b32 s6, s10
; VI-NEXT: s_mov_b32 s7, s11 ; VI-NEXT: s_mov_b32 s7, s11
; VI-NEXT: buffer_load_ushort v0, off, s[0:3], 0 ; VI-NEXT: buffer_load_ushort v0, off, s[12:15], 0
; VI-NEXT: buffer_load_ushort v1, off, s[12:15], 0 ; VI-NEXT: buffer_load_ushort v1, off, s[16:19], 0
; VI-NEXT: buffer_load_ushort v2, off, s[4:7], 0 ; VI-NEXT: buffer_load_ushort v2, off, s[4:7], 0
; VI-NEXT: s_mov_b32 s8, s0
; VI-NEXT: s_mov_b32 s9, s1
; VI-NEXT: s_waitcnt vmcnt(2) ; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_cmp_gt_f16_e32 vcc, 0.5, v0 ; VI-NEXT: v_cmp_gt_f16_e32 vcc, 0.5, v0
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc ; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; VI-NEXT: buffer_store_short v0, off, s[8:11], 0 ; VI-NEXT: buffer_store_short v0, off, s[8:11], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
half addrspace(1)* %r, half addrspace(1)* %r,
half addrspace(1)* %a, half addrspace(1)* %a,
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; VI-LABEL: select_f16_imm_c: ; VI-LABEL: select_f16_imm_c:
; VI: ; %bb.0: ; %entry ; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; VI-NEXT: s_mov_b32 s11, 0xf000 ; VI-NEXT: s_mov_b32 s11, 0xf000
; VI-NEXT: s_mov_b32 s10, -1 ; VI-NEXT: s_mov_b32 s10, -1
; VI-NEXT: s_mov_b32 s14, s10 ; VI-NEXT: s_mov_b32 s14, s10
; VI-NEXT: s_mov_b32 s15, s11 ; VI-NEXT: s_mov_b32 s15, s11
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s8, s0 ; VI-NEXT: s_mov_b32 s12, s2
; VI-NEXT: s_mov_b32 s9, s1 ; VI-NEXT: s_mov_b32 s13, s3
; VI-NEXT: s_mov_b32 s0, s2 ; VI-NEXT: s_mov_b32 s16, s4
; VI-NEXT: s_mov_b32 s1, s3 ; VI-NEXT: s_mov_b32 s17, s5
; VI-NEXT: s_mov_b32 s2, s10
; VI-NEXT: s_mov_b32 s3, s11
; VI-NEXT: s_mov_b32 s12, s4
; VI-NEXT: s_mov_b32 s13, s5
; VI-NEXT: buffer_load_ushort v0, off, s[0:3], 0
; VI-NEXT: buffer_load_ushort v1, off, s[12:15], 0
; VI-NEXT: s_mov_b32 s4, s6 ; VI-NEXT: s_mov_b32 s4, s6
; VI-NEXT: s_mov_b32 s5, s7 ; VI-NEXT: s_mov_b32 s5, s7
; VI-NEXT: s_mov_b32 s18, s10
; VI-NEXT: s_mov_b32 s19, s11
; VI-NEXT: s_mov_b32 s6, s10 ; VI-NEXT: s_mov_b32 s6, s10
; VI-NEXT: s_mov_b32 s7, s11 ; VI-NEXT: s_mov_b32 s7, s11
; VI-NEXT: buffer_load_ushort v3, off, s[4:7], 0 ; VI-NEXT: buffer_load_ushort v0, off, s[12:15], 0
; VI-NEXT: v_mov_b32_e32 v2, 0x3800 ; VI-NEXT: buffer_load_ushort v1, off, s[16:19], 0
; VI-NEXT: buffer_load_ushort v2, off, s[4:7], 0
; VI-NEXT: v_mov_b32_e32 v3, 0x3800
; VI-NEXT: s_mov_b32 s8, s0
; VI-NEXT: s_mov_b32 s9, s1
; VI-NEXT: s_waitcnt vmcnt(1) ; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_cmp_nlt_f16_e32 vcc, v0, v1 ; VI-NEXT: v_cmp_nlt_f16_e32 vcc, v0, v1
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc ; VI-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
; VI-NEXT: buffer_store_short v0, off, s[8:11], 0 ; VI-NEXT: buffer_store_short v0, off, s[8:11], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
half addrspace(1)* %r, half addrspace(1)* %r,
half addrspace(1)* %a, half addrspace(1)* %a,
half addrspace(1)* %b, half addrspace(1)* %b,
half addrspace(1)* %d) { half addrspace(1)* %d) {
entry: entry:
%a.val = load volatile half, half addrspace(1)* %a %a.val = load volatile half, half addrspace(1)* %a
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; VI-LABEL: select_f16_imm_d: ; VI-LABEL: select_f16_imm_d:
; VI: ; %bb.0: ; %entry ; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; VI-NEXT: s_mov_b32 s11, 0xf000 ; VI-NEXT: s_mov_b32 s11, 0xf000
; VI-NEXT: s_mov_b32 s10, -1 ; VI-NEXT: s_mov_b32 s10, -1
; VI-NEXT: s_mov_b32 s14, s10 ; VI-NEXT: s_mov_b32 s14, s10
; VI-NEXT: s_mov_b32 s15, s11 ; VI-NEXT: s_mov_b32 s15, s11
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s8, s0 ; VI-NEXT: s_mov_b32 s12, s2
; VI-NEXT: s_mov_b32 s9, s1 ; VI-NEXT: s_mov_b32 s13, s3
; VI-NEXT: s_mov_b32 s0, s2 ; VI-NEXT: s_mov_b32 s16, s4
; VI-NEXT: s_mov_b32 s1, s3 ; VI-NEXT: s_mov_b32 s17, s5
; VI-NEXT: s_mov_b32 s2, s10
; VI-NEXT: s_mov_b32 s3, s11
; VI-NEXT: s_mov_b32 s12, s4
; VI-NEXT: s_mov_b32 s13, s5
; VI-NEXT: buffer_load_ushort v0, off, s[0:3], 0
; VI-NEXT: buffer_load_ushort v1, off, s[12:15], 0
; VI-NEXT: s_mov_b32 s4, s6 ; VI-NEXT: s_mov_b32 s4, s6
; VI-NEXT: s_mov_b32 s5, s7 ; VI-NEXT: s_mov_b32 s5, s7
; VI-NEXT: s_mov_b32 s18, s10
; VI-NEXT: s_mov_b32 s19, s11
; VI-NEXT: s_mov_b32 s6, s10 ; VI-NEXT: s_mov_b32 s6, s10
; VI-NEXT: s_mov_b32 s7, s11 ; VI-NEXT: s_mov_b32 s7, s11
; VI-NEXT: buffer_load_ushort v3, off, s[4:7], 0 ; VI-NEXT: buffer_load_ushort v0, off, s[12:15], 0
; VI-NEXT: v_mov_b32_e32 v2, 0x3800 ; VI-NEXT: buffer_load_ushort v1, off, s[16:19], 0
; VI-NEXT: buffer_load_ushort v2, off, s[4:7], 0
; VI-NEXT: v_mov_b32_e32 v3, 0x3800
; VI-NEXT: s_mov_b32 s8, s0
; VI-NEXT: s_mov_b32 s9, s1
; VI-NEXT: s_waitcnt vmcnt(1) ; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_cmp_lt_f16_e32 vcc, v0, v1 ; VI-NEXT: v_cmp_lt_f16_e32 vcc, v0, v1
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc ; VI-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
; VI-NEXT: buffer_store_short v0, off, s[8:11], 0 ; VI-NEXT: buffer_store_short v0, off, s[8:11], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
half addrspace(1)* %r, half addrspace(1)* %r,
half addrspace(1)* %a, half addrspace(1)* %a,
half addrspace(1)* %b, half addrspace(1)* %b,
half addrspace(1)* %c) { half addrspace(1)* %c) {
entry: entry:
%a.val = load volatile half, half addrspace(1)* %a %a.val = load volatile half, half addrspace(1)* %a
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; VI-LABEL: select_v2f16: ; VI-LABEL: select_v2f16:
; VI: ; %bb.0: ; %entry ; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x44 ; VI-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x44
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_mov_b32 s18, s2 ; VI-NEXT: s_mov_b32 s18, s2
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: s_mov_b32 s16, s6
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s17, s7
; VI-NEXT: s_mov_b32 s4, s6 ; VI-NEXT: s_mov_b32 s19, s3
; VI-NEXT: s_mov_b32 s5, s7 ; VI-NEXT: s_mov_b32 s20, s8
; VI-NEXT: s_mov_b32 s6, s2 ; VI-NEXT: s_mov_b32 s21, s9
; VI-NEXT: s_mov_b32 s7, s3
; VI-NEXT: s_mov_b32 s16, s8
; VI-NEXT: s_mov_b32 s17, s9
; VI-NEXT: s_mov_b32 s8, s10 ; VI-NEXT: s_mov_b32 s8, s10
; VI-NEXT: s_mov_b32 s9, s11 ; VI-NEXT: s_mov_b32 s9, s11
; VI-NEXT: s_mov_b32 s19, s3 ; VI-NEXT: s_mov_b32 s22, s2
; VI-NEXT: s_mov_b32 s23, s3
; VI-NEXT: s_mov_b32 s10, s2 ; VI-NEXT: s_mov_b32 s10, s2
; VI-NEXT: s_mov_b32 s11, s3 ; VI-NEXT: s_mov_b32 s11, s3
; VI-NEXT: s_mov_b32 s14, s2 ; VI-NEXT: s_mov_b32 s14, s2
; VI-NEXT: s_mov_b32 s15, s3 ; VI-NEXT: s_mov_b32 s15, s3
; VI-NEXT: buffer_load_dword v0, off, s[4:7], 0 ; VI-NEXT: buffer_load_dword v0, off, s[16:19], 0
; VI-NEXT: buffer_load_dword v1, off, s[16:19], 0 ; VI-NEXT: buffer_load_dword v1, off, s[20:23], 0
; VI-NEXT: buffer_load_dword v2, off, s[12:15], 0 ; VI-NEXT: buffer_load_dword v2, off, s[12:15], 0
; VI-NEXT: buffer_load_dword v3, off, s[8:11], 0 ; VI-NEXT: buffer_load_dword v3, off, s[8:11], 0
; VI-NEXT: s_mov_b32 s0, s4
; VI-NEXT: s_mov_b32 s1, s5
; VI-NEXT: s_waitcnt vmcnt(3) ; VI-NEXT: s_waitcnt vmcnt(3)
; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v0 ; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v0
; VI-NEXT: s_waitcnt vmcnt(2) ; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_cmp_lt_f16_e32 vcc, v0, v1 ; VI-NEXT: v_cmp_lt_f16_e32 vcc, v0, v1
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v1 ; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc ; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v2 ; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v2
Show All 25 Lines
; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s11, 0xf000 ; SI-NEXT: s_mov_b32 s11, 0xf000
; SI-NEXT: s_mov_b32 s10, -1 ; SI-NEXT: s_mov_b32 s10, -1
; SI-NEXT: s_mov_b32 s14, s10 ; SI-NEXT: s_mov_b32 s14, s10
; SI-NEXT: s_mov_b32 s15, s11 ; SI-NEXT: s_mov_b32 s15, s11
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s12, s2 ; SI-NEXT: s_mov_b32 s12, s2
; SI-NEXT: s_mov_b32 s13, s3
; SI-NEXT: s_mov_b32 s16, s4 ; SI-NEXT: s_mov_b32 s16, s4
; SI-NEXT: s_mov_b32 s17, s5 ; SI-NEXT: s_mov_b32 s17, s5
; SI-NEXT: s_mov_b32 s4, s6 ; SI-NEXT: s_mov_b32 s4, s6
; SI-NEXT: s_mov_b32 s5, s7 ; SI-NEXT: s_mov_b32 s5, s7
; SI-NEXT: s_mov_b32 s13, s3
; SI-NEXT: s_mov_b32 s6, s10
; SI-NEXT: s_mov_b32 s7, s11
; SI-NEXT: s_mov_b32 s18, s10 ; SI-NEXT: s_mov_b32 s18, s10
; SI-NEXT: s_mov_b32 s19, s11 ; SI-NEXT: s_mov_b32 s19, s11
; SI-NEXT: s_mov_b32 s6, s10
; SI-NEXT: s_mov_b32 s7, s11
; SI-NEXT: buffer_load_dword v0, off, s[12:15], 0 ; SI-NEXT: buffer_load_dword v0, off, s[12:15], 0
; SI-NEXT: buffer_load_dword v1, off, s[16:19], 0 ; SI-NEXT: buffer_load_dword v1, off, s[16:19], 0
; SI-NEXT: buffer_load_dword v2, off, s[4:7], 0 ; SI-NEXT: buffer_load_dword v2, off, s[4:7], 0
; SI-NEXT: s_mov_b32 s2, 0x3f200000 ; SI-NEXT: s_mov_b32 s2, 0x3f200000
; SI-NEXT: s_mov_b32 s8, s0 ; SI-NEXT: s_mov_b32 s8, s0
; SI-NEXT: s_mov_b32 s9, s1 ; SI-NEXT: s_mov_b32 s9, s1
; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v0 ; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
Show All 21 Lines
; VI-LABEL: select_v2f16_imm_a: ; VI-LABEL: select_v2f16_imm_a:
; VI: ; %bb.0: ; %entry ; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; VI-NEXT: s_mov_b32 s11, 0xf000 ; VI-NEXT: s_mov_b32 s11, 0xf000
; VI-NEXT: s_mov_b32 s10, -1 ; VI-NEXT: s_mov_b32 s10, -1
; VI-NEXT: s_mov_b32 s14, s10 ; VI-NEXT: s_mov_b32 s14, s10
; VI-NEXT: s_mov_b32 s15, s11 ; VI-NEXT: s_mov_b32 s15, s11
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s8, s0 ; VI-NEXT: s_mov_b32 s12, s2
; VI-NEXT: s_mov_b32 s9, s1 ; VI-NEXT: s_mov_b32 s13, s3
; VI-NEXT: s_mov_b32 s0, s2 ; VI-NEXT: s_mov_b32 s16, s4
; VI-NEXT: s_mov_b32 s1, s3 ; VI-NEXT: s_mov_b32 s17, s5
; VI-NEXT: s_mov_b32 s12, s4
; VI-NEXT: s_mov_b32 s13, s5
; VI-NEXT: s_mov_b32 s4, s6 ; VI-NEXT: s_mov_b32 s4, s6
; VI-NEXT: s_mov_b32 s5, s7 ; VI-NEXT: s_mov_b32 s5, s7
; VI-NEXT: s_mov_b32 s2, s10 ; VI-NEXT: s_mov_b32 s18, s10
; VI-NEXT: s_mov_b32 s3, s11 ; VI-NEXT: s_mov_b32 s19, s11
; VI-NEXT: s_mov_b32 s6, s10 ; VI-NEXT: s_mov_b32 s6, s10
; VI-NEXT: s_mov_b32 s7, s11 ; VI-NEXT: s_mov_b32 s7, s11
; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_load_dword v0, off, s[12:15], 0
; VI-NEXT: buffer_load_dword v1, off, s[12:15], 0 ; VI-NEXT: buffer_load_dword v1, off, s[16:19], 0
; VI-NEXT: buffer_load_dword v2, off, s[4:7], 0 ; VI-NEXT: buffer_load_dword v2, off, s[4:7], 0
; VI-NEXT: s_movk_i32 s0, 0x3900 ; VI-NEXT: s_movk_i32 s2, 0x3900
; VI-NEXT: s_mov_b32 s8, s0
; VI-NEXT: s_mov_b32 s9, s1
; VI-NEXT: s_waitcnt vmcnt(2) ; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v0 ; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; VI-NEXT: v_cmp_lt_f16_e32 vcc, 0.5, v0 ; VI-NEXT: v_cmp_lt_f16_e32 vcc, 0.5, v0
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc ; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 ; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 ; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; VI-NEXT: v_cmp_lt_f16_e32 vcc, s0, v3 ; VI-NEXT: v_cmp_lt_f16_e32 vcc, s2, v3
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; VI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0 ; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
<2 x half> addrspace(1)* %r, <2 x half> addrspace(1)* %r,
<2 x half> addrspace(1)* %b, <2 x half> addrspace(1)* %b,
<2 x half> addrspace(1)* %c, <2 x half> addrspace(1)* %c,
Show All 13 Lines
; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s11, 0xf000 ; SI-NEXT: s_mov_b32 s11, 0xf000
; SI-NEXT: s_mov_b32 s10, -1 ; SI-NEXT: s_mov_b32 s10, -1
; SI-NEXT: s_mov_b32 s14, s10 ; SI-NEXT: s_mov_b32 s14, s10
; SI-NEXT: s_mov_b32 s15, s11 ; SI-NEXT: s_mov_b32 s15, s11
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s12, s2 ; SI-NEXT: s_mov_b32 s12, s2
; SI-NEXT: s_mov_b32 s13, s3
; SI-NEXT: s_mov_b32 s16, s4 ; SI-NEXT: s_mov_b32 s16, s4
; SI-NEXT: s_mov_b32 s17, s5 ; SI-NEXT: s_mov_b32 s17, s5
; SI-NEXT: s_mov_b32 s4, s6 ; SI-NEXT: s_mov_b32 s4, s6
; SI-NEXT: s_mov_b32 s5, s7 ; SI-NEXT: s_mov_b32 s5, s7
; SI-NEXT: s_mov_b32 s13, s3
; SI-NEXT: s_mov_b32 s6, s10
; SI-NEXT: s_mov_b32 s7, s11
; SI-NEXT: s_mov_b32 s18, s10 ; SI-NEXT: s_mov_b32 s18, s10
; SI-NEXT: s_mov_b32 s19, s11 ; SI-NEXT: s_mov_b32 s19, s11
; SI-NEXT: s_mov_b32 s6, s10
; SI-NEXT: s_mov_b32 s7, s11
; SI-NEXT: buffer_load_dword v0, off, s[12:15], 0 ; SI-NEXT: buffer_load_dword v0, off, s[12:15], 0
; SI-NEXT: buffer_load_dword v1, off, s[16:19], 0 ; SI-NEXT: buffer_load_dword v1, off, s[16:19], 0
; SI-NEXT: buffer_load_dword v2, off, s[4:7], 0 ; SI-NEXT: buffer_load_dword v2, off, s[4:7], 0
; SI-NEXT: s_mov_b32 s2, 0x3f200000 ; SI-NEXT: s_mov_b32 s2, 0x3f200000
; SI-NEXT: s_mov_b32 s8, s0 ; SI-NEXT: s_mov_b32 s8, s0
; SI-NEXT: s_mov_b32 s9, s1 ; SI-NEXT: s_mov_b32 s9, s1
; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v0 ; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
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; VI-LABEL: select_v2f16_imm_b: ; VI-LABEL: select_v2f16_imm_b:
; VI: ; %bb.0: ; %entry ; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; VI-NEXT: s_mov_b32 s11, 0xf000 ; VI-NEXT: s_mov_b32 s11, 0xf000
; VI-NEXT: s_mov_b32 s10, -1 ; VI-NEXT: s_mov_b32 s10, -1
; VI-NEXT: s_mov_b32 s14, s10 ; VI-NEXT: s_mov_b32 s14, s10
; VI-NEXT: s_mov_b32 s15, s11 ; VI-NEXT: s_mov_b32 s15, s11
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s8, s0 ; VI-NEXT: s_mov_b32 s12, s2
; VI-NEXT: s_mov_b32 s9, s1 ; VI-NEXT: s_mov_b32 s13, s3
; VI-NEXT: s_mov_b32 s0, s2 ; VI-NEXT: s_mov_b32 s16, s4
; VI-NEXT: s_mov_b32 s1, s3 ; VI-NEXT: s_mov_b32 s17, s5
; VI-NEXT: s_mov_b32 s12, s4
; VI-NEXT: s_mov_b32 s13, s5
; VI-NEXT: s_mov_b32 s4, s6 ; VI-NEXT: s_mov_b32 s4, s6
; VI-NEXT: s_mov_b32 s5, s7 ; VI-NEXT: s_mov_b32 s5, s7
; VI-NEXT: s_mov_b32 s2, s10 ; VI-NEXT: s_mov_b32 s18, s10
; VI-NEXT: s_mov_b32 s3, s11 ; VI-NEXT: s_mov_b32 s19, s11
; VI-NEXT: s_mov_b32 s6, s10 ; VI-NEXT: s_mov_b32 s6, s10
; VI-NEXT: s_mov_b32 s7, s11 ; VI-NEXT: s_mov_b32 s7, s11
; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_load_dword v0, off, s[12:15], 0
; VI-NEXT: buffer_load_dword v1, off, s[12:15], 0 ; VI-NEXT: buffer_load_dword v1, off, s[16:19], 0
; VI-NEXT: buffer_load_dword v2, off, s[4:7], 0 ; VI-NEXT: buffer_load_dword v2, off, s[4:7], 0
; VI-NEXT: s_movk_i32 s0, 0x3900 ; VI-NEXT: s_movk_i32 s2, 0x3900
; VI-NEXT: s_mov_b32 s8, s0
; VI-NEXT: s_mov_b32 s9, s1
; VI-NEXT: s_waitcnt vmcnt(2) ; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v0 ; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; VI-NEXT: v_cmp_gt_f16_e32 vcc, 0.5, v0 ; VI-NEXT: v_cmp_gt_f16_e32 vcc, 0.5, v0
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc ; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 ; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 ; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; VI-NEXT: v_cmp_gt_f16_e32 vcc, s0, v3 ; VI-NEXT: v_cmp_gt_f16_e32 vcc, s2, v3
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; VI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0 ; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
<2 x half> addrspace(1)* %r, <2 x half> addrspace(1)* %r,
<2 x half> addrspace(1)* %a, <2 x half> addrspace(1)* %a,
<2 x half> addrspace(1)* %c, <2 x half> addrspace(1)* %c,
Show All 12 Lines
; SI-LABEL: select_v2f16_imm_c: ; SI-LABEL: select_v2f16_imm_c:
; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s11, 0xf000 ; SI-NEXT: s_mov_b32 s11, 0xf000
; SI-NEXT: s_mov_b32 s10, -1 ; SI-NEXT: s_mov_b32 s10, -1
; SI-NEXT: s_mov_b32 s14, s10 ; SI-NEXT: s_mov_b32 s14, s10
; SI-NEXT: s_mov_b32 s15, s11 ; SI-NEXT: s_mov_b32 s15, s11
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s16, s4
; SI-NEXT: s_mov_b32 s17, s5
; SI-NEXT: s_mov_b32 s12, s2 ; SI-NEXT: s_mov_b32 s12, s2
; SI-NEXT: s_mov_b32 s13, s3 ; SI-NEXT: s_mov_b32 s13, s3
; SI-NEXT: s_mov_b32 s18, s10 ; SI-NEXT: s_mov_b32 s16, s4
; SI-NEXT: s_mov_b32 s19, s11 ; SI-NEXT: s_mov_b32 s17, s5
; SI-NEXT: s_mov_b32 s4, s6 ; SI-NEXT: s_mov_b32 s4, s6
; SI-NEXT: s_mov_b32 s5, s7 ; SI-NEXT: s_mov_b32 s5, s7
; SI-NEXT: s_mov_b32 s18, s10
; SI-NEXT: s_mov_b32 s19, s11
; SI-NEXT: s_mov_b32 s6, s10 ; SI-NEXT: s_mov_b32 s6, s10
; SI-NEXT: s_mov_b32 s7, s11 ; SI-NEXT: s_mov_b32 s7, s11
; SI-NEXT: buffer_load_dword v0, off, s[12:15], 0 ; SI-NEXT: buffer_load_dword v0, off, s[12:15], 0
; SI-NEXT: buffer_load_dword v1, off, s[4:7], 0 ; SI-NEXT: buffer_load_dword v1, off, s[16:19], 0
; SI-NEXT: buffer_load_dword v3, off, s[16:19], 0 ; SI-NEXT: buffer_load_dword v2, off, s[4:7], 0
; SI-NEXT: v_mov_b32_e32 v2, 0x3f200000 ; SI-NEXT: v_mov_b32_e32 v3, 0x3f200000
; SI-NEXT: s_mov_b32 s8, s0 ; SI-NEXT: s_mov_b32 s8, s0
; SI-NEXT: s_mov_b32 s9, s1 ; SI-NEXT: s_mov_b32 s9, s1
; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_cvt_f32_f16_e32 v4, v0 ; SI-NEXT: v_cvt_f32_f16_e32 v4, v0
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v1
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v3 ; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0 ; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-NEXT: v_cvt_f32_f16_e32 v5, v5 ; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
; SI-NEXT: v_cvt_f32_f16_e32 v6, v6 ; SI-NEXT: v_cvt_f32_f16_e32 v6, v6
; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1 ; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
; SI-NEXT: v_cmp_nlt_f32_e32 vcc, v0, v5 ; SI-NEXT: v_cmp_nlt_f32_e32 vcc, v0, v5
; SI-NEXT: v_cndmask_b32_e32 v0, v2, v6, vcc ; SI-NEXT: v_cndmask_b32_e32 v0, v3, v6, vcc
; SI-NEXT: v_cmp_nlt_f32_e32 vcc, v4, v3 ; SI-NEXT: v_cmp_nlt_f32_e32 vcc, v4, v1
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0 ; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: v_cndmask_b32_e32 v1, 0.5, v1, vcc ; SI-NEXT: v_cndmask_b32_e32 v1, 0.5, v2, vcc
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 ; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_or_b32_e32 v0, v1, v0 ; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0 ; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: select_v2f16_imm_c: ; VI-LABEL: select_v2f16_imm_c:
; VI: ; %bb.0: ; %entry ; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; VI-NEXT: s_mov_b32 s11, 0xf000 ; VI-NEXT: s_mov_b32 s11, 0xf000
; VI-NEXT: s_mov_b32 s10, -1 ; VI-NEXT: s_mov_b32 s10, -1
; VI-NEXT: s_mov_b32 s14, s10 ; VI-NEXT: s_mov_b32 s14, s10
; VI-NEXT: s_mov_b32 s15, s11 ; VI-NEXT: s_mov_b32 s15, s11
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s8, s0 ; VI-NEXT: s_mov_b32 s12, s2
; VI-NEXT: s_mov_b32 s9, s1 ; VI-NEXT: s_mov_b32 s13, s3
; VI-NEXT: s_mov_b32 s0, s2 ; VI-NEXT: s_mov_b32 s16, s4
; VI-NEXT: s_mov_b32 s1, s3 ; VI-NEXT: s_mov_b32 s17, s5
; VI-NEXT: s_mov_b32 s12, s4
; VI-NEXT: s_mov_b32 s13, s5
; VI-NEXT: s_mov_b32 s2, s10
; VI-NEXT: s_mov_b32 s3, s11
; VI-NEXT: s_mov_b32 s4, s6 ; VI-NEXT: s_mov_b32 s4, s6
; VI-NEXT: s_mov_b32 s5, s7 ; VI-NEXT: s_mov_b32 s5, s7
; VI-NEXT: s_mov_b32 s18, s10
; VI-NEXT: s_mov_b32 s19, s11
; VI-NEXT: s_mov_b32 s6, s10 ; VI-NEXT: s_mov_b32 s6, s10
; VI-NEXT: s_mov_b32 s7, s11 ; VI-NEXT: s_mov_b32 s7, s11
; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_load_dword v0, off, s[12:15], 0
; VI-NEXT: buffer_load_dword v1, off, s[4:7], 0 ; VI-NEXT: buffer_load_dword v1, off, s[16:19], 0
; VI-NEXT: buffer_load_dword v4, off, s[12:15], 0 ; VI-NEXT: buffer_load_dword v2, off, s[4:7], 0
; VI-NEXT: v_mov_b32_e32 v2, 0x3800 ; VI-NEXT: v_mov_b32_e32 v3, 0x3800
; VI-NEXT: v_mov_b32_e32 v3, 0x3900 ; VI-NEXT: v_mov_b32_e32 v4, 0x3900
; VI-NEXT: s_mov_b32 s8, s0
; VI-NEXT: s_mov_b32 s9, s1
; VI-NEXT: s_waitcnt vmcnt(2) ; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v0 ; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v0
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_cmp_nlt_f16_e32 vcc, v0, v1
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cmp_nlt_f16_e32 vcc, v0, v4 ; VI-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v4 ; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: v_cmp_nlt_f16_e32 vcc, v6, v5 ; VI-NEXT: v_cmp_nlt_f16_e32 vcc, v6, v5
; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc ; VI-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0 ; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
<2 x half> addrspace(1)* %r, <2 x half> addrspace(1)* %r,
<2 x half> addrspace(1)* %a, <2 x half> addrspace(1)* %a,
<2 x half> addrspace(1)* %b, <2 x half> addrspace(1)* %b,
<2 x half> addrspace(1)* %d) { <2 x half> addrspace(1)* %d) {
Show All 11 Lines
; SI-LABEL: select_v2f16_imm_d: ; SI-LABEL: select_v2f16_imm_d:
; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s11, 0xf000 ; SI-NEXT: s_mov_b32 s11, 0xf000
; SI-NEXT: s_mov_b32 s10, -1 ; SI-NEXT: s_mov_b32 s10, -1
; SI-NEXT: s_mov_b32 s14, s10 ; SI-NEXT: s_mov_b32 s14, s10
; SI-NEXT: s_mov_b32 s15, s11 ; SI-NEXT: s_mov_b32 s15, s11
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s16, s4
; SI-NEXT: s_mov_b32 s17, s5
; SI-NEXT: s_mov_b32 s12, s2 ; SI-NEXT: s_mov_b32 s12, s2
; SI-NEXT: s_mov_b32 s13, s3 ; SI-NEXT: s_mov_b32 s13, s3
; SI-NEXT: s_mov_b32 s18, s10 ; SI-NEXT: s_mov_b32 s16, s4
; SI-NEXT: s_mov_b32 s19, s11 ; SI-NEXT: s_mov_b32 s17, s5
; SI-NEXT: s_mov_b32 s4, s6 ; SI-NEXT: s_mov_b32 s4, s6
; SI-NEXT: s_mov_b32 s5, s7 ; SI-NEXT: s_mov_b32 s5, s7
; SI-NEXT: s_mov_b32 s18, s10
; SI-NEXT: s_mov_b32 s19, s11
; SI-NEXT: s_mov_b32 s6, s10 ; SI-NEXT: s_mov_b32 s6, s10
; SI-NEXT: s_mov_b32 s7, s11 ; SI-NEXT: s_mov_b32 s7, s11
; SI-NEXT: buffer_load_dword v0, off, s[12:15], 0 ; SI-NEXT: buffer_load_dword v0, off, s[12:15], 0
; SI-NEXT: buffer_load_dword v1, off, s[4:7], 0 ; SI-NEXT: buffer_load_dword v1, off, s[16:19], 0
; SI-NEXT: buffer_load_dword v3, off, s[16:19], 0 ; SI-NEXT: buffer_load_dword v2, off, s[4:7], 0
; SI-NEXT: v_mov_b32_e32 v2, 0x3f200000 ; SI-NEXT: v_mov_b32_e32 v3, 0x3f200000
; SI-NEXT: s_mov_b32 s8, s0 ; SI-NEXT: s_mov_b32 s8, s0
; SI-NEXT: s_mov_b32 s9, s1 ; SI-NEXT: s_mov_b32 s9, s1
; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v0 ; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v1 ; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v1
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v3 ; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; SI-NEXT: v_cvt_f32_f16_e32 v4, v4 ; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
; SI-NEXT: v_cvt_f32_f16_e32 v5, v5 ; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0 ; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-NEXT: v_cvt_f32_f16_e32 v6, v6 ; SI-NEXT: v_cvt_f32_f16_e32 v6, v6
; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1 ; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
; SI-NEXT: v_cmp_lt_f32_e32 vcc, v4, v5 ; SI-NEXT: v_cmp_lt_f32_e32 vcc, v4, v5
; SI-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc ; SI-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
; SI-NEXT: v_cmp_lt_f32_e32 vcc, v0, v3 ; SI-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; SI-NEXT: v_cndmask_b32_e32 v0, 0.5, v1, vcc ; SI-NEXT: v_cndmask_b32_e32 v0, 0.5, v2, vcc
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0 ; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v3
; SI-NEXT: v_or_b32_e32 v0, v0, v1 ; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0 ; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: select_v2f16_imm_d: ; VI-LABEL: select_v2f16_imm_d:
; VI: ; %bb.0: ; %entry ; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; VI-NEXT: s_mov_b32 s11, 0xf000 ; VI-NEXT: s_mov_b32 s11, 0xf000
; VI-NEXT: s_mov_b32 s10, -1 ; VI-NEXT: s_mov_b32 s10, -1
; VI-NEXT: s_mov_b32 s14, s10 ; VI-NEXT: s_mov_b32 s14, s10
; VI-NEXT: s_mov_b32 s15, s11 ; VI-NEXT: s_mov_b32 s15, s11
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s8, s0 ; VI-NEXT: s_mov_b32 s12, s2
; VI-NEXT: s_mov_b32 s9, s1 ; VI-NEXT: s_mov_b32 s13, s3
; VI-NEXT: s_mov_b32 s0, s2 ; VI-NEXT: s_mov_b32 s16, s4
; VI-NEXT: s_mov_b32 s1, s3 ; VI-NEXT: s_mov_b32 s17, s5
; VI-NEXT: s_mov_b32 s12, s4
; VI-NEXT: s_mov_b32 s13, s5
; VI-NEXT: s_mov_b32 s2, s10
; VI-NEXT: s_mov_b32 s3, s11
; VI-NEXT: s_mov_b32 s4, s6 ; VI-NEXT: s_mov_b32 s4, s6
; VI-NEXT: s_mov_b32 s5, s7 ; VI-NEXT: s_mov_b32 s5, s7
; VI-NEXT: s_mov_b32 s18, s10
; VI-NEXT: s_mov_b32 s19, s11
; VI-NEXT: s_mov_b32 s6, s10 ; VI-NEXT: s_mov_b32 s6, s10
; VI-NEXT: s_mov_b32 s7, s11 ; VI-NEXT: s_mov_b32 s7, s11
; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_load_dword v0, off, s[12:15], 0
; VI-NEXT: buffer_load_dword v1, off, s[4:7], 0 ; VI-NEXT: buffer_load_dword v1, off, s[16:19], 0
; VI-NEXT: buffer_load_dword v4, off, s[12:15], 0 ; VI-NEXT: buffer_load_dword v2, off, s[4:7], 0
; VI-NEXT: v_mov_b32_e32 v2, 0x3800 ; VI-NEXT: v_mov_b32_e32 v3, 0x3800
; VI-NEXT: v_mov_b32_e32 v3, 0x3900 ; VI-NEXT: v_mov_b32_e32 v4, 0x3900
; VI-NEXT: s_mov_b32 s8, s0
; VI-NEXT: s_mov_b32 s9, s1
; VI-NEXT: s_waitcnt vmcnt(2) ; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v0 ; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v0
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_cmp_lt_f16_e32 vcc, v0, v1
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cmp_lt_f16_e32 vcc, v0, v4 ; VI-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v4 ; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: v_cmp_lt_f16_e32 vcc, v6, v5 ; VI-NEXT: v_cmp_lt_f16_e32 vcc, v6, v5
; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc ; VI-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0 ; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
<2 x half> addrspace(1)* %r, <2 x half> addrspace(1)* %r,
<2 x half> addrspace(1)* %a, <2 x half> addrspace(1)* %a,
<2 x half> addrspace(1)* %b, <2 x half> addrspace(1)* %b,
<2 x half> addrspace(1)* %c) { <2 x half> addrspace(1)* %c) {
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llvm/test/CodeGen/AMDGPU/shift-i64-opts.ll

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @lshr_i64_32(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
store i64 %shl, i64 addrspace(1)* %out store i64 %shl, i64 addrspace(1)* %out
ret void ret void
} }
; Make sure the and of the constant doesn't prevent bfe from forming ; Make sure the and of the constant doesn't prevent bfe from forming
; after 64-bit shift is split. ; after 64-bit shift is split.
; GCN-LABEL: {{^}}lshr_and_i64_35: ; GCN-LABEL: {{^}}lshr_and_i64_35:
; GCN: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; GCN: buffer_load_dword v[[LO:[0-9]+]] ; GCN-DAG: buffer_load_dword v[[LO:[0-9]+]]
; GCN: v_bfe_u32 v[[BFE:[0-9]+]], v[[LO]], 8, 23 ; GCN: v_bfe_u32 v[[BFE:[0-9]+]], v[[LO]], 8, 23
; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}} ; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}}
define amdgpu_kernel void @lshr_and_i64_35(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { define amdgpu_kernel void @lshr_and_i64_35(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
%val = load i64, i64 addrspace(1)* %in %val = load i64, i64 addrspace(1)* %in
%and = and i64 %val, 9223372036854775807 ; 0x7fffffffffffffff %and = and i64 %val, 9223372036854775807 ; 0x7fffffffffffffff
%shl = lshr i64 %and, 40 %shl = lshr i64 %and, 40
store i64 %shl, i64 addrspace(1)* %out store i64 %shl, i64 addrspace(1)* %out
ret void ret void
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llvm/test/CodeGen/AMDGPU/shl.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn-- -mcpu=verde -verify-machineinstrs | FileCheck %s -allow-deprecated-dag-overlap -check-prefixes=FUNC,GCN,SI ; RUN: llc < %s -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn-- -mcpu=verde -verify-machineinstrs | FileCheck %s -allow-deprecated-dag-overlap -check-prefixes=FUNC,GCN,SI
; XUN: llc < %s -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s -check-prefixes=FUNC,GCN,VI ; XUN: llc < %s -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s -check-prefixes=FUNC,GCN,VI
; RUN: llc < %s -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600-- -mcpu=redwood -verify-machineinstrs | FileCheck %s -allow-deprecated-dag-overlap -check-prefixes=FUNC,EG ; RUN: llc < %s -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600-- -mcpu=redwood -verify-machineinstrs | FileCheck %s -allow-deprecated-dag-overlap -check-prefixes=FUNC,EG
declare i32 @llvm.amdgcn.workitem.id.x() #0 declare i32 @llvm.amdgcn.workitem.id.x() #0
declare i32 @llvm.amdgcn.workgroup.id.x() #0 declare i32 @llvm.amdgcn.workgroup.id.x() #0
define amdgpu_kernel void @shl_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { define amdgpu_kernel void @shl_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
; GCN-LABEL: shl_v2i32: ; GCN-LABEL: shl_v2i32:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_mov_b32 s10, s2
; GCN-NEXT: s_mov_b32 s11, s3
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s8, s6
; GCN-NEXT: s_mov_b32 s9, s7
; GCN-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
; GCN-NEXT: s_mov_b32 s0, s4 ; GCN-NEXT: s_mov_b32 s0, s4
; GCN-NEXT: s_mov_b32 s1, s5 ; GCN-NEXT: s_mov_b32 s1, s5
; GCN-NEXT: s_mov_b32 s4, s6
; GCN-NEXT: s_mov_b32 s5, s7
; GCN-NEXT: s_mov_b32 s6, s2
; GCN-NEXT: s_mov_b32 s7, s3
; GCN-NEXT: buffer_load_dwordx4 v[0:3], off, s[4:7], 0
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_lshl_b32_e32 v1, v1, v3 ; GCN-NEXT: v_lshl_b32_e32 v1, v1, v3
; GCN-NEXT: v_lshl_b32_e32 v0, v0, v2 ; GCN-NEXT: v_lshl_b32_e32 v0, v0, v2
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; EG-LABEL: shl_v2i32: ; EG-LABEL: shl_v2i32:
; EG: ; %bb.0: ; EG: ; %bb.0:
Show All 22 Lines
} }
define amdgpu_kernel void @shl_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { define amdgpu_kernel void @shl_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
; GCN-LABEL: shl_v4i32: ; GCN-LABEL: shl_v4i32:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_mov_b32 s10, s2
; GCN-NEXT: s_mov_b32 s11, s3
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s8, s6
; GCN-NEXT: s_mov_b32 s9, s7
; GCN-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
; GCN-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16
; GCN-NEXT: s_mov_b32 s0, s4 ; GCN-NEXT: s_mov_b32 s0, s4
; GCN-NEXT: s_mov_b32 s1, s5 ; GCN-NEXT: s_mov_b32 s1, s5
; GCN-NEXT: s_mov_b32 s4, s6
; GCN-NEXT: s_mov_b32 s5, s7
; GCN-NEXT: s_mov_b32 s6, s2
; GCN-NEXT: s_mov_b32 s7, s3
; GCN-NEXT: buffer_load_dwordx4 v[0:3], off, s[4:7], 0
; GCN-NEXT: buffer_load_dwordx4 v[4:7], off, s[4:7], 0 offset:16
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_lshl_b32_e32 v3, v3, v7 ; GCN-NEXT: v_lshl_b32_e32 v3, v3, v7
; GCN-NEXT: v_lshl_b32_e32 v2, v2, v6 ; GCN-NEXT: v_lshl_b32_e32 v2, v2, v6
; GCN-NEXT: v_lshl_b32_e32 v1, v1, v5 ; GCN-NEXT: v_lshl_b32_e32 v1, v1, v5
; GCN-NEXT: v_lshl_b32_e32 v0, v0, v4 ; GCN-NEXT: v_lshl_b32_e32 v0, v0, v4
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
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; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_mov_b32 s10, s2 ; GCN-NEXT: s_mov_b32 s10, s2
; GCN-NEXT: s_mov_b32 s11, s3 ; GCN-NEXT: s_mov_b32 s11, s3
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s8, s6 ; GCN-NEXT: s_mov_b32 s8, s6
; GCN-NEXT: s_mov_b32 s9, s7 ; GCN-NEXT: s_mov_b32 s9, s7
; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GCN-NEXT: s_mov_b64 s[12:13], s[6:7]
; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_mov_b32 s14, 0 ; GCN-NEXT: s_mov_b32 s14, 0
; GCN-NEXT: s_mov_b32 s15, s3 ; GCN-NEXT: s_mov_b32 s15, s3
; GCN-NEXT: s_mov_b64 s[12:13], s[6:7]
; GCN-NEXT: buffer_load_dword v2, off, s[8:11], 0 ; GCN-NEXT: buffer_load_dword v2, off, s[8:11], 0
; GCN-NEXT: buffer_load_dword v0, v[0:1], s[12:15], 0 addr64 offset:4 ; GCN-NEXT: buffer_load_dword v0, v[0:1], s[12:15], 0 addr64 offset:4
; GCN-NEXT: s_mov_b32 s6, 0xffff
; GCN-NEXT: s_mov_b32 s0, s4 ; GCN-NEXT: s_mov_b32 s0, s4
; GCN-NEXT: s_mov_b32 s4, 0xffff
; GCN-NEXT: s_mov_b32 s1, s5 ; GCN-NEXT: s_mov_b32 s1, s5
; GCN-NEXT: s_waitcnt vmcnt(1) ; GCN-NEXT: s_waitcnt vmcnt(1)
; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v2 ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v0 ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GCN-NEXT: v_and_b32_e32 v0, s4, v0 ; GCN-NEXT: v_and_b32_e32 v0, s6, v0
; GCN-NEXT: v_lshl_b32_e32 v0, v2, v0 ; GCN-NEXT: v_lshl_b32_e32 v0, v2, v0
; GCN-NEXT: v_lshl_b32_e32 v1, v1, v3 ; GCN-NEXT: v_lshl_b32_e32 v1, v1, v3
; GCN-NEXT: v_and_b32_e32 v0, s4, v0 ; GCN-NEXT: v_and_b32_e32 v0, s6, v0
; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GCN-NEXT: v_or_b32_e32 v0, v0, v1 ; GCN-NEXT: v_or_b32_e32 v0, v0, v1
; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; EG-LABEL: shl_v2i16: ; EG-LABEL: shl_v2i16:
; EG: ; %bb.0: ; EG: ; %bb.0:
; EG-NEXT: ALU 2, @12, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 2, @12, KC0[CB0:0-32], KC1[]
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; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_mov_b32 s2, 0 ; GCN-NEXT: s_mov_b32 s2, 0
; GCN-NEXT: v_lshlrev_b32_e32 v0, 3, v0 ; GCN-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b64 s[0:1], s[6:7] ; GCN-NEXT: s_mov_b64 s[0:1], s[6:7]
; GCN-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 ; GCN-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
; GCN-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[0:3], 0 addr64 offset:8 ; GCN-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[0:3], 0 addr64 offset:8
; GCN-NEXT: s_mov_b32 s8, 0xffff ; GCN-NEXT: s_mov_b32 s0, 0xffff
; GCN-NEXT: s_mov_b64 s[6:7], s[2:3] ; GCN-NEXT: s_mov_b64 s[6:7], s[2:3]
; GCN-NEXT: s_waitcnt vmcnt(1) ; GCN-NEXT: s_waitcnt vmcnt(1)
; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v2 ; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_and_b32_e32 v8, s8, v4 ; GCN-NEXT: v_and_b32_e32 v8, s0, v4
; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 ; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; GCN-NEXT: v_and_b32_e32 v9, s8, v5 ; GCN-NEXT: v_and_b32_e32 v9, s0, v5
; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v3 ; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v3
; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 ; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GCN-NEXT: v_lshl_b32_e32 v5, v7, v5 ; GCN-NEXT: v_lshl_b32_e32 v5, v7, v5
; GCN-NEXT: v_lshl_b32_e32 v3, v3, v9 ; GCN-NEXT: v_lshl_b32_e32 v3, v3, v9
; GCN-NEXT: v_lshl_b32_e32 v4, v6, v4 ; GCN-NEXT: v_lshl_b32_e32 v4, v6, v4
; GCN-NEXT: v_lshl_b32_e32 v2, v2, v8 ; GCN-NEXT: v_lshl_b32_e32 v2, v2, v8
; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5 ; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GCN-NEXT: v_and_b32_e32 v3, s8, v3 ; GCN-NEXT: v_and_b32_e32 v3, s0, v3
; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GCN-NEXT: v_and_b32_e32 v2, s8, v2 ; GCN-NEXT: v_and_b32_e32 v2, s0, v2
; GCN-NEXT: v_or_b32_e32 v3, v3, v5 ; GCN-NEXT: v_or_b32_e32 v3, v3, v5
; GCN-NEXT: v_or_b32_e32 v2, v2, v4 ; GCN-NEXT: v_or_b32_e32 v2, v2, v4
; GCN-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 ; GCN-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; EG-LABEL: shl_v4i16: ; EG-LABEL: shl_v4i16:
; EG: ; %bb.0: ; EG: ; %bb.0:
; EG-NEXT: ALU 2, @12, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 2, @12, KC0[CB0:0-32], KC1[]
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} }
define amdgpu_kernel void @shl_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) { define amdgpu_kernel void @shl_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) {
; GCN-LABEL: shl_v4i64: ; GCN-LABEL: shl_v4i64:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_mov_b32 s10, s2
; GCN-NEXT: s_mov_b32 s11, s3
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s8, s6
; GCN-NEXT: s_mov_b32 s9, s7
; GCN-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
; GCN-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16
; GCN-NEXT: buffer_load_dwordx4 v[8:11], off, s[8:11], 0 offset:32
; GCN-NEXT: buffer_load_dwordx4 v[11:14], off, s[8:11], 0 offset:48
; GCN-NEXT: s_mov_b32 s0, s4 ; GCN-NEXT: s_mov_b32 s0, s4
; GCN-NEXT: s_mov_b32 s1, s5 ; GCN-NEXT: s_mov_b32 s1, s5
; GCN-NEXT: s_mov_b32 s4, s6
; GCN-NEXT: s_mov_b32 s5, s7
; GCN-NEXT: s_mov_b32 s6, s2
; GCN-NEXT: s_mov_b32 s7, s3
; GCN-NEXT: buffer_load_dwordx4 v[0:3], off, s[4:7], 0
; GCN-NEXT: buffer_load_dwordx4 v[4:7], off, s[4:7], 0 offset:16
; GCN-NEXT: buffer_load_dwordx4 v[8:11], off, s[4:7], 0 offset:32
; GCN-NEXT: buffer_load_dwordx4 v[11:14], off, s[4:7], 0 offset:48
; GCN-NEXT: s_waitcnt vmcnt(1) ; GCN-NEXT: s_waitcnt vmcnt(1)
; GCN-NEXT: v_lshl_b64 v[2:3], v[2:3], v10 ; GCN-NEXT: v_lshl_b64 v[2:3], v[2:3], v10
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_lshl_b64 v[6:7], v[6:7], v13 ; GCN-NEXT: v_lshl_b64 v[6:7], v[6:7], v13
; GCN-NEXT: v_lshl_b64 v[4:5], v[4:5], v11 ; GCN-NEXT: v_lshl_b64 v[4:5], v[4:5], v11
; GCN-NEXT: v_lshl_b64 v[0:1], v[0:1], v8 ; GCN-NEXT: v_lshl_b64 v[0:1], v[0:1], v8
; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16 ; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
▲ Show 20 Lines • Show All 974 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/shl.v2i16.ll

Show First 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_pk_lshlrev_b16 v0, v0, v4 ; GFX9-NEXT: v_pk_lshlrev_b16 v0, v0, v4
; GFX9-NEXT: global_store_dword v[2:3], v0, off ; GFX9-NEXT: global_store_dword v[2:3], v0, off
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: v_shl_v2i16: ; VI-LABEL: v_shl_v2i16:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v5, v[0:1]
; VI-NEXT: flat_load_dword v2, v[2:3]
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v4
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v4, vcc, 4, v0
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1]
; VI-NEXT: flat_load_dword v1, v[4:5]
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_lshlrev_b16_e32 v4, v1, v0 ; VI-NEXT: v_lshlrev_b16_e32 v3, v2, v5
; VI-NEXT: v_lshlrev_b16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-NEXT: v_lshlrev_b16_sdwa v2, v2, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-NEXT: v_or_b32_e32 v0, v4, v0 ; VI-NEXT: v_or_b32_e32 v2, v3, v2
; VI-NEXT: flat_store_dword v[2:3], v0 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; CI-LABEL: v_shl_v2i16: ; CI-LABEL: v_shl_v2i16:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; CI-NEXT: s_mov_b32 s3, 0xf000 ; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0 ; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; CI-NEXT: v_mov_b32_e32 v1, 0 ; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_mov_b64 s[0:1], s[6:7] ; CI-NEXT: s_mov_b64 s[0:1], s[6:7]
; CI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 ; CI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64
; CI-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 ; CI-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4
; CI-NEXT: s_mov_b32 s8, 0xffff ; CI-NEXT: s_mov_b32 s0, 0xffff
; CI-NEXT: s_mov_b64 s[6:7], s[2:3] ; CI-NEXT: s_mov_b64 s[6:7], s[2:3]
; CI-NEXT: s_waitcnt vmcnt(1) ; CI-NEXT: s_waitcnt vmcnt(1)
; CI-NEXT: v_lshrrev_b32_e32 v4, 16, v2 ; CI-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; CI-NEXT: s_waitcnt vmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_and_b32_e32 v5, s8, v3 ; CI-NEXT: v_and_b32_e32 v5, s0, v3
; CI-NEXT: v_lshrrev_b32_e32 v3, 16, v3 ; CI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; CI-NEXT: v_lshl_b32_e32 v3, v4, v3 ; CI-NEXT: v_lshl_b32_e32 v3, v4, v3
; CI-NEXT: v_lshl_b32_e32 v2, v2, v5 ; CI-NEXT: v_lshl_b32_e32 v2, v2, v5
; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; CI-NEXT: v_and_b32_e32 v2, s8, v2 ; CI-NEXT: v_and_b32_e32 v2, s0, v2
; CI-NEXT: v_or_b32_e32 v2, v2, v3 ; CI-NEXT: v_or_b32_e32 v2, v2, v3
; CI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64 ; CI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
%out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
%b_ptr = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %in.gep, i32 1 %b_ptr = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %in.gep, i32 1
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; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_load_dword s0, s[0:1], 0x34 ; VI-NEXT: s_load_dword s0, s[0:1], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s7 ; VI-NEXT: v_mov_b32_e32 v1, s7
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v3, v[0:1]
; VI-NEXT: s_lshr_b32 s1, s0, 16 ; VI-NEXT: s_lshr_b32 s1, s0, 16
; VI-NEXT: v_mov_b32_e32 v4, s1 ; VI-NEXT: v_add_u32_e32 v0, vcc, s4, v2
; VI-NEXT: v_mov_b32_e32 v3, s5 ; VI-NEXT: v_mov_b32_e32 v2, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v2 ; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_lshlrev_b16_e32 v1, s0, v0 ; VI-NEXT: v_lshlrev_b16_e32 v4, s0, v3
; VI-NEXT: v_lshlrev_b16_sdwa v0, v4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; VI-NEXT: v_lshlrev_b16_sdwa v2, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_or_b32_e32 v0, v1, v0 ; VI-NEXT: v_or_b32_e32 v2, v4, v2
; VI-NEXT: flat_store_dword v[2:3], v0 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; CI-LABEL: shl_v_s_v2i16: ; CI-LABEL: shl_v_s_v2i16:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; CI-NEXT: s_load_dword s0, s[0:1], 0xd ; CI-NEXT: s_load_dword s8, s[0:1], 0xd
; CI-NEXT: s_mov_b32 s8, 0xffff
; CI-NEXT: s_mov_b32 s3, 0xf000 ; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0 ; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_lshr_b32 s9, s0, 16
; CI-NEXT: s_and_b32 s10, s0, s8
; CI-NEXT: s_mov_b64 s[0:1], s[6:7] ; CI-NEXT: s_mov_b64 s[0:1], s[6:7]
; CI-NEXT: v_mov_b32_e32 v1, 0 ; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 ; CI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64
; CI-NEXT: s_mov_b32 s0, 0xffff
; CI-NEXT: s_lshr_b32 s1, s8, 16
; CI-NEXT: s_and_b32 s8, s8, s0
; CI-NEXT: s_mov_b64 s[6:7], s[2:3] ; CI-NEXT: s_mov_b64 s[6:7], s[2:3]
; CI-NEXT: s_waitcnt vmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_lshrrev_b32_e32 v3, 16, v2 ; CI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
; CI-NEXT: v_lshlrev_b32_e32 v2, s10, v2 ; CI-NEXT: v_lshlrev_b32_e32 v2, s8, v2
; CI-NEXT: v_lshlrev_b32_e32 v3, s9, v3 ; CI-NEXT: v_lshlrev_b32_e32 v3, s1, v3
; CI-NEXT: v_and_b32_e32 v2, s8, v2 ; CI-NEXT: v_and_b32_e32 v2, s0, v2
; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; CI-NEXT: v_or_b32_e32 v2, v2, v3 ; CI-NEXT: v_or_b32_e32 v2, v2, v3
; CI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64 ; CI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
%out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
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; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_load_dword s0, s[0:1], 0x34 ; VI-NEXT: s_load_dword s0, s[0:1], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s7 ; VI-NEXT: v_mov_b32_e32 v1, s7
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v3, v[0:1]
; VI-NEXT: s_lshr_b32 s1, s0, 16 ; VI-NEXT: s_lshr_b32 s1, s0, 16
; VI-NEXT: v_mov_b32_e32 v4, s1 ; VI-NEXT: v_add_u32_e32 v0, vcc, s4, v2
; VI-NEXT: v_mov_b32_e32 v3, s5 ; VI-NEXT: v_mov_b32_e32 v2, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v2 ; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_lshlrev_b16_e64 v1, v0, s0 ; VI-NEXT: v_lshlrev_b16_e64 v4, v3, s0
; VI-NEXT: v_lshlrev_b16_sdwa v0, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; VI-NEXT: v_lshlrev_b16_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v1, v0 ; VI-NEXT: v_or_b32_e32 v2, v4, v2
; VI-NEXT: flat_store_dword v[2:3], v0 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; CI-LABEL: shl_s_v_v2i16: ; CI-LABEL: shl_s_v_v2i16:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; CI-NEXT: s_load_dword s8, s[0:1], 0xd ; CI-NEXT: s_load_dword s8, s[0:1], 0xd
; CI-NEXT: s_mov_b32 s3, 0xf000 ; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0 ; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_mov_b64 s[0:1], s[6:7] ; CI-NEXT: s_mov_b64 s[0:1], s[6:7]
; CI-NEXT: v_mov_b32_e32 v1, 0 ; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 ; CI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64
; CI-NEXT: s_mov_b32 s0, 0xffff ; CI-NEXT: s_mov_b32 s0, 0xffff
; CI-NEXT: s_lshr_b32 s9, s8, 16 ; CI-NEXT: s_lshr_b32 s1, s8, 16
; CI-NEXT: s_mov_b64 s[6:7], s[2:3] ; CI-NEXT: s_mov_b64 s[6:7], s[2:3]
; CI-NEXT: s_waitcnt vmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_and_b32_e32 v3, s0, v2 ; CI-NEXT: v_and_b32_e32 v3, s0, v2
; CI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 ; CI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; CI-NEXT: v_lshl_b32_e32 v2, s9, v2 ; CI-NEXT: v_lshl_b32_e32 v2, s1, v2
; CI-NEXT: v_lshl_b32_e32 v3, s8, v3 ; CI-NEXT: v_lshl_b32_e32 v3, s8, v3
; CI-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; CI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; CI-NEXT: v_and_b32_e32 v3, s0, v3 ; CI-NEXT: v_and_b32_e32 v3, s0, v3
; CI-NEXT: v_or_b32_e32 v2, v3, v2 ; CI-NEXT: v_or_b32_e32 v2, v3, v2
; CI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64 ; CI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
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; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: v_mov_b32_e32 v4, 8 ; VI-NEXT: v_mov_b32_e32 v4, 8
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v3, v[0:1]
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_lshlrev_b16_e64 v1, v0, 8 ; VI-NEXT: v_lshlrev_b16_e64 v2, v3, 8
; VI-NEXT: v_lshlrev_b16_sdwa v0, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; VI-NEXT: v_lshlrev_b16_sdwa v3, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v1, v0 ; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: flat_store_dword v[2:3], v0 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; CI-LABEL: shl_imm_v_v2i16: ; CI-LABEL: shl_imm_v_v2i16:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; CI-NEXT: s_mov_b32 s3, 0xf000 ; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0 ; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; VI-LABEL: shl_v_imm_v2i16: ; VI-LABEL: shl_v_imm_v2i16:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v3, v[0:1]
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v3
; VI-NEXT: v_and_b32_e32 v1, 0xff000000, v1 ; VI-NEXT: v_and_b32_e32 v2, 0xff000000, v2
; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0 ; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v3
; VI-NEXT: v_or_b32_e32 v0, v0, v1 ; VI-NEXT: v_or_b32_e32 v2, v3, v2
; VI-NEXT: flat_store_dword v[2:3], v0 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; CI-LABEL: shl_v_imm_v2i16: ; CI-LABEL: shl_v_imm_v2i16:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; CI-NEXT: s_mov_b32 s3, 0xf000 ; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0 ; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
Show All 16 Lines; CI-NEXT: s_endpgm
store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep
ret void ret void
} }
define amdgpu_kernel void @v_shl_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) #0 { define amdgpu_kernel void @v_shl_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) #0 {
; GFX9-LABEL: v_shl_v4i16: ; GFX9-LABEL: v_shl_v4i16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 3, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v4, 3, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v4
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: global_load_dwordx2 v[4:5], v[0:1], off ; GFX9-NEXT: global_load_dwordx2 v[2:3], v[0:1], off
; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off offset:8 ; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off offset:8
; GFX9-NEXT: v_mov_b32_e32 v3, s1 ; GFX9-NEXT: v_mov_b32_e32 v5, s1
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, s0, v4
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_pk_lshlrev_b16 v1, v1, v5 ; GFX9-NEXT: v_pk_lshlrev_b16 v1, v1, v3
; GFX9-NEXT: v_pk_lshlrev_b16 v0, v0, v4 ; GFX9-NEXT: v_pk_lshlrev_b16 v0, v0, v2
; GFX9-NEXT: global_store_dwordx2 v[2:3], v[0:1], off ; GFX9-NEXT: global_store_dwordx2 v[4:5], v[0:1], off
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: v_shl_v4i16: ; VI-LABEL: v_shl_v4i16:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v0 ; VI-NEXT: v_lshlrev_b32_e32 v4, 3, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2 ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v4, vcc, 8, v0
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] ; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; VI-NEXT: flat_load_dwordx2 v[4:5], v[4:5] ; VI-NEXT: flat_load_dwordx2 v[2:3], v[2:3]
; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_add_u32_e32 v4, vcc, s0, v4
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_lshlrev_b16_e32 v6, v5, v1 ; VI-NEXT: v_lshlrev_b16_e32 v6, v3, v1
; VI-NEXT: v_lshlrev_b16_sdwa v1, v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-NEXT: v_lshlrev_b16_sdwa v1, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b16_e32 v5, v4, v0 ; VI-NEXT: v_lshlrev_b16_e32 v3, v2, v0
; VI-NEXT: v_lshlrev_b16_sdwa v0, v4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-NEXT: v_lshlrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-NEXT: v_or_b32_e32 v1, v6, v1 ; VI-NEXT: v_or_b32_e32 v1, v6, v1
; VI-NEXT: v_or_b32_e32 v0, v5, v0 ; VI-NEXT: v_or_b32_e32 v0, v3, v0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; CI-LABEL: v_shl_v4i16: ; CI-LABEL: v_shl_v4i16:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; CI-NEXT: s_mov_b32 s3, 0xf000 ; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0 ; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 ; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; CI-NEXT: v_mov_b32_e32 v1, 0 ; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_mov_b64 s[0:1], s[6:7] ; CI-NEXT: s_mov_b64 s[0:1], s[6:7]
; CI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 ; CI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
; CI-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[0:3], 0 addr64 offset:8 ; CI-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[0:3], 0 addr64 offset:8
; CI-NEXT: s_mov_b32 s8, 0xffff ; CI-NEXT: s_mov_b32 s0, 0xffff
; CI-NEXT: s_mov_b64 s[6:7], s[2:3] ; CI-NEXT: s_mov_b64 s[6:7], s[2:3]
; CI-NEXT: s_waitcnt vmcnt(1) ; CI-NEXT: s_waitcnt vmcnt(1)
; CI-NEXT: v_lshrrev_b32_e32 v6, 16, v2 ; CI-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; CI-NEXT: s_waitcnt vmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_and_b32_e32 v8, s8, v4 ; CI-NEXT: v_and_b32_e32 v8, s0, v4
; CI-NEXT: v_lshrrev_b32_e32 v4, 16, v4 ; CI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; CI-NEXT: v_and_b32_e32 v9, s8, v5 ; CI-NEXT: v_and_b32_e32 v9, s0, v5
; CI-NEXT: v_lshrrev_b32_e32 v7, 16, v3 ; CI-NEXT: v_lshrrev_b32_e32 v7, 16, v3
; CI-NEXT: v_lshrrev_b32_e32 v5, 16, v5 ; CI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; CI-NEXT: v_lshl_b32_e32 v5, v7, v5 ; CI-NEXT: v_lshl_b32_e32 v5, v7, v5
; CI-NEXT: v_lshl_b32_e32 v3, v3, v9 ; CI-NEXT: v_lshl_b32_e32 v3, v3, v9
; CI-NEXT: v_lshl_b32_e32 v4, v6, v4 ; CI-NEXT: v_lshl_b32_e32 v4, v6, v4
; CI-NEXT: v_lshl_b32_e32 v2, v2, v8 ; CI-NEXT: v_lshl_b32_e32 v2, v2, v8
; CI-NEXT: v_lshlrev_b32_e32 v5, 16, v5 ; CI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; CI-NEXT: v_and_b32_e32 v3, s8, v3 ; CI-NEXT: v_and_b32_e32 v3, s0, v3
; CI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; CI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; CI-NEXT: v_and_b32_e32 v2, s8, v2 ; CI-NEXT: v_and_b32_e32 v2, s0, v2
; CI-NEXT: v_or_b32_e32 v3, v3, v5 ; CI-NEXT: v_or_b32_e32 v3, v3, v5
; CI-NEXT: v_or_b32_e32 v2, v2, v4 ; CI-NEXT: v_or_b32_e32 v2, v2, v4
; CI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 ; CI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%in.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %in, i64 %tid.ext %in.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %in, i64 %tid.ext
%out.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %out, i64 %tid.ext
Show All 24 Lines
; GFX9-NEXT: global_store_dwordx2 v[2:3], v[0:1], off ; GFX9-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: shl_v_imm_v4i16: ; VI-LABEL: shl_v_imm_v4i16:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] ; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2 ; VI-NEXT: s_mov_b32 s2, 0xff000000
; VI-NEXT: s_mov_b32 s0, 0xff000000
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_lshlrev_b32_e32 v4, 8, v1 ; VI-NEXT: v_lshlrev_b32_e32 v4, 8, v1
; VI-NEXT: v_lshlrev_b16_e32 v5, 8, v0 ; VI-NEXT: v_lshlrev_b16_e32 v5, 8, v0
; VI-NEXT: v_lshlrev_b32_e32 v0, 8, v0 ; VI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; VI-NEXT: v_and_b32_e32 v0, s0, v0 ; VI-NEXT: v_and_b32_e32 v0, s2, v0
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1 ; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1
; VI-NEXT: v_and_b32_e32 v4, s0, v4 ; VI-NEXT: v_and_b32_e32 v4, s2, v4
; VI-NEXT: v_or_b32_e32 v1, v1, v4 ; VI-NEXT: v_or_b32_e32 v1, v1, v4
; VI-NEXT: v_or_b32_e32 v0, v5, v0 ; VI-NEXT: v_or_b32_e32 v0, v5, v0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; CI-LABEL: shl_v_imm_v4i16: ; CI-LABEL: shl_v_imm_v4i16:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; CI-NEXT: s_mov_b32 s3, 0xf000 ; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0 ; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 ; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; CI-NEXT: v_mov_b32_e32 v1, 0 ; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_mov_b64 s[0:1], s[6:7] ; CI-NEXT: s_mov_b64 s[0:1], s[6:7]
; CI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 ; CI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
; CI-NEXT: s_mov_b32 s8, 0xff00 ; CI-NEXT: s_mov_b32 s0, 0xff00
; CI-NEXT: s_mov_b64 s[6:7], s[2:3] ; CI-NEXT: s_mov_b64 s[6:7], s[2:3]
; CI-NEXT: s_waitcnt vmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_lshrrev_b32_e32 v4, 8, v3 ; CI-NEXT: v_lshrrev_b32_e32 v4, 8, v3
; CI-NEXT: v_lshlrev_b32_e32 v3, 8, v3 ; CI-NEXT: v_lshlrev_b32_e32 v3, 8, v3
; CI-NEXT: v_and_b32_e32 v4, s8, v4 ; CI-NEXT: v_and_b32_e32 v4, s0, v4
; CI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 ; CI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; CI-NEXT: v_and_b32_e32 v3, s8, v3 ; CI-NEXT: v_and_b32_e32 v3, s0, v3
; CI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; CI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; CI-NEXT: v_or_b32_e32 v3, v3, v4 ; CI-NEXT: v_or_b32_e32 v3, v3, v4
; CI-NEXT: v_and_b32_e32 v2, 0xff00ff00, v2 ; CI-NEXT: v_and_b32_e32 v2, 0xff00ff00, v2
; CI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 ; CI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%in.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %in, i64 %tid.ext %in.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %in, i64 %tid.ext
Show All 11 Lines

llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll

Show First 20 Lines • Show All 106 Lines • ▼ Show 20 Lines
; VI-LABEL: v_test_i32_x_sub_64_multi_use: ; VI-LABEL: v_test_i32_x_sub_64_multi_use:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v3, v[0:1]
; VI-NEXT: flat_load_dword v4, v[0:1] ; VI-NEXT: flat_load_dword v4, v[0:1]
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: s_waitcnt vmcnt(1) lgkmcnt(1) ; VI-NEXT: s_waitcnt vmcnt(1) lgkmcnt(1)
; VI-NEXT: v_subrev_u32_e32 v1, vcc, 64, v4 ; VI-NEXT: v_subrev_u32_e32 v2, vcc, 64, v3
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_subrev_u32_e32 v0, vcc, 64, v0 ; VI-NEXT: v_subrev_u32_e32 v3, vcc, 64, v4
; VI-NEXT: flat_store_dword v[2:3], v1 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: flat_store_dword v[2:3], v0 ; VI-NEXT: flat_store_dword v[0:1], v3
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_test_i32_x_sub_64_multi_use: ; GFX9-LABEL: v_test_i32_x_sub_64_multi_use:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: global_load_dword v3, v[0:1], off
; GFX9-NEXT: global_load_dword v4, v[0:1], off ; GFX9-NEXT: global_load_dword v4, v[0:1], off
; GFX9-NEXT: global_load_dword v0, v[0:1], off ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s1 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: s_waitcnt vmcnt(1) ; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_subrev_u32_e32 v1, 64, v4 ; GFX9-NEXT: v_subrev_u32_e32 v2, 64, v3
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_subrev_u32_e32 v0, 64, v0 ; GFX9-NEXT: v_subrev_u32_e32 v3, 64, v4
; GFX9-NEXT: global_store_dword v[2:3], v1, off ; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: global_store_dword v[2:3], v0, off ; GFX9-NEXT: global_store_dword v[0:1], v3, off
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: v_test_i32_x_sub_64_multi_use: ; GFX10-LABEL: v_test_i32_x_sub_64_multi_use:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; VI-LABEL: v_test_i16_x_sub_64_multi_use: ; VI-LABEL: v_test_i16_x_sub_64_multi_use:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v2, 1, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 1, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_ushort v3, v[0:1]
; VI-NEXT: flat_load_ushort v4, v[0:1] ; VI-NEXT: flat_load_ushort v4, v[0:1]
; VI-NEXT: flat_load_ushort v0, v[0:1] ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: s_waitcnt vmcnt(1) lgkmcnt(1) ; VI-NEXT: s_waitcnt vmcnt(1) lgkmcnt(1)
; VI-NEXT: v_subrev_u16_e32 v1, 64, v4 ; VI-NEXT: v_subrev_u16_e32 v2, 64, v3
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_subrev_u16_e32 v0, 64, v0 ; VI-NEXT: v_subrev_u16_e32 v3, 64, v4
; VI-NEXT: flat_store_short v[2:3], v1 ; VI-NEXT: flat_store_short v[0:1], v2
; VI-NEXT: flat_store_short v[2:3], v0 ; VI-NEXT: flat_store_short v[0:1], v3
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_test_i16_x_sub_64_multi_use: ; GFX9-LABEL: v_test_i16_x_sub_64_multi_use:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 1, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 1, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: global_load_ushort v3, v[0:1], off
; GFX9-NEXT: global_load_ushort v4, v[0:1], off ; GFX9-NEXT: global_load_ushort v4, v[0:1], off
; GFX9-NEXT: global_load_ushort v0, v[0:1], off ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s1 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: s_waitcnt vmcnt(1) ; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_subrev_u16_e32 v1, 64, v4 ; GFX9-NEXT: v_subrev_u16_e32 v2, 64, v3
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_subrev_u16_e32 v0, 64, v0 ; GFX9-NEXT: v_subrev_u16_e32 v3, 64, v4
; GFX9-NEXT: global_store_short v[2:3], v1, off ; GFX9-NEXT: global_store_short v[0:1], v2, off
; GFX9-NEXT: global_store_short v[2:3], v0, off ; GFX9-NEXT: global_store_short v[0:1], v3, off
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: v_test_i16_x_sub_64_multi_use: ; GFX10-LABEL: v_test_i16_x_sub_64_multi_use:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 1, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 1, v0
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: v_add_i32_e32 v2, vcc, 0xffc00000, v2 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0xffc00000, v2
; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: v_test_v2i16_x_sub_64_64: ; VI-LABEL: v_test_v2i16_x_sub_64_64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: v_mov_b32_e32 v4, 64
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v3, v[0:1]
; VI-NEXT: v_mov_b32_e32 v1, 64 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_sub_u16_sdwa v1, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; VI-NEXT: v_sub_u16_sdwa v2, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_subrev_u16_e32 v0, 64, v0 ; VI-NEXT: v_subrev_u16_e32 v3, 64, v3
; VI-NEXT: v_or_b32_e32 v0, v0, v1 ; VI-NEXT: v_or_b32_e32 v2, v3, v2
; VI-NEXT: flat_store_dword v[2:3], v0 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_test_v2i16_x_sub_64_64: ; GFX9-LABEL: v_test_v2i16_x_sub_64_64:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
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; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: v_mov_b32_e32 v4, 64 ; VI-NEXT: v_mov_b32_e32 v4, 64
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v3, v[0:1]
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_add_u16_e32 v1, -7, v0 ; VI-NEXT: v_add_u16_e32 v2, -7, v3
; VI-NEXT: v_sub_u16_sdwa v0, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; VI-NEXT: v_sub_u16_sdwa v3, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v1, v0 ; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: flat_store_dword v[2:3], v0 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_test_v2i16_x_sub_7_64: ; GFX9-LABEL: v_test_v2i16_x_sub_7_64:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
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; SI-NEXT: v_add_i32_e32 v2, vcc, 0xff850000, v2 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0xff850000, v2
; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: v_test_v2i16_x_sub_64_123: ; VI-LABEL: v_test_v2i16_x_sub_64_123:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: v_mov_b32_e32 v4, 0xffffff85
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v3, v[0:1]
; VI-NEXT: v_mov_b32_e32 v1, 0xffffff85 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_add_u16_sdwa v1, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; VI-NEXT: v_add_u16_sdwa v2, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_subrev_u16_e32 v0, 64, v0 ; VI-NEXT: v_subrev_u16_e32 v3, 64, v3
; VI-NEXT: v_or_b32_e32 v0, v0, v1 ; VI-NEXT: v_or_b32_e32 v2, v3, v2
; VI-NEXT: flat_store_dword v[2:3], v0 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_test_v2i16_x_sub_64_123: ; GFX9-LABEL: v_test_v2i16_x_sub_64_123:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
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; VI-LABEL: v_test_v2i16_x_sub_7_0: ; VI-LABEL: v_test_v2i16_x_sub_7_0:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v3, v[0:1]
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v0 ; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
; VI-NEXT: v_add_u16_e32 v0, -7, v0 ; VI-NEXT: v_add_u16_e32 v3, -7, v3
; VI-NEXT: v_or_b32_e32 v0, v0, v1 ; VI-NEXT: v_or_b32_e32 v2, v3, v2
; VI-NEXT: flat_store_dword v[2:3], v0 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_test_v2i16_x_sub_7_0: ; GFX9-LABEL: v_test_v2i16_x_sub_7_0:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
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; SI-NEXT: v_add_i32_e32 v2, vcc, 0xffe00000, v2 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0xffe00000, v2
; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: v_test_v2i16_x_add_neg32_neg32: ; VI-LABEL: v_test_v2i16_x_add_neg32_neg32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: v_mov_b32_e32 v4, 32
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v3, v[0:1]
; VI-NEXT: v_mov_b32_e32 v1, 32 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_sub_u16_sdwa v1, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; VI-NEXT: v_sub_u16_sdwa v2, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_subrev_u16_e32 v0, 32, v0 ; VI-NEXT: v_subrev_u16_e32 v3, 32, v3
; VI-NEXT: v_or_b32_e32 v0, v0, v1 ; VI-NEXT: v_or_b32_e32 v2, v3, v2
; VI-NEXT: flat_store_dword v[2:3], v0 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_test_v2i16_x_add_neg32_neg32: ; GFX9-LABEL: v_test_v2i16_x_add_neg32_neg32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
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; VI-LABEL: v_test_v2i16_x_add_neg32_0: ; VI-LABEL: v_test_v2i16_x_add_neg32_0:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v3, v[0:1]
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v0 ; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
; VI-NEXT: v_subrev_u16_e32 v0, 32, v0 ; VI-NEXT: v_subrev_u16_e32 v3, 32, v3
; VI-NEXT: v_or_b32_e32 v0, v0, v1 ; VI-NEXT: v_or_b32_e32 v2, v3, v2
; VI-NEXT: flat_store_dword v[2:3], v0 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_test_v2i16_x_add_neg32_0: ; GFX9-LABEL: v_test_v2i16_x_add_neg32_0:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
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; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: v_mov_b32_e32 v4, -16 ; VI-NEXT: v_mov_b32_e32 v4, -16
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v3, v[0:1]
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_add_u16_e32 v1, -16, v0 ; VI-NEXT: v_add_u16_e32 v2, -16, v3
; VI-NEXT: v_add_u16_sdwa v0, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; VI-NEXT: v_add_u16_sdwa v3, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v1, v0 ; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: flat_store_dword v[2:3], v0 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_test_v2i16_x_add_neg16_neg16: ; GFX9-LABEL: v_test_v2i16_x_add_neg16_neg16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
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; VI-LABEL: v_test_v2i16_x_add_neg16_0: ; VI-LABEL: v_test_v2i16_x_add_neg16_0:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v3, v[0:1]
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v0 ; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
; VI-NEXT: v_add_u16_e32 v0, -16, v0 ; VI-NEXT: v_add_u16_e32 v3, -16, v3
; VI-NEXT: v_or_b32_e32 v0, v0, v1 ; VI-NEXT: v_or_b32_e32 v2, v3, v2
; VI-NEXT: flat_store_dword v[2:3], v0 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_test_v2i16_x_add_neg16_0: ; GFX9-LABEL: v_test_v2i16_x_add_neg16_0:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
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; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: v_test_v2i16_x_add_neg_fpone: ; VI-LABEL: v_test_v2i16_x_add_neg_fpone:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v3, v[0:1]
; VI-NEXT: s_movk_i32 s2, 0xc400
; VI-NEXT: v_mov_b32_e32 v4, s2
; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1]
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
; VI-NEXT: s_movk_i32 s0, 0xc400
; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_add_u16_e32 v1, s0, v0 ; VI-NEXT: v_add_u16_e32 v2, s2, v3
; VI-NEXT: v_add_u16_sdwa v0, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; VI-NEXT: v_add_u16_sdwa v3, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v1, v0 ; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: flat_store_dword v[2:3], v0 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_test_v2i16_x_add_neg_fpone: ; GFX9-LABEL: v_test_v2i16_x_add_neg_fpone:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
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; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: v_test_v2i16_x_add_neg_negfpone: ; VI-LABEL: v_test_v2i16_x_add_neg_negfpone:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v3, v[0:1]
; VI-NEXT: s_movk_i32 s2, 0x4400
; VI-NEXT: v_mov_b32_e32 v4, s2
; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1]
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
; VI-NEXT: s_movk_i32 s0, 0x4400
; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_add_u16_e32 v1, s0, v0 ; VI-NEXT: v_add_u16_e32 v2, s2, v3
; VI-NEXT: v_add_u16_sdwa v0, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; VI-NEXT: v_add_u16_sdwa v3, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v1, v0 ; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: flat_store_dword v[2:3], v0 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_test_v2i16_x_add_neg_negfpone: ; GFX9-LABEL: v_test_v2i16_x_add_neg_negfpone:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
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; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: v_test_v2i16_x_add_neg_fptwo: ; VI-LABEL: v_test_v2i16_x_add_neg_fptwo:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v3, v[0:1]
; VI-NEXT: s_movk_i32 s2, 0x4000
; VI-NEXT: v_mov_b32_e32 v4, s2
; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1]
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
; VI-NEXT: s_movk_i32 s0, 0x4000
; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_add_u16_e32 v1, s0, v0 ; VI-NEXT: v_add_u16_e32 v2, s2, v3
; VI-NEXT: v_add_u16_sdwa v0, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; VI-NEXT: v_add_u16_sdwa v3, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v1, v0 ; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: flat_store_dword v[2:3], v0 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_test_v2i16_x_add_neg_fptwo: ; GFX9-LABEL: v_test_v2i16_x_add_neg_fptwo:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
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; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: v_test_v2i16_x_add_neg_negfptwo: ; VI-LABEL: v_test_v2i16_x_add_neg_negfptwo:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v3, v[0:1]
; VI-NEXT: s_movk_i32 s2, 0xc000
; VI-NEXT: v_mov_b32_e32 v4, s2
; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1]
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
; VI-NEXT: s_movk_i32 s0, 0xc000
; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_add_u16_e32 v1, s0, v0 ; VI-NEXT: v_add_u16_e32 v2, s2, v3
; VI-NEXT: v_add_u16_sdwa v0, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; VI-NEXT: v_add_u16_sdwa v3, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v1, v0 ; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: flat_store_dword v[2:3], v0 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_test_v2i16_x_add_neg_negfptwo: ; GFX9-LABEL: v_test_v2i16_x_add_neg_negfptwo:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
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llvm/test/CodeGen/AMDGPU/sign_extend.ll

Show First 20 Lines • Show All 393 Lines • ▼ Show 20 Lines
; FIXME: need to optimize same sequence as above test to avoid ; FIXME: need to optimize same sequence as above test to avoid
; this shift. ; this shift.
define amdgpu_kernel void @v_sext_v4i8_to_v4i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { define amdgpu_kernel void @v_sext_v4i8_to_v4i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
; SI-LABEL: v_sext_v4i8_to_v4i32: ; SI-LABEL: v_sext_v4i8_to_v4i32:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_mov_b32 s10, s2
; SI-NEXT: s_mov_b32 s11, s3
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s8, s6
; SI-NEXT: s_mov_b32 s9, s7
; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0
; SI-NEXT: s_mov_b32 s0, s4 ; SI-NEXT: s_mov_b32 s0, s4
; SI-NEXT: s_mov_b32 s1, s5 ; SI-NEXT: s_mov_b32 s1, s5
; SI-NEXT: s_mov_b32 s4, s6
; SI-NEXT: s_mov_b32 s5, s7
; SI-NEXT: s_mov_b32 s6, s2
; SI-NEXT: s_mov_b32 s7, s3
; SI-NEXT: buffer_load_dword v0, off, s[4:7], 0
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_ashrrev_i32_e32 v1, 24, v0 ; SI-NEXT: v_ashrrev_i32_e32 v1, 24, v0
; SI-NEXT: v_bfe_i32 v2, v0, 16, 8 ; SI-NEXT: v_bfe_i32 v2, v0, 16, 8
; SI-NEXT: v_bfe_i32 v3, v0, 8, 8 ; SI-NEXT: v_bfe_i32 v3, v0, 8, 8
; SI-NEXT: v_bfe_i32 v0, v0, 0, 8 ; SI-NEXT: v_bfe_i32 v0, v0, 0, 8
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: buffer_store_dword v3, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v3, off, s[0:3], 0
; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0
; SI-NEXT: buffer_store_dword v1, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v1, off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: v_sext_v4i8_to_v4i32: ; VI-LABEL: v_sext_v4i8_to_v4i32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_mov_b32 s10, s2
; VI-NEXT: s_mov_b32 s11, s3
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s8, s6
; VI-NEXT: s_mov_b32 s9, s7
; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: s_mov_b32 s0, s4
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s1, s5
; VI-NEXT: s_mov_b32 s4, s6
; VI-NEXT: s_mov_b32 s5, s7
; VI-NEXT: s_mov_b32 s6, s2
; VI-NEXT: s_mov_b32 s7, s3
; VI-NEXT: buffer_load_dword v0, off, s[4:7], 0
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshrrev_b16_e32 v1, 8, v0 ; VI-NEXT: v_lshrrev_b16_e32 v1, 8, v0
; VI-NEXT: v_ashrrev_i32_e32 v2, 24, v0 ; VI-NEXT: v_ashrrev_i32_e32 v2, 24, v0
; VI-NEXT: v_bfe_i32 v3, v0, 16, 8 ; VI-NEXT: v_bfe_i32 v3, v0, 16, 8
; VI-NEXT: v_bfe_i32 v0, v0, 0, 8 ; VI-NEXT: v_bfe_i32 v0, v0, 0, 8
; VI-NEXT: v_bfe_i32 v1, v1, 0, 8 ; VI-NEXT: v_bfe_i32 v1, v1, 0, 8
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: buffer_store_dword v1, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v1, off, s[0:3], 0
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} }
define amdgpu_kernel void @v_sext_v4i16_to_v4i32(i32 addrspace(1)* %out, i64 addrspace(1)* %in) nounwind { define amdgpu_kernel void @v_sext_v4i16_to_v4i32(i32 addrspace(1)* %out, i64 addrspace(1)* %in) nounwind {
; SI-LABEL: v_sext_v4i16_to_v4i32: ; SI-LABEL: v_sext_v4i16_to_v4i32:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_mov_b32 s10, s2
; SI-NEXT: s_mov_b32 s11, s3
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s8, s6
; SI-NEXT: s_mov_b32 s9, s7
; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
; SI-NEXT: s_mov_b32 s0, s4 ; SI-NEXT: s_mov_b32 s0, s4
; SI-NEXT: s_mov_b32 s1, s5 ; SI-NEXT: s_mov_b32 s1, s5
; SI-NEXT: s_mov_b32 s4, s6
; SI-NEXT: s_mov_b32 s5, s7
; SI-NEXT: s_mov_b32 s6, s2
; SI-NEXT: s_mov_b32 s7, s3
; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 0
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_ashr_i64 v[2:3], v[0:1], 48 ; SI-NEXT: v_ashr_i64 v[2:3], v[0:1], 48
; SI-NEXT: v_ashrrev_i32_e32 v3, 16, v0 ; SI-NEXT: v_ashrrev_i32_e32 v3, 16, v0
; SI-NEXT: v_bfe_i32 v0, v0, 0, 16 ; SI-NEXT: v_bfe_i32 v0, v0, 0, 16
; SI-NEXT: v_bfe_i32 v1, v1, 0, 16 ; SI-NEXT: v_bfe_i32 v1, v1, 0, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: buffer_store_dword v3, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v3, off, s[0:3], 0
; SI-NEXT: buffer_store_dword v1, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v1, off, s[0:3], 0
; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: v_sext_v4i16_to_v4i32: ; VI-LABEL: v_sext_v4i16_to_v4i32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_mov_b32 s10, s2
; VI-NEXT: s_mov_b32 s11, s3
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s8, s6
; VI-NEXT: s_mov_b32 s9, s7
; VI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: s_mov_b32 s0, s4
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s1, s5
; VI-NEXT: s_mov_b32 s4, s6
; VI-NEXT: s_mov_b32 s5, s7
; VI-NEXT: s_mov_b32 s6, s2
; VI-NEXT: s_mov_b32 s7, s3
; VI-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 0
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_ashrrev_i32_e32 v3, 16, v0 ; VI-NEXT: v_ashrrev_i32_e32 v3, 16, v0
; VI-NEXT: v_bfe_i32 v0, v0, 0, 16 ; VI-NEXT: v_bfe_i32 v0, v0, 0, 16
; VI-NEXT: v_ashrrev_i32_e32 v2, 16, v1 ; VI-NEXT: v_ashrrev_i32_e32 v2, 16, v1
; VI-NEXT: v_bfe_i32 v1, v1, 0, 16 ; VI-NEXT: v_bfe_i32 v1, v1, 0, 16
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: buffer_store_dword v3, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v3, off, s[0:3], 0
; VI-NEXT: buffer_store_dword v1, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v1, off, s[0:3], 0
Show All 19 Lines

llvm/test/CodeGen/AMDGPU/sub.v2i16.ll

Show All 24 Lines
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1 ; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: v_test_sub_v2i16: ; VI-LABEL: v_test_sub_v2i16:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s7 ; VI-NEXT: v_mov_b32_e32 v1, s7
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v3, s9 ; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s8, v2 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v0, v[0:1]
; VI-NEXT: flat_load_dword v1, v[2:3] ; VI-NEXT: flat_load_dword v1, v[2:3]
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: s_mov_b32 s7, 0xf000
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s6, -1
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_sub_u16_e32 v2, v0, v1 ; VI-NEXT: v_sub_u16_e32 v2, v0, v1
; VI-NEXT: v_sub_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-NEXT: v_sub_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-NEXT: v_or_b32_e32 v0, v2, v0 ; VI-NEXT: v_or_b32_e32 v0, v2, v0
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid
%gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid %gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid
%gep.in1 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in1, i32 %tid %gep.in1 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in1, i32 %tid
%a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0 %a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0
%b = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in1 %b = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in1
%add = sub <2 x i16> %a, %b %add = sub <2 x i16> %a, %b
Show All 22 Lines
; VI-LABEL: s_test_sub_v2i16: ; VI-LABEL: s_test_sub_v2i16:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34 ; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: s_mov_b32 s0, s4
; VI-NEXT: s_mov_b32 s1, s5
; VI-NEXT: s_load_dword s4, s[6:7], 0x0 ; VI-NEXT: s_load_dword s4, s[6:7], 0x0
; VI-NEXT: s_load_dword s5, s[8:9], 0x0 ; VI-NEXT: s_load_dword s6, s[8:9], 0x0
; VI-NEXT: s_mov_b32 s1, s5
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_lshr_b32 s6, s4, 16 ; VI-NEXT: s_lshr_b32 s5, s4, 16
; VI-NEXT: s_lshr_b32 s7, s5, 16 ; VI-NEXT: s_lshr_b32 s7, s6, 16
; VI-NEXT: s_sub_i32 s4, s4, s5 ; VI-NEXT: s_sub_i32 s4, s4, s6
; VI-NEXT: s_sub_i32 s5, s6, s7 ; VI-NEXT: s_sub_i32 s5, s5, s7
; VI-NEXT: s_and_b32 s4, s4, 0xffff ; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s5, 16 ; VI-NEXT: s_lshl_b32 s5, s5, 16
; VI-NEXT: s_or_b32 s4, s4, s5 ; VI-NEXT: s_or_b32 s4, s4, s5
; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%a = load <2 x i16>, <2 x i16> addrspace(4)* %in0 %a = load <2 x i16>, <2 x i16> addrspace(4)* %in0
%b = load <2 x i16>, <2 x i16> addrspace(4)* %in1 %b = load <2 x i16>, <2 x i16> addrspace(4)* %in1
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
; GFX9-NEXT: s_mov_b32 s1, s5 ; GFX9-NEXT: s_mov_b32 s1, s5
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_pk_sub_i16 v0, v0, s4 ; GFX9-NEXT: v_pk_sub_i16 v0, v0, s4
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: v_test_sub_v2i16_constant: ; VI-LABEL: v_test_sub_v2i16_constant:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; VI-NEXT: v_mov_b32_e32 v2, 0xfffffe38
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s7 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v0, v[0:1]
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: v_mov_b32_e32 v1, 0xfffffe38
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_add_u16_e32 v1, 0xffffff85, v0 ; VI-NEXT: v_add_u16_e32 v2, 0xffffff85, v0
; VI-NEXT: v_add_u16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; VI-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v1, v0 ; VI-NEXT: v_or_b32_e32 v0, v2, v0
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid
%gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid %gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid
%a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0 %a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0
%add = sub <2 x i16> %a, <i16 123, i16 456> %add = sub <2 x i16> %a, <i16 123, i16 456>
store <2 x i16> %add, <2 x i16> addrspace(1)* %out store <2 x i16> %add, <2 x i16> addrspace(1)* %out
Show All 18 Lines
; GFX9-NEXT: s_mov_b32 s1, s5 ; GFX9-NEXT: s_mov_b32 s1, s5
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_pk_sub_i16 v0, v0, s4 ; GFX9-NEXT: v_pk_sub_i16 v0, v0, s4
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: v_test_sub_v2i16_neg_constant: ; VI-LABEL: v_test_sub_v2i16_neg_constant:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; VI-NEXT: v_mov_b32_e32 v2, 0x3df
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s7 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v0, v[0:1]
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: v_mov_b32_e32 v1, 0x3df
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_add_u16_e32 v1, 0x34d, v0 ; VI-NEXT: v_add_u16_e32 v2, 0x34d, v0
; VI-NEXT: v_add_u16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; VI-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v1, v0 ; VI-NEXT: v_or_b32_e32 v0, v2, v0
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid
%gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid %gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid
%a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0 %a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0
%add = sub <2 x i16> %a, <i16 -845, i16 -991> %add = sub <2 x i16> %a, <i16 -845, i16 -991>
store <2 x i16> %add, <2 x i16> addrspace(1)* %out store <2 x i16> %add, <2 x i16> addrspace(1)* %out
Show All 16 Lines
; GFX9-NEXT: s_mov_b32 s1, s5 ; GFX9-NEXT: s_mov_b32 s1, s5
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_pk_sub_i16 v0, v0, -1 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_sub_i16 v0, v0, -1 op_sel_hi:[1,0]
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: v_test_sub_v2i16_inline_neg1: ; VI-LABEL: v_test_sub_v2i16_inline_neg1:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; VI-NEXT: v_mov_b32_e32 v2, 1
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s7 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v0, v[0:1]
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: v_mov_b32_e32 v1, 1
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_add_u16_e32 v1, 1, v0 ; VI-NEXT: v_add_u16_e32 v2, 1, v0
; VI-NEXT: v_add_u16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; VI-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v1, v0 ; VI-NEXT: v_or_b32_e32 v0, v2, v0
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid
%gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid %gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid
%a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0 %a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0
%add = sub <2 x i16> %a, <i16 -1, i16 -1> %add = sub <2 x i16> %a, <i16 -1, i16 -1>
store <2 x i16> %add, <2 x i16> addrspace(1)* %out store <2 x i16> %add, <2 x i16> addrspace(1)* %out
Show All 16 Lines
; GFX9-NEXT: s_mov_b32 s1, s5 ; GFX9-NEXT: s_mov_b32 s1, s5
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_pk_sub_i16 v0, v0, 32 ; GFX9-NEXT: v_pk_sub_i16 v0, v0, 32
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: v_test_sub_v2i16_inline_lo_zero_hi: ; VI-LABEL: v_test_sub_v2i16_inline_lo_zero_hi:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s7 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v0, v[0:1]
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v0 ; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v0
; VI-NEXT: v_subrev_u16_e32 v0, 32, v0 ; VI-NEXT: v_subrev_u16_e32 v0, 32, v0
; VI-NEXT: v_or_b32_e32 v0, v0, v1 ; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines; VI-NEXT: s_endpgm
ret void ret void
} }
; FIXME: Need to handle non-uniform case for function below (load without gep). ; FIXME: Need to handle non-uniform case for function below (load without gep).
define amdgpu_kernel void @v_test_sub_v2i16_zext_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0, <2 x i16> addrspace(1)* %in1) #1 { define amdgpu_kernel void @v_test_sub_v2i16_zext_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0, <2 x i16> addrspace(1)* %in1) #1 {
; GFX9-LABEL: v_test_sub_v2i16_zext_to_v2i32: ; GFX9-LABEL: v_test_sub_v2i16_zext_to_v2i32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, s7 ; GFX9-NEXT: v_mov_b32_e32 v1, s7
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s6, v2 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s6, v2
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: v_mov_b32_e32 v3, s9 ; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s8, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: global_load_dword v0, v[0:1], off ; GFX9-NEXT: global_load_dword v0, v[0:1], off
; GFX9-NEXT: global_load_dword v1, v[2:3], off ; GFX9-NEXT: global_load_dword v1, v[2:3], off
; GFX9-NEXT: s_mov_b32 s0, s4 ; GFX9-NEXT: s_mov_b32 s7, 0xf000
; GFX9-NEXT: s_mov_b32 s1, s5 ; GFX9-NEXT: s_mov_b32 s6, -1
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1 ; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: v_test_sub_v2i16_zext_to_v2i32: ; VI-LABEL: v_test_sub_v2i16_zext_to_v2i32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s7 ; VI-NEXT: v_mov_b32_e32 v1, s7
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v3, s9 ; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s8, v2 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: flat_load_dword v1, v[0:1] ; VI-NEXT: flat_load_dword v1, v[0:1]
; VI-NEXT: flat_load_dword v2, v[2:3] ; VI-NEXT: flat_load_dword v2, v[2:3]
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: s_mov_b32 s7, 0xf000
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s6, -1
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_sub_u16_e32 v0, v1, v2 ; VI-NEXT: v_sub_u16_e32 v0, v1, v2
; VI-NEXT: v_sub_u16_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-NEXT: v_sub_u16_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.out = getelementptr inbounds <2 x i32>, <2 x i32> addrspace(1)* %out, i32 %tid %gep.out = getelementptr inbounds <2 x i32>, <2 x i32> addrspace(1)* %out, i32 %tid
%gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid %gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid
%gep.in1 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in1, i32 %tid %gep.in1 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in1, i32 %tid
%a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0 %a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0
%b = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in1 %b = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in1
%add = sub <2 x i16> %a, %b %add = sub <2 x i16> %a, %b
%ext = zext <2 x i16> %add to <2 x i32> %ext = zext <2 x i16> %add to <2 x i32>
store <2 x i32> %ext, <2 x i32> addrspace(1)* %out store <2 x i32> %ext, <2 x i32> addrspace(1)* %out
ret void ret void
} }
; FIXME: Need to handle non-uniform case for function below (load without gep). ; FIXME: Need to handle non-uniform case for function below (load without gep).
define amdgpu_kernel void @v_test_sub_v2i16_zext_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0, <2 x i16> addrspace(1)* %in1) #1 { define amdgpu_kernel void @v_test_sub_v2i16_zext_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0, <2 x i16> addrspace(1)* %in1) #1 {
; GFX9-LABEL: v_test_sub_v2i16_zext_to_v2i64: ; GFX9-LABEL: v_test_sub_v2i16_zext_to_v2i64:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, s7 ; GFX9-NEXT: v_mov_b32_e32 v1, s7
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s6, v2 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s6, v2
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: v_mov_b32_e32 v3, s9 ; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, s8, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v3, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: global_load_dword v0, v[0:1], off ; GFX9-NEXT: global_load_dword v0, v[0:1], off
; GFX9-NEXT: global_load_dword v1, v[4:5], off ; GFX9-NEXT: global_load_dword v1, v[2:3], off
; GFX9-NEXT: s_mov_b32 s0, s4 ; GFX9-NEXT: s_mov_b32 s7, 0xf000
; GFX9-NEXT: s_mov_b32 s1, s5 ; GFX9-NEXT: s_mov_b32 s6, -1
; GFX9-NEXT: v_mov_b32_e32 v3, 0 ; GFX9-NEXT: v_mov_b32_e32 v3, 0
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_pk_sub_i16 v1, v0, v1 ; GFX9-NEXT: v_pk_sub_i16 v1, v0, v1
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v1 ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v1 ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: v_test_sub_v2i16_zext_to_v2i64: ; VI-LABEL: v_test_sub_v2i16_zext_to_v2i64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s7 ; VI-NEXT: v_mov_b32_e32 v1, s7
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v3, s9 ; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s8, v2 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: flat_load_dword v4, v[0:1] ; VI-NEXT: flat_load_dword v4, v[0:1]
; VI-NEXT: flat_load_dword v2, v[2:3] ; VI-NEXT: flat_load_dword v2, v[2:3]
; VI-NEXT: v_mov_b32_e32 v1, 0 ; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: s_mov_b32 s7, 0xf000
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s6, -1
; VI-NEXT: v_mov_b32_e32 v3, v1 ; VI-NEXT: v_mov_b32_e32 v3, v1
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_sub_u16_e32 v0, v4, v2 ; VI-NEXT: v_sub_u16_e32 v0, v4, v2
; VI-NEXT: v_sub_u16_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-NEXT: v_sub_u16_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.out = getelementptr inbounds <2 x i64>, <2 x i64> addrspace(1)* %out, i32 %tid %gep.out = getelementptr inbounds <2 x i64>, <2 x i64> addrspace(1)* %out, i32 %tid
%gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid %gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid
%gep.in1 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in1, i32 %tid %gep.in1 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in1, i32 %tid
%a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0 %a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0
%b = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in1 %b = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in1
%add = sub <2 x i16> %a, %b %add = sub <2 x i16> %a, %b
%ext = zext <2 x i16> %add to <2 x i64> %ext = zext <2 x i16> %add to <2 x i64>
store <2 x i64> %ext, <2 x i64> addrspace(1)* %out store <2 x i64> %ext, <2 x i64> addrspace(1)* %out
ret void ret void
} }
; FIXME: Need to handle non-uniform case for function below (load without gep). ; FIXME: Need to handle non-uniform case for function below (load without gep).
define amdgpu_kernel void @v_test_sub_v2i16_sext_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0, <2 x i16> addrspace(1)* %in1) #1 { define amdgpu_kernel void @v_test_sub_v2i16_sext_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0, <2 x i16> addrspace(1)* %in1) #1 {
; GFX9-LABEL: v_test_sub_v2i16_sext_to_v2i32: ; GFX9-LABEL: v_test_sub_v2i16_sext_to_v2i32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, s7 ; GFX9-NEXT: v_mov_b32_e32 v1, s7
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s6, v2 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s6, v2
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: v_mov_b32_e32 v3, s9 ; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s8, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: global_load_dword v0, v[0:1], off ; GFX9-NEXT: global_load_dword v0, v[0:1], off
; GFX9-NEXT: global_load_dword v1, v[2:3], off ; GFX9-NEXT: global_load_dword v1, v[2:3], off
; GFX9-NEXT: s_mov_b32 s0, s4 ; GFX9-NEXT: s_mov_b32 s7, 0xf000
; GFX9-NEXT: s_mov_b32 s1, s5 ; GFX9-NEXT: s_mov_b32 s6, -1
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1 ; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 16, v0 ; GFX9-NEXT: v_ashrrev_i32_e32 v1, 16, v0
; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 16 ; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: v_test_sub_v2i16_sext_to_v2i32: ; VI-LABEL: v_test_sub_v2i16_sext_to_v2i32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s7 ; VI-NEXT: v_mov_b32_e32 v1, s7
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v3, s9 ; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s8, v2 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v0, v[0:1]
; VI-NEXT: flat_load_dword v1, v[2:3] ; VI-NEXT: flat_load_dword v1, v[2:3]
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: s_mov_b32 s7, 0xf000
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s6, -1
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_sub_u16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-NEXT: v_sub_u16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-NEXT: v_sub_u16_e32 v0, v0, v1 ; VI-NEXT: v_sub_u16_e32 v0, v0, v1
; VI-NEXT: v_bfe_i32 v0, v0, 0, 16 ; VI-NEXT: v_bfe_i32 v0, v0, 0, 16
; VI-NEXT: v_bfe_i32 v1, v2, 0, 16 ; VI-NEXT: v_bfe_i32 v1, v2, 0, 16
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.out = getelementptr inbounds <2 x i32>, <2 x i32> addrspace(1)* %out, i32 %tid %gep.out = getelementptr inbounds <2 x i32>, <2 x i32> addrspace(1)* %out, i32 %tid
%gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid %gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid
%gep.in1 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in1, i32 %tid %gep.in1 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in1, i32 %tid
%a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0 %a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0
%b = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in1 %b = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in1
%add = sub <2 x i16> %a, %b %add = sub <2 x i16> %a, %b
%ext = sext <2 x i16> %add to <2 x i32> %ext = sext <2 x i16> %add to <2 x i32>
store <2 x i32> %ext, <2 x i32> addrspace(1)* %out store <2 x i32> %ext, <2 x i32> addrspace(1)* %out
ret void ret void
} }
; FIXME: Need to handle non-uniform case for function below (load without gep). ; FIXME: Need to handle non-uniform case for function below (load without gep).
define amdgpu_kernel void @v_test_sub_v2i16_sext_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0, <2 x i16> addrspace(1)* %in1) #1 { define amdgpu_kernel void @v_test_sub_v2i16_sext_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0, <2 x i16> addrspace(1)* %in1) #1 {
; GFX9-LABEL: v_test_sub_v2i16_sext_to_v2i64: ; GFX9-LABEL: v_test_sub_v2i16_sext_to_v2i64:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, s7 ; GFX9-NEXT: v_mov_b32_e32 v1, s7
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s6, v2 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s6, v2
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: v_mov_b32_e32 v3, s9 ; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s8, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: global_load_dword v0, v[0:1], off ; GFX9-NEXT: global_load_dword v0, v[0:1], off
; GFX9-NEXT: global_load_dword v1, v[2:3], off ; GFX9-NEXT: global_load_dword v1, v[2:3], off
; GFX9-NEXT: s_mov_b32 s0, s4 ; GFX9-NEXT: s_mov_b32 s7, 0xf000
; GFX9-NEXT: s_mov_b32 s1, s5 ; GFX9-NEXT: s_mov_b32 s6, -1
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_pk_sub_i16 v1, v0, v1 ; GFX9-NEXT: v_pk_sub_i16 v1, v0, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v1 ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX9-NEXT: v_bfe_i32 v0, v1, 0, 16 ; GFX9-NEXT: v_bfe_i32 v0, v1, 0, 16
; GFX9-NEXT: v_bfe_i32 v2, v2, 0, 16 ; GFX9-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v2 ; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX9-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: v_test_sub_v2i16_sext_to_v2i64: ; VI-LABEL: v_test_sub_v2i16_sext_to_v2i64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s7 ; VI-NEXT: v_mov_b32_e32 v1, s7
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v3, s9 ; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s8, v2 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v0, v[0:1]
; VI-NEXT: flat_load_dword v1, v[2:3] ; VI-NEXT: flat_load_dword v1, v[2:3]
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: s_mov_b32 s7, 0xf000
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s6, -1
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: v_sub_u16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-NEXT: v_sub_u16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-NEXT: v_sub_u16_e32 v0, v0, v1 ; VI-NEXT: v_sub_u16_e32 v0, v0, v1
; VI-NEXT: v_bfe_i32 v0, v0, 0, 16 ; VI-NEXT: v_bfe_i32 v0, v0, 0, 16
; VI-NEXT: v_bfe_i32 v2, v2, 0, 16 ; VI-NEXT: v_bfe_i32 v2, v2, 0, 16
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; VI-NEXT: v_ashrrev_i32_e32 v3, 31, v2 ; VI-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.out = getelementptr inbounds <2 x i64>, <2 x i64> addrspace(1)* %out, i32 %tid %gep.out = getelementptr inbounds <2 x i64>, <2 x i64> addrspace(1)* %out, i32 %tid
%gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid %gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid
%gep.in1 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in1, i32 %tid %gep.in1 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in1, i32 %tid
%a = load <2 x i16>, <2 x i16> addrspace(1)* %gep.in0 %a = load <2 x i16>, <2 x i16> addrspace(1)* %gep.in0
%b = load <2 x i16>, <2 x i16> addrspace(1)* %gep.in1 %b = load <2 x i16>, <2 x i16> addrspace(1)* %gep.in1
%add = sub <2 x i16> %a, %b %add = sub <2 x i16> %a, %b
Show All 9 Lines

llvm/test/CodeGen/AMDGPU/trunc-combine.ll

Show First 20 Lines • Show All 100 Lines • ▼ Show 20 Lines
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: truncate_high_elt_extract_vector: ; VI-LABEL: truncate_high_elt_extract_vector:
; VI: ; %bb.0: ; %bb ; VI: ; %bb.0: ; %bb
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_load_dword s2, s[4:5], 0x0
; VI-NEXT: s_load_dword s3, s[6:7], 0x0
; VI-NEXT: v_mov_b32_e32 v0, s0 ; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: s_load_dword s0, s[4:5], 0x0
; VI-NEXT: s_load_dword s1, s[6:7], 0x0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_sext_i32_i16 s0, s0 ; VI-NEXT: s_sext_i32_i16 s0, s2
; VI-NEXT: s_sext_i32_i16 s1, s1 ; VI-NEXT: s_sext_i32_i16 s1, s3
; VI-NEXT: v_mov_b32_e32 v2, s0 ; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: v_mul_i32_i24_e32 v2, s1, v2 ; VI-NEXT: v_mul_i32_i24_e32 v2, s1, v2
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 ; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; VI-NEXT: flat_store_dword v[0:1], v2 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
bb: bb:
%tmp = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %arg, i64 undef %tmp = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %arg, i64 undef
%tmp3 = load <2 x i16>, <2 x i16> addrspace(1)* %tmp, align 4 %tmp3 = load <2 x i16>, <2 x i16> addrspace(1)* %tmp, align 4
Show All 35 Lines

llvm/test/CodeGen/AMDGPU/udiv64.ll

Show First 20 Lines • Show All 1,818 Lines • ▼ Show 20 Lines; GCN-IR-NEXT: s_endpgm
%result = udiv i64 24, %x.shr %result = udiv i64 24, %x.shr
store i64 %result, i64 addrspace(1)* %out store i64 %result, i64 addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @s_test_udiv24_k_den_i64(i64 addrspace(1)* %out, i64 %x) { define amdgpu_kernel void @s_test_udiv24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
; GCN-LABEL: s_test_udiv24_k_den_i64: ; GCN-LABEL: s_test_udiv24_k_den_i64:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s6, 0x46b6fe00 ; GCN-NEXT: s_lshr_b32 s2, s3, 8
; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2
; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_mov_b32 s2, 0x46b6fe00
; GCN-NEXT: s_lshr_b32 s0, s7, 8 ; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s0 ; GCN-NEXT: s_mov_b32 s5, s1
; GCN-NEXT: s_mov_b32 s0, s4
; GCN-NEXT: s_mov_b32 s1, s5
; GCN-NEXT: v_mul_f32_e32 v1, 0x38331158, v0 ; GCN-NEXT: v_mul_f32_e32 v1, 0x38331158, v0
; GCN-NEXT: v_trunc_f32_e32 v1, v1 ; GCN-NEXT: v_trunc_f32_e32 v1, v1
; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1 ; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1
; GCN-NEXT: v_mad_f32 v0, -v1, s6, v0 ; GCN-NEXT: v_mad_f32 v0, -v1, s2, v0
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s6 ; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s2
; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc ; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0 ; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GCN-IR-LABEL: s_test_udiv24_k_den_i64: ; GCN-IR-LABEL: s_test_udiv24_k_den_i64:
; GCN-IR: ; %bb.0: ; GCN-IR: ; %bb.0:
; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
; GCN-IR-NEXT: s_mov_b32 s6, -1
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_mov_b32 s6, 0x46b6fe00 ; GCN-IR-NEXT: s_lshr_b32 s2, s3, 8
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s2
; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: s_mov_b32 s2, 0x46b6fe00
; GCN-IR-NEXT: s_lshr_b32 s0, s7, 8 ; GCN-IR-NEXT: s_mov_b32 s4, s0
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s0 ; GCN-IR-NEXT: s_mov_b32 s5, s1
; GCN-IR-NEXT: s_mov_b32 s0, s4
; GCN-IR-NEXT: s_mov_b32 s1, s5
; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x38331158, v0 ; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x38331158, v0
; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1 ; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1
; GCN-IR-NEXT: v_mad_f32 v0, -v1, s6, v0 ; GCN-IR-NEXT: v_mad_f32 v0, -v1, s2, v0
; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s6 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s2
; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0 ; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-IR-NEXT: s_endpgm ; GCN-IR-NEXT: s_endpgm
%x.shr = lshr i64 %x, 40 %x.shr = lshr i64 %x, 40
%result = udiv i64 %x.shr, 23423 %result = udiv i64 %x.shr, 23423
store i64 %result, i64 addrspace(1)* %out store i64 %result, i64 addrspace(1)* %out
ret void ret void
} }
define i64 @v_test_udiv24_k_num_i64(i64 %x) { define i64 @v_test_udiv24_k_num_i64(i64 %x) {
▲ Show 20 Lines • Show All 104 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/urem64.ll

Show First 20 Lines • Show All 1,473 Lines • ▼ Show 20 Lines; GCN-IR-NEXT: s_endpgm
%result = urem i64 24, %x.shr %result = urem i64 24, %x.shr
store i64 %result, i64 addrspace(1)* %out store i64 %result, i64 addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @s_test_urem24_k_den_i64(i64 addrspace(1)* %out, i64 %x) { define amdgpu_kernel void @s_test_urem24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
; GCN-LABEL: s_test_urem24_k_den_i64: ; GCN-LABEL: s_test_urem24_k_den_i64:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-NEXT: s_mov_b32 s1, 0x46b6fe00 ; GCN-NEXT: s_mov_b32 s4, 0x46b6fe00
; GCN-NEXT: s_movk_i32 s0, 0x5b7f ; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_lshr_b32 s6, s7, 8 ; GCN-NEXT: s_lshr_b32 s2, s3, 8
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s6 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2
; GCN-NEXT: s_movk_i32 s3, 0x5b7f
; GCN-NEXT: s_mov_b32 s5, s1
; GCN-NEXT: v_mul_f32_e32 v1, 0x38331158, v0 ; GCN-NEXT: v_mul_f32_e32 v1, 0x38331158, v0
; GCN-NEXT: v_trunc_f32_e32 v1, v1 ; GCN-NEXT: v_trunc_f32_e32 v1, v1
; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1 ; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1
; GCN-NEXT: v_mad_f32 v0, -v1, s1, v0 ; GCN-NEXT: v_mad_f32 v0, -v1, s4, v0
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s1 ; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s4
; GCN-NEXT: s_mov_b32 s1, s5 ; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc ; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
; GCN-NEXT: v_mul_lo_u32 v0, v0, s0 ; GCN-NEXT: v_mul_lo_u32 v0, v0, s3
; GCN-NEXT: s_mov_b32 s0, s4
; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: v_sub_i32_e32 v0, vcc, s6, v0 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0 ; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GCN-IR-LABEL: s_test_urem24_k_den_i64: ; GCN-IR-LABEL: s_test_urem24_k_den_i64:
; GCN-IR: ; %bb.0: ; GCN-IR: ; %bb.0:
; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-IR-NEXT: s_mov_b32 s1, 0x46b6fe00 ; GCN-IR-NEXT: s_mov_b32 s4, 0x46b6fe00
; GCN-IR-NEXT: s_movk_i32 s0, 0x5b7f ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s6, -1
; GCN-IR-NEXT: s_mov_b32 s2, -1
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_lshr_b32 s6, s7, 8 ; GCN-IR-NEXT: s_lshr_b32 s2, s3, 8
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s6 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s2
; GCN-IR-NEXT: s_movk_i32 s3, 0x5b7f
; GCN-IR-NEXT: s_mov_b32 s5, s1
; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x38331158, v0 ; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x38331158, v0
; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1 ; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1
; GCN-IR-NEXT: v_mad_f32 v0, -v1, s1, v0 ; GCN-IR-NEXT: v_mad_f32 v0, -v1, s4, v0
; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s1 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s4
; GCN-IR-NEXT: s_mov_b32 s1, s5 ; GCN-IR-NEXT: s_mov_b32 s4, s0
; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s0 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s3
; GCN-IR-NEXT: s_mov_b32 s0, s4
; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s6, v0 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0 ; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-IR-NEXT: s_endpgm ; GCN-IR-NEXT: s_endpgm
%x.shr = lshr i64 %x, 40 %x.shr = lshr i64 %x, 40
%result = urem i64 %x.shr, 23423 %result = urem i64 %x.shr, 23423
store i64 %result, i64 addrspace(1)* %out store i64 %result, i64 addrspace(1)* %out
ret void ret void
} }
define i64 @v_test_urem24_k_num_i64(i64 %x) { define i64 @v_test_urem24_k_num_i64(i64 %x) {
▲ Show 20 Lines • Show All 114 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/v_madak_f16.ll

Show First 20 Lines • Show All 74 Lines • ▼ Show 20 Lines
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s16, s8 ; SI-NEXT: s_mov_b32 s16, s8
; SI-NEXT: s_mov_b32 s17, s9 ; SI-NEXT: s_mov_b32 s17, s9
; SI-NEXT: s_mov_b32 s19, s3 ; SI-NEXT: s_mov_b32 s19, s3
; SI-NEXT: s_mov_b32 s8, s10 ; SI-NEXT: s_mov_b32 s8, s10
; SI-NEXT: s_mov_b32 s9, s11 ; SI-NEXT: s_mov_b32 s9, s11
; SI-NEXT: s_mov_b32 s10, s2 ; SI-NEXT: s_mov_b32 s10, s2
; SI-NEXT: s_mov_b32 s11, s3 ; SI-NEXT: s_mov_b32 s11, s3
; SI-NEXT: buffer_load_ushort v0, off, s[16:19], 0
; SI-NEXT: buffer_load_ushort v1, off, s[8:11], 0
; SI-NEXT: s_mov_b32 s14, s2 ; SI-NEXT: s_mov_b32 s14, s2
; SI-NEXT: s_mov_b32 s15, s3 ; SI-NEXT: s_mov_b32 s15, s3
; SI-NEXT: buffer_load_ushort v3, off, s[12:15], 0 ; SI-NEXT: buffer_load_ushort v0, off, s[16:19], 0
; SI-NEXT: v_mov_b32_e32 v2, 0x41200000 ; SI-NEXT: buffer_load_ushort v1, off, s[8:11], 0
; SI-NEXT: buffer_load_ushort v2, off, s[12:15], 0
; SI-NEXT: v_mov_b32_e32 v3, 0x41200000
; SI-NEXT: s_mov_b32 s0, s4 ; SI-NEXT: s_mov_b32 s0, s4
; SI-NEXT: s_mov_b32 s1, s5 ; SI-NEXT: s_mov_b32 s1, s5
; SI-NEXT: s_mov_b32 s8, s6 ; SI-NEXT: s_mov_b32 s8, s6
; SI-NEXT: s_mov_b32 s9, s7 ; SI-NEXT: s_mov_b32 s9, s7
; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0 ; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1 ; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v3, v3 ; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
; SI-NEXT: v_madak_f32 v1, v0, v1, 0x41200000 ; SI-NEXT: v_madak_f32 v1, v0, v1, 0x41200000
; SI-NEXT: v_mac_f32_e32 v2, v0, v3 ; SI-NEXT: v_mac_f32_e32 v3, v0, v2
; SI-NEXT: v_cvt_f16_f32_e32 v0, v1 ; SI-NEXT: v_cvt_f16_f32_e32 v0, v1
; SI-NEXT: v_cvt_f16_f32_e32 v1, v2 ; SI-NEXT: v_cvt_f16_f32_e32 v1, v3
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
; SI-NEXT: buffer_store_short v1, off, s[8:11], 0 ; SI-NEXT: buffer_store_short v1, off, s[8:11], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: madak_f16_use_2: ; VI-LABEL: madak_f16_use_2:
; VI: ; %bb.0: ; %entry ; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x44 ; VI-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x44
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_mov_b32 s18, s2 ; VI-NEXT: s_mov_b32 s18, s2
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s16, s8 ; VI-NEXT: s_mov_b32 s16, s8
; VI-NEXT: s_mov_b32 s17, s9 ; VI-NEXT: s_mov_b32 s17, s9
; VI-NEXT: s_mov_b32 s19, s3 ; VI-NEXT: s_mov_b32 s19, s3
; VI-NEXT: s_mov_b32 s8, s10 ; VI-NEXT: s_mov_b32 s8, s10
; VI-NEXT: s_mov_b32 s9, s11 ; VI-NEXT: s_mov_b32 s9, s11
; VI-NEXT: s_mov_b32 s10, s2 ; VI-NEXT: s_mov_b32 s10, s2
; VI-NEXT: s_mov_b32 s11, s3 ; VI-NEXT: s_mov_b32 s11, s3
; VI-NEXT: buffer_load_ushort v0, off, s[16:19], 0
; VI-NEXT: buffer_load_ushort v1, off, s[8:11], 0
; VI-NEXT: s_mov_b32 s14, s2 ; VI-NEXT: s_mov_b32 s14, s2
; VI-NEXT: s_mov_b32 s15, s3 ; VI-NEXT: s_mov_b32 s15, s3
; VI-NEXT: buffer_load_ushort v3, off, s[12:15], 0 ; VI-NEXT: buffer_load_ushort v0, off, s[16:19], 0
; VI-NEXT: v_mov_b32_e32 v2, 0x4900 ; VI-NEXT: buffer_load_ushort v1, off, s[8:11], 0
; VI-NEXT: buffer_load_ushort v2, off, s[12:15], 0
; VI-NEXT: v_mov_b32_e32 v3, 0x4900
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: s_mov_b32 s0, s4
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s1, s5
; VI-NEXT: s_mov_b32 s4, s6 ; VI-NEXT: s_mov_b32 s8, s6
; VI-NEXT: s_mov_b32 s5, s7 ; VI-NEXT: s_mov_b32 s9, s7
; VI-NEXT: s_mov_b32 s6, s2
; VI-NEXT: s_mov_b32 s7, s3
; VI-NEXT: s_waitcnt vmcnt(1) ; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_madak_f16 v1, v0, v1, 0x4900 ; VI-NEXT: v_madak_f16 v1, v0, v1, 0x4900
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mac_f16_e32 v2, v0, v3 ; VI-NEXT: v_mac_f16_e32 v3, v0, v2
; VI-NEXT: buffer_store_short v1, off, s[0:3], 0 ; VI-NEXT: buffer_store_short v1, off, s[0:3], 0
; VI-NEXT: buffer_store_short v2, off, s[4:7], 0 ; VI-NEXT: buffer_store_short v3, off, s[8:11], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
half addrspace(1)* %r0, half addrspace(1)* %r0,
half addrspace(1)* %r1, half addrspace(1)* %r1,
half addrspace(1)* %a, half addrspace(1)* %a,
half addrspace(1)* %b, half addrspace(1)* %b,
half addrspace(1)* %c) #0 { half addrspace(1)* %c) #0 {
entry: entry:
%a.val = load volatile half, half addrspace(1)* %a %a.val = load volatile half, half addrspace(1)* %a
Show All 14 Lines

llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll

Show All 30 Lines; GCN-NEXT: s_endpgm
ret void ret void
} }
define amdgpu_kernel void @extract_insert_different_dynelt_v4i32(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in, i32 %val, i32 %idx0, i32 %idx1) #1 { define amdgpu_kernel void @extract_insert_different_dynelt_v4i32(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in, i32 %val, i32 %idx0, i32 %idx1) #1 {
; GCN-LABEL: extract_insert_different_dynelt_v4i32: ; GCN-LABEL: extract_insert_different_dynelt_v4i32:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd ; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
; GCN-NEXT: v_mov_b32_e32 v2, 0 ; GCN-NEXT: v_mov_b32_e32 v5, 0
; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_mov_b32 s2, 0 ; GCN-NEXT: s_mov_b32 s2, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b64 s[0:1], s[6:7] ; GCN-NEXT: s_mov_b64 s[0:1], s[6:7]
; GCN-NEXT: v_lshlrev_b32_e32 v1, 4, v0 ; GCN-NEXT: v_lshlrev_b32_e32 v4, 4, v0
; GCN-NEXT: v_lshlrev_b32_e32 v4, 2, v0 ; GCN-NEXT: buffer_load_dwordx4 v[1:4], v[4:5], s[0:3], 0 addr64
; GCN-NEXT: v_mov_b32_e32 v5, v2 ; GCN-NEXT: v_lshlrev_b32_e32 v6, 2, v0
; GCN-NEXT: buffer_load_dwordx4 v[0:3], v[1:2], s[0:3], 0 addr64 ; GCN-NEXT: v_mov_b32_e32 v0, s8
; GCN-NEXT: v_mov_b32_e32 v6, s8
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s9, 3 ; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s9, 3
; GCN-NEXT: v_mov_b32_e32 v7, v5
; GCN-NEXT: s_mov_b64 s[6:7], s[2:3] ; GCN-NEXT: s_mov_b64 s[6:7], s[2:3]
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc ; GCN-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s9, 2 ; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s9, 2
; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc ; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s9, 1 ; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s9, 1
; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc ; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s9, 0 ; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s9, 0
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s10, 1 ; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s10, 1
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s10, 2
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s10, 3 ; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s10, 2
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GCN-NEXT: buffer_store_dword v0, v[4:5], s[4:7], 0 addr64 ; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s10, 3
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GCN-NEXT: buffer_store_dword v0, v[6:7], s[4:7], 0 addr64
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%id.ext = sext i32 %id to i64 %id.ext = sext i32 %id to i64
%gep.in = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %in, i64 %id.ext %gep.in = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %in, i64 %id.ext
%gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %id.ext %gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %id.ext
%vec = load <4 x i32>, <4 x i32> addrspace(1)* %gep.in %vec = load <4 x i32>, <4 x i32> addrspace(1)* %gep.in
%insert = insertelement <4 x i32> %vec, i32 %val, i32 %idx0 %insert = insertelement <4 x i32> %vec, i32 %val, i32 %idx0
%extract = extractelement <4 x i32> %insert, i32 %idx1 %extract = extractelement <4 x i32> %insert, i32 %idx1
▲ Show 20 Lines • Show All 60 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll

Show First 20 Lines • Show All 102 Lines • ▼ Show 20 Lines
} }
define <4 x half> @shuffle_v4f16_35u5(<4 x half> addrspace(1)* %arg0, <4 x half> addrspace(1)* %arg1) { define <4 x half> @shuffle_v4f16_35u5(<4 x half> addrspace(1)* %arg0, <4 x half> addrspace(1)* %arg1) {
; GFX9-LABEL: shuffle_v4f16_35u5: ; GFX9-LABEL: shuffle_v4f16_35u5:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: global_load_dword v2, v[2:3], off ; GFX9-NEXT: global_load_dword v2, v[2:3], off
; GFX9-NEXT: global_load_dword v0, v[0:1], off offset:4 ; GFX9-NEXT: global_load_dword v0, v[0:1], off offset:4
; GFX9-NEXT: v_mov_b32_e32 v3, 0xffff ; GFX9-NEXT: v_mov_b32_e32 v1, 0xffff
; GFX9-NEXT: s_waitcnt vmcnt(1) ; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v2 ; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v2
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_and_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX9-NEXT: v_and_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0 ; GFX9-NEXT: v_lshl_or_b32 v0, v3, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, v2 ; GFX9-NEXT: v_mov_b32_e32 v1, v2
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
%val0 = load <4 x half>, <4 x half> addrspace(1)* %arg0 %val0 = load <4 x half>, <4 x half> addrspace(1)* %arg0
%val1 = load <4 x half>, <4 x half> addrspace(1)* %arg1 %val1 = load <4 x half>, <4 x half> addrspace(1)* %arg1
%shuffle = shufflevector <4 x half> %val0, <4 x half> %val1, <4 x i32> <i32 3, i32 5, i32 undef, i32 5> %shuffle = shufflevector <4 x half> %val0, <4 x half> %val1, <4 x i32> <i32 3, i32 5, i32 undef, i32 5>
ret <4 x half> %shuffle ret <4 x half> %shuffle
} }
define <4 x half> @shuffle_v4f16_357u(<4 x half> addrspace(1)* %arg0, <4 x half> addrspace(1)* %arg1) { define <4 x half> @shuffle_v4f16_357u(<4 x half> addrspace(1)* %arg0, <4 x half> addrspace(1)* %arg1) {
; GFX9-LABEL: shuffle_v4f16_357u: ; GFX9-LABEL: shuffle_v4f16_357u:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: global_load_dwordx2 v[2:3], v[2:3], off ; GFX9-NEXT: global_load_dwordx2 v[2:3], v[2:3], off
; GFX9-NEXT: global_load_dword v0, v[0:1], off offset:4 ; GFX9-NEXT: global_load_dword v0, v[0:1], off offset:4
; GFX9-NEXT: v_mov_b32_e32 v4, 0xffff ; GFX9-NEXT: v_mov_b32_e32 v1, 0xffff
; GFX9-NEXT: s_waitcnt vmcnt(1) ; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_and_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX9-NEXT: v_and_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v3 ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v3
; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0 ; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
%val0 = load <4 x half>, <4 x half> addrspace(1)* %arg0 %val0 = load <4 x half>, <4 x half> addrspace(1)* %arg0
%val1 = load <4 x half>, <4 x half> addrspace(1)* %arg1 %val1 = load <4 x half>, <4 x half> addrspace(1)* %arg1
%shuffle = shufflevector <4 x half> %val0, <4 x half> %val1, <4 x i32> <i32 3, i32 5, i32 7, i32 undef> %shuffle = shufflevector <4 x half> %val0, <4 x half> %val1, <4 x i32> <i32 3, i32 5, i32 7, i32 undef>
ret <4 x half> %shuffle ret <4 x half> %shuffle
} }
▲ Show 20 Lines • Show All 687 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -amdgpu-codegenprepare-widen-constant-loads=0 -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s ; RUN: llc -amdgpu-codegenprepare-widen-constant-loads=0 -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
; RUN: llc -amdgpu-codegenprepare-widen-constant-loads=0 -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s ; RUN: llc -amdgpu-codegenprepare-widen-constant-loads=0 -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
define amdgpu_kernel void @widen_i16_constant_load(i16 addrspace(4)* %arg) { define amdgpu_kernel void @widen_i16_constant_load(i16 addrspace(4)* %arg) {
; SI-LABEL: widen_i16_constant_load: ; SI-LABEL: widen_i16_constant_load:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s4, 0 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s7, 0xf000 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_mov_b32 s5, s4
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_load_dword s0, s[0:1], 0x0 ; SI-NEXT: s_load_dword s1, s[0:1], 0x0
; SI-NEXT: s_mov_b32 s0, 0
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_addk_i32 s0, 0x3e7 ; SI-NEXT: s_addk_i32 s1, 0x3e7
; SI-NEXT: s_or_b32 s0, s0, 4 ; SI-NEXT: s_or_b32 s4, s1, 4
; SI-NEXT: v_mov_b32_e32 v0, s0 ; SI-NEXT: s_mov_b32 s1, s0
; SI-NEXT: buffer_store_short v0, off, s[4:7], 0 ; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: widen_i16_constant_load: ; VI-LABEL: widen_i16_constant_load:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; VI-NEXT: v_mov_b32_e32 v0, 0 ; VI-NEXT: v_mov_b32_e32 v0, 0
; VI-NEXT: v_mov_b32_e32 v1, 0 ; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
Show All 10 Lines; VI-NEXT: s_endpgm
store i16 %or, i16 addrspace(1)* null store i16 %or, i16 addrspace(1)* null
ret void ret void
} }
define amdgpu_kernel void @widen_i16_constant_load_zext_i32(i16 addrspace(4)* %arg) { define amdgpu_kernel void @widen_i16_constant_load_zext_i32(i16 addrspace(4)* %arg) {
; SI-LABEL: widen_i16_constant_load_zext_i32: ; SI-LABEL: widen_i16_constant_load_zext_i32:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s4, 0 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s7, 0xf000 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_mov_b32 s5, s4
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_load_dword s0, s[0:1], 0x0 ; SI-NEXT: s_load_dword s1, s[0:1], 0x0
; SI-NEXT: s_mov_b32 s0, 0
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_and_b32 s0, s0, 0xffff ; SI-NEXT: s_and_b32 s1, s1, 0xffff
; SI-NEXT: s_addk_i32 s0, 0x3e7 ; SI-NEXT: s_addk_i32 s1, 0x3e7
; SI-NEXT: s_or_b32 s0, s0, 4 ; SI-NEXT: s_or_b32 s4, s1, 4
; SI-NEXT: v_mov_b32_e32 v0, s0 ; SI-NEXT: s_mov_b32 s1, s0
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: widen_i16_constant_load_zext_i32: ; VI-LABEL: widen_i16_constant_load_zext_i32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; VI-NEXT: v_mov_b32_e32 v0, 0 ; VI-NEXT: v_mov_b32_e32 v0, 0
; VI-NEXT: v_mov_b32_e32 v1, 0 ; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
Show All 12 Lines; VI-NEXT: s_endpgm
store i32 %or, i32 addrspace(1)* null store i32 %or, i32 addrspace(1)* null
ret void ret void
} }
define amdgpu_kernel void @widen_i16_constant_load_sext_i32(i16 addrspace(4)* %arg) { define amdgpu_kernel void @widen_i16_constant_load_sext_i32(i16 addrspace(4)* %arg) {
; SI-LABEL: widen_i16_constant_load_sext_i32: ; SI-LABEL: widen_i16_constant_load_sext_i32:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s4, 0 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s7, 0xf000 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_mov_b32 s5, s4
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_load_dword s0, s[0:1], 0x0 ; SI-NEXT: s_load_dword s1, s[0:1], 0x0
; SI-NEXT: s_mov_b32 s0, 0
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_sext_i32_i16 s0, s0 ; SI-NEXT: s_sext_i32_i16 s1, s1
; SI-NEXT: s_addk_i32 s0, 0x3e7 ; SI-NEXT: s_addk_i32 s1, 0x3e7
; SI-NEXT: s_or_b32 s0, s0, 4 ; SI-NEXT: s_or_b32 s4, s1, 4
; SI-NEXT: v_mov_b32_e32 v0, s0 ; SI-NEXT: s_mov_b32 s1, s0
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: widen_i16_constant_load_sext_i32: ; VI-LABEL: widen_i16_constant_load_sext_i32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; VI-NEXT: v_mov_b32_e32 v0, 0 ; VI-NEXT: v_mov_b32_e32 v0, 0
; VI-NEXT: v_mov_b32_e32 v1, 0 ; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
Show All 11 Lines; VI-NEXT: s_endpgm
%or = or i32 %add, 4 %or = or i32 %add, 4
store i32 %or, i32 addrspace(1)* null store i32 %or, i32 addrspace(1)* null
ret void ret void
} }
define amdgpu_kernel void @widen_i17_constant_load(i17 addrspace(4)* %arg) { define amdgpu_kernel void @widen_i17_constant_load(i17 addrspace(4)* %arg) {
; SI-LABEL: widen_i17_constant_load: ; SI-LABEL: widen_i17_constant_load:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s0, 0 ; SI-NEXT: s_mov_b32 s0, 0
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_mov_b32 s1, s0 ; SI-NEXT: s_mov_b32 s1, s0
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_load_dword s7, s[8:9], 0x0 ; SI-NEXT: s_load_dword s7, s[6:7], 0x0
; SI-NEXT: s_mov_b32 s4, 2 ; SI-NEXT: s_mov_b32 s4, 2
; SI-NEXT: s_mov_b32 s5, s0 ; SI-NEXT: s_mov_b32 s5, s0
; SI-NEXT: s_mov_b32 s6, s2 ; SI-NEXT: s_mov_b32 s6, s2
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_add_i32 s7, s7, 34 ; SI-NEXT: s_add_i32 s7, s7, 34
; SI-NEXT: s_or_b32 s7, s7, 4 ; SI-NEXT: s_or_b32 s7, s7, 4
; SI-NEXT: s_bfe_u32 s8, s7, 0x10010 ; SI-NEXT: s_bfe_u32 s8, s7, 0x10010
; SI-NEXT: v_mov_b32_e32 v0, s7 ; SI-NEXT: v_mov_b32_e32 v0, s7
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines; VI-NEXT: s_endpgm
store half %add, half addrspace(1)* null store half %add, half addrspace(1)* null
ret void ret void
} }
; FIXME: valu usage on VI ; FIXME: valu usage on VI
define amdgpu_kernel void @widen_v2i8_constant_load(<2 x i8> addrspace(4)* %arg) { define amdgpu_kernel void @widen_v2i8_constant_load(<2 x i8> addrspace(4)* %arg) {
; SI-LABEL: widen_v2i8_constant_load: ; SI-LABEL: widen_v2i8_constant_load:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s4, 0 ; SI-NEXT: s_mov_b32 s0, 0
; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_mov_b32 s5, s4
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_load_dword s0, s[0:1], 0x0 ; SI-NEXT: s_load_dword s1, s[2:3], 0x0
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_and_b32 s1, s0, 0xff00 ; SI-NEXT: s_and_b32 s4, s1, 0xff00
; SI-NEXT: s_add_i32 s0, s0, 12 ; SI-NEXT: s_add_i32 s1, s1, 12
; SI-NEXT: s_or_b32 s0, s0, 4 ; SI-NEXT: s_or_b32 s1, s1, 4
; SI-NEXT: s_and_b32 s0, s0, 0xff ; SI-NEXT: s_and_b32 s1, s1, 0xff
; SI-NEXT: s_or_b32 s0, s1, s0 ; SI-NEXT: s_or_b32 s1, s4, s1
; SI-NEXT: s_addk_i32 s0, 0x2c00 ; SI-NEXT: s_addk_i32 s1, 0x2c00
; SI-NEXT: s_or_b32 s0, s0, 0x300 ; SI-NEXT: s_or_b32 s4, s1, 0x300
; SI-NEXT: v_mov_b32_e32 v0, s0 ; SI-NEXT: s_mov_b32 s1, s0
; SI-NEXT: buffer_store_short v0, off, s[4:7], 0 ; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: widen_v2i8_constant_load: ; VI-LABEL: widen_v2i8_constant_load:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; VI-NEXT: v_mov_b32_e32 v0, 44 ; VI-NEXT: v_mov_b32_e32 v0, 44
; VI-NEXT: v_mov_b32_e32 v1, 3 ; VI-NEXT: v_mov_b32_e32 v1, 3
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines; VI-NEXT: s_endpgm
store i16 %or, i16 addrspace(1)* null store i16 %or, i16 addrspace(1)* null
ret void ret void
} }
define amdgpu_kernel void @widen_i1_constant_load(i1 addrspace(4)* %arg) { define amdgpu_kernel void @widen_i1_constant_load(i1 addrspace(4)* %arg) {
; SI-LABEL: widen_i1_constant_load: ; SI-LABEL: widen_i1_constant_load:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s4, 0 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s7, 0xf000 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_mov_b32 s5, s4
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_load_dword s0, s[0:1], 0x0 ; SI-NEXT: s_load_dword s1, s[0:1], 0x0
; SI-NEXT: s_mov_b32 s0, 0
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_and_b32 s0, s0, 1 ; SI-NEXT: s_and_b32 s4, s1, 1
; SI-NEXT: v_mov_b32_e32 v0, s0 ; SI-NEXT: s_mov_b32 s1, s0
; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0 ; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: widen_i1_constant_load: ; VI-LABEL: widen_i1_constant_load:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; VI-NEXT: v_mov_b32_e32 v0, 0 ; VI-NEXT: v_mov_b32_e32 v0, 0
; VI-NEXT: v_mov_b32_e32 v1, 0 ; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_load_dword s0, s[0:1], 0x0 ; VI-NEXT: s_load_dword s0, s[0:1], 0x0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_and_b32 s0, s0, 1 ; VI-NEXT: s_and_b32 s0, s0, 1
; VI-NEXT: v_mov_b32_e32 v2, s0 ; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_byte v[0:1], v2 ; VI-NEXT: flat_store_byte v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%load = load i1, i1 addrspace(4)* %arg, align 4 %load = load i1, i1 addrspace(4)* %arg, align 4
%and = and i1 %load, true %and = and i1 %load, true
store i1 %and, i1 addrspace(1)* null store i1 %and, i1 addrspace(1)* null
ret void ret void
} }
define amdgpu_kernel void @widen_i16_zextload_i64_constant_load(i16 addrspace(4)* %arg) { define amdgpu_kernel void @widen_i16_zextload_i64_constant_load(i16 addrspace(4)* %arg) {
; SI-LABEL: widen_i16_zextload_i64_constant_load: ; SI-LABEL: widen_i16_zextload_i64_constant_load:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s4, 0 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s7, 0xf000 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_mov_b32 s5, s4
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_load_dword s0, s[0:1], 0x0 ; SI-NEXT: s_load_dword s1, s[0:1], 0x0
; SI-NEXT: s_mov_b32 s0, 0
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_and_b32 s0, s0, 0xffff ; SI-NEXT: s_and_b32 s1, s1, 0xffff
; SI-NEXT: s_addk_i32 s0, 0x3e7 ; SI-NEXT: s_addk_i32 s1, 0x3e7
; SI-NEXT: s_or_b32 s0, s0, 4 ; SI-NEXT: s_or_b32 s4, s1, 4
; SI-NEXT: v_mov_b32_e32 v0, s0 ; SI-NEXT: s_mov_b32 s1, s0
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: widen_i16_zextload_i64_constant_load: ; VI-LABEL: widen_i16_zextload_i64_constant_load:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; VI-NEXT: v_mov_b32_e32 v0, 0 ; VI-NEXT: v_mov_b32_e32 v0, 0
; VI-NEXT: v_mov_b32_e32 v1, 0 ; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
Show All 12 Lines; VI-NEXT: s_endpgm
store i32 %or, i32 addrspace(1)* null store i32 %or, i32 addrspace(1)* null
ret void ret void
} }
define amdgpu_kernel void @widen_i1_zext_to_i64_constant_load(i1 addrspace(4)* %arg) { define amdgpu_kernel void @widen_i1_zext_to_i64_constant_load(i1 addrspace(4)* %arg) {
; SI-LABEL: widen_i1_zext_to_i64_constant_load: ; SI-LABEL: widen_i1_zext_to_i64_constant_load:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s4, 0 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s7, 0xf000 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_mov_b32 s5, s4
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_load_dword s0, s[0:1], 0x0 ; SI-NEXT: s_load_dword s1, s[0:1], 0x0
; SI-NEXT: s_mov_b32 s0, 0
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_and_b32 s0, s0, 1 ; SI-NEXT: s_and_b32 s1, s1, 1
; SI-NEXT: s_add_u32 s0, s0, 0x3e7 ; SI-NEXT: s_add_u32 s4, s1, 0x3e7
; SI-NEXT: s_addc_u32 s1, 0, 0 ; SI-NEXT: s_addc_u32 s5, 0, 0
; SI-NEXT: v_mov_b32_e32 v0, s0 ; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s1 ; SI-NEXT: s_mov_b32 s1, s0
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: widen_i1_zext_to_i64_constant_load: ; VI-LABEL: widen_i1_zext_to_i64_constant_load:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; VI-NEXT: v_mov_b32_e32 v0, 0 ; VI-NEXT: v_mov_b32_e32 v0, 0
; VI-NEXT: v_mov_b32_e32 v1, 0 ; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines; VI-NEXT: s_endpgm
store i16 %or, i16 addrspace(1)* null store i16 %or, i16 addrspace(1)* null
ret void ret void
} }
define amdgpu_kernel void @widen_i16_global_invariant_load(i16 addrspace(1)* %arg) { define amdgpu_kernel void @widen_i16_global_invariant_load(i16 addrspace(1)* %arg) {
; SI-LABEL: widen_i16_global_invariant_load: ; SI-LABEL: widen_i16_global_invariant_load:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s4, 0 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s7, 0xf000 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_mov_b32 s5, s4
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_load_dword s0, s[0:1], 0x0 ; SI-NEXT: s_load_dword s1, s[0:1], 0x0
; SI-NEXT: s_mov_b32 s0, 0
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_addk_i32 s0, 0x3e7 ; SI-NEXT: s_addk_i32 s1, 0x3e7
; SI-NEXT: s_or_b32 s0, s0, 1 ; SI-NEXT: s_or_b32 s4, s1, 1
; SI-NEXT: v_mov_b32_e32 v0, s0 ; SI-NEXT: s_mov_b32 s1, s0
; SI-NEXT: buffer_store_short v0, off, s[4:7], 0 ; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: widen_i16_global_invariant_load: ; VI-LABEL: widen_i16_global_invariant_load:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; VI-NEXT: v_mov_b32_e32 v0, 0 ; VI-NEXT: v_mov_b32_e32 v0, 0
; VI-NEXT: v_mov_b32_e32 v1, 0 ; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
Show All 17 Lines

llvm/test/CodeGen/PowerPC/PR33671.ll

Show All 20 Linesentry:
%0 = bitcast i32* %arrayidx to <4 x i32>* %0 = bitcast i32* %arrayidx to <4 x i32>*
%arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2
%1 = bitcast i32* %arrayidx1 to <4 x i32>* %1 = bitcast i32* %arrayidx1 to <4 x i32>*
%2 = load <4 x i32>, <4 x i32>* %1, align 16 %2 = load <4 x i32>, <4 x i32>* %1, align 16
store <4 x i32> %2, <4 x i32>* %0, align 16 store <4 x i32> %2, <4 x i32>* %0, align 16
ret void ret void
; CHECK-LABEL: test2 ; CHECK-LABEL: test2
; CHECK: addi 3, 3, 8 ; CHECK: addi 3, 3, 8
; CHECK: lxvx [[LD:[0-9]+]], 0, 3
; CHECK: addi [[REG:[0-9]+]], 4, 4 ; CHECK: addi [[REG:[0-9]+]], 4, 4
; CHECK: lxvx [[LD:[0-9]+]], 0, 3
; CHECK: stxvx [[LD]], 0, [[REG]] ; CHECK: stxvx [[LD]], 0, [[REG]]
} }

llvm/test/CodeGen/PowerPC/botheightreduce.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -run-pass=machine-scheduler -o - %s | FileCheck %s
---
# Check that machine-scheduler's BotHeightReduce heuristic puts the LD 8 in
# between the final run of MULLDs and the LDXs that feed them, to try to hide
# the latency of the LDXs.
name: test
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: test
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $x3, $x4
; CHECK: [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x4
; CHECK: [[COPY1:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x3
; CHECK: [[ADDI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY1]], 1
; CHECK: [[CMPLDI:%[0-9]+]]:crrc = CMPLDI [[COPY]], 1
; CHECK: [[LI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = LI8 1
; CHECK: [[ISEL8_:%[0-9]+]]:g8rc = ISEL8 [[COPY]], [[LI8_]], [[CMPLDI]].sub_gt
; CHECK: MTCTR8loop [[ISEL8_]], implicit-def dead $ctr8
; CHECK: [[LI8_1:%[0-9]+]]:g8rc = LI8 0
; CHECK: [[LI8_2:%[0-9]+]]:g8rc = LI8 2
; CHECK: [[LI8_3:%[0-9]+]]:g8rc = LI8 3
; CHECK: [[LI8_4:%[0-9]+]]:g8rc = LI8 5
; CHECK: [[LI8_5:%[0-9]+]]:g8rc = LI8 6
; CHECK: [[LI8_6:%[0-9]+]]:g8rc = LI8 7
; CHECK: bb.1:
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK: [[ADDI8_1:%[0-9]+]]:g8rc = ADDI8 [[ADDI8_]], 1
; CHECK: [[LD:%[0-9]+]]:g8rc = LD 0, [[ADDI8_]] :: (load 8)
; CHECK: [[LDX:%[0-9]+]]:g8rc = LDX [[ADDI8_]], [[LI8_]] :: (load 8)
; CHECK: [[LDX1:%[0-9]+]]:g8rc = LDX [[ADDI8_]], [[LI8_3]] :: (load 8)
; CHECK: [[LD1:%[0-9]+]]:g8rc = LD 4, [[ADDI8_]] :: (load 8)
; CHECK: [[LDX2:%[0-9]+]]:g8rc = LDX [[ADDI8_]], [[LI8_4]] :: (load 8)
; CHECK: [[LDX3:%[0-9]+]]:g8rc = LDX [[ADDI8_]], [[LI8_5]] :: (load 8)
; CHECK: [[LDX4:%[0-9]+]]:g8rc = LDX [[ADDI8_]], [[LI8_6]] :: (load 8)
; CHECK: [[LDX5:%[0-9]+]]:g8rc = LDX [[ADDI8_]], [[LI8_2]] :: (load 8)
; CHECK: [[MULLD:%[0-9]+]]:g8rc = MULLD [[LDX]], [[LD]]
; CHECK: [[LD2:%[0-9]+]]:g8rc = LD 8, [[ADDI8_]] :: (load 8)
; CHECK: [[MULLD1:%[0-9]+]]:g8rc = MULLD [[MULLD]], [[LDX5]]
; CHECK: [[MULLD2:%[0-9]+]]:g8rc = MULLD [[MULLD1]], [[LDX1]]
; CHECK: [[MULLD3:%[0-9]+]]:g8rc = MULLD [[MULLD2]], [[LD1]]
; CHECK: [[MULLD4:%[0-9]+]]:g8rc = MULLD [[MULLD3]], [[LDX2]]
; CHECK: [[MULLD5:%[0-9]+]]:g8rc = MULLD [[MULLD4]], [[LDX3]]
; CHECK: [[MULLD6:%[0-9]+]]:g8rc = MULLD [[MULLD5]], [[LDX4]]
; CHECK: [[MADDLD8_:%[0-9]+]]:g8rc = MADDLD8 [[MULLD6]], [[LD2]], [[MADDLD8_]]
; CHECK: [[COPY2:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY [[ADDI8_1]]
; CHECK: BDNZ8 %bb.1, implicit-def dead $ctr8, implicit $ctr8
; CHECK: B %bb.2
; CHECK: bb.2:
bb.0:
liveins: $x3, $x4
%0:g8rc_and_g8rc_nox0 = COPY $x4
%1:g8rc_and_g8rc_nox0 = COPY $x3
%2:g8rc_and_g8rc_nox0 = ADDI8 %1, 1
%3:crrc = CMPLDI %0, 1
%4:g8rc_and_g8rc_nox0 = LI8 1
%5:g8rc = ISEL8 %0, %4, %3.sub_gt
MTCTR8loop %5, implicit-def dead $ctr8
%6:g8rc = LI8 0
%7:g8rc = LI8 2
%8:g8rc = LI8 3
%9:g8rc = LI8 5
%10:g8rc = LI8 6
%11:g8rc = LI8 7
bb.1:
%12:g8rc = ADDI8 %2, 1
%13:g8rc = LD 0, %2 :: (load 8)
%14:g8rc = LDX %2, %4 :: (load 8)
%16:g8rc = LDX %2, %8 :: (load 8)
%17:g8rc = LD 4, %2 :: (load 8)
%18:g8rc = LDX %2, %9 :: (load 8)
%19:g8rc = LDX %2, %10 :: (load 8)
%20:g8rc = LDX %2, %11 :: (load 8)
%21:g8rc = LD 8, %2 :: (load 8)
%22:g8rc = MULLD %14, %13
%15:g8rc = LDX %2, %7 :: (load 8)
%23:g8rc = MULLD %22, %15
%24:g8rc = MULLD %23, %16
%25:g8rc = MULLD %24, %17
%26:g8rc = MULLD %25, %18
%27:g8rc = MULLD %26, %19
%28:g8rc = MULLD %27, %20
%6:g8rc = MADDLD8 %28, %21, %6
%2:g8rc_and_g8rc_nox0 = COPY %12
BDNZ8 %bb.1, implicit-def dead $ctr8, implicit $ctr8
B %bb.2
bb.2:
...

llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll

Show First 20 Lines • Show All 411 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: lxsiwzx v2, r3, r4 ; CHECK-P8-NEXT: lxsiwzx v2, r3, r4
; CHECK-P8-NEXT: lvx v3, 0, r5 ; CHECK-P8-NEXT: lvx v3, 0, r5
; CHECK-P8-NEXT: vperm v2, v4, v2, v3 ; CHECK-P8-NEXT: vperm v2, v4, v2, v3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: no_RAUW_in_combine_during_legalize: ; CHECK-P9-LABEL: no_RAUW_in_combine_during_legalize:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: sldi r4, r4, 2 ; CHECK-P9-NEXT: sldi r4, r4, 2
; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: lxsiwzx v2, r3, r4 ; CHECK-P9-NEXT: lxsiwzx v2, r3, r4
; CHECK-P9-NEXT: addis r3, r2, .LCPI16_0@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI16_0@toc@ha
; CHECK-P9-NEXT: addi r3, r3, .LCPI16_0@toc@l ; CHECK-P9-NEXT: addi r3, r3, .LCPI16_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r3 ; CHECK-P9-NEXT: lxvx v3, 0, r3
; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-NOVSX-LABEL: no_RAUW_in_combine_during_legalize: ; CHECK-NOVSX-LABEL: no_RAUW_in_combine_during_legalize:
; CHECK-NOVSX: # %bb.0: # %entry ; CHECK-NOVSX: # %bb.0: # %entry
; CHECK-NOVSX-NEXT: sldi r4, r4, 2 ; CHECK-NOVSX-NEXT: sldi r4, r4, 2
; CHECK-NOVSX-NEXT: vxor v2, v2, v2 ; CHECK-NOVSX-NEXT: vxor v2, v2, v2
; CHECK-NOVSX-NEXT: lwzx r3, r3, r4 ; CHECK-NOVSX-NEXT: lwzx r3, r3, r4
Show All 18 Lines

llvm/test/CodeGen/PowerPC/dform-adjust.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 < %s | FileCheck %s ; RUN: -mcpu=pwr9 < %s | FileCheck %s
define dso_local i64 @test1(i8* nocapture readonly %p, i32 signext %count) local_unnamed_addr #0 { define dso_local i64 @test1(i8* nocapture readonly %p, i32 signext %count) local_unnamed_addr #0 {
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li 5, -13 ; CHECK-NEXT: li 5, -13
; CHECK-NEXT: lxvx 0, 3, 5
; CHECK-NEXT: li 5, 19
; CHECK-NEXT: lxvx 1, 3, 5
; CHECK-NEXT: li 5, 3
; CHECK-NEXT: li 6, 7 ; CHECK-NEXT: li 6, 7
; CHECK-NEXT: li 7, 11 ; CHECK-NEXT: li 7, 11
; CHECK-NEXT: li 8, 15 ; CHECK-NEXT: li 8, 15
; CHECK-NEXT: mfvsrld 9, 0 ; CHECK-NEXT: lxvx 0, 3, 5
; CHECK-NEXT: ldx 5, 3, 5 ; CHECK-NEXT: li 5, 19
; CHECK-NEXT: ldx 6, 3, 6 ; CHECK-NEXT: ldx 6, 3, 6
; CHECK-NEXT: ldx 7, 3, 7 ; CHECK-NEXT: ldx 7, 3, 7
; CHECK-NEXT: lxvx 1, 3, 5
; CHECK-NEXT: li 5, 3
; CHECK-NEXT: ldx 5, 3, 5
; CHECK-NEXT: ldx 3, 3, 8 ; CHECK-NEXT: ldx 3, 3, 8
; CHECK-NEXT: mfvsrld 9, 0
; CHECK-NEXT: mffprd 8, 0 ; CHECK-NEXT: mffprd 8, 0
; CHECK-NEXT: mfvsrld 10, 1 ; CHECK-NEXT: mfvsrld 10, 1
; CHECK-NEXT: mffprd 11, 1 ; CHECK-NEXT: mffprd 11, 1
; CHECK-NEXT: mulld 8, 9, 8 ; CHECK-NEXT: mulld 8, 9, 8
; CHECK-NEXT: mulld 5, 8, 5 ; CHECK-NEXT: mulld 5, 8, 5
; CHECK-NEXT: mulld 5, 5, 10 ; CHECK-NEXT: mulld 5, 5, 10
; CHECK-NEXT: mulld 5, 5, 11 ; CHECK-NEXT: mulld 5, 5, 11
; CHECK-NEXT: mulld 5, 5, 6 ; CHECK-NEXT: mulld 5, 5, 6
▲ Show 20 Lines • Show All 98 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/extract-and-store.ll

Show First 20 Lines • Show All 502 Lines • ▼ Show 20 Lines
; CHECK-P9-NEXT: li r3, 4 ; CHECK-P9-NEXT: li r3, 4
; CHECK-P9-NEXT: stxsiwx vs34, r5, r3 ; CHECK-P9-NEXT: stxsiwx vs34, r5, r3
; CHECK-P9-NEXT: stfiwx f0, 0, r5 ; CHECK-P9-NEXT: stfiwx f0, 0, r5
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P9-BE-LABEL: test_consecutive_i32: ; CHECK-P9-BE-LABEL: test_consecutive_i32:
; CHECK-P9-BE: # %bb.0: # %entry ; CHECK-P9-BE: # %bb.0: # %entry
; CHECK-P9-BE-NEXT: xxsldwi vs0, vs34, vs34, 3 ; CHECK-P9-BE-NEXT: xxsldwi vs0, vs34, vs34, 3
; CHECK-P9-BE-NEXT: li r3, 4
; CHECK-P9-BE-NEXT: stfiwx f0, 0, r5 ; CHECK-P9-BE-NEXT: stfiwx f0, 0, r5
; CHECK-P9-BE-NEXT: xxsldwi vs0, vs34, vs34, 1 ; CHECK-P9-BE-NEXT: xxsldwi vs0, vs34, vs34, 1
; CHECK-P9-BE-NEXT: li r3, 4
; CHECK-P9-BE-NEXT: stfiwx f0, r5, r3 ; CHECK-P9-BE-NEXT: stfiwx f0, r5, r3
; CHECK-P9-BE-NEXT: blr ; CHECK-P9-BE-NEXT: blr
entry: entry:
%vecext = extractelement <4 x i32> %a, i32 0 %vecext = extractelement <4 x i32> %a, i32 0
store i32 %vecext, i32* %b, align 4 store i32 %vecext, i32* %b, align 4
%vecext1 = extractelement <4 x i32> %a, i32 2 %vecext1 = extractelement <4 x i32> %a, i32 2
%arrayidx2 = getelementptr inbounds i32, i32* %b, i64 1 %arrayidx2 = getelementptr inbounds i32, i32* %b, i64 1
Show All 17 Lines
; CHECK-BE-NEXT: li r3, 4 ; CHECK-BE-NEXT: li r3, 4
; CHECK-BE-NEXT: stxsiwx vs34, 0, r5 ; CHECK-BE-NEXT: stxsiwx vs34, 0, r5
; CHECK-BE-NEXT: stfiwx f0, r5, r3 ; CHECK-BE-NEXT: stfiwx f0, r5, r3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-P9-LABEL: test_consecutive_float: ; CHECK-P9-LABEL: test_consecutive_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: xxsldwi vs0, vs34, vs34, 1 ; CHECK-P9-NEXT: xxsldwi vs0, vs34, vs34, 1
; CHECK-P9-NEXT: li r3, 4
; CHECK-P9-NEXT: stfiwx f0, 0, r5 ; CHECK-P9-NEXT: stfiwx f0, 0, r5
; CHECK-P9-NEXT: xxsldwi vs0, vs34, vs34, 3 ; CHECK-P9-NEXT: xxsldwi vs0, vs34, vs34, 3
; CHECK-P9-NEXT: li r3, 4
; CHECK-P9-NEXT: stfiwx f0, r5, r3 ; CHECK-P9-NEXT: stfiwx f0, r5, r3
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P9-BE-LABEL: test_consecutive_float: ; CHECK-P9-BE-LABEL: test_consecutive_float:
; CHECK-P9-BE: # %bb.0: # %entry ; CHECK-P9-BE: # %bb.0: # %entry
; CHECK-P9-BE-NEXT: xxsldwi vs0, vs34, vs34, 2 ; CHECK-P9-BE-NEXT: xxsldwi vs0, vs34, vs34, 2
; CHECK-P9-BE-NEXT: li r3, 4 ; CHECK-P9-BE-NEXT: li r3, 4
; CHECK-P9-BE-NEXT: stxsiwx vs34, 0, r5 ; CHECK-P9-BE-NEXT: stxsiwx vs34, 0, r5
Show All 34 Lines
; CHECK-BE-NEXT: xxsldwi vs0, vs34, vs0, 2 ; CHECK-BE-NEXT: xxsldwi vs0, vs34, vs0, 2
; CHECK-BE-NEXT: stfiwx f1, r5, r4 ; CHECK-BE-NEXT: stfiwx f1, r5, r4
; CHECK-BE-NEXT: stxvw4x vs0, 0, r5 ; CHECK-BE-NEXT: stxvw4x vs0, 0, r5
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-P9-LABEL: test_stores_exceed_vec_size: ; CHECK-P9-LABEL: test_stores_exceed_vec_size:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r3, r2, .LCPI16_0@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI16_0@toc@ha
; CHECK-P9-NEXT: xxsldwi vs0, vs34, vs34, 1
; CHECK-P9-NEXT: addi r3, r3, .LCPI16_0@toc@l ; CHECK-P9-NEXT: addi r3, r3, .LCPI16_0@toc@l
; CHECK-P9-NEXT: lxvx vs35, 0, r3 ; CHECK-P9-NEXT: lxvx vs35, 0, r3
; CHECK-P9-NEXT: xxsldwi vs0, vs34, vs34, 1
; CHECK-P9-NEXT: li r3, 16 ; CHECK-P9-NEXT: li r3, 16
; CHECK-P9-NEXT: stfiwx f0, r5, r3 ; CHECK-P9-NEXT: stfiwx f0, r5, r3
; CHECK-P9-NEXT: li r3, 20 ; CHECK-P9-NEXT: li r3, 20
; CHECK-P9-NEXT: stxsiwx vs34, r5, r3 ; CHECK-P9-NEXT: stxsiwx vs34, r5, r3
; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: stxv vs35, 0(r5) ; CHECK-P9-NEXT: stxv vs35, 0(r5)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P9-BE-LABEL: test_stores_exceed_vec_size: ; CHECK-P9-BE-LABEL: test_stores_exceed_vec_size:
; CHECK-P9-BE: # %bb.0: # %entry ; CHECK-P9-BE: # %bb.0: # %entry
; CHECK-P9-BE-NEXT: xxspltw vs0, vs34, 0 ; CHECK-P9-BE-NEXT: xxspltw vs0, vs34, 0
; CHECK-P9-BE-NEXT: xxsldwi vs0, vs34, vs0, 2
; CHECK-P9-BE-NEXT: li r3, 16 ; CHECK-P9-BE-NEXT: li r3, 16
; CHECK-P9-BE-NEXT: stxsiwx vs34, r5, r3 ; CHECK-P9-BE-NEXT: stxsiwx vs34, r5, r3
; CHECK-P9-BE-NEXT: li r3, 20 ; CHECK-P9-BE-NEXT: li r3, 20
; CHECK-P9-BE-NEXT: xxsldwi vs0, vs34, vs0, 2
; CHECK-P9-BE-NEXT: stxv vs0, 0(r5) ; CHECK-P9-BE-NEXT: stxv vs0, 0(r5)
; CHECK-P9-BE-NEXT: xxsldwi vs0, vs34, vs34, 1 ; CHECK-P9-BE-NEXT: xxsldwi vs0, vs34, vs34, 1
; CHECK-P9-BE-NEXT: stfiwx f0, r5, r3 ; CHECK-P9-BE-NEXT: stfiwx f0, r5, r3
; CHECK-P9-BE-NEXT: blr ; CHECK-P9-BE-NEXT: blr
entry: entry:
%vecext = extractelement <4 x i32> %a, i32 2 %vecext = extractelement <4 x i32> %a, i32 2
store i32 %vecext, i32* %b, align 4 store i32 %vecext, i32* %b, align 4
%vecext1 = extractelement <4 x i32> %a, i32 3 %vecext1 = extractelement <4 x i32> %a, i32 3
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; CHECK-BE-NEXT: stb r4, 2(r5) ; CHECK-BE-NEXT: stb r4, 2(r5)
; CHECK-BE-NEXT: stb r6, 3(r5) ; CHECK-BE-NEXT: stb r6, 3(r5)
; CHECK-BE-NEXT: stb r3, 4(r5) ; CHECK-BE-NEXT: stb r3, 4(r5)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-P9-LABEL: test_5_consecutive_stores_of_bytes: ; CHECK-P9-LABEL: test_5_consecutive_stores_of_bytes:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: vsldoi v3, v2, v2, 4 ; CHECK-P9-NEXT: vsldoi v3, v2, v2, 4
; CHECK-P9-NEXT: li r3, 1
; CHECK-P9-NEXT: stxsibx vs35, 0, r5 ; CHECK-P9-NEXT: stxsibx vs35, 0, r5
; CHECK-P9-NEXT: vsldoi v3, v2, v2, 12 ; CHECK-P9-NEXT: vsldoi v3, v2, v2, 12
; CHECK-P9-NEXT: li r3, 1
; CHECK-P9-NEXT: stxsibx vs35, r5, r3 ; CHECK-P9-NEXT: stxsibx vs35, r5, r3
; CHECK-P9-NEXT: vsldoi v3, v2, v2, 15 ; CHECK-P9-NEXT: vsldoi v3, v2, v2, 15
; CHECK-P9-NEXT: li r3, 2 ; CHECK-P9-NEXT: li r3, 2
; CHECK-P9-NEXT: stxsibx vs35, r5, r3 ; CHECK-P9-NEXT: stxsibx vs35, r5, r3
; CHECK-P9-NEXT: vsldoi v3, v2, v2, 1 ; CHECK-P9-NEXT: vsldoi v3, v2, v2, 1
; CHECK-P9-NEXT: li r3, 3 ; CHECK-P9-NEXT: li r3, 3
; CHECK-P9-NEXT: vsldoi v2, v2, v2, 2 ; CHECK-P9-NEXT: vsldoi v2, v2, v2, 2
; CHECK-P9-NEXT: stxsibx vs35, r5, r3 ; CHECK-P9-NEXT: stxsibx vs35, r5, r3
; CHECK-P9-NEXT: li r3, 4 ; CHECK-P9-NEXT: li r3, 4
; CHECK-P9-NEXT: stxsibx vs34, r5, r3 ; CHECK-P9-NEXT: stxsibx vs34, r5, r3
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P9-BE-LABEL: test_5_consecutive_stores_of_bytes: ; CHECK-P9-BE-LABEL: test_5_consecutive_stores_of_bytes:
; CHECK-P9-BE: # %bb.0: # %entry ; CHECK-P9-BE: # %bb.0: # %entry
; CHECK-P9-BE-NEXT: vsldoi v3, v2, v2, 13 ; CHECK-P9-BE-NEXT: vsldoi v3, v2, v2, 13
; CHECK-P9-BE-NEXT: li r3, 1
; CHECK-P9-BE-NEXT: stxsibx vs35, 0, r5 ; CHECK-P9-BE-NEXT: stxsibx vs35, 0, r5
; CHECK-P9-BE-NEXT: vsldoi v3, v2, v2, 5 ; CHECK-P9-BE-NEXT: vsldoi v3, v2, v2, 5
; CHECK-P9-BE-NEXT: li r3, 1
; CHECK-P9-BE-NEXT: stxsibx vs35, r5, r3 ; CHECK-P9-BE-NEXT: stxsibx vs35, r5, r3
; CHECK-P9-BE-NEXT: vsldoi v3, v2, v2, 2 ; CHECK-P9-BE-NEXT: vsldoi v3, v2, v2, 2
; CHECK-P9-BE-NEXT: li r3, 2 ; CHECK-P9-BE-NEXT: li r3, 2
; CHECK-P9-BE-NEXT: stxsibx vs35, r5, r3 ; CHECK-P9-BE-NEXT: stxsibx vs35, r5, r3
; CHECK-P9-BE-NEXT: li r3, 3 ; CHECK-P9-BE-NEXT: li r3, 3
; CHECK-P9-BE-NEXT: stxsibx vs34, r5, r3 ; CHECK-P9-BE-NEXT: stxsibx vs34, r5, r3
; CHECK-P9-BE-NEXT: vsldoi v2, v2, v2, 15 ; CHECK-P9-BE-NEXT: vsldoi v2, v2, v2, 15
; CHECK-P9-BE-NEXT: li r3, 4 ; CHECK-P9-BE-NEXT: li r3, 4
▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
; CHECK-P9-NEXT: stxsibx vs35, r5, r3 ; CHECK-P9-NEXT: stxsibx vs35, r5, r3
; CHECK-P9-NEXT: vsldoi v3, v2, v2, 1 ; CHECK-P9-NEXT: vsldoi v3, v2, v2, 1
; CHECK-P9-NEXT: li r3, 3 ; CHECK-P9-NEXT: li r3, 3
; CHECK-P9-NEXT: stxsibx vs35, r5, r3 ; CHECK-P9-NEXT: stxsibx vs35, r5, r3
; CHECK-P9-NEXT: vsldoi v3, v2, v2, 2 ; CHECK-P9-NEXT: vsldoi v3, v2, v2, 2
; CHECK-P9-NEXT: li r3, 4 ; CHECK-P9-NEXT: li r3, 4
; CHECK-P9-NEXT: stxsibx vs35, r5, r3 ; CHECK-P9-NEXT: stxsibx vs35, r5, r3
; CHECK-P9-NEXT: vsldoi v3, v2, v2, 4 ; CHECK-P9-NEXT: vsldoi v3, v2, v2, 4
; CHECK-P9-NEXT: li r3, 5
; CHECK-P9-NEXT: stxsibx vs35, 0, r5 ; CHECK-P9-NEXT: stxsibx vs35, 0, r5
; CHECK-P9-NEXT: vsldoi v3, v2, v2, 8 ; CHECK-P9-NEXT: vsldoi v3, v2, v2, 8
; CHECK-P9-NEXT: li r3, 5
; CHECK-P9-NEXT: stxsibx vs35, r5, r3 ; CHECK-P9-NEXT: stxsibx vs35, r5, r3
; CHECK-P9-NEXT: vsldoi v3, v2, v2, 13 ; CHECK-P9-NEXT: vsldoi v3, v2, v2, 13
; CHECK-P9-NEXT: li r3, 6 ; CHECK-P9-NEXT: li r3, 6
; CHECK-P9-NEXT: stxsibx vs35, r5, r3 ; CHECK-P9-NEXT: stxsibx vs35, r5, r3
; CHECK-P9-NEXT: vsldoi v3, v2, v2, 11 ; CHECK-P9-NEXT: vsldoi v3, v2, v2, 11
; CHECK-P9-NEXT: li r3, 7 ; CHECK-P9-NEXT: li r3, 7
; CHECK-P9-NEXT: stxsibx vs35, r5, r3 ; CHECK-P9-NEXT: stxsibx vs35, r5, r3
; CHECK-P9-NEXT: vsldoi v3, v2, v2, 6 ; CHECK-P9-NEXT: vsldoi v3, v2, v2, 6
Show All 22 Lines
; CHECK-P9-BE-NEXT: stxsibx vs35, r5, r3 ; CHECK-P9-BE-NEXT: stxsibx vs35, r5, r3
; CHECK-P9-BE-NEXT: vsldoi v3, v2, v2, 2 ; CHECK-P9-BE-NEXT: vsldoi v3, v2, v2, 2
; CHECK-P9-BE-NEXT: li r3, 2 ; CHECK-P9-BE-NEXT: li r3, 2
; CHECK-P9-BE-NEXT: stxsibx vs35, r5, r3 ; CHECK-P9-BE-NEXT: stxsibx vs35, r5, r3
; CHECK-P9-BE-NEXT: vsldoi v3, v2, v2, 15 ; CHECK-P9-BE-NEXT: vsldoi v3, v2, v2, 15
; CHECK-P9-BE-NEXT: li r3, 4 ; CHECK-P9-BE-NEXT: li r3, 4
; CHECK-P9-BE-NEXT: stxsibx vs35, r5, r3 ; CHECK-P9-BE-NEXT: stxsibx vs35, r5, r3
; CHECK-P9-BE-NEXT: vsldoi v3, v2, v2, 13 ; CHECK-P9-BE-NEXT: vsldoi v3, v2, v2, 13
; CHECK-P9-BE-NEXT: li r3, 5
; CHECK-P9-BE-NEXT: stxsibx vs35, 0, r5 ; CHECK-P9-BE-NEXT: stxsibx vs35, 0, r5
; CHECK-P9-BE-NEXT: vsldoi v3, v2, v2, 9 ; CHECK-P9-BE-NEXT: vsldoi v3, v2, v2, 9
; CHECK-P9-BE-NEXT: li r3, 5
; CHECK-P9-BE-NEXT: stxsibx vs35, r5, r3 ; CHECK-P9-BE-NEXT: stxsibx vs35, r5, r3
; CHECK-P9-BE-NEXT: vsldoi v3, v2, v2, 4 ; CHECK-P9-BE-NEXT: vsldoi v3, v2, v2, 4
; CHECK-P9-BE-NEXT: li r3, 6 ; CHECK-P9-BE-NEXT: li r3, 6
; CHECK-P9-BE-NEXT: stxsibx vs35, r5, r3 ; CHECK-P9-BE-NEXT: stxsibx vs35, r5, r3
; CHECK-P9-BE-NEXT: vsldoi v3, v2, v2, 6 ; CHECK-P9-BE-NEXT: vsldoi v3, v2, v2, 6
; CHECK-P9-BE-NEXT: li r3, 7 ; CHECK-P9-BE-NEXT: li r3, 7
; CHECK-P9-BE-NEXT: stxsibx vs35, r5, r3 ; CHECK-P9-BE-NEXT: stxsibx vs35, r5, r3
; CHECK-P9-BE-NEXT: vsldoi v3, v2, v2, 11 ; CHECK-P9-BE-NEXT: vsldoi v3, v2, v2, 11
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
; CHECK-P9-NEXT: xxsldwi vs0, vs35, vs35, 1 ; CHECK-P9-NEXT: xxsldwi vs0, vs35, vs35, 1
; CHECK-P9-NEXT: stfiwx f0, 0, r7 ; CHECK-P9-NEXT: stfiwx f0, 0, r7
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P9-BE-LABEL: test_elements_from_two_vec: ; CHECK-P9-BE-LABEL: test_elements_from_two_vec:
; CHECK-P9-BE: # %bb.0: # %entry ; CHECK-P9-BE: # %bb.0: # %entry
; CHECK-P9-BE-NEXT: xxsldwi vs0, vs34, vs34, 3 ; CHECK-P9-BE-NEXT: xxsldwi vs0, vs34, vs34, 3
; CHECK-P9-BE-NEXT: li r3, 4 ; CHECK-P9-BE-NEXT: li r3, 4
; CHECK-P9-BE-NEXT: stfiwx f0, r7, r3
; CHECK-P9-BE-NEXT: stxsiwx vs35, 0, r7 ; CHECK-P9-BE-NEXT: stxsiwx vs35, 0, r7
; CHECK-P9-BE-NEXT: stfiwx f0, r7, r3
; CHECK-P9-BE-NEXT: blr ; CHECK-P9-BE-NEXT: blr
entry: entry:
%vecext = extractelement <4 x i32> %a, i32 0 %vecext = extractelement <4 x i32> %a, i32 0
%arrayidx = getelementptr inbounds i32, i32* %c, i64 1 %arrayidx = getelementptr inbounds i32, i32* %c, i64 1
store i32 %vecext, i32* %arrayidx, align 4 store i32 %vecext, i32* %arrayidx, align 4
%vecext1 = extractelement <4 x i32> %b, i32 1 %vecext1 = extractelement <4 x i32> %b, i32 1
store i32 %vecext1, i32* %c, align 4 store i32 %vecext1, i32* %c, align 4
ret void ret void
Show All 31 Lines
; CHECK-P9-NEXT: stfiwx f0, 0, r9 ; CHECK-P9-NEXT: stfiwx f0, 0, r9
; CHECK-P9-NEXT: xxsldwi vs0, vs36, vs36, 1 ; CHECK-P9-NEXT: xxsldwi vs0, vs36, vs36, 1
; CHECK-P9-NEXT: stfiwx f0, r9, r3 ; CHECK-P9-NEXT: stfiwx f0, r9, r3
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P9-BE-LABEL: test_elements_from_three_vec: ; CHECK-P9-BE-LABEL: test_elements_from_three_vec:
; CHECK-P9-BE: # %bb.0: # %entry ; CHECK-P9-BE: # %bb.0: # %entry
; CHECK-P9-BE-NEXT: xxsldwi vs0, vs34, vs34, 2 ; CHECK-P9-BE-NEXT: xxsldwi vs0, vs34, vs34, 2
; CHECK-P9-BE-NEXT: li r3, 4
; CHECK-P9-BE-NEXT: stfiwx f0, 0, r9 ; CHECK-P9-BE-NEXT: stfiwx f0, 0, r9
; CHECK-P9-BE-NEXT: xxsldwi vs0, vs35, vs35, 1 ; CHECK-P9-BE-NEXT: xxsldwi vs0, vs35, vs35, 1
; CHECK-P9-BE-NEXT: li r3, 4
; CHECK-P9-BE-NEXT: stfiwx f0, r9, r3 ; CHECK-P9-BE-NEXT: stfiwx f0, r9, r3
; CHECK-P9-BE-NEXT: li r3, 8 ; CHECK-P9-BE-NEXT: li r3, 8
; CHECK-P9-BE-NEXT: stxsiwx vs36, r9, r3 ; CHECK-P9-BE-NEXT: stxsiwx vs36, r9, r3
; CHECK-P9-BE-NEXT: blr ; CHECK-P9-BE-NEXT: blr
entry: entry:
%vecext = extractelement <4 x float> %a, i32 3 %vecext = extractelement <4 x float> %a, i32 3
store float %vecext, float* %d, align 4 store float %vecext, float* %d, align 4
%vecext1 = extractelement <4 x float> %b, i32 2 %vecext1 = extractelement <4 x float> %b, i32 2
%arrayidx2 = getelementptr inbounds float, float* %d, i64 1 %arrayidx2 = getelementptr inbounds float, float* %d, i64 1
store float %vecext1, float* %arrayidx2, align 4 store float %vecext1, float* %arrayidx2, align 4
%vecext3 = extractelement <4 x float> %c, i32 1 %vecext3 = extractelement <4 x float> %c, i32 1
%arrayidx4 = getelementptr inbounds float, float* %d, i64 2 %arrayidx4 = getelementptr inbounds float, float* %d, i64 2
store float %vecext3, float* %arrayidx4, align 4 store float %vecext3, float* %arrayidx4, align 4
ret void ret void
} }

llvm/test/CodeGen/PowerPC/f128-aggregates.ll

Show First 20 Lines • Show All 222 Lines • ▼ Show 20 Linesentry:
ret fp128 %0 ret fp128 %0
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define fp128 @testMixedAggregate_03([4 x i128] %sa.coerce) { define fp128 @testMixedAggregate_03([4 x i128] %sa.coerce) {
; CHECK-LABEL: testMixedAggregate_03: ; CHECK-LABEL: testMixedAggregate_03:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK: mtvsrwa v2, r3 ; CHECK: mtvsrwa v2, r3
; CHECK: xscvsdqp v2, v2 ; CHECK-DAG: xscvsdqp v2, v2
; CHECK: mtvsrdd v3, r6, r5 ; CHECK-DAG: mtvsrdd v3, r6, r5
; CHECK: xsaddqp v2, v3, v2 ; CHECK: xsaddqp v2, v3, v2
; CHECK: mtvsrd v[[REG1:[0-9]+]], r10 ; CHECK: mtvsrd v[[REG1:[0-9]+]], r10
; CHECK: xscvsdqp v[[REG:[0-9]+]], v[[REG1]] ; CHECK: xscvsdqp v[[REG:[0-9]+]], v[[REG1]]
; CHECK: xsaddqp v2, v2, v[[REG]] ; CHECK: xsaddqp v2, v2, v[[REG]]
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%sa.coerce.fca.0.extract = extractvalue [4 x i128] %sa.coerce, 0 %sa.coerce.fca.0.extract = extractvalue [4 x i128] %sa.coerce, 0
%sa.sroa.0.0.extract.trunc = trunc i128 %sa.coerce.fca.0.extract to i32 %sa.sroa.0.0.extract.trunc = trunc i128 %sa.coerce.fca.0.extract to i32
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; CHECK-DAG: cmpwi r3, 1 ; CHECK-DAG: cmpwi r3, 1
; CHECK-DAG: std r5, 48(r1) ; CHECK-DAG: std r5, 48(r1)
; CHECK-DAG: addis [[REG:r[0-9]+]], r2, .LCPI17_0@toc@ha ; CHECK-DAG: addis [[REG:r[0-9]+]], r2, .LCPI17_0@toc@ha
; CHECK-DAG: addi [[REG1:r[0-9]+]], [[REG]], .LCPI17_0@toc@l ; CHECK-DAG: addi [[REG1:r[0-9]+]], [[REG]], .LCPI17_0@toc@l
; CHECK-DAG: lxvx v2, 0, [[REG1]] ; CHECK-DAG: lxvx v2, 0, [[REG1]]
; CHECK-NEXT: bltlr cr0 ; CHECK-NEXT: bltlr cr0
; CHECK-NEXT: # %bb.1: # %if.end ; CHECK-NEXT: # %bb.1: # %if.end
; CHECK-NEXT: addi r3, r1, 40 ; CHECK-NEXT: addi r3, r1, 40
; CHECK-NEXT: addi [[REG2:r[0-9]+]], r1, 72
; CHECK-NEXT: lxvx v3, 0, r3 ; CHECK-NEXT: lxvx v3, 0, r3
; CHECK-NEXT: std [[REG2]], -8(r1)
; CHECK-NEXT: xsaddqp v2, v3, v2 ; CHECK-NEXT: xsaddqp v2, v3, v2
; CHECK-NEXT: lxv v3, 16(r3) ; CHECK-NEXT: lxv v3, 16(r3)
; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: addi [[REG2:r[0-9]+]], r1, 72
; CHECK-NEXT: std [[REG2]], -8(r1)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%ap = alloca i8*, align 8 %ap = alloca i8*, align 8
%0 = bitcast i8** %ap to i8* %0 = bitcast i8** %ap to i8*
call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %0) #2 call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %0) #2
%cmp = icmp slt i32 %count, 1 %cmp = icmp slt i32 %count, 1
br i1 %cmp, label %cleanup, label %if.end br i1 %cmp, label %cleanup, label %if.end
Show All 25 Lines

llvm/test/CodeGen/PowerPC/f128-conv.ll

Show First 20 Lines • Show All 438 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @qpConv2dp_03(double* nocapture %res, i32 signext %idx) { define void @qpConv2dp_03(double* nocapture %res, i32 signext %idx) {
; CHECK-LABEL: qpConv2dp_03: ; CHECK-LABEL: qpConv2dp_03:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC7@toc@ha ; CHECK-NEXT: addis r5, r2, .LC7@toc@ha
; CHECK-NEXT: sldi r4, r4, 3
; CHECK-NEXT: ld r5, .LC7@toc@l(r5) ; CHECK-NEXT: ld r5, .LC7@toc@l(r5)
; CHECK-NEXT: lxvx v2, 0, r5 ; CHECK-NEXT: lxvx v2, 0, r5
; CHECK-NEXT: xscvqpdp v2, v2 ; CHECK-NEXT: xscvqpdp v2, v2
; CHECK-NEXT: sldi r4, r4, 3
; CHECK-NEXT: stxsdx v2, r3, r4 ; CHECK-NEXT: stxsdx v2, r3, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = load fp128, fp128* getelementptr inbounds ([4 x fp128], [4 x fp128]* @f128Array, i64 0, i64 0), align 16 %0 = load fp128, fp128* getelementptr inbounds ([4 x fp128], [4 x fp128]* @f128Array, i64 0, i64 0), align 16
%conv = fptrunc fp128 %0 to double %conv = fptrunc fp128 %0 to double
%idxprom = sext i32 %idx to i64 %idxprom = sext i32 %idx to i64
%arrayidx = getelementptr inbounds double, double* %res, i64 %idxprom %arrayidx = getelementptr inbounds double, double* %res, i64 %idxprom
store double %conv, double* %arrayidx, align 8 store double %conv, double* %arrayidx, align 8
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @qpConv2sp_03(float* nocapture %res, i32 signext %idx) { define void @qpConv2sp_03(float* nocapture %res, i32 signext %idx) {
; CHECK-LABEL: qpConv2sp_03: ; CHECK-LABEL: qpConv2sp_03:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC7@toc@ha ; CHECK-NEXT: addis r5, r2, .LC7@toc@ha
; CHECK-NEXT: sldi r4, r4, 2
; CHECK-NEXT: ld r5, .LC7@toc@l(r5) ; CHECK-NEXT: ld r5, .LC7@toc@l(r5)
; CHECK-NEXT: lxv v2, 48(r5) ; CHECK-NEXT: lxv v2, 48(r5)
; CHECK-NEXT: xscvqpdpo v2, v2 ; CHECK-NEXT: xscvqpdpo v2, v2
; CHECK-NEXT: xsrsp f0, v2 ; CHECK-NEXT: xsrsp f0, v2
; CHECK-NEXT: sldi r4, r4, 2
; CHECK-NEXT: stfsx f0, r3, r4 ; CHECK-NEXT: stfsx f0, r3, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = load fp128, fp128* getelementptr inbounds ([4 x fp128], [4 x fp128]* @f128Array, i64 0, i64 3), align 16 %0 = load fp128, fp128* getelementptr inbounds ([4 x fp128], [4 x fp128]* @f128Array, i64 0, i64 3), align 16
%conv = fptrunc fp128 %0 to float %conv = fptrunc fp128 %0 to float
%idxprom = sext i32 %idx to i64 %idxprom = sext i32 %idx to i64
%arrayidx = getelementptr inbounds float, float* %res, i64 %idxprom %arrayidx = getelementptr inbounds float, float* %res, i64 %idxprom
store float %conv, float* %arrayidx, align 4 store float %conv, float* %arrayidx, align 4
▲ Show 20 Lines • Show All 310 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/f128-passByValue.ll

Show First 20 Lines • Show All 147 Lines • ▼ Show 20 Lines
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define fp128 @mixParam_02(fp128 %p1, double %p2, i64* nocapture %p3, define fp128 @mixParam_02(fp128 %p1, double %p2, i64* nocapture %p3,
; CHECK-LABEL: mixParam_02: ; CHECK-LABEL: mixParam_02:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK: lwz r3, 96(r1) ; CHECK: lwz r3, 96(r1)
; CHECK: add r4, r7, r9 ; CHECK: add r4, r7, r9
; CHECK: xscpsgndp v[[REG0:[0-9]+]], f1, f1
; CHECK: add r4, r4, r10 ; CHECK: add r4, r4, r10
; CHECK: xscvdpqp v[[REG0]], v[[REG0]]
; CHECK: add r3, r4, r3 ; CHECK: add r3, r4, r3
; CHECK: clrldi r3, r3, 32 ; CHECK: clrldi r3, r3, 32
; CHECK: std r3, 0(r6) ; CHECK: std r3, 0(r6)
; CHECK: lxv v[[REG1:[0-9]+]], 0(r8) ; CHECK: lxv v[[REG1:[0-9]+]], 0(r8)
; CHECK: xscpsgndp v[[REG0:[0-9]+]], f1, f1
; CHECK: xscvdpqp v[[REG0]], v[[REG0]]
; CHECK: xsaddqp v2, v[[REG1]], v2 ; CHECK: xsaddqp v2, v[[REG1]], v2
; CHECK: xsaddqp v2, v2, v3 ; CHECK: xsaddqp v2, v2, v3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
i16 signext %p4, fp128* nocapture readonly %p5, i16 signext %p4, fp128* nocapture readonly %p5,
i32 signext %p6, i8 zeroext %p7, i32 zeroext %p8) { i32 signext %p6, i8 zeroext %p7, i32 zeroext %p8) {
entry: entry:
%conv = sext i16 %p4 to i32 %conv = sext i16 %p4 to i32
%add = add nsw i32 %conv, %p6 %add = add nsw i32 %conv, %p6
Show All 9 Linesentry:
ret fp128 %add7 ret fp128 %add7
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define fastcc fp128 @mixParam_02f(fp128 %p1, double %p2, i64* nocapture %p3, define fastcc fp128 @mixParam_02f(fp128 %p1, double %p2, i64* nocapture %p3,
; CHECK-LABEL: mixParam_02f: ; CHECK-LABEL: mixParam_02f:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: add r4, r4, r6 ; CHECK-NEXT: add r4, r4, r6
; CHECK-NEXT: xscpsgndp v[[REG0:[0-9]+]], f1, f1
; CHECK-NEXT: add r4, r4, r7 ; CHECK-NEXT: add r4, r4, r7
; CHECK-NEXT: xscvdpqp v[[REG0]], v[[REG0]]
; CHECK-NEXT: add r4, r4, r8 ; CHECK-NEXT: add r4, r4, r8
; CHECK-NEXT: clrldi r4, r4, 32 ; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-DAG: std r4, 0(r3) ; CHECK-DAG: std r4, 0(r3)
; CHECK-DAG: lxv v[[REG1:[0-9]+]], 0(r5) ; CHECK-DAG: lxv v[[REG1:[0-9]+]], 0(r5)
; CHECK-NEXT: xscpsgndp v[[REG0:[0-9]+]], f1, f1
; CHECK-NEXT: xscvdpqp v[[REG0]], v[[REG0]]
; CHECK-NEXT: xsaddqp v2, v[[REG1]], v2 ; CHECK-NEXT: xsaddqp v2, v[[REG1]], v2
; CHECK-NEXT: xsaddqp v2, v2, v[[REG0]] ; CHECK-NEXT: xsaddqp v2, v2, v[[REG0]]
; CHECK-NEXT: blr ; CHECK-NEXT: blr
i16 signext %p4, fp128* nocapture readonly %p5, i16 signext %p4, fp128* nocapture readonly %p5,
i32 signext %p6, i8 zeroext %p7, i32 zeroext %p8) { i32 signext %p6, i8 zeroext %p7, i32 zeroext %p8) {
entry: entry:
%conv = sext i16 %p4 to i32 %conv = sext i16 %p4 to i32
%add = add nsw i32 %conv, %p6 %add = add nsw i32 %conv, %p6
▲ Show 20 Lines • Show All 65 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/float-load-store-pair.ll

Show All 26 Lines
; so the fpr is only used to load/store float argument ; so the fpr is only used to load/store float argument
define signext i32 @test() nounwind { define signext i32 @test() nounwind {
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1) ; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -192(1) ; CHECK-NEXT: stdu 1, -192(1)
; CHECK-NEXT: addis 3, 2, a1@toc@ha ; CHECK-NEXT: addis 3, 2, a1@toc@ha
; CHECK-NEXT: addis 5, 2, a16@toc@ha
; CHECK-NEXT: addis 6, 2, a17@toc@ha
; CHECK-NEXT: addis 4, 2, a15@toc@ha
; CHECK-NEXT: lfd 1, a1@toc@l(3) ; CHECK-NEXT: lfd 1, a1@toc@l(3)
; CHECK-NEXT: addis 3, 2, a2@toc@ha ; CHECK-NEXT: addis 3, 2, a2@toc@ha
; CHECK-NEXT: addi 5, 5, a16@toc@l
; CHECK-NEXT: addi 6, 6, a17@toc@l
; CHECK-NEXT: ld 4, a15@toc@l(4)
; CHECK-NEXT: lfd 2, a2@toc@l(3) ; CHECK-NEXT: lfd 2, a2@toc@l(3)
; CHECK-NEXT: addis 3, 2, a3@toc@ha ; CHECK-NEXT: addis 3, 2, a3@toc@ha
; CHECK-NEXT: lxvx 34, 0, 6
; CHECK-NEXT: lxvx 0, 0, 5
; CHECK-NEXT: li 5, 152
; CHECK-NEXT: lfd 3, a3@toc@l(3) ; CHECK-NEXT: lfd 3, a3@toc@l(3)
; CHECK-NEXT: addis 3, 2, a4@toc@ha ; CHECK-NEXT: addis 3, 2, a4@toc@ha
; CHECK-NEXT: lfd 4, a4@toc@l(3) ; CHECK-NEXT: lfd 4, a4@toc@l(3)
; CHECK-NEXT: addis 3, 2, a5@toc@ha ; CHECK-NEXT: addis 3, 2, a5@toc@ha
; CHECK-NEXT: lfd 5, a5@toc@l(3) ; CHECK-NEXT: lfd 5, a5@toc@l(3)
; CHECK-NEXT: addis 3, 2, a6@toc@ha ; CHECK-NEXT: addis 3, 2, a6@toc@ha
; CHECK-NEXT: lfd 6, a6@toc@l(3) ; CHECK-NEXT: lfd 6, a6@toc@l(3)
; CHECK-NEXT: addis 3, 2, a7@toc@ha ; CHECK-NEXT: addis 3, 2, a7@toc@ha
; CHECK-NEXT: lfd 7, a7@toc@l(3) ; CHECK-NEXT: lfd 7, a7@toc@l(3)
; CHECK-NEXT: addis 3, 2, a8@toc@ha ; CHECK-NEXT: addis 3, 2, a8@toc@ha
; CHECK-NEXT: lfd 8, a8@toc@l(3) ; CHECK-NEXT: lfd 8, a8@toc@l(3)
; CHECK-NEXT: addis 3, 2, a9@toc@ha ; CHECK-NEXT: addis 3, 2, a9@toc@ha
; CHECK-NEXT: lfd 9, a9@toc@l(3) ; CHECK-NEXT: lfd 9, a9@toc@l(3)
; CHECK-NEXT: addis 3, 2, a10@toc@ha ; CHECK-NEXT: addis 3, 2, a10@toc@ha
; CHECK-NEXT: lfd 10, a10@toc@l(3) ; CHECK-NEXT: lfd 10, a10@toc@l(3)
; CHECK-NEXT: addis 3, 2, a11@toc@ha ; CHECK-NEXT: addis 3, 2, a11@toc@ha
; CHECK-NEXT: lfd 11, a11@toc@l(3) ; CHECK-NEXT: lfd 11, a11@toc@l(3)
; CHECK-NEXT: addis 3, 2, a12@toc@ha ; CHECK-NEXT: addis 3, 2, a12@toc@ha
; CHECK-NEXT: addis 5, 2, a16@toc@ha
; CHECK-NEXT: addis 6, 2, a17@toc@ha
; CHECK-NEXT: addi 6, 6, a17@toc@l
; CHECK-NEXT: lxvx 34, 0, 6
; CHECK-NEXT: lfd 12, a12@toc@l(3) ; CHECK-NEXT: lfd 12, a12@toc@l(3)
; CHECK-NEXT: addis 3, 2, a13@toc@ha ; CHECK-NEXT: addis 3, 2, a13@toc@ha
; CHECK-NEXT: addi 5, 5, a16@toc@l
; CHECK-NEXT: addis 4, 2, a15@toc@ha
; CHECK-NEXT: lxvx 0, 0, 5
; CHECK-NEXT: ld 4, a15@toc@l(4)
; CHECK-NEXT: li 5, 152
; CHECK-NEXT: lfd 13, a13@toc@l(3) ; CHECK-NEXT: lfd 13, a13@toc@l(3)
; CHECK-NEXT: addis 3, 2, a14@toc@ha ; CHECK-NEXT: addis 3, 2, a14@toc@ha
; CHECK-NEXT: ld 3, a14@toc@l(3) ; CHECK-NEXT: ld 3, a14@toc@l(3)
; CHECK-NEXT: stxvx 0, 1, 5 ; CHECK-NEXT: stxvx 0, 1, 5
; CHECK-NEXT: std 4, 144(1) ; CHECK-NEXT: std 4, 144(1)
; CHECK-NEXT: std 3, 136(1) ; CHECK-NEXT: std 3, 136(1)
; CHECK-NEXT: bl _Z3fooddddddddddddddd ; CHECK-NEXT: bl _Z3fooddddddddddddddd
; CHECK-NEXT: nop ; CHECK-NEXT: nop
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llvm/test/CodeGen/PowerPC/handle-f16-storage-type.ll

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; CHECK-NEXT: mtfprwz f1, r4 ; CHECK-NEXT: mtfprwz f1, r4
; CHECK-NEXT: xscvhpdp f1, f1 ; CHECK-NEXT: xscvhpdp f1, f1
; CHECK-NEXT: lhz r4, 4(r3) ; CHECK-NEXT: lhz r4, 4(r3)
; CHECK-NEXT: mtfprwz f2, r4 ; CHECK-NEXT: mtfprwz f2, r4
; CHECK-NEXT: xscvhpdp f2, f2 ; CHECK-NEXT: xscvhpdp f2, f2
; CHECK-NEXT: lhz r3, 0(r3) ; CHECK-NEXT: lhz r3, 0(r3)
; CHECK-NEXT: xxmrghd vs0, vs0, vs1 ; CHECK-NEXT: xxmrghd vs0, vs0, vs1
; CHECK-NEXT: mtfprwz f3, r3 ; CHECK-NEXT: mtfprwz f3, r3
; CHECK-NEXT: xvcvdpsp vs35, vs0
; CHECK-NEXT: xscvhpdp f3, f3 ; CHECK-NEXT: xscvhpdp f3, f3
; CHECK-NEXT: xxmrghd vs2, vs2, vs3 ; CHECK-NEXT: xxmrghd vs2, vs2, vs3
; CHECK-NEXT: xvcvdpsp vs34, vs2 ; CHECK-NEXT: xvcvdpsp vs34, vs2
; CHECK-NEXT: xvcvdpsp vs35, vs0
; CHECK-NEXT: vmrgew v2, v3, v2 ; CHECK-NEXT: vmrgew v2, v3, v2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; SOFT-LABEL: test_extend32_vec4: ; SOFT-LABEL: test_extend32_vec4:
; SOFT: # %bb.0: ; SOFT: # %bb.0:
; SOFT-NEXT: mflr r0 ; SOFT-NEXT: mflr r0
; SOFT-NEXT: std r27, -40(r1) # 8-byte Folded Spill ; SOFT-NEXT: std r27, -40(r1) # 8-byte Folded Spill
; SOFT-NEXT: std r28, -32(r1) # 8-byte Folded Spill ; SOFT-NEXT: std r28, -32(r1) # 8-byte Folded Spill
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; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; CHECK-LABEL: test_trunc32_vec4: ; CHECK-LABEL: test_trunc32_vec4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: xxsldwi vs0, vs34, vs34, 3 ; CHECK-NEXT: xxsldwi vs0, vs34, vs34, 3
; CHECK-NEXT: xxsldwi vs1, vs34, vs34, 1
; CHECK-NEXT: xscvspdpn f0, vs0 ; CHECK-NEXT: xscvspdpn f0, vs0
; CHECK-NEXT: xscvspdpn f1, vs1
; CHECK-NEXT: xscvdphp f0, f0 ; CHECK-NEXT: xscvdphp f0, f0
; CHECK-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: xxswapd vs0, vs34 ; CHECK-NEXT: xxswapd vs0, vs34
; CHECK-NEXT: xxsldwi vs1, vs34, vs34, 1
; CHECK-NEXT: xscvspdpn f1, vs1
; CHECK-NEXT: xscvspdpn f0, vs0 ; CHECK-NEXT: xscvspdpn f0, vs0
; CHECK-NEXT: xscvdphp f0, f0 ; CHECK-NEXT: xscvdphp f0, f0
; CHECK-NEXT: xscvdphp f1, f1 ; CHECK-NEXT: xscvdphp f1, f1
; CHECK-NEXT: mffprwz r4, f1 ; CHECK-NEXT: mffprwz r4, f1
; CHECK-NEXT: xscvspdpn f1, vs34 ; CHECK-NEXT: xscvspdpn f1, vs34
; CHECK-NEXT: xscvdphp f1, f1 ; CHECK-NEXT: xscvdphp f1, f1
; CHECK-NEXT: sth r4, 4(r5) ; CHECK-NEXT: sth r4, 4(r5)
; CHECK-NEXT: mffprwz r4, f0 ; CHECK-NEXT: mffprwz r4, f0
; CHECK-NEXT: sth r4, 2(r5)
; CHECK-NEXT: sth r3, 0(r5) ; CHECK-NEXT: sth r3, 0(r5)
; CHECK-NEXT: sth r4, 2(r5)
; CHECK-NEXT: mffprwz r6, f1 ; CHECK-NEXT: mffprwz r6, f1
; CHECK-NEXT: sth r6, 6(r5) ; CHECK-NEXT: sth r6, 6(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; SOFT-LABEL: test_trunc32_vec4: ; SOFT-LABEL: test_trunc32_vec4:
; SOFT: # %bb.0: ; SOFT: # %bb.0:
; SOFT-NEXT: mflr r0 ; SOFT-NEXT: mflr r0
; SOFT-NEXT: std r26, -48(r1) # 8-byte Folded Spill ; SOFT-NEXT: std r26, -48(r1) # 8-byte Folded Spill
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; CHECK-NEXT: xxswapd vs0, vs34 ; CHECK-NEXT: xxswapd vs0, vs34
; CHECK-NEXT: xscvdphp f0, f0 ; CHECK-NEXT: xscvdphp f0, f0
; CHECK-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: xxswapd vs0, vs35 ; CHECK-NEXT: xxswapd vs0, vs35
; CHECK-NEXT: xscvdphp f0, f0 ; CHECK-NEXT: xscvdphp f0, f0
; CHECK-NEXT: xscvdphp f1, vs34 ; CHECK-NEXT: xscvdphp f1, vs34
; CHECK-NEXT: mffprwz r4, f1 ; CHECK-NEXT: mffprwz r4, f1
; CHECK-NEXT: xscvdphp f1, vs35 ; CHECK-NEXT: xscvdphp f1, vs35
; CHECK-NEXT: sth r3, 0(r7)
; CHECK-NEXT: sth r4, 2(r7) ; CHECK-NEXT: sth r4, 2(r7)
; CHECK-NEXT: mffprwz r4, f0 ; CHECK-NEXT: mffprwz r4, f0
; CHECK-NEXT: sth r4, 4(r7) ; CHECK-NEXT: sth r4, 4(r7)
; CHECK-NEXT: sth r3, 0(r7)
; CHECK-NEXT: mffprwz r5, f1 ; CHECK-NEXT: mffprwz r5, f1
; CHECK-NEXT: sth r5, 6(r7) ; CHECK-NEXT: sth r5, 6(r7)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; SOFT-LABEL: test_trunc64_vec4: ; SOFT-LABEL: test_trunc64_vec4:
; SOFT: # %bb.0: ; SOFT: # %bb.0:
; SOFT-NEXT: mflr r0 ; SOFT-NEXT: mflr r0
; SOFT-NEXT: std r26, -48(r1) # 8-byte Folded Spill ; SOFT-NEXT: std r26, -48(r1) # 8-byte Folded Spill
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; P8-NEXT: lfd f31, -8(r1) # 8-byte Folded Reload ; P8-NEXT: lfd f31, -8(r1) # 8-byte Folded Reload
; P8-NEXT: ld r30, -24(r1) # 8-byte Folded Reload ; P8-NEXT: ld r30, -24(r1) # 8-byte Folded Reload
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; CHECK-LABEL: test_sitofp_fadd_i32: ; CHECK-LABEL: test_sitofp_fadd_i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mtfprwa f1, r3 ; CHECK-NEXT: mtfprwa f1, r3
; CHECK-NEXT: xscvsxdsp f1, f1
; CHECK-NEXT: lhz r4, 0(r4) ; CHECK-NEXT: lhz r4, 0(r4)
; CHECK-NEXT: xscvsxdsp f1, f1
; CHECK-NEXT: mtfprwz f0, r4 ; CHECK-NEXT: mtfprwz f0, r4
; CHECK-NEXT: xscvhpdp f0, f0 ; CHECK-NEXT: xscvhpdp f0, f0
; CHECK-NEXT: xscvdphp f1, f1 ; CHECK-NEXT: xscvdphp f1, f1
; CHECK-NEXT: mffprwz r3, f1 ; CHECK-NEXT: mffprwz r3, f1
; CHECK-NEXT: mtfprwz f1, r3 ; CHECK-NEXT: mtfprwz f1, r3
; CHECK-NEXT: xscvhpdp f1, f1 ; CHECK-NEXT: xscvhpdp f1, f1
; CHECK-NEXT: xsaddsp f1, f0, f1 ; CHECK-NEXT: xsaddsp f1, f0, f1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
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llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll

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; CHECK-P8-BE-NEXT: addi r3, r3, .LCPI3_0@toc@l ; CHECK-P8-BE-NEXT: addi r3, r3, .LCPI3_0@toc@l
; CHECK-P8-BE-NEXT: lxvw4x v3, 0, r3 ; CHECK-P8-BE-NEXT: lxvw4x v3, 0, r3
; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
; ;
; CHECK-P9-BE-LABEL: load_swap11: ; CHECK-P9-BE-LABEL: load_swap11:
; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE: # %bb.0:
; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI3_0@toc@ha ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI3_0@toc@ha
; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI3_0@toc@l
; CHECK-P9-BE-NEXT: lxv v2, 0(r4) ; CHECK-P9-BE-NEXT: lxv v2, 0(r4)
; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI3_0@toc@l
; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 ; CHECK-P9-BE-NEXT: lxvx v3, 0, r3
; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-BE-NEXT: blr ; CHECK-P9-BE-NEXT: blr
%v1 = load <4 x i32>, <4 x i32>* %vp1 %v1 = load <4 x i32>, <4 x i32>* %vp1
%v2 = load <4 x i32>, <4 x i32>* %vp2 %v2 = load <4 x i32>, <4 x i32>* %vp2
%v3 = shufflevector <4 x i32> %v1, <4 x i32> %v2, <4 x i32> <i32 7, i32 6, i32 5, i32 4> %v3 = shufflevector <4 x i32> %v1, <4 x i32> %v2, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
ret <4 x i32> %v3 ret <4 x i32> %v3
} }
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; CHECK-P8-BE-NEXT: addi r3, r3, .LCPI5_0@toc@l ; CHECK-P8-BE-NEXT: addi r3, r3, .LCPI5_0@toc@l
; CHECK-P8-BE-NEXT: lxvw4x v3, 0, r3 ; CHECK-P8-BE-NEXT: lxvw4x v3, 0, r3
; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
; ;
; CHECK-P9-BE-LABEL: load_swap21: ; CHECK-P9-BE-LABEL: load_swap21:
; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE: # %bb.0:
; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha
; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI5_0@toc@l
; CHECK-P9-BE-NEXT: lxv v2, 0(r4) ; CHECK-P9-BE-NEXT: lxv v2, 0(r4)
; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI5_0@toc@l
; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 ; CHECK-P9-BE-NEXT: lxvx v3, 0, r3
; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-BE-NEXT: blr ; CHECK-P9-BE-NEXT: blr
%v1 = load <8 x i16>, <8 x i16>* %vp1 %v1 = load <8 x i16>, <8 x i16>* %vp1
%v2 = load <8 x i16>, <8 x i16>* %vp2 %v2 = load <8 x i16>, <8 x i16>* %vp2
%v3 = shufflevector <8 x i16> %v1, <8 x i16> %v2, <8 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8> %v3 = shufflevector <8 x i16> %v1, <8 x i16> %v2, <8 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
ret <8 x i16> %v3 ret <8 x i16> %v3
} }
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; CHECK-P8-BE-NEXT: addi r3, r3, .LCPI10_0@toc@l ; CHECK-P8-BE-NEXT: addi r3, r3, .LCPI10_0@toc@l
; CHECK-P8-BE-NEXT: lxvw4x v3, 0, r3 ; CHECK-P8-BE-NEXT: lxvw4x v3, 0, r3
; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
; ;
; CHECK-P9-BE-LABEL: load_swap51: ; CHECK-P9-BE-LABEL: load_swap51:
; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE: # %bb.0:
; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI10_0@toc@ha ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI10_0@toc@ha
; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI10_0@toc@l
; CHECK-P9-BE-NEXT: lxv v2, 0(r4) ; CHECK-P9-BE-NEXT: lxv v2, 0(r4)
; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI10_0@toc@l
; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 ; CHECK-P9-BE-NEXT: lxvx v3, 0, r3
; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-BE-NEXT: blr ; CHECK-P9-BE-NEXT: blr
%v1 = load <4 x float>, <4 x float>* %vp1 %v1 = load <4 x float>, <4 x float>* %vp1
%v2 = load <4 x float>, <4 x float>* %vp2 %v2 = load <4 x float>, <4 x float>* %vp2
%v3 = shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 7, i32 6, i32 5, i32 4> %v3 = shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
ret <4 x float> %v3 ret <4 x float> %v3
} }
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llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll

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; } ; }
define i64 @test_no_prep(i8* %0, i32 signext %1) { define i64 @test_no_prep(i8* %0, i32 signext %1) {
; CHECK-LABEL: test_no_prep: ; CHECK-LABEL: test_no_prep:
; CHECK: addi r3, r3, 4004 ; CHECK: addi r3, r3, 4004
; CHECK: .LBB0_2: # ; CHECK: .LBB0_2: #
; CHECK-NEXT: ldx r9, r3, r6 ; CHECK-NEXT: ldx r9, r3, r6
; CHECK-NEXT: ldx r10, r3, r7 ; CHECK-NEXT: ldx r10, r3, r7
; CHECK-NEXT: mulld r9, r10, r9
; CHECK-NEXT: ldx r11, r3, r8 ; CHECK-NEXT: ldx r11, r3, r8
; CHECK-NEXT: mulld r9, r9, r11
; CHECK-NEXT: ld r12, 0(r3) ; CHECK-NEXT: ld r12, 0(r3)
; CHECK-NEXT: addi r3, r3, 1 ; CHECK-NEXT: addi r3, r3, 1
; CHECK-NEXT: mulld r9, r10, r9
; CHECK-NEXT: mulld r9, r9, r11
; CHECK-NEXT: maddld r5, r9, r12, r5 ; CHECK-NEXT: maddld r5, r9, r12, r5
; CHECK-NEXT: bdnz .LBB0_2 ; CHECK-NEXT: bdnz .LBB0_2
%3 = sext i32 %1 to i64 %3 = sext i32 %1 to i64
%4 = icmp eq i32 %1, 0 %4 = icmp eq i32 %1, 0
br i1 %4, label %27, label %5 br i1 %4, label %27, label %5
5: ; preds = %2, %5 5: ; preds = %2, %5
%6 = phi i64 [ %25, %5 ], [ 0, %2 ] %6 = phi i64 [ %25, %5 ], [ 0, %2 ]
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; } ; }
define i64 @test_ds_prep(i8* %0, i32 signext %1) { define i64 @test_ds_prep(i8* %0, i32 signext %1) {
; CHECK-LABEL: test_ds_prep: ; CHECK-LABEL: test_ds_prep:
; CHECK: addi r6, r3, 4002 ; CHECK: addi r6, r3, 4002
; CHECK: .LBB1_2: # ; CHECK: .LBB1_2: #
; CHECK-NEXT: ldx r9, r6, r7 ; CHECK-NEXT: ldx r9, r6, r7
; CHECK-NEXT: ld r10, 0(r6) ; CHECK-NEXT: ld r10, 0(r6)
; CHECK-NEXT: mulld r9, r10, r9
; CHECK-NEXT: ldx r11, r6, r5 ; CHECK-NEXT: ldx r11, r6, r5
; CHECK-NEXT: mulld r9, r9, r11
; CHECK-NEXT: addi r8, r6, 1 ; CHECK-NEXT: addi r8, r6, 1
; CHECK-NEXT: ld r6, 4(r6) ; CHECK-NEXT: ld r6, 4(r6)
; CHECK-NEXT: mulld r9, r10, r9
; CHECK-NEXT: mulld r9, r9, r11
; CHECK-NEXT: maddld r3, r9, r6, r3 ; CHECK-NEXT: maddld r3, r9, r6, r3
; CHECK-NEXT: mr r6, r8 ; CHECK-NEXT: mr r6, r8
; CHECK-NEXT: bdnz .LBB1_2 ; CHECK-NEXT: bdnz .LBB1_2
%3 = sext i32 %1 to i64 %3 = sext i32 %1 to i64
%4 = icmp eq i32 %1, 0 %4 = icmp eq i32 %1, 0
br i1 %4, label %27, label %5 br i1 %4, label %27, label %5
5: ; preds = %2, %5 5: ; preds = %2, %5
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;} ;}
define i64 @test_max_number_reminder(i8* %0, i32 signext %1) { define i64 @test_max_number_reminder(i8* %0, i32 signext %1) {
; CHECK-LABEL: test_max_number_reminder: ; CHECK-LABEL: test_max_number_reminder:
; CHECK: addi r9, r3, 4002 ; CHECK: addi r9, r3, 4002
; CHECK: .LBB2_2: # ; CHECK: .LBB2_2: #
; CHECK-NEXT: ldx r12, r9, r6 ; CHECK-NEXT: ldx r12, r9, r6
; CHECK-NEXT: ld r0, 0(r9) ; CHECK-NEXT: ld r0, 0(r9)
; CHECK-NEXT: mulld r12, r0, r12 ; CHECK-NEXT: ldx r30, r9, r5
; CHECK-NEXT: ldx r29, r9, r7
; CHECK-NEXT: addi r11, r9, 1 ; CHECK-NEXT: addi r11, r9, 1
; CHECK-NEXT: ldx r30, r9, r7 ; CHECK-NEXT: mulld r12, r0, r12
; CHECK-NEXT: ld r29, 4(r9) ; CHECK-NEXT: ld r28, 4(r9)
; CHECK-NEXT: ldx r28, r9, r8 ; CHECK-NEXT: ldx r27, r9, r8
; CHECK-NEXT: ld r27, 12(r9) ; CHECK-NEXT: ld r26, 12(r9)
; CHECK-NEXT: ld r26, 8(r9) ; CHECK-NEXT: ld r25, 8(r9)
; CHECK-NEXT: ldx r25, r9, r10 ; CHECK-NEXT: ldx r9, r9, r10
; CHECK-NEXT: ldx r9, r9, r5 ; CHECK-NEXT: mulld r12, r12, r30
; CHECK-NEXT: mulld r9, r12, r9 ; CHECK-NEXT: mulld r12, r12, r29
; CHECK-NEXT: mulld r9, r9, r30 ; CHECK-NEXT: mulld r12, r12, r28
; CHECK-NEXT: mulld r9, r9, r29 ; CHECK-NEXT: mulld r12, r12, r27
; CHECK-NEXT: mulld r9, r9, r28 ; CHECK-NEXT: mulld r12, r12, r26
; CHECK-NEXT: mulld r9, r9, r27 ; CHECK-NEXT: mulld r12, r12, r25
; CHECK-NEXT: mulld r9, r9, r26 ; CHECK-NEXT: maddld r3, r12, r9, r3
; CHECK-NEXT: maddld r3, r9, r25, r3
; CHECK-NEXT: mr r9, r11 ; CHECK-NEXT: mr r9, r11
; CHECK-NEXT: bdnz .LBB2_2 ; CHECK-NEXT: bdnz .LBB2_2
%3 = sext i32 %1 to i64 %3 = sext i32 %1 to i64
%4 = icmp eq i32 %1, 0 %4 = icmp eq i32 %1, 0
br i1 %4, label %47, label %5 br i1 %4, label %47, label %5
5: ; preds = %2, %5 5: ; preds = %2, %5
%6 = phi i64 [ %45, %5 ], [ 0, %2 ] %6 = phi i64 [ %45, %5 ], [ 0, %2 ]
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; } ; }
define dso_local i64 @test_update_ds_prep_interact(i8* %0, i32 signext %1) { define dso_local i64 @test_update_ds_prep_interact(i8* %0, i32 signext %1) {
; CHECK-LABEL: test_update_ds_prep_interact: ; CHECK-LABEL: test_update_ds_prep_interact:
; CHECK: addi r3, r3, 3998 ; CHECK: addi r3, r3, 3998
; CHECK: .LBB3_2: # ; CHECK: .LBB3_2: #
; CHECK-NEXT: ldu r8, 4(r3) ; CHECK-NEXT: ldu r8, 4(r3)
; CHECK-NEXT: ldx r9, r3, r7 ; CHECK-NEXT: ldx r9, r3, r7
; CHECK-NEXT: mulld r8, r8, r9
; CHECK-NEXT: ldx r10, r3, r6 ; CHECK-NEXT: ldx r10, r3, r6
; CHECK-NEXT: mulld r8, r8, r10
; CHECK-NEXT: ld r11, 4(r3) ; CHECK-NEXT: ld r11, 4(r3)
; CHECK-NEXT: mulld r8, r8, r9
; CHECK-NEXT: mulld r8, r8, r10
; CHECK-NEXT: maddld r5, r8, r11, r5 ; CHECK-NEXT: maddld r5, r8, r11, r5
; CHECK-NEXT: bdnz .LBB3_2 ; CHECK-NEXT: bdnz .LBB3_2
%3 = sext i32 %1 to i64 %3 = sext i32 %1 to i64
%4 = icmp eq i32 %1, 0 %4 = icmp eq i32 %1, 0
br i1 %4, label %28, label %5 br i1 %4, label %28, label %5
5: ; preds = %2, %5 5: ; preds = %2, %5
%6 = phi i64 [ %26, %5 ], [ 0, %2 ] %6 = phi i64 [ %26, %5 ], [ 0, %2 ]
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define dso_local i64 @test_ds_multiple_chains(i8* %0, i8* %1, i32 signext %2) { define dso_local i64 @test_ds_multiple_chains(i8* %0, i8* %1, i32 signext %2) {
; CHECK-LABEL: test_ds_multiple_chains: ; CHECK-LABEL: test_ds_multiple_chains:
; CHECK: addi r3, r3, 4001 ; CHECK: addi r3, r3, 4001
; CHECK: addi r4, r4, 4001 ; CHECK: addi r4, r4, 4001
; CHECK: .LBB5_2: # ; CHECK: .LBB5_2: #
; CHECK-NEXT: ld r8, 0(r3) ; CHECK-NEXT: ld r8, 0(r3)
; CHECK-NEXT: ldx r9, r3, r7 ; CHECK-NEXT: ldx r9, r3, r7
; CHECK-NEXT: mulld r8, r9, r8 ; CHECK-NEXT: ld r10, 4(r3)
; CHECK-NEXT: ld r9, 4(r3) ; CHECK-NEXT: ld r11, 8(r3)
; CHECK-NEXT: mulld r8, r8, r9
; CHECK-NEXT: ld r10, 8(r3)
; CHECK-NEXT: addi r3, r3, 1 ; CHECK-NEXT: addi r3, r3, 1
; CHECK-NEXT: mulld r8, r9, r8
; CHECK-NEXT: ld r12, 0(r4)
; CHECK-NEXT: ldx r0, r4, r7
; CHECK-NEXT: ld r30, 4(r4)
; CHECK-NEXT: ld r9, 8(r4)
; CHECK-NEXT: addi r4, r4, 1
; CHECK-NEXT: mulld r8, r8, r10 ; CHECK-NEXT: mulld r8, r8, r10
; CHECK-NEXT: ld r11, 0(r4)
; CHECK-NEXT: mulld r8, r8, r11 ; CHECK-NEXT: mulld r8, r8, r11
; CHECK-NEXT: ldx r12, r4, r7
; CHECK-NEXT: mulld r8, r8, r12 ; CHECK-NEXT: mulld r8, r8, r12
; CHECK-NEXT: ld r0, 4(r4)
; CHECK-NEXT: mulld r8, r8, r0 ; CHECK-NEXT: mulld r8, r8, r0
; CHECK-NEXT: ld r30, 8(r4) ; CHECK-NEXT: mulld r8, r8, r30
; CHECK-NEXT: addi r4, r4, 1 ; CHECK-NEXT: maddld r6, r8, r9, r6
; CHECK-NEXT: maddld r6, r8, r30, r6
; CHECK-NEXT: bdnz .LBB5_2 ; CHECK-NEXT: bdnz .LBB5_2
%4 = sext i32 %2 to i64 %4 = sext i32 %2 to i64
%5 = icmp eq i32 %2, 0 %5 = icmp eq i32 %2, 0
br i1 %5, label %45, label %6 br i1 %5, label %45, label %6
6: ; preds = %3, %6 6: ; preds = %3, %6
%7 = phi i64 [ %43, %6 ], [ 0, %3 ] %7 = phi i64 [ %43, %6 ], [ 0, %3 ]
%8 = phi i64 [ %42, %6 ], [ 0, %3 ] %8 = phi i64 [ %42, %6 ], [ 0, %3 ]
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define float @test_ds_combine_float_int(i8* %0, i32 signext %1) { define float @test_ds_combine_float_int(i8* %0, i32 signext %1) {
; CHECK-LABEL: test_ds_combine_float_int: ; CHECK-LABEL: test_ds_combine_float_int:
; CHECK: addi r3, r3, 4002 ; CHECK: addi r3, r3, 4002
; CHECK: .LBB8_2: # ; CHECK: .LBB8_2: #
; CHECK-NEXT: lfd f4, 0(r3) ; CHECK-NEXT: lfd f4, 0(r3)
; CHECK-NEXT: lfsx f0, r3, r4 ; CHECK-NEXT: lfsx f0, r3, r4
; CHECK-NEXT: xscvuxdsp f4, f4 ; CHECK-NEXT: xscvuxdsp f4, f4
; CHECK-NEXT: lfs f2, 20(r3) ; CHECK-NEXT: lfs f2, 20(r3)
; CHECK-NEXT: xsmulsp f0, f0, f4
; CHECK-NEXT: xsmulsp f0, f2, f0
; CHECK-NEXT: lfs f3, 60(r3) ; CHECK-NEXT: lfs f3, 60(r3)
; CHECK-NEXT: addi r3, r3, 1 ; CHECK-NEXT: addi r3, r3, 1
; CHECK-NEXT: xsmulsp f0, f0, f4
; CHECK-NEXT: xsmulsp f0, f2, f0
; CHECK-NEXT: xsmulsp f0, f3, f0 ; CHECK-NEXT: xsmulsp f0, f3, f0
; CHECK-NEXT: xsaddsp f1, f1, f0 ; CHECK-NEXT: xsaddsp f1, f1, f0
; CHECK-NEXT: bdnz .LBB8_2 ; CHECK-NEXT: bdnz .LBB8_2
%3 = icmp sgt i32 %1, 0 %3 = icmp sgt i32 %1, 0
br i1 %3, label %4, label %29 br i1 %3, label %4, label %29
4: ; preds = %2 4: ; preds = %2
%5 = zext i32 %1 to i64 %5 = zext i32 %1 to i64
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llvm/test/CodeGen/PowerPC/machine-pre.ll

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; CHECK-P9-NEXT: cmplwi r3, 0 ; CHECK-P9-NEXT: cmplwi r3, 0
; CHECK-P9-NEXT: bne cr0, .LBB1_3 ; CHECK-P9-NEXT: bne cr0, .LBB1_3
; CHECK-P9-NEXT: # %bb.6: # %sw.bb ; CHECK-P9-NEXT: # %bb.6: # %sw.bb
; CHECK-P9-NEXT: # ; CHECK-P9-NEXT: #
; CHECK-P9-NEXT: mulli r3, r29, 13 ; CHECK-P9-NEXT: mulli r3, r29, 13
; CHECK-P9-NEXT: b .LBB1_2 ; CHECK-P9-NEXT: b .LBB1_2
; CHECK-P9-NEXT: .LBB1_7: # %while.end ; CHECK-P9-NEXT: .LBB1_7: # %while.end
; CHECK-P9-NEXT: lis r3, -13108 ; CHECK-P9-NEXT: lis r3, -13108
; CHECK-P9-NEXT: ori r3, r3, 52429
; CHECK-P9-NEXT: mullw r3, r28, r3
; CHECK-P9-NEXT: lis r4, 13107 ; CHECK-P9-NEXT: lis r4, 13107
; CHECK-P9-NEXT: ori r3, r3, 52429
; CHECK-P9-NEXT: ori r4, r4, 13108 ; CHECK-P9-NEXT: ori r4, r4, 13108
; CHECK-P9-NEXT: mullw r3, r28, r3
; CHECK-P9-NEXT: cmplw r3, r4 ; CHECK-P9-NEXT: cmplw r3, r4
; CHECK-P9-NEXT: blt cr0, .LBB1_9 ; CHECK-P9-NEXT: blt cr0, .LBB1_9
; CHECK-P9-NEXT: # %bb.8: # %if.then8 ; CHECK-P9-NEXT: # %bb.8: # %if.then8
; CHECK-P9-NEXT: mulli r3, r29, 13 ; CHECK-P9-NEXT: mulli r3, r29, 13
; CHECK-P9-NEXT: mulli r5, r30, 23 ; CHECK-P9-NEXT: mulli r5, r30, 23
; CHECK-P9-NEXT: extsw r4, r28 ; CHECK-P9-NEXT: extsw r4, r28
; CHECK-P9-NEXT: extsw r3, r3 ; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: extsw r5, r5 ; CHECK-P9-NEXT: extsw r5, r5
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llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll

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; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -80(1) ; PC64LE9-NEXT: stdu 1, -80(1)
; PC64LE9-NEXT: lfs 31, 0(3) ; PC64LE9-NEXT: lfs 31, 0(3)
; PC64LE9-NEXT: mr 29, 3 ; PC64LE9-NEXT: mr 29, 3
; PC64LE9-NEXT: li 3, 0 ; PC64LE9-NEXT: li 3, 0
; PC64LE9-NEXT: xxlxor 2, 2, 2 ; PC64LE9-NEXT: xxlxor 2, 2, 2
; PC64LE9-NEXT: xxlxor 4, 4, 4 ; PC64LE9-NEXT: xxlxor 4, 4, 4
; PC64LE9-NEXT: mr 30, 4
; PC64LE9-NEXT: std 3, 8(4) ; PC64LE9-NEXT: std 3, 8(4)
; PC64LE9-NEXT: fmr 1, 31 ; PC64LE9-NEXT: fmr 1, 31
; PC64LE9-NEXT: fmr 3, 31 ; PC64LE9-NEXT: fmr 3, 31
; PC64LE9-NEXT: mr 30, 4
; PC64LE9-NEXT: stfd 31, 0(4) ; PC64LE9-NEXT: stfd 31, 0(4)
; PC64LE9-NEXT: bl __gcc_qadd ; PC64LE9-NEXT: bl __gcc_qadd
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: fmr 3, 1 ; PC64LE9-NEXT: fmr 3, 1
; PC64LE9-NEXT: fmr 4, 2 ; PC64LE9-NEXT: fmr 4, 2
; PC64LE9-NEXT: fmr 30, 1 ; PC64LE9-NEXT: fmr 30, 1
; PC64LE9-NEXT: fmr 29, 2 ; PC64LE9-NEXT: fmr 29, 2
; PC64LE9-NEXT: stfd 2, 24(30) ; PC64LE9-NEXT: stfd 2, 24(30)
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llvm/test/CodeGen/PowerPC/pr45432.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s
%0 = type { double, [0 x %1] } %0 = type { double, [0 x %1] }
%1 = type { i32 } %1 = type { i32 }
@f = external dso_local thread_local local_unnamed_addr global %0, align 8 @f = external dso_local thread_local local_unnamed_addr global %0, align 8
@g = external dso_local local_unnamed_addr global i32, align 4 @g = external dso_local local_unnamed_addr global i32, align 4
; Function Attrs: nounwind ; Function Attrs: nounwind
define dso_local void @h() local_unnamed_addr #0 { define dso_local void @h() local_unnamed_addr #0 {
; CHECK-LABEL: h: ; CHECK-LABEL: h:
; CHECK: # %bb.0: # %bb ; CHECK: # %bb.0: # %bb
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1) ; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -64(1) ; CHECK-NEXT: stdu 1, -64(1)
; CHECK-NEXT: addis 3, 2, g@toc@ha ; CHECK-NEXT: addis 3, 2, g@toc@ha
; CHECK-NEXT: lwz 3, g@toc@l(3)
; CHECK-NEXT: std 30, 48(1) # 8-byte Folded Spill ; CHECK-NEXT: std 30, 48(1) # 8-byte Folded Spill
; CHECK-NEXT: lwz 3, g@toc@l(3)
; CHECK-NEXT: extswsli 30, 3, 2 ; CHECK-NEXT: extswsli 30, 3, 2
; CHECK-NEXT: addis 3, 2, f@got@tlsld@ha ; CHECK-NEXT: addis 3, 2, f@got@tlsld@ha
; CHECK-NEXT: addi 3, 3, f@got@tlsld@l ; CHECK-NEXT: addi 3, 3, f@got@tlsld@l
; CHECK-NEXT: bl __tls_get_addr(f@tlsld) ; CHECK-NEXT: bl __tls_get_addr(f@tlsld)
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addis 3, 3, f@dtprel@ha ; CHECK-NEXT: addis 3, 3, f@dtprel@ha
; CHECK-NEXT: addi 3, 3, f@dtprel@l ; CHECK-NEXT: addi 3, 3, f@dtprel@l
; CHECK-NEXT: add 3, 3, 30 ; CHECK-NEXT: add 3, 3, 30
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llvm/test/CodeGen/PowerPC/pr45448.ll

Show All 14 Lines
; CHECK-NEXT: .LBB0_3: # %fail194 ; CHECK-NEXT: .LBB0_3: # %fail194
; CHECK-NEXT: .LBB0_4: # %L294 ; CHECK-NEXT: .LBB0_4: # %L294
; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB0_6 ; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB0_6
; CHECK-NEXT: # %bb.5: # %L294 ; CHECK-NEXT: # %bb.5: # %L294
; CHECK-NEXT: bc 4, 4*cr5+lt, .LBB0_7 ; CHECK-NEXT: bc 4, 4*cr5+lt, .LBB0_7
; CHECK-NEXT: .LBB0_6: # %L1057.preheader ; CHECK-NEXT: .LBB0_6: # %L1057.preheader
; CHECK-NEXT: .LBB0_7: # %L670 ; CHECK-NEXT: .LBB0_7: # %L670
; CHECK-NEXT: lis r5, 4095 ; CHECK-NEXT: lis r5, 4095
; CHECK-NEXT: ori r5, r5, 65533
; CHECK-NEXT: sldi r5, r5, 4
; CHECK-NEXT: cmpdi r3, 0 ; CHECK-NEXT: cmpdi r3, 0
; CHECK-NEXT: sradi r4, r3, 63 ; CHECK-NEXT: sradi r4, r3, 63
; CHECK-NEXT: ori r5, r5, 65533
; CHECK-NEXT: crnot 4*cr5+gt, eq
; CHECK-NEXT: sldi r5, r5, 4
; CHECK-NEXT: mulhdu r3, r3, r5 ; CHECK-NEXT: mulhdu r3, r3, r5
; CHECK-NEXT: maddld r6, r4, r5, r3 ; CHECK-NEXT: maddld r6, r4, r5, r3
; CHECK-NEXT: crnot 4*cr5+gt, eq
; CHECK-NEXT: cmpld r6, r3 ; CHECK-NEXT: cmpld r6, r3
; CHECK-NEXT: mulld r3, r4, r5 ; CHECK-NEXT: mulld r3, r4, r5
; CHECK-NEXT: cmpldi cr1, r3, 0 ; CHECK-NEXT: cmpldi cr1, r3, 0
; CHECK-NEXT: crandc 4*cr5+lt, lt, 4*cr1+eq ; CHECK-NEXT: crandc 4*cr5+lt, lt, 4*cr1+eq
; CHECK-NEXT: mulhdu. r3, r4, r5 ; CHECK-NEXT: mulhdu. r3, r4, r5
; CHECK-NEXT: bc 4, 4*cr5+gt, .LBB0_10 ; CHECK-NEXT: bc 4, 4*cr5+gt, .LBB0_10
; CHECK-NEXT: # %bb.8: # %L670 ; CHECK-NEXT: # %bb.8: # %L670
; CHECK-NEXT: crorc 4*cr5+lt, 4*cr5+lt, eq ; CHECK-NEXT: crorc 4*cr5+lt, 4*cr5+lt, eq
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llvm/test/CodeGen/PowerPC/pr45628.ll

Show First 20 Lines • Show All 217 Lines • ▼ Show 20 Lines
; P9-NOVSX-NEXT: addi r3, r1, -32 ; P9-NOVSX-NEXT: addi r3, r1, -32
; P9-NOVSX-NEXT: stvx v2, 0, r3 ; P9-NOVSX-NEXT: stvx v2, 0, r3
; P9-NOVSX-NEXT: ld r4, -32(r1) ; P9-NOVSX-NEXT: ld r4, -32(r1)
; P9-NOVSX-NEXT: ld r3, -24(r1) ; P9-NOVSX-NEXT: ld r3, -24(r1)
; P9-NOVSX-NEXT: rotldi r5, r4, 28 ; P9-NOVSX-NEXT: rotldi r5, r4, 28
; P9-NOVSX-NEXT: rldimi r5, r3, 28, 0 ; P9-NOVSX-NEXT: rldimi r5, r3, 28, 0
; P9-NOVSX-NEXT: rotldi r3, r3, 28 ; P9-NOVSX-NEXT: rotldi r3, r3, 28
; P9-NOVSX-NEXT: rldimi r3, r4, 28, 0 ; P9-NOVSX-NEXT: rldimi r3, r4, 28, 0
; P9-NOVSX-NEXT: std r5, -8(r1)
; P9-NOVSX-NEXT: std r3, -16(r1) ; P9-NOVSX-NEXT: std r3, -16(r1)
; P9-NOVSX-NEXT: addi r3, r1, -16 ; P9-NOVSX-NEXT: addi r3, r1, -16
; P9-NOVSX-NEXT: std r5, -8(r1)
; P9-NOVSX-NEXT: lvx v2, 0, r3 ; P9-NOVSX-NEXT: lvx v2, 0, r3
; P9-NOVSX-NEXT: blr ; P9-NOVSX-NEXT: blr
; ;
; P8-VSX-LABEL: rotl_28: ; P8-VSX-LABEL: rotl_28:
; P8-VSX: # %bb.0: # %entry ; P8-VSX: # %bb.0: # %entry
; P8-VSX-NEXT: xxswapd vs0, v2 ; P8-VSX-NEXT: xxswapd vs0, v2
; P8-VSX-NEXT: mfvsrd r3, v2 ; P8-VSX-NEXT: mfvsrd r3, v2
; P8-VSX-NEXT: rotldi r5, r3, 28 ; P8-VSX-NEXT: rotldi r5, r3, 28
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llvm/test/CodeGen/PowerPC/pre-inc-disable.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=pwr9 -O3 -verify-machineinstrs -ppc-vsr-nums-as-vr \ ; RUN: llc -mcpu=pwr9 -O3 -verify-machineinstrs -ppc-vsr-nums-as-vr \
; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -mcpu=pwr9 -O3 -verify-machineinstrs -ppc-vsr-nums-as-vr \ ; RUN: llc -mcpu=pwr9 -O3 -verify-machineinstrs -ppc-vsr-nums-as-vr \
; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64-unknown-linux-gnu \
; RUN: < %s | FileCheck %s --check-prefix=P9BE ; RUN: < %s | FileCheck %s --check-prefix=P9BE
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define signext i32 @test_pre_inc_disable_1(i8* nocapture readonly %pix1, i32 signext %i_stride_pix1, i8* nocapture readonly %pix2) { define signext i32 @test_pre_inc_disable_1(i8* nocapture readonly %pix1, i32 signext %i_stride_pix1, i8* nocapture readonly %pix2) {
; CHECK-LABEL: test_pre_inc_disable_1: ; CHECK-LABEL: test_pre_inc_disable_1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxsd v5, 0(r5) ; CHECK-NEXT: lxsd v5, 0(r5)
; CHECK-NEXT: addis r5, r2, .LCPI0_0@toc@ha ; CHECK-NEXT: addis r5, r2, .LCPI0_0@toc@ha
; CHECK-NEXT: xxlxor v3, v3, v3
; CHECK-NEXT: li r6, 0
; CHECK-NEXT: addi r5, r5, .LCPI0_0@toc@l ; CHECK-NEXT: addi r5, r5, .LCPI0_0@toc@l
; CHECK-NEXT: lxvx v2, 0, r5 ; CHECK-NEXT: lxvx v2, 0, r5
; CHECK-NEXT: addis r5, r2, .LCPI0_1@toc@ha ; CHECK-NEXT: addis r5, r2, .LCPI0_1@toc@ha
; CHECK-NEXT: addi r5, r5, .LCPI0_1@toc@l ; CHECK-NEXT: addi r5, r5, .LCPI0_1@toc@l
; CHECK-NEXT: lxvx v4, 0, r5 ; CHECK-NEXT: lxvx v4, 0, r5
; CHECK-NEXT: li r5, 4 ; CHECK-NEXT: li r5, 4
; CHECK-NEXT: xxlxor v3, v3, v3
; CHECK-NEXT: vperm v0, v3, v5, v2 ; CHECK-NEXT: vperm v0, v3, v5, v2
; CHECK-NEXT: mtctr r5 ; CHECK-NEXT: mtctr r5
; CHECK-NEXT: li r5, 0 ; CHECK-NEXT: li r5, 0
; CHECK-NEXT: vperm v1, v3, v5, v4 ; CHECK-NEXT: vperm v1, v3, v5, v4
; CHECK-NEXT: li r6, 0
; CHECK-NEXT: xvnegsp v5, v0 ; CHECK-NEXT: xvnegsp v5, v0
; CHECK-NEXT: xvnegsp v0, v1 ; CHECK-NEXT: xvnegsp v0, v1
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_1: # %for.cond1.preheader ; CHECK-NEXT: .LBB0_1: # %for.cond1.preheader
; CHECK-NEXT: # ; CHECK-NEXT: #
; CHECK-NEXT: lxsd v1, 0(r3) ; CHECK-NEXT: lxsd v1, 0(r3)
; CHECK-NEXT: add r7, r3, r4
; CHECK-NEXT: vperm v6, v3, v1, v4 ; CHECK-NEXT: vperm v6, v3, v1, v4
; CHECK-NEXT: vperm v1, v3, v1, v2 ; CHECK-NEXT: vperm v1, v3, v1, v2
; CHECK-NEXT: xvnegsp v1, v1 ; CHECK-NEXT: xvnegsp v1, v1
; CHECK-NEXT: xvnegsp v6, v6 ; CHECK-NEXT: xvnegsp v6, v6
; CHECK-NEXT: add r7, r3, r4
; CHECK-NEXT: vabsduw v1, v1, v5 ; CHECK-NEXT: vabsduw v1, v1, v5
; CHECK-NEXT: vabsduw v6, v6, v0 ; CHECK-NEXT: vabsduw v6, v6, v0
; CHECK-NEXT: vadduwm v1, v6, v1 ; CHECK-NEXT: vadduwm v1, v6, v1
; CHECK-NEXT: xxswapd v6, v1 ; CHECK-NEXT: xxswapd v6, v1
; CHECK-NEXT: vadduwm v1, v1, v6 ; CHECK-NEXT: vadduwm v1, v1, v6
; CHECK-NEXT: xxspltw v6, v1, 2 ; CHECK-NEXT: xxspltw v6, v1, 2
; CHECK-NEXT: vadduwm v1, v1, v6 ; CHECK-NEXT: vadduwm v1, v1, v6
; CHECK-NEXT: lxsdx v6, r3, r4 ; CHECK-NEXT: lxsdx v6, r3, r4
; CHECK-NEXT: vextuwrx r3, r5, v1 ; CHECK-NEXT: vextuwrx r3, r5, v1
; CHECK-NEXT: vperm v7, v3, v6, v4 ; CHECK-NEXT: vperm v7, v3, v6, v4
; CHECK-NEXT: vperm v6, v3, v6, v2 ; CHECK-NEXT: vperm v6, v3, v6, v2
; CHECK-NEXT: add r6, r3, r6
; CHECK-NEXT: add r3, r7, r4
; CHECK-NEXT: xvnegsp v6, v6 ; CHECK-NEXT: xvnegsp v6, v6
; CHECK-NEXT: xvnegsp v1, v7 ; CHECK-NEXT: xvnegsp v1, v7
; CHECK-NEXT: vabsduw v6, v6, v5 ; CHECK-NEXT: vabsduw v6, v6, v5
; CHECK-NEXT: add r6, r3, r6
; CHECK-NEXT: vabsduw v1, v1, v0 ; CHECK-NEXT: vabsduw v1, v1, v0
; CHECK-NEXT: vadduwm v1, v1, v6 ; CHECK-NEXT: vadduwm v1, v1, v6
; CHECK-NEXT: xxswapd v6, v1 ; CHECK-NEXT: xxswapd v6, v1
; CHECK-NEXT: vadduwm v1, v1, v6 ; CHECK-NEXT: vadduwm v1, v1, v6
; CHECK-NEXT: xxspltw v6, v1, 2 ; CHECK-NEXT: xxspltw v6, v1, 2
; CHECK-NEXT: vadduwm v1, v1, v6 ; CHECK-NEXT: vadduwm v1, v1, v6
; CHECK-NEXT: vextuwrx r8, r5, v1 ; CHECK-NEXT: vextuwrx r8, r5, v1
; CHECK-NEXT: add r3, r7, r4
; CHECK-NEXT: add r6, r8, r6 ; CHECK-NEXT: add r6, r8, r6
; CHECK-NEXT: bdnz .LBB0_1 ; CHECK-NEXT: bdnz .LBB0_1
; CHECK-NEXT: # %bb.2: # %for.cond.cleanup ; CHECK-NEXT: # %bb.2: # %for.cond.cleanup
; CHECK-NEXT: extsw r3, r6 ; CHECK-NEXT: extsw r3, r6
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; P9BE-LABEL: test_pre_inc_disable_1: ; P9BE-LABEL: test_pre_inc_disable_1:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: lfd f0, 0(r5) ; P9BE-NEXT: lfd f0, 0(r5)
; P9BE-NEXT: addis r5, r2, .LCPI0_0@toc@ha ; P9BE-NEXT: addis r5, r2, .LCPI0_0@toc@ha
; P9BE-NEXT: xxlxor v3, v3, v3
; P9BE-NEXT: li r6, 0
; P9BE-NEXT: addi r5, r5, .LCPI0_0@toc@l ; P9BE-NEXT: addi r5, r5, .LCPI0_0@toc@l
; P9BE-NEXT: lxvx v2, 0, r5 ; P9BE-NEXT: lxvx v2, 0, r5
; P9BE-NEXT: addis r5, r2, .LCPI0_1@toc@ha ; P9BE-NEXT: addis r5, r2, .LCPI0_1@toc@ha
; P9BE-NEXT: xxlor v5, vs0, vs0
; P9BE-NEXT: addi r5, r5, .LCPI0_1@toc@l ; P9BE-NEXT: addi r5, r5, .LCPI0_1@toc@l
; P9BE-NEXT: lxvx v4, 0, r5 ; P9BE-NEXT: lxvx v4, 0, r5
; P9BE-NEXT: li r5, 4 ; P9BE-NEXT: li r5, 4
; P9BE-NEXT: xxlor v5, vs0, vs0
; P9BE-NEXT: xxlxor v3, v3, v3
; P9BE-NEXT: vperm v0, v3, v5, v2 ; P9BE-NEXT: vperm v0, v3, v5, v2
; P9BE-NEXT: mtctr r5 ; P9BE-NEXT: mtctr r5
; P9BE-NEXT: li r5, 0 ; P9BE-NEXT: li r5, 0
; P9BE-NEXT: vperm v1, v3, v5, v4 ; P9BE-NEXT: vperm v1, v3, v5, v4
; P9BE-NEXT: li r6, 0
; P9BE-NEXT: xvnegsp v5, v0 ; P9BE-NEXT: xvnegsp v5, v0
; P9BE-NEXT: xvnegsp v0, v1 ; P9BE-NEXT: xvnegsp v0, v1
; P9BE-NEXT: .p2align 4 ; P9BE-NEXT: .p2align 4
; P9BE-NEXT: .LBB0_1: # %for.cond1.preheader ; P9BE-NEXT: .LBB0_1: # %for.cond1.preheader
; P9BE-NEXT: # ; P9BE-NEXT: #
; P9BE-NEXT: lfd f0, 0(r3) ; P9BE-NEXT: lfd f0, 0(r3)
; P9BE-NEXT: add r7, r3, r4
; P9BE-NEXT: xxlor v1, vs0, vs0 ; P9BE-NEXT: xxlor v1, vs0, vs0
; P9BE-NEXT: lfdx f0, r3, r4 ; P9BE-NEXT: lfdx f0, r3, r4
; P9BE-NEXT: vperm v6, v3, v1, v4 ; P9BE-NEXT: vperm v6, v3, v1, v4
; P9BE-NEXT: vperm v1, v3, v1, v2 ; P9BE-NEXT: vperm v1, v3, v1, v2
; P9BE-NEXT: xvnegsp v1, v1 ; P9BE-NEXT: xvnegsp v1, v1
; P9BE-NEXT: xvnegsp v6, v6 ; P9BE-NEXT: xvnegsp v6, v6
; P9BE-NEXT: vabsduw v1, v1, v5 ; P9BE-NEXT: vabsduw v1, v1, v5
; P9BE-NEXT: vabsduw v6, v6, v0 ; P9BE-NEXT: vabsduw v6, v6, v0
; P9BE-NEXT: vadduwm v1, v6, v1 ; P9BE-NEXT: vadduwm v1, v6, v1
; P9BE-NEXT: xxswapd v6, v1 ; P9BE-NEXT: xxswapd v6, v1
; P9BE-NEXT: vadduwm v1, v1, v6 ; P9BE-NEXT: vadduwm v1, v1, v6
; P9BE-NEXT: xxspltw v6, v1, 1 ; P9BE-NEXT: xxspltw v6, v1, 1
; P9BE-NEXT: vadduwm v1, v1, v6 ; P9BE-NEXT: vadduwm v1, v1, v6
; P9BE-NEXT: xxlor v6, vs0, vs0 ; P9BE-NEXT: xxlor v6, vs0, vs0
; P9BE-NEXT: vperm v7, v3, v6, v4 ; P9BE-NEXT: vperm v7, v3, v6, v4
; P9BE-NEXT: vperm v6, v3, v6, v2 ; P9BE-NEXT: vperm v6, v3, v6, v2
; P9BE-NEXT: add r7, r3, r4
; P9BE-NEXT: vextuwlx r3, r5, v1 ; P9BE-NEXT: vextuwlx r3, r5, v1
; P9BE-NEXT: xvnegsp v6, v6 ; P9BE-NEXT: xvnegsp v6, v6
; P9BE-NEXT: add r6, r3, r6
; P9BE-NEXT: xvnegsp v1, v7 ; P9BE-NEXT: xvnegsp v1, v7
; P9BE-NEXT: vabsduw v1, v1, v0 ; P9BE-NEXT: add r3, r7, r4
; P9BE-NEXT: vabsduw v6, v6, v5 ; P9BE-NEXT: vabsduw v6, v6, v5
; P9BE-NEXT: vabsduw v1, v1, v0
; P9BE-NEXT: vadduwm v1, v1, v6 ; P9BE-NEXT: vadduwm v1, v1, v6
; P9BE-NEXT: xxswapd v6, v1 ; P9BE-NEXT: xxswapd v6, v1
; P9BE-NEXT: add r6, r3, r6
; P9BE-NEXT: vadduwm v1, v1, v6 ; P9BE-NEXT: vadduwm v1, v1, v6
; P9BE-NEXT: xxspltw v6, v1, 1 ; P9BE-NEXT: xxspltw v6, v1, 1
; P9BE-NEXT: vadduwm v1, v1, v6 ; P9BE-NEXT: vadduwm v1, v1, v6
; P9BE-NEXT: vextuwlx r8, r5, v1 ; P9BE-NEXT: vextuwlx r8, r5, v1
; P9BE-NEXT: add r3, r7, r4
; P9BE-NEXT: add r6, r8, r6 ; P9BE-NEXT: add r6, r8, r6
; P9BE-NEXT: bdnz .LBB0_1 ; P9BE-NEXT: bdnz .LBB0_1
; P9BE-NEXT: # %bb.2: # %for.cond.cleanup ; P9BE-NEXT: # %bb.2: # %for.cond.cleanup
; P9BE-NEXT: extsw r3, r6 ; P9BE-NEXT: extsw r3, r6
; P9BE-NEXT: blr ; P9BE-NEXT: blr
entry: entry:
%idx.ext = sext i32 %i_stride_pix1 to i64 %idx.ext = sext i32 %i_stride_pix1 to i64
%0 = bitcast i8* %pix2 to <8 x i8>* %0 = bitcast i8* %pix2 to <8 x i8>*
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define signext i32 @test_pre_inc_disable_2(i8* nocapture readonly %pix1, i8* nocapture readonly %pix2) { define signext i32 @test_pre_inc_disable_2(i8* nocapture readonly %pix1, i8* nocapture readonly %pix2) {
; CHECK-LABEL: test_pre_inc_disable_2: ; CHECK-LABEL: test_pre_inc_disable_2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxsd v2, 0(r3) ; CHECK-NEXT: lxsd v2, 0(r3)
; CHECK-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-NEXT: addis r3, r2, .LCPI1_0@toc@ha
; CHECK-NEXT: lxsd v1, 0(r4)
; CHECK-NEXT: xxlxor v3, v3, v3
; CHECK-NEXT: addi r3, r3, .LCPI1_0@toc@l ; CHECK-NEXT: addi r3, r3, .LCPI1_0@toc@l
; CHECK-NEXT: lxvx v4, 0, r3 ; CHECK-NEXT: lxvx v4, 0, r3
; CHECK-NEXT: addis r3, r2, .LCPI1_1@toc@ha ; CHECK-NEXT: addis r3, r2, .LCPI1_1@toc@ha
; CHECK-NEXT: addi r3, r3, .LCPI1_1@toc@l ; CHECK-NEXT: addi r3, r3, .LCPI1_1@toc@l
; CHECK-NEXT: lxvx v0, 0, r3 ; CHECK-NEXT: lxvx v0, 0, r3
; CHECK-NEXT: lxsd v1, 0(r4) ; CHECK-NEXT: li r3, 0
; CHECK-NEXT: xxlxor v3, v3, v3
; CHECK-NEXT: vperm v5, v3, v2, v4 ; CHECK-NEXT: vperm v5, v3, v2, v4
; CHECK-NEXT: vperm v2, v3, v2, v0 ; CHECK-NEXT: vperm v2, v3, v2, v0
; CHECK-NEXT: vperm v0, v3, v1, v0 ; CHECK-NEXT: vperm v0, v3, v1, v0
; CHECK-NEXT: vperm v3, v3, v1, v4 ; CHECK-NEXT: vperm v3, v3, v1, v4
; CHECK-NEXT: vabsduw v2, v2, v0 ; CHECK-NEXT: vabsduw v2, v2, v0
; CHECK-NEXT: vabsduw v3, v5, v3 ; CHECK-NEXT: vabsduw v3, v5, v3
; CHECK-NEXT: vadduwm v2, v3, v2 ; CHECK-NEXT: vadduwm v2, v3, v2
; CHECK-NEXT: xxswapd v3, v2 ; CHECK-NEXT: xxswapd v3, v2
; CHECK-NEXT: vadduwm v2, v2, v3 ; CHECK-NEXT: vadduwm v2, v2, v3
; CHECK-NEXT: xxspltw v3, v2, 2 ; CHECK-NEXT: xxspltw v3, v2, 2
; CHECK-NEXT: vadduwm v2, v2, v3 ; CHECK-NEXT: vadduwm v2, v2, v3
; CHECK-NEXT: li r3, 0
; CHECK-NEXT: vextuwrx r3, r3, v2 ; CHECK-NEXT: vextuwrx r3, r3, v2
; CHECK-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; P9BE-LABEL: test_pre_inc_disable_2: ; P9BE-LABEL: test_pre_inc_disable_2:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: lfd f0, 0(r3) ; P9BE-NEXT: lfd f0, 0(r3)
; P9BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha
; P9BE-NEXT: xxlxor v3, v3, v3
; P9BE-NEXT: addi r3, r3, .LCPI1_0@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI1_0@toc@l
; P9BE-NEXT: lxvx v4, 0, r3 ; P9BE-NEXT: lxvx v4, 0, r3
; P9BE-NEXT: addis r3, r2, .LCPI1_1@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI1_1@toc@ha
; P9BE-NEXT: addi r3, r3, .LCPI1_1@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI1_1@toc@l
; P9BE-NEXT: xxlor v2, vs0, vs0 ; P9BE-NEXT: xxlor v2, vs0, vs0
; P9BE-NEXT: lfd f0, 0(r4) ; P9BE-NEXT: lfd f0, 0(r4)
; P9BE-NEXT: lxvx v0, 0, r3 ; P9BE-NEXT: lxvx v0, 0, r3
; P9BE-NEXT: xxlxor v3, v3, v3
; P9BE-NEXT: xxlor v1, vs0, vs0 ; P9BE-NEXT: xxlor v1, vs0, vs0
; P9BE-NEXT: li r3, 0
; P9BE-NEXT: vperm v5, v3, v2, v4 ; P9BE-NEXT: vperm v5, v3, v2, v4
; P9BE-NEXT: vperm v2, v3, v2, v0 ; P9BE-NEXT: vperm v2, v3, v2, v0
; P9BE-NEXT: vperm v0, v3, v1, v0 ; P9BE-NEXT: vperm v0, v3, v1, v0
; P9BE-NEXT: vperm v3, v3, v1, v4 ; P9BE-NEXT: vperm v3, v3, v1, v4
; P9BE-NEXT: vabsduw v2, v2, v0 ; P9BE-NEXT: vabsduw v2, v2, v0
; P9BE-NEXT: vabsduw v3, v5, v3 ; P9BE-NEXT: vabsduw v3, v5, v3
; P9BE-NEXT: vadduwm v2, v3, v2 ; P9BE-NEXT: vadduwm v2, v3, v2
; P9BE-NEXT: xxswapd v3, v2 ; P9BE-NEXT: xxswapd v3, v2
; P9BE-NEXT: vadduwm v2, v2, v3 ; P9BE-NEXT: vadduwm v2, v2, v3
; P9BE-NEXT: xxspltw v3, v2, 1 ; P9BE-NEXT: xxspltw v3, v2, 1
; P9BE-NEXT: vadduwm v2, v2, v3 ; P9BE-NEXT: vadduwm v2, v2, v3
; P9BE-NEXT: li r3, 0
; P9BE-NEXT: vextuwlx r3, r3, v2 ; P9BE-NEXT: vextuwlx r3, r3, v2
; P9BE-NEXT: extsw r3, r3 ; P9BE-NEXT: extsw r3, r3
; P9BE-NEXT: blr ; P9BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %pix1 to <8 x i8>* %0 = bitcast i8* %pix1 to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 1 %1 = load <8 x i8>, <8 x i8>* %0, align 1
%2 = zext <8 x i8> %1 to <8 x i32> %2 = zext <8 x i8> %1 to <8 x i32>
%3 = bitcast i8* %pix2 to <8 x i8>* %3 = bitcast i8* %pix2 to <8 x i8>*
Show All 39 Lines
;} ;}
define void @test32(i8* nocapture readonly %pix2, i32 signext %i_pix2) { define void @test32(i8* nocapture readonly %pix2, i32 signext %i_pix2) {
; CHECK-LABEL: test32: ; CHECK-LABEL: test32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: add r5, r3, r4 ; CHECK-NEXT: add r5, r3, r4
; CHECK-NEXT: lxsiwzx v2, r3, r4 ; CHECK-NEXT: lxsiwzx v2, r3, r4
; CHECK-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; CHECK-NEXT: addis r3, r2, .LCPI2_0@toc@ha
; CHECK-NEXT: xxlxor v3, v3, v3
; CHECK-NEXT: addi r3, r3, .LCPI2_0@toc@l ; CHECK-NEXT: addi r3, r3, .LCPI2_0@toc@l
; CHECK-NEXT: lxvx v4, 0, r3 ; CHECK-NEXT: lxvx v4, 0, r3
; CHECK-NEXT: li r3, 4 ; CHECK-NEXT: li r3, 4
; CHECK-NEXT: lxsiwzx v5, r5, r3 ; CHECK-NEXT: lxsiwzx v5, r5, r3
; CHECK-NEXT: xxlxor v3, v3, v3
; CHECK-NEXT: vperm v2, v2, v3, v4 ; CHECK-NEXT: vperm v2, v2, v3, v4
; CHECK-NEXT: vperm v3, v5, v3, v4 ; CHECK-NEXT: vperm v3, v5, v3, v4
; CHECK-NEXT: vspltisw v4, 8 ; CHECK-NEXT: vspltisw v4, 8
; CHECK-NEXT: vnegw v3, v3 ; CHECK-NEXT: vnegw v3, v3
; CHECK-NEXT: vadduwm v4, v4, v4 ; CHECK-NEXT: vadduwm v4, v4, v4
; CHECK-NEXT: vslw v3, v3, v4 ; CHECK-NEXT: vslw v3, v3, v4
; CHECK-NEXT: vsubuwm v2, v3, v2 ; CHECK-NEXT: vsubuwm v2, v3, v2
; CHECK-NEXT: xxswapd vs0, v2 ; CHECK-NEXT: xxswapd vs0, v2
; CHECK-NEXT: stxvx vs0, 0, r3 ; CHECK-NEXT: stxvx vs0, 0, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; P9BE-LABEL: test32: ; P9BE-LABEL: test32:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: add r5, r3, r4 ; P9BE-NEXT: add r5, r3, r4
; P9BE-NEXT: lfiwzx f0, r3, r4 ; P9BE-NEXT: lfiwzx f0, r3, r4
; P9BE-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI2_0@toc@ha
; P9BE-NEXT: xxlxor v3, v3, v3
; P9BE-NEXT: xxsldwi v2, f0, f0, 1
; P9BE-NEXT: addi r3, r3, .LCPI2_0@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI2_0@toc@l
; P9BE-NEXT: lxvx v4, 0, r3 ; P9BE-NEXT: lxvx v4, 0, r3
; P9BE-NEXT: li r3, 4 ; P9BE-NEXT: li r3, 4
; P9BE-NEXT: xxsldwi v2, f0, f0, 1
; P9BE-NEXT: lfiwzx f0, r5, r3 ; P9BE-NEXT: lfiwzx f0, r5, r3
; P9BE-NEXT: xxlxor v3, v3, v3
; P9BE-NEXT: vperm v2, v3, v2, v4 ; P9BE-NEXT: vperm v2, v3, v2, v4
; P9BE-NEXT: xxsldwi v5, f0, f0, 1 ; P9BE-NEXT: xxsldwi v5, f0, f0, 1
; P9BE-NEXT: vperm v3, v3, v5, v4 ; P9BE-NEXT: vperm v3, v3, v5, v4
; P9BE-NEXT: vspltisw v4, 8 ; P9BE-NEXT: vspltisw v4, 8
; P9BE-NEXT: vnegw v3, v3 ; P9BE-NEXT: vnegw v3, v3
; P9BE-NEXT: vadduwm v4, v4, v4 ; P9BE-NEXT: vadduwm v4, v4, v4
; P9BE-NEXT: vslw v3, v3, v4 ; P9BE-NEXT: vslw v3, v3, v4
; P9BE-NEXT: vsubuwm v2, v3, v2 ; P9BE-NEXT: vsubuwm v2, v3, v2
Show All 23 Linesentry:
store <4 x i32> %13, <4 x i32>* undef, align 16 store <4 x i32> %13, <4 x i32>* undef, align 16
ret void ret void
} }
define void @test16(i16* nocapture readonly %sums, i32 signext %delta, i32 signext %thresh) { define void @test16(i16* nocapture readonly %sums, i32 signext %delta, i32 signext %thresh) {
; CHECK-LABEL: test16: ; CHECK-LABEL: test16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sldi r4, r4, 1 ; CHECK-NEXT: sldi r4, r4, 1
; CHECK-NEXT: add r6, r3, r4
; CHECK-NEXT: li r7, 16 ; CHECK-NEXT: li r7, 16
; CHECK-NEXT: lxsihzx v2, r6, r7 ; CHECK-NEXT: add r6, r3, r4
; CHECK-NEXT: lxsihzx v4, r3, r4 ; CHECK-NEXT: lxsihzx v4, r3, r4
; CHECK-NEXT: addis r3, r2, .LCPI3_0@toc@ha
; CHECK-NEXT: lxsihzx v2, r6, r7
; CHECK-NEXT: li r6, 0 ; CHECK-NEXT: li r6, 0
; CHECK-NEXT: addi r3, r3, .LCPI3_0@toc@l
; CHECK-NEXT: mtvsrd v3, r6 ; CHECK-NEXT: mtvsrd v3, r6
; CHECK-NEXT: vsplth v4, v4, 3 ; CHECK-NEXT: vsplth v4, v4, 3
; CHECK-NEXT: vsplth v2, v2, 3 ; CHECK-NEXT: vsplth v2, v2, 3
; CHECK-NEXT: addis r3, r2, .LCPI3_0@toc@ha
; CHECK-NEXT: addi r3, r3, .LCPI3_0@toc@l
; CHECK-NEXT: vmrghh v4, v3, v4 ; CHECK-NEXT: vmrghh v4, v3, v4
; CHECK-NEXT: vmrghh v2, v3, v2 ; CHECK-NEXT: vmrghh v2, v3, v2
; CHECK-NEXT: vsplth v3, v3, 3 ; CHECK-NEXT: vsplth v3, v3, 3
; CHECK-NEXT: vmrglw v3, v4, v3 ; CHECK-NEXT: vmrglw v3, v4, v3
; CHECK-NEXT: lxvx v4, 0, r3 ; CHECK-NEXT: lxvx v4, 0, r3
; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: li r3, 0
; CHECK-NEXT: vperm v2, v2, v3, v4 ; CHECK-NEXT: vperm v2, v2, v3, v4
; CHECK-NEXT: xxspltw v3, v2, 2 ; CHECK-NEXT: xxspltw v3, v2, 2
; CHECK-NEXT: vadduwm v2, v2, v3 ; CHECK-NEXT: vadduwm v2, v2, v3
; CHECK-NEXT: vextuwrx r3, r3, v2 ; CHECK-NEXT: vextuwrx r3, r3, v2
; CHECK-NEXT: cmpw r3, r5 ; CHECK-NEXT: cmpw r3, r5
; CHECK-NEXT: bgelr+ cr0 ; CHECK-NEXT: bgelr+ cr0
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; ;
; P9BE-LABEL: test16: ; P9BE-LABEL: test16:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: sldi r4, r4, 1 ; P9BE-NEXT: sldi r4, r4, 1
; P9BE-NEXT: add r6, r3, r4
; P9BE-NEXT: li r7, 16 ; P9BE-NEXT: li r7, 16
; P9BE-NEXT: lxsihzx v2, r6, r7 ; P9BE-NEXT: add r6, r3, r4
; P9BE-NEXT: lxsihzx v4, r3, r4 ; P9BE-NEXT: lxsihzx v4, r3, r4
; P9BE-NEXT: addis r3, r2, .LCPI3_0@toc@ha
; P9BE-NEXT: lxsihzx v2, r6, r7
; P9BE-NEXT: li r6, 0 ; P9BE-NEXT: li r6, 0
; P9BE-NEXT: addi r3, r3, .LCPI3_0@toc@l
; P9BE-NEXT: sldi r6, r6, 48 ; P9BE-NEXT: sldi r6, r6, 48
; P9BE-NEXT: vsplth v4, v4, 3 ; P9BE-NEXT: vsplth v4, v4, 3
; P9BE-NEXT: mtvsrd v3, r6 ; P9BE-NEXT: mtvsrd v3, r6
; P9BE-NEXT: vsplth v2, v2, 3 ; P9BE-NEXT: vsplth v2, v2, 3
; P9BE-NEXT: addis r3, r2, .LCPI3_0@toc@ha
; P9BE-NEXT: addi r3, r3, .LCPI3_0@toc@l
; P9BE-NEXT: vmrghh v4, v3, v4 ; P9BE-NEXT: vmrghh v4, v3, v4
; P9BE-NEXT: vmrghh v2, v3, v2 ; P9BE-NEXT: vmrghh v2, v3, v2
; P9BE-NEXT: vsplth v3, v3, 0 ; P9BE-NEXT: vsplth v3, v3, 0
; P9BE-NEXT: vmrghw v3, v3, v4 ; P9BE-NEXT: vmrghw v3, v3, v4
; P9BE-NEXT: lxvx v4, 0, r3 ; P9BE-NEXT: lxvx v4, 0, r3
; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: li r3, 0
; P9BE-NEXT: vperm v2, v3, v2, v4 ; P9BE-NEXT: vperm v2, v3, v2, v4
; P9BE-NEXT: xxspltw v3, v2, 1 ; P9BE-NEXT: xxspltw v3, v2, 1
Show All 38 Lines
; CHECK-LABEL: test8: ; CHECK-LABEL: test8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: add r6, r3, r4 ; CHECK-NEXT: add r6, r3, r4
; CHECK-NEXT: lxsibzx v2, r3, r4 ; CHECK-NEXT: lxsibzx v2, r3, r4
; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: li r3, 0
; CHECK-NEXT: mtvsrd v3, r3 ; CHECK-NEXT: mtvsrd v3, r3
; CHECK-NEXT: li r3, 8 ; CHECK-NEXT: li r3, 8
; CHECK-NEXT: lxsibzx v5, r6, r3 ; CHECK-NEXT: lxsibzx v5, r6, r3
; CHECK-NEXT: vspltb v4, v3, 7
; CHECK-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; CHECK-NEXT: addis r3, r2, .LCPI4_0@toc@ha
; CHECK-NEXT: addi r3, r3, .LCPI4_0@toc@l
; CHECK-NEXT: vspltb v2, v2, 7 ; CHECK-NEXT: vspltb v2, v2, 7
; CHECK-NEXT: addi r3, r3, .LCPI4_0@toc@l
; CHECK-NEXT: vmrghb v2, v3, v2 ; CHECK-NEXT: vmrghb v2, v3, v2
; CHECK-NEXT: vspltb v4, v3, 7
; CHECK-NEXT: vspltb v5, v5, 7 ; CHECK-NEXT: vspltb v5, v5, 7
; CHECK-NEXT: vmrglh v2, v2, v4 ; CHECK-NEXT: vmrglh v2, v2, v4
; CHECK-NEXT: vmrghb v3, v3, v5 ; CHECK-NEXT: vmrghb v3, v3, v5
; CHECK-NEXT: vmrglw v2, v2, v4 ; CHECK-NEXT: vmrglw v2, v2, v4
; CHECK-NEXT: vmrglh v3, v3, v4 ; CHECK-NEXT: vmrglh v3, v3, v4
; CHECK-NEXT: vmrglw v3, v4, v3 ; CHECK-NEXT: vmrglw v3, v4, v3
; CHECK-NEXT: lxvx v4, 0, r3 ; CHECK-NEXT: lxvx v4, 0, r3
; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: li r3, 0
; CHECK-NEXT: vperm v2, v3, v2, v4 ; CHECK-NEXT: vperm v2, v3, v2, v4
; CHECK-NEXT: xxspltw v3, v2, 2 ; CHECK-NEXT: xxspltw v3, v2, 2
; CHECK-NEXT: vadduwm v2, v2, v3 ; CHECK-NEXT: vadduwm v2, v2, v3
; CHECK-NEXT: vextuwrx r3, r3, v2 ; CHECK-NEXT: vextuwrx r3, r3, v2
; CHECK-NEXT: cmpw r3, r5 ; CHECK-NEXT: cmpw r3, r5
; CHECK-NEXT: bgelr+ cr0 ; CHECK-NEXT: bgelr+ cr0
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; ;
; P9BE-LABEL: test8: ; P9BE-LABEL: test8:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: add r6, r3, r4 ; P9BE-NEXT: add r6, r3, r4
; P9BE-NEXT: li r7, 8 ; P9BE-NEXT: li r7, 8
; P9BE-NEXT: lxsibzx v2, r6, r7
; P9BE-NEXT: lxsibzx v4, r3, r4 ; P9BE-NEXT: lxsibzx v4, r3, r4
; P9BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha
; P9BE-NEXT: lxsibzx v2, r6, r7
; P9BE-NEXT: li r6, 0 ; P9BE-NEXT: li r6, 0
; P9BE-NEXT: addi r3, r3, .LCPI4_0@toc@l
; P9BE-NEXT: sldi r6, r6, 56 ; P9BE-NEXT: sldi r6, r6, 56
; P9BE-NEXT: vspltb v4, v4, 7 ; P9BE-NEXT: vspltb v4, v4, 7
; P9BE-NEXT: mtvsrd v3, r6 ; P9BE-NEXT: mtvsrd v3, r6
; P9BE-NEXT: vspltb v2, v2, 7 ; P9BE-NEXT: vspltb v2, v2, 7
; P9BE-NEXT: vmrghb v4, v3, v4 ; P9BE-NEXT: vmrghb v4, v3, v4
; P9BE-NEXT: vmrghb v2, v3, v2 ; P9BE-NEXT: vmrghb v2, v3, v2
; P9BE-NEXT: vspltb v3, v3, 0 ; P9BE-NEXT: vspltb v3, v3, 0
; P9BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha
; P9BE-NEXT: addi r3, r3, .LCPI4_0@toc@l
; P9BE-NEXT: vmrghh v4, v4, v3 ; P9BE-NEXT: vmrghh v4, v4, v3
; P9BE-NEXT: xxspltw v3, v3, 0 ; P9BE-NEXT: xxspltw v3, v3, 0
; P9BE-NEXT: vmrghw v2, v4, v2 ; P9BE-NEXT: vmrghw v2, v4, v2
; P9BE-NEXT: lxvx v4, 0, r3 ; P9BE-NEXT: lxvx v4, 0, r3
; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: li r3, 0
; P9BE-NEXT: vperm v2, v3, v2, v4 ; P9BE-NEXT: vperm v2, v3, v2, v4
; P9BE-NEXT: xxspltw v3, v2, 1 ; P9BE-NEXT: xxspltw v3, v2, 1
; P9BE-NEXT: vadduwm v2, v2, v3 ; P9BE-NEXT: vadduwm v2, v2, v3
Show All 35 Lines

llvm/test/CodeGen/PowerPC/recipest.ll

Show First 20 Lines • Show All 798 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: xsmuldp 0, 0, 3 ; CHECK-P8-NEXT: xsmuldp 0, 0, 3
; CHECK-P8-NEXT: .LBB20_2: ; CHECK-P8-NEXT: .LBB20_2:
; CHECK-P8-NEXT: fmr 1, 0 ; CHECK-P8-NEXT: fmr 1, 0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: foo3_fmf: ; CHECK-P9-LABEL: foo3_fmf:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: addis 3, 2, .LCPI20_2@toc@ha ; CHECK-P9-NEXT: addis 3, 2, .LCPI20_2@toc@ha
; CHECK-P9-NEXT: lfd 2, .LCPI20_2@toc@l(3)
; CHECK-P9-NEXT: xsabsdp 0, 1 ; CHECK-P9-NEXT: xsabsdp 0, 1
; CHECK-P9-NEXT: lfd 2, .LCPI20_2@toc@l(3)
; CHECK-P9-NEXT: xscmpudp 0, 0, 2 ; CHECK-P9-NEXT: xscmpudp 0, 0, 2
; CHECK-P9-NEXT: xxlxor 0, 0, 0 ; CHECK-P9-NEXT: xxlxor 0, 0, 0
; CHECK-P9-NEXT: blt 0, .LBB20_2 ; CHECK-P9-NEXT: blt 0, .LBB20_2
; CHECK-P9-NEXT: # %bb.1: ; CHECK-P9-NEXT: # %bb.1:
; CHECK-P9-NEXT: xsrsqrtedp 0, 1 ; CHECK-P9-NEXT: xsrsqrtedp 0, 1
; CHECK-P9-NEXT: addis 3, 2, .LCPI20_0@toc@ha ; CHECK-P9-NEXT: addis 3, 2, .LCPI20_0@toc@ha
; CHECK-P9-NEXT: lfs 3, .LCPI20_0@toc@l(3) ; CHECK-P9-NEXT: lfs 3, .LCPI20_0@toc@l(3)
; CHECK-P9-NEXT: addis 3, 2, .LCPI20_1@toc@ha ; CHECK-P9-NEXT: addis 3, 2, .LCPI20_1@toc@ha
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; CHECK-P8-NEXT: xsmulsp 0, 0, 2 ; CHECK-P8-NEXT: xsmulsp 0, 0, 2
; CHECK-P8-NEXT: .LBB22_2: ; CHECK-P8-NEXT: .LBB22_2:
; CHECK-P8-NEXT: fmr 1, 0 ; CHECK-P8-NEXT: fmr 1, 0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: goo3_fmf: ; CHECK-P9-LABEL: goo3_fmf:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: addis 3, 2, .LCPI22_2@toc@ha ; CHECK-P9-NEXT: addis 3, 2, .LCPI22_2@toc@ha
; CHECK-P9-NEXT: lfs 2, .LCPI22_2@toc@l(3)
; CHECK-P9-NEXT: xsabsdp 0, 1 ; CHECK-P9-NEXT: xsabsdp 0, 1
; CHECK-P9-NEXT: lfs 2, .LCPI22_2@toc@l(3)
; CHECK-P9-NEXT: fcmpu 0, 0, 2 ; CHECK-P9-NEXT: fcmpu 0, 0, 2
; CHECK-P9-NEXT: xxlxor 0, 0, 0 ; CHECK-P9-NEXT: xxlxor 0, 0, 0
; CHECK-P9-NEXT: blt 0, .LBB22_2 ; CHECK-P9-NEXT: blt 0, .LBB22_2
; CHECK-P9-NEXT: # %bb.1: ; CHECK-P9-NEXT: # %bb.1:
; CHECK-P9-NEXT: xsrsqrtesp 0, 1 ; CHECK-P9-NEXT: xsrsqrtesp 0, 1
; CHECK-P9-NEXT: addis 3, 2, .LCPI22_0@toc@ha ; CHECK-P9-NEXT: addis 3, 2, .LCPI22_0@toc@ha
; CHECK-P9-NEXT: lfs 2, .LCPI22_0@toc@l(3) ; CHECK-P9-NEXT: lfs 2, .LCPI22_0@toc@l(3)
; CHECK-P9-NEXT: addis 3, 2, .LCPI22_1@toc@ha ; CHECK-P9-NEXT: addis 3, 2, .LCPI22_1@toc@ha
▲ Show 20 Lines • Show All 308 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/rematerializable-instruction-machine-licm.ll

Show All 22 Lines
; CHECK-NEXT: .cfi_offset r26, -48 ; CHECK-NEXT: .cfi_offset r26, -48
; CHECK-NEXT: .cfi_offset r27, -40 ; CHECK-NEXT: .cfi_offset r27, -40
; CHECK-NEXT: .cfi_offset r28, -32 ; CHECK-NEXT: .cfi_offset r28, -32
; CHECK-NEXT: .cfi_offset r29, -24 ; CHECK-NEXT: .cfi_offset r29, -24
; CHECK-NEXT: .cfi_offset r30, -16 ; CHECK-NEXT: .cfi_offset r30, -16
; CHECK-NEXT: .cfi_offset r31, -8 ; CHECK-NEXT: .cfi_offset r31, -8
; CHECK-NEXT: .cfi_offset r2, -152 ; CHECK-NEXT: .cfi_offset r2, -152
; CHECK-NEXT: lis 5, 4 ; CHECK-NEXT: lis 5, 4
; CHECK-NEXT: std 30, 704(1) # 8-byte Folded Spill
; CHECK-NEXT: std 29, 696(1) # 8-byte Folded Spill
; CHECK-NEXT: ori 6, 5, 6292 ; CHECK-NEXT: ori 6, 5, 6292
; CHECK-NEXT: std 28, 688(1) # 8-byte Folded Spill
; CHECK-NEXT: std 27, 680(1) # 8-byte Folded Spill
; CHECK-NEXT: std 26, 672(1) # 8-byte Folded Spill
; CHECK-NEXT: std 25, 664(1) # 8-byte Folded Spill
; CHECK-NEXT: ori 5, 5, 6291 ; CHECK-NEXT: ori 5, 5, 6291
; CHECK-NEXT: std 14, 576(1) # 8-byte Folded Spill
; CHECK-NEXT: std 15, 584(1) # 8-byte Folded Spill
; CHECK-NEXT: std 16, 592(1) # 8-byte Folded Spill
; CHECK-NEXT: std 17, 600(1) # 8-byte Folded Spill
; CHECK-NEXT: std 18, 608(1) # 8-byte Folded Spill
; CHECK-NEXT: std 19, 616(1) # 8-byte Folded Spill
; CHECK-NEXT: std 20, 624(1) # 8-byte Folded Spill
; CHECK-NEXT: std 21, 632(1) # 8-byte Folded Spill
; CHECK-NEXT: std 22, 640(1) # 8-byte Folded Spill
; CHECK-NEXT: std 23, 648(1) # 8-byte Folded Spill
; CHECK-NEXT: std 24, 656(1) # 8-byte Folded Spill
; CHECK-NEXT: std 31, 712(1) # 8-byte Folded Spill
; CHECK-NEXT: std 2, 568(1) # 8-byte Folded Spill
; CHECK-NEXT: sldi 6, 6, 32 ; CHECK-NEXT: sldi 6, 6, 32
; CHECK-NEXT: oris 7, 6, 13030 ; CHECK-NEXT: oris 7, 6, 13030
; CHECK-NEXT: oris 8, 6, 13066 ; CHECK-NEXT: oris 8, 6, 13066
; CHECK-NEXT: ori 7, 7, 3704
; CHECK-NEXT: oris 9, 6, 13054 ; CHECK-NEXT: oris 9, 6, 13054
; CHECK-NEXT: oris 10, 6, 13042
; CHECK-NEXT: oris 11, 6, 13078
; CHECK-NEXT: oris 12, 6, 13115
; CHECK-NEXT: oris 0, 6, 13103
; CHECK-NEXT: oris 30, 6, 13091
; CHECK-NEXT: oris 29, 6, 13127
; CHECK-NEXT: oris 28, 6, 13164
; CHECK-NEXT: oris 27, 6, 13152
; CHECK-NEXT: oris 26, 6, 13139
; CHECK-NEXT: oris 25, 6, 13176
; CHECK-NEXT: ori 7, 7, 3704
; CHECK-NEXT: ori 8, 8, 44408 ; CHECK-NEXT: ori 8, 8, 44408
; CHECK-NEXT: ori 9, 9, 30840 ; CHECK-NEXT: ori 9, 9, 30840
; CHECK-NEXT: add 7, 4, 7
; CHECK-NEXT: oris 10, 6, 13042
; CHECK-NEXT: ori 10, 10, 17272 ; CHECK-NEXT: ori 10, 10, 17272
; CHECK-NEXT: std 7, 384(1) # 8-byte Folded Spill
; CHECK-NEXT: add 7, 4, 8
; CHECK-NEXT: oris 11, 6, 13078
; CHECK-NEXT: ori 11, 11, 57976 ; CHECK-NEXT: ori 11, 11, 57976
; CHECK-NEXT: std 7, 376(1) # 8-byte Folded Spill
; CHECK-NEXT: add 7, 4, 9
; CHECK-NEXT: oris 12, 6, 13115
; CHECK-NEXT: ori 12, 12, 33144 ; CHECK-NEXT: ori 12, 12, 33144
; CHECK-NEXT: std 7, 368(1) # 8-byte Folded Spill
; CHECK-NEXT: add 7, 4, 10
; CHECK-NEXT: oris 0, 6, 13103
; CHECK-NEXT: ori 0, 0, 19576 ; CHECK-NEXT: ori 0, 0, 19576
; CHECK-NEXT: std 7, 360(1) # 8-byte Folded Spill
; CHECK-NEXT: add 7, 4, 11
; CHECK-NEXT: std 30, 704(1) # 8-byte Folded Spill
; CHECK-NEXT: oris 30, 6, 13091
; CHECK-NEXT: ori 30, 30, 6008 ; CHECK-NEXT: ori 30, 30, 6008
; CHECK-NEXT: std 7, 352(1) # 8-byte Folded Spill
; CHECK-NEXT: add 7, 4, 12
; CHECK-NEXT: std 29, 696(1) # 8-byte Folded Spill
; CHECK-NEXT: oris 29, 6, 13127
; CHECK-NEXT: ori 29, 29, 46712 ; CHECK-NEXT: ori 29, 29, 46712
; CHECK-NEXT: ori 28, 28, 21880
; CHECK-NEXT: ori 27, 27, 8312
; CHECK-NEXT: ori 26, 26, 60280
; CHECK-NEXT: ori 25, 25, 35448
; CHECK-NEXT: add 7, 4, 7
; CHECK-NEXT: sldi 5, 5, 32 ; CHECK-NEXT: sldi 5, 5, 32
; CHECK-NEXT: oris 5, 5, 29347 ; CHECK-NEXT: oris 5, 5, 29347
; CHECK-NEXT: ori 5, 5, 20088 ; CHECK-NEXT: ori 5, 5, 20088
; CHECK-NEXT: std 7, 384(1) # 8-byte Folded Spill
; CHECK-NEXT: add 7, 4, 8
; CHECK-NEXT: lis 8, 402 ; CHECK-NEXT: lis 8, 402
; CHECK-NEXT: std 7, 376(1) # 8-byte Folded Spill
; CHECK-NEXT: add 7, 4, 9
; CHECK-NEXT: lis 9, 451 ; CHECK-NEXT: lis 9, 451
; CHECK-NEXT: std 7, 368(1) # 8-byte Folded Spill
; CHECK-NEXT: add 7, 4, 10
; CHECK-NEXT: lis 10, 500 ; CHECK-NEXT: lis 10, 500
; CHECK-NEXT: std 7, 360(1) # 8-byte Folded Spill
; CHECK-NEXT: add 7, 4, 11
; CHECK-NEXT: lis 11, 549 ; CHECK-NEXT: lis 11, 549
; CHECK-NEXT: std 31, 712(1) # 8-byte Folded Spill ; CHECK-NEXT: std 7, 352(1) # 8-byte Folded Spill
; CHECK-NEXT: std 2, 568(1) # 8-byte Folded Spill ; CHECK-NEXT: add 7, 4, 12
; CHECK-NEXT: std 7, 344(1) # 8-byte Folded Spill ; CHECK-NEXT: std 7, 344(1) # 8-byte Folded Spill
; CHECK-NEXT: add 7, 4, 0 ; CHECK-NEXT: add 7, 4, 0
; CHECK-NEXT: std 28, 688(1) # 8-byte Folded Spill
; CHECK-NEXT: oris 28, 6, 13164
; CHECK-NEXT: ori 28, 28, 21880
; CHECK-NEXT: std 7, 336(1) # 8-byte Folded Spill ; CHECK-NEXT: std 7, 336(1) # 8-byte Folded Spill
; CHECK-NEXT: add 7, 4, 30 ; CHECK-NEXT: add 7, 4, 30
; CHECK-NEXT: std 27, 680(1) # 8-byte Folded Spill
; CHECK-NEXT: oris 27, 6, 13152
; CHECK-NEXT: ori 27, 27, 8312
; CHECK-NEXT: std 7, 328(1) # 8-byte Folded Spill ; CHECK-NEXT: std 7, 328(1) # 8-byte Folded Spill
; CHECK-NEXT: add 7, 4, 29 ; CHECK-NEXT: add 7, 4, 29
; CHECK-NEXT: std 26, 672(1) # 8-byte Folded Spill
; CHECK-NEXT: oris 26, 6, 13139
; CHECK-NEXT: ori 26, 26, 60280
; CHECK-NEXT: std 7, 320(1) # 8-byte Folded Spill ; CHECK-NEXT: std 7, 320(1) # 8-byte Folded Spill
; CHECK-NEXT: add 7, 4, 28 ; CHECK-NEXT: add 7, 4, 28
; CHECK-NEXT: std 25, 664(1) # 8-byte Folded Spill
; CHECK-NEXT: oris 25, 6, 13176
; CHECK-NEXT: ori 25, 25, 35448
; CHECK-NEXT: std 7, 312(1) # 8-byte Folded Spill ; CHECK-NEXT: std 7, 312(1) # 8-byte Folded Spill
; CHECK-NEXT: add 7, 4, 27 ; CHECK-NEXT: add 7, 4, 27
; CHECK-NEXT: std 7, 304(1) # 8-byte Folded Spill ; CHECK-NEXT: std 7, 304(1) # 8-byte Folded Spill
; CHECK-NEXT: add 7, 4, 26 ; CHECK-NEXT: add 7, 4, 26
; CHECK-NEXT: std 7, 296(1) # 8-byte Folded Spill ; CHECK-NEXT: std 7, 296(1) # 8-byte Folded Spill
; CHECK-NEXT: add 7, 4, 25 ; CHECK-NEXT: add 7, 4, 25
; CHECK-NEXT: std 7, 288(1) # 8-byte Folded Spill ; CHECK-NEXT: std 7, 288(1) # 8-byte Folded Spill
; CHECK-NEXT: oris 7, 6, 13213 ; CHECK-NEXT: oris 7, 6, 13213
; CHECK-NEXT: ori 7, 7, 10616 ; CHECK-NEXT: ori 7, 7, 10616
; CHECK-NEXT: add 7, 4, 7 ; CHECK-NEXT: add 7, 4, 7
; CHECK-NEXT: std 7, 280(1) # 8-byte Folded Spill ; CHECK-NEXT: std 7, 280(1) # 8-byte Folded Spill
; CHECK-NEXT: oris 7, 6, 13200 ; CHECK-NEXT: oris 7, 6, 13200
; CHECK-NEXT: oris 6, 6, 13188 ; CHECK-NEXT: oris 6, 6, 13188
; CHECK-NEXT: ori 7, 7, 62584 ; CHECK-NEXT: ori 7, 7, 62584
; CHECK-NEXT: ori 6, 6, 49016 ; CHECK-NEXT: ori 6, 6, 49016
; CHECK-NEXT: add 7, 4, 7 ; CHECK-NEXT: add 7, 4, 7
; CHECK-NEXT: add 6, 4, 6 ; CHECK-NEXT: add 6, 4, 6
; CHECK-NEXT: add 4, 4, 5 ; CHECK-NEXT: add 4, 4, 5
; CHECK-NEXT: lis 5, 268 ; CHECK-NEXT: lis 5, 268
; CHECK-NEXT: std 4, 256(1) # 8-byte Folded Spill ; CHECK-NEXT: std 4, 256(1) # 8-byte Folded Spill
; CHECK-NEXT: lis 4, 585 ; CHECK-NEXT: lis 4, 585
; CHECK-NEXT: std 6, 264(1) # 8-byte Folded Spill
; CHECK-NEXT: lis 6, 305
; CHECK-NEXT: std 7, 272(1) # 8-byte Folded Spill
; CHECK-NEXT: lis 7, 354
; CHECK-NEXT: ori 4, 4, 61440 ; CHECK-NEXT: ori 4, 4, 61440
; CHECK-NEXT: std 4, 560(1) # 8-byte Folded Spill ; CHECK-NEXT: std 4, 560(1) # 8-byte Folded Spill
; CHECK-NEXT: lis 4, 48 ; CHECK-NEXT: lis 4, 48
; CHECK-NEXT: ori 4, 4, 54272 ; CHECK-NEXT: ori 4, 4, 54272
; CHECK-NEXT: std 4, 552(1) # 8-byte Folded Spill ; CHECK-NEXT: std 4, 552(1) # 8-byte Folded Spill
; CHECK-NEXT: lis 4, 97 ; CHECK-NEXT: lis 4, 97
; CHECK-NEXT: ori 4, 4, 43008 ; CHECK-NEXT: ori 4, 4, 43008
; CHECK-NEXT: std 4, 544(1) # 8-byte Folded Spill ; CHECK-NEXT: std 4, 544(1) # 8-byte Folded Spill
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
; CHECK-NEXT: lis 4, 170 ; CHECK-NEXT: lis 4, 170
; CHECK-NEXT: ori 4, 4, 58880 ; CHECK-NEXT: ori 4, 4, 58880
; CHECK-NEXT: std 4, 200(1) # 8-byte Folded Spill ; CHECK-NEXT: std 4, 200(1) # 8-byte Folded Spill
; CHECK-NEXT: lis 4, 219 ; CHECK-NEXT: lis 4, 219
; CHECK-NEXT: ori 4, 4, 47616 ; CHECK-NEXT: ori 4, 4, 47616
; CHECK-NEXT: std 4, 192(1) # 8-byte Folded Spill ; CHECK-NEXT: std 4, 192(1) # 8-byte Folded Spill
; CHECK-NEXT: ori 4, 5, 36352 ; CHECK-NEXT: ori 4, 5, 36352
; CHECK-NEXT: lis 5, 317 ; CHECK-NEXT: lis 5, 317
; CHECK-NEXT: ld 30, 192(1) # 8-byte Folded Reload
; CHECK-NEXT: std 4, 184(1) # 8-byte Folded Spill ; CHECK-NEXT: std 4, 184(1) # 8-byte Folded Spill
; CHECK-NEXT: ori 4, 5, 25088 ; CHECK-NEXT: ori 4, 5, 25088
; CHECK-NEXT: lis 5, 366 ; CHECK-NEXT: lis 5, 366
; CHECK-NEXT: ld 29, 184(1) # 8-byte Folded Reload
; CHECK-NEXT: std 4, 176(1) # 8-byte Folded Spill ; CHECK-NEXT: std 4, 176(1) # 8-byte Folded Spill
; CHECK-NEXT: ori 4, 5, 13824 ; CHECK-NEXT: ori 4, 5, 13824
; CHECK-NEXT: lis 5, 415 ; CHECK-NEXT: lis 5, 415
; CHECK-NEXT: ld 28, 176(1) # 8-byte Folded Reload
; CHECK-NEXT: std 4, 168(1) # 8-byte Folded Spill ; CHECK-NEXT: std 4, 168(1) # 8-byte Folded Spill
; CHECK-NEXT: ori 4, 5, 2560 ; CHECK-NEXT: ori 4, 5, 2560
; CHECK-NEXT: lis 5, 463 ; CHECK-NEXT: lis 5, 463
; CHECK-NEXT: ld 27, 168(1) # 8-byte Folded Reload
; CHECK-NEXT: std 4, 160(1) # 8-byte Folded Spill ; CHECK-NEXT: std 4, 160(1) # 8-byte Folded Spill
; CHECK-NEXT: ori 4, 5, 56832 ; CHECK-NEXT: ori 4, 5, 56832
; CHECK-NEXT: lis 5, 512 ; CHECK-NEXT: lis 5, 512
; CHECK-NEXT: ld 26, 160(1) # 8-byte Folded Reload
; CHECK-NEXT: std 4, 152(1) # 8-byte Folded Spill ; CHECK-NEXT: std 4, 152(1) # 8-byte Folded Spill
; CHECK-NEXT: ori 4, 5, 45568 ; CHECK-NEXT: ori 4, 5, 45568
; CHECK-NEXT: lis 5, 561 ; CHECK-NEXT: lis 5, 561
; CHECK-NEXT: ld 25, 152(1) # 8-byte Folded Reload
; CHECK-NEXT: std 4, 144(1) # 8-byte Folded Spill ; CHECK-NEXT: std 4, 144(1) # 8-byte Folded Spill
; CHECK-NEXT: ori 4, 5, 34304 ; CHECK-NEXT: ori 4, 5, 34304
; CHECK-NEXT: lis 5, 12 ; CHECK-NEXT: lis 5, 12
; CHECK-NEXT: ld 24, 144(1) # 8-byte Folded Reload
; CHECK-NEXT: std 4, 136(1) # 8-byte Folded Spill ; CHECK-NEXT: std 4, 136(1) # 8-byte Folded Spill
; CHECK-NEXT: ori 4, 5, 13568 ; CHECK-NEXT: ori 4, 5, 13568
; CHECK-NEXT: lis 5, 61 ; CHECK-NEXT: lis 5, 61
; CHECK-NEXT: ld 23, 136(1) # 8-byte Folded Reload
; CHECK-NEXT: std 4, 128(1) # 8-byte Folded Spill ; CHECK-NEXT: std 4, 128(1) # 8-byte Folded Spill
; CHECK-NEXT: ori 4, 5, 2304 ; CHECK-NEXT: ori 4, 5, 2304
; CHECK-NEXT: lis 5, 109 ; CHECK-NEXT: lis 5, 109
; CHECK-NEXT: std 4, 120(1) # 8-byte Folded Spill ; CHECK-NEXT: std 4, 120(1) # 8-byte Folded Spill
; CHECK-NEXT: ori 4, 5, 56576 ; CHECK-NEXT: ori 4, 5, 56576
; CHECK-NEXT: lis 5, 158 ; CHECK-NEXT: lis 5, 158
; CHECK-NEXT: ld 0, 120(1) # 8-byte Folded Reload
; CHECK-NEXT: std 4, 112(1) # 8-byte Folded Spill ; CHECK-NEXT: std 4, 112(1) # 8-byte Folded Spill
; CHECK-NEXT: ori 4, 5, 45312 ; CHECK-NEXT: ori 4, 5, 45312
; CHECK-NEXT: lis 5, 207 ; CHECK-NEXT: lis 5, 207
; CHECK-NEXT: ld 22, 112(1) # 8-byte Folded Reload
; CHECK-NEXT: std 4, 104(1) # 8-byte Folded Spill ; CHECK-NEXT: std 4, 104(1) # 8-byte Folded Spill
; CHECK-NEXT: ori 4, 5, 34048 ; CHECK-NEXT: ori 4, 5, 34048
; CHECK-NEXT: lis 5, 256 ; CHECK-NEXT: lis 5, 256
; CHECK-NEXT: std 6, 264(1) # 8-byte Folded Spill ; CHECK-NEXT: ld 21, 104(1) # 8-byte Folded Reload
; CHECK-NEXT: lis 6, 305
; CHECK-NEXT: ld 30, 192(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 29, 184(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 28, 176(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 27, 168(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 26, 160(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 25, 152(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 0, 120(1) # 8-byte Folded Reload
; CHECK-NEXT: std 4, 96(1) # 8-byte Folded Spill ; CHECK-NEXT: std 4, 96(1) # 8-byte Folded Spill
; CHECK-NEXT: ori 4, 5, 22784 ; CHECK-NEXT: ori 4, 5, 22784
; CHECK-NEXT: std 7, 272(1) # 8-byte Folded Spill ; CHECK-NEXT: ld 5, 248(1) # 8-byte Folded Reload
; CHECK-NEXT: lis 7, 354 ; CHECK-NEXT: ld 20, 96(1) # 8-byte Folded Reload
; CHECK-NEXT: std 4, 88(1) # 8-byte Folded Spill ; CHECK-NEXT: std 4, 88(1) # 8-byte Folded Spill
; CHECK-NEXT: ori 4, 6, 11520 ; CHECK-NEXT: ori 4, 6, 11520
; CHECK-NEXT: ld 6, 240(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 6, 240(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 19, 88(1) # 8-byte Folded Reload
; CHECK-NEXT: std 4, 80(1) # 8-byte Folded Spill ; CHECK-NEXT: std 4, 80(1) # 8-byte Folded Spill
; CHECK-NEXT: ori 4, 7, 256 ; CHECK-NEXT: ori 4, 7, 256
; CHECK-NEXT: ld 7, 232(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 7, 232(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 18, 80(1) # 8-byte Folded Reload
; CHECK-NEXT: std 4, 72(1) # 8-byte Folded Spill ; CHECK-NEXT: std 4, 72(1) # 8-byte Folded Spill
; CHECK-NEXT: ori 4, 8, 54528 ; CHECK-NEXT: ori 4, 8, 54528
; CHECK-NEXT: ld 8, 224(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 8, 224(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 17, 72(1) # 8-byte Folded Reload
; CHECK-NEXT: std 4, 64(1) # 8-byte Folded Spill ; CHECK-NEXT: std 4, 64(1) # 8-byte Folded Spill
; CHECK-NEXT: ori 4, 9, 43264 ; CHECK-NEXT: ori 4, 9, 43264
; CHECK-NEXT: ld 9, 216(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 9, 216(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 16, 64(1) # 8-byte Folded Reload
; CHECK-NEXT: std 4, 56(1) # 8-byte Folded Spill ; CHECK-NEXT: std 4, 56(1) # 8-byte Folded Spill
; CHECK-NEXT: ori 4, 10, 32000 ; CHECK-NEXT: ori 4, 10, 32000
; CHECK-NEXT: ld 10, 208(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 10, 208(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 15, 56(1) # 8-byte Folded Reload
; CHECK-NEXT: std 4, 48(1) # 8-byte Folded Spill ; CHECK-NEXT: std 4, 48(1) # 8-byte Folded Spill
; CHECK-NEXT: ori 4, 11, 20736 ; CHECK-NEXT: ori 4, 11, 20736
; CHECK-NEXT: ld 11, 200(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 11, 200(1) # 8-byte Folded Reload
; CHECK-NEXT: std 4, 40(1) # 8-byte Folded Spill
; CHECK-NEXT: std 14, 576(1) # 8-byte Folded Spill
; CHECK-NEXT: std 15, 584(1) # 8-byte Folded Spill
; CHECK-NEXT: std 16, 592(1) # 8-byte Folded Spill
; CHECK-NEXT: std 17, 600(1) # 8-byte Folded Spill
; CHECK-NEXT: std 18, 608(1) # 8-byte Folded Spill
; CHECK-NEXT: std 19, 616(1) # 8-byte Folded Spill
; CHECK-NEXT: std 20, 624(1) # 8-byte Folded Spill
; CHECK-NEXT: std 21, 632(1) # 8-byte Folded Spill
; CHECK-NEXT: std 22, 640(1) # 8-byte Folded Spill
; CHECK-NEXT: std 23, 648(1) # 8-byte Folded Spill
; CHECK-NEXT: std 24, 656(1) # 8-byte Folded Spill
; CHECK-NEXT: ld 5, 248(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 24, 144(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 23, 136(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 22, 112(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 21, 104(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 20, 96(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 19, 88(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 18, 80(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 17, 72(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 16, 64(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 15, 56(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 14, 48(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 14, 48(1) # 8-byte Folded Reload
; CHECK-NEXT: std 4, 40(1) # 8-byte Folded Spill
; CHECK-NEXT: li 4, 0 ; CHECK-NEXT: li 4, 0
; CHECK-NEXT: ld 31, 40(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 31, 40(1) # 8-byte Folded Reload
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_1: # =>This Loop Header: Depth=1 ; CHECK-NEXT: .LBB0_1: # =>This Loop Header: Depth=1
; CHECK-NEXT: # Child Loop BB0_2 Depth 2 ; CHECK-NEXT: # Child Loop BB0_2 Depth 2
; CHECK-NEXT: stw 4, 396(1) # 4-byte Folded Spill ; CHECK-NEXT: stw 4, 396(1) # 4-byte Folded Spill
; CHECK-NEXT: li 4, 83 ; CHECK-NEXT: li 4, 83
; CHECK-NEXT: mtctr 4 ; CHECK-NEXT: mtctr 4
; CHECK-NEXT: ld 12, 256(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 12, 256(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 4, 128(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 4, 128(1) # 8-byte Folded Reload
; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .p2align 5
; CHECK-NEXT: .LBB0_2: # Parent Loop BB0_1 Depth=1 ; CHECK-NEXT: .LBB0_2: # Parent Loop BB0_1 Depth=1
; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: # => This Inner Loop Header: Depth=2
; CHECK-NEXT: ld 2, 560(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 2, 560(1) # 8-byte Folded Reload
; CHECK-NEXT: stdux 3, 12, 2 ; CHECK-NEXT: stdux 3, 12, 2
; CHECK-NEXT: ld 2, 552(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 2, 552(1) # 8-byte Folded Reload
; CHECK-NEXT: stdx 3, 12, 5 ; CHECK-NEXT: stdx 3, 12, 5
; CHECK-NEXT: stdx 3, 12, 6
; CHECK-NEXT: stdx 3, 12, 7
; CHECK-NEXT: stdx 3, 12, 8
; CHECK-NEXT: stdx 3, 12, 9
; CHECK-NEXT: stdx 3, 12, 10
; CHECK-NEXT: stdx 3, 12, 11
; CHECK-NEXT: stdx 3, 12, 30
; CHECK-NEXT: stdx 3, 12, 29
; CHECK-NEXT: stdx 3, 12, 28
; CHECK-NEXT: stdx 3, 12, 27
; CHECK-NEXT: stdx 3, 12, 26
; CHECK-NEXT: stdx 3, 12, 25
; CHECK-NEXT: stdx 3, 12, 24
; CHECK-NEXT: stdx 3, 12, 23
; CHECK-NEXT: stdx 3, 12, 4
; CHECK-NEXT: stdx 3, 12, 0
; CHECK-NEXT: stdx 3, 12, 22
; CHECK-NEXT: stdx 3, 12, 21
; CHECK-NEXT: stdx 3, 12, 20
; CHECK-NEXT: stdx 3, 12, 19
; CHECK-NEXT: stdx 3, 12, 18
; CHECK-NEXT: stdx 3, 12, 17
; CHECK-NEXT: stdx 3, 12, 16
; CHECK-NEXT: stdx 3, 12, 15
; CHECK-NEXT: stdx 3, 12, 14
; CHECK-NEXT: stdx 3, 12, 31
; CHECK-NEXT: stdx 3, 12, 2 ; CHECK-NEXT: stdx 3, 12, 2
; CHECK-NEXT: ld 2, 544(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 2, 544(1) # 8-byte Folded Reload
; CHECK-NEXT: stdx 3, 12, 2 ; CHECK-NEXT: stdx 3, 12, 2
; CHECK-NEXT: ld 2, 536(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 2, 536(1) # 8-byte Folded Reload
; CHECK-NEXT: stdx 3, 12, 2 ; CHECK-NEXT: stdx 3, 12, 2
; CHECK-NEXT: ld 2, 528(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 2, 528(1) # 8-byte Folded Reload
; CHECK-NEXT: stdx 3, 12, 2 ; CHECK-NEXT: stdx 3, 12, 2
; CHECK-NEXT: ld 2, 520(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 2, 520(1) # 8-byte Folded Reload
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; CHECK-NEXT: ld 2, 424(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 2, 424(1) # 8-byte Folded Reload
; CHECK-NEXT: stdx 3, 12, 2 ; CHECK-NEXT: stdx 3, 12, 2
; CHECK-NEXT: ld 2, 416(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 2, 416(1) # 8-byte Folded Reload
; CHECK-NEXT: stdx 3, 12, 2 ; CHECK-NEXT: stdx 3, 12, 2
; CHECK-NEXT: ld 2, 408(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 2, 408(1) # 8-byte Folded Reload
; CHECK-NEXT: stdx 3, 12, 2 ; CHECK-NEXT: stdx 3, 12, 2
; CHECK-NEXT: ld 2, 400(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 2, 400(1) # 8-byte Folded Reload
; CHECK-NEXT: stdx 3, 12, 2 ; CHECK-NEXT: stdx 3, 12, 2
; CHECK-NEXT: stdx 3, 12, 6
; CHECK-NEXT: stdx 3, 12, 7
; CHECK-NEXT: stdx 3, 12, 8
; CHECK-NEXT: stdx 3, 12, 9
; CHECK-NEXT: stdx 3, 12, 10
; CHECK-NEXT: stdx 3, 12, 11
; CHECK-NEXT: stdx 3, 12, 30
; CHECK-NEXT: stdx 3, 12, 29
; CHECK-NEXT: stdx 3, 12, 28
; CHECK-NEXT: stdx 3, 12, 27
; CHECK-NEXT: stdx 3, 12, 26
; CHECK-NEXT: stdx 3, 12, 25
; CHECK-NEXT: stdx 3, 12, 24
; CHECK-NEXT: stdx 3, 12, 23
; CHECK-NEXT: stdx 3, 12, 4
; CHECK-NEXT: stdx 3, 12, 0
; CHECK-NEXT: stdx 3, 12, 22
; CHECK-NEXT: stdx 3, 12, 21
; CHECK-NEXT: stdx 3, 12, 20
; CHECK-NEXT: stdx 3, 12, 19
; CHECK-NEXT: stdx 3, 12, 18
; CHECK-NEXT: stdx 3, 12, 17
; CHECK-NEXT: stdx 3, 12, 16
; CHECK-NEXT: stdx 3, 12, 15
; CHECK-NEXT: stdx 3, 12, 14
; CHECK-NEXT: stdx 3, 12, 31
; CHECK-NEXT: bdnz .LBB0_2 ; CHECK-NEXT: bdnz .LBB0_2
; CHECK-NEXT: # %bb.3: ; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: ld 12, 384(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 12, 384(1) # 8-byte Folded Reload
; CHECK-NEXT: lwz 4, 396(1) # 4-byte Folded Reload
; CHECK-NEXT: addi 4, 4, 1
; CHECK-NEXT: std 3, 0(12) ; CHECK-NEXT: std 3, 0(12)
; CHECK-NEXT: ld 12, 376(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 12, 376(1) # 8-byte Folded Reload
; CHECK-NEXT: std 3, 0(12) ; CHECK-NEXT: std 3, 0(12)
; CHECK-NEXT: ld 12, 368(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 12, 368(1) # 8-byte Folded Reload
; CHECK-NEXT: std 3, 0(12) ; CHECK-NEXT: std 3, 0(12)
; CHECK-NEXT: ld 12, 360(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 12, 360(1) # 8-byte Folded Reload
; CHECK-NEXT: std 3, 0(12) ; CHECK-NEXT: std 3, 0(12)
; CHECK-NEXT: ld 12, 352(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 12, 352(1) # 8-byte Folded Reload
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; CHECK-NEXT: std 3, 0(12) ; CHECK-NEXT: std 3, 0(12)
; CHECK-NEXT: ld 12, 304(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 12, 304(1) # 8-byte Folded Reload
; CHECK-NEXT: std 3, 0(12) ; CHECK-NEXT: std 3, 0(12)
; CHECK-NEXT: ld 12, 296(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 12, 296(1) # 8-byte Folded Reload
; CHECK-NEXT: std 3, 0(12) ; CHECK-NEXT: std 3, 0(12)
; CHECK-NEXT: ld 12, 288(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 12, 288(1) # 8-byte Folded Reload
; CHECK-NEXT: std 3, 0(12) ; CHECK-NEXT: std 3, 0(12)
; CHECK-NEXT: ld 12, 280(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 12, 280(1) # 8-byte Folded Reload
; CHECK-NEXT: lwz 4, 396(1) # 4-byte Folded Reload
; CHECK-NEXT: addi 4, 4, 1
; CHECK-NEXT: std 3, 0(12) ; CHECK-NEXT: std 3, 0(12)
; CHECK-NEXT: ld 12, 272(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 12, 272(1) # 8-byte Folded Reload
; CHECK-NEXT: std 3, 0(12) ; CHECK-NEXT: std 3, 0(12)
; CHECK-NEXT: xoris 12, 4, 6 ; CHECK-NEXT: xoris 12, 4, 6
; CHECK-NEXT: cmplwi 12, 6784 ; CHECK-NEXT: cmplwi 12, 6784
; CHECK-NEXT: ld 12, 264(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 12, 264(1) # 8-byte Folded Reload
; CHECK-NEXT: std 3, 0(12) ; CHECK-NEXT: std 3, 0(12)
; CHECK-NEXT: bne 0, .LBB0_1 ; CHECK-NEXT: bne 0, .LBB0_1
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llvm/test/CodeGen/PowerPC/remove-redundant-load-imm.ll

Show All 34 Lines
define void @redundancy_on_ppc_and_other_targets() nounwind { define void @redundancy_on_ppc_and_other_targets() nounwind {
; PPC64LE-LABEL: redundancy_on_ppc_and_other_targets: ; PPC64LE-LABEL: redundancy_on_ppc_and_other_targets:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: mflr 0 ; PPC64LE-NEXT: mflr 0
; PPC64LE-NEXT: std 0, 16(1) ; PPC64LE-NEXT: std 0, 16(1)
; PPC64LE-NEXT: stdu 1, -32(1) ; PPC64LE-NEXT: stdu 1, -32(1)
; PPC64LE-NEXT: addis 3, 2, .LC0@toc@ha ; PPC64LE-NEXT: addis 3, 2, .LC0@toc@ha
; PPC64LE-NEXT: ld 3, .LC0@toc@l(3)
; PPC64LE-NEXT: li 4, 0 ; PPC64LE-NEXT: li 4, 0
; PPC64LE-NEXT: ld 3, .LC0@toc@l(3)
; PPC64LE-NEXT: std 4, 0(3) ; PPC64LE-NEXT: std 4, 0(3)
; PPC64LE-NEXT: bl barney.94 ; PPC64LE-NEXT: bl barney.94
; PPC64LE-NEXT: nop ; PPC64LE-NEXT: nop
store i32* null, i32** @global.6 store i32* null, i32** @global.6
call void @barney.94(i8* undef, i32 0) call void @barney.94(i8* undef, i32 0)
unreachable unreachable
} }

llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll

Show First 20 Lines • Show All 160 Lines • ▼ Show 20 Linesentry:
ret <4 x float> %vecins ret <4 x float> %vecins
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define <2 x float> @s2v_test_f2(float* nocapture readonly %f64, <2 x float> %vec) { define <2 x float> @s2v_test_f2(float* nocapture readonly %f64, <2 x float> %vec) {
; P9LE-LABEL: s2v_test_f2: ; P9LE-LABEL: s2v_test_f2:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: addi r3, r3, 4 ; P9LE-NEXT: addi r3, r3, 4
; P9LE-NEXT: lxsiwzx v3, 0, r3
; P9LE-NEXT: vmrglw v2, v2, v2 ; P9LE-NEXT: vmrglw v2, v2, v2
; P9LE-NEXT: lxsiwzx v3, 0, r3
; P9LE-NEXT: vmrghw v2, v2, v3 ; P9LE-NEXT: vmrghw v2, v2, v3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; P9BE-LABEL: s2v_test_f2: ; P9BE-LABEL: s2v_test_f2:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE: addi r3, r3, 4 ; P9BE: addi r3, r3, 4
; P9BE-DAG: xxspltw v2, v2, 1 ; P9BE-DAG: xxspltw v2, v2, 1
; P9BE-DAG: lfiwzx f0, 0, r3 ; P9BE-DAG: lfiwzx f0, 0, r3
Show All 24 Linesentry:
ret <2 x float> %vecins ret <2 x float> %vecins
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define <2 x float> @s2v_test_f3(float* nocapture readonly %f64, <2 x float> %vec, i32 signext %Idx) { define <2 x float> @s2v_test_f3(float* nocapture readonly %f64, <2 x float> %vec, i32 signext %Idx) {
; P9LE-LABEL: s2v_test_f3: ; P9LE-LABEL: s2v_test_f3:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: sldi r4, r7, 2 ; P9LE-NEXT: sldi r4, r7, 2
; P9LE-NEXT: lxsiwzx v3, r3, r4
; P9LE-NEXT: vmrglw v2, v2, v2 ; P9LE-NEXT: vmrglw v2, v2, v2
; P9LE-NEXT: lxsiwzx v3, r3, r4
; P9LE-NEXT: vmrghw v2, v2, v3 ; P9LE-NEXT: vmrghw v2, v2, v3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; P9BE-LABEL: s2v_test_f3: ; P9BE-LABEL: s2v_test_f3:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE: sldi r4, r7, 2 ; P9BE: sldi r4, r7, 2
; P9BE: lfiwzx f0, r3, r4 ; P9BE-DAG: lfiwzx f0, r3, r4
; P9BE-DAG: xxspltw v2, v2, 1 ; P9BE-DAG: xxspltw v2, v2, 1
; P9BE-DAG: xxsldwi v3, f0, f0, 1 ; P9BE: xxsldwi v3, f0, f0, 1
; P9BE: vmrghw v2, v3, v2 ; P9BE: vmrghw v2, v3, v2
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; P8LE-LABEL: s2v_test_f3: ; P8LE-LABEL: s2v_test_f3:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: vmrglw v2, v2, v2 ; P8LE-NEXT: vmrglw v2, v2, v2
; P8LE-NEXT: sldi r4, r7, 2 ; P8LE-NEXT: sldi r4, r7, 2
; P8LE-NEXT: lxsiwzx v3, r3, r4 ; P8LE-NEXT: lxsiwzx v3, r3, r4
Show All 16 Linesentry:
ret <2 x float> %vecins ret <2 x float> %vecins
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define <2 x float> @s2v_test_f4(float* nocapture readonly %f64, <2 x float> %vec) { define <2 x float> @s2v_test_f4(float* nocapture readonly %f64, <2 x float> %vec) {
; P9LE-LABEL: s2v_test_f4: ; P9LE-LABEL: s2v_test_f4:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: addi r3, r3, 4 ; P9LE-NEXT: addi r3, r3, 4
; P9LE-NEXT: lxsiwzx v3, 0, r3
; P9LE-NEXT: vmrglw v2, v2, v2 ; P9LE-NEXT: vmrglw v2, v2, v2
; P9LE-NEXT: lxsiwzx v3, 0, r3
; P9LE-NEXT: vmrghw v2, v2, v3 ; P9LE-NEXT: vmrghw v2, v2, v3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; P9BE-LABEL: s2v_test_f4: ; P9BE-LABEL: s2v_test_f4:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE: addi r3, r3, 4 ; P9BE: addi r3, r3, 4
; P9BE: lfiwzx f0, 0, r3 ; P9BE-DAG: lfiwzx f0, 0, r3
; P9BE-DAG: xxspltw v2, v2, 1 ; P9BE-DAG: xxspltw v2, v2, 1
; P9BE-DAG: xxsldwi v3, f0, f0, 1 ; P9BE: xxsldwi v3, f0, f0, 1
; P9BE: vmrghw v2, v3, v2 ; P9BE: vmrghw v2, v3, v2
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; P8LE-LABEL: s2v_test_f4: ; P8LE-LABEL: s2v_test_f4:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: vmrglw v2, v2, v2 ; P8LE-NEXT: vmrglw v2, v2, v2
; P8LE-NEXT: addi r3, r3, 4 ; P8LE-NEXT: addi r3, r3, 4
; P8LE-NEXT: lxsiwzx v3, 0, r3 ; P8LE-NEXT: lxsiwzx v3, 0, r3
▲ Show 20 Lines • Show All 55 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/sched-addi.ll

Show All 12 Lines
; CHECK-P9-LABEL: test: ; CHECK-P9-LABEL: test:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ld 5, 0(5) ; CHECK-P9-NEXT: ld 5, 0(5)
; CHECK-P9-NEXT: addis 6, 2, scalars@toc@ha ; CHECK-P9-NEXT: addis 6, 2, scalars@toc@ha
; CHECK-P9-NEXT: addi 6, 6, scalars@toc@l ; CHECK-P9-NEXT: addi 6, 6, scalars@toc@l
; CHECK-P9-NEXT: addi 6, 6, 16 ; CHECK-P9-NEXT: addi 6, 6, 16
; CHECK-P9-NEXT: rldicr 5, 5, 0, 58 ; CHECK-P9-NEXT: rldicr 5, 5, 0, 58
; CHECK-P9-NEXT: addi 5, 5, -32 ; CHECK-P9-NEXT: addi 5, 5, -32
; CHECK-P9-NEXT: lxvdsx 0, 0, 6
; CHECK-P9-NEXT: rldicl 5, 5, 59, 5 ; CHECK-P9-NEXT: rldicl 5, 5, 59, 5
; CHECK-P9-NEXT: addi 5, 5, 1 ; CHECK-P9-NEXT: addi 5, 5, 1
; CHECK-P9-NEXT: lxvdsx 0, 0, 6
; CHECK-P9-NEXT: mtctr 5 ; CHECK-P9-NEXT: mtctr 5
; CHECK-P9-NEXT: .p2align 4 ; CHECK-P9-NEXT: .p2align 4
; CHECK-P9-NEXT: .LBB0_1: # %vector.body ; CHECK-P9-NEXT: .LBB0_1: # %vector.body
; CHECK-P9-NEXT: # ; CHECK-P9-NEXT: #
; CHECK-P9-NEXT: lxv 1, 16(4) ; CHECK-P9-NEXT: lxv 1, 16(4)
; CHECK-P9-NEXT: lxv 2, 0(4) ; CHECK-P9-NEXT: lxv 2, 0(4)
; CHECK-P9-NEXT: lxv 3, 48(4) ; CHECK-P9-NEXT: lxv 3, 48(4)
; CHECK-P9-NEXT: lxv 4, 32(4) ; CHECK-P9-NEXT: lxv 4, 32(4)
; CHECK-P9-NEXT: xvmuldp 2, 2, 0 ; CHECK-P9-NEXT: xvmuldp 2, 2, 0
; CHECK-P9-NEXT: lxv 5, 240(4) ; CHECK-P9-NEXT: lxv 5, 240(4)
; CHECK-P9-NEXT: lxv 6, 224(4) ; CHECK-P9-NEXT: lxv 6, 224(4)
; CHECK-P9-NEXT: xvmuldp 1, 1, 0 ; CHECK-P9-NEXT: xvmuldp 1, 1, 0
; CHECK-P9-NEXT: xvmuldp 4, 4, 0 ; CHECK-P9-NEXT: xvmuldp 4, 4, 0
; CHECK-P9-NEXT: xvmuldp 3, 3, 0 ; CHECK-P9-NEXT: xvmuldp 3, 3, 0
; CHECK-P9-NEXT: xvmuldp 5, 5, 0 ; CHECK-P9-NEXT: xvmuldp 5, 5, 0
; CHECK-P9-NEXT: addi 4, 4, 256
; CHECK-P9-NEXT: xvmuldp 6, 6, 0
; CHECK-P9-NEXT: stxv 1, 16(3) ; CHECK-P9-NEXT: stxv 1, 16(3)
; CHECK-P9-NEXT: stxv 2, 0(3)
; CHECK-P9-NEXT: stxv 3, 48(3) ; CHECK-P9-NEXT: stxv 3, 48(3)
; CHECK-P9-NEXT: stxv 4, 32(3) ; CHECK-P9-NEXT: stxv 4, 32(3)
; CHECK-P9-NEXT: stxv 5, 240(3) ; CHECK-P9-NEXT: stxv 5, 240(3)
; CHECK-P9-NEXT: addi 4, 4, 256
; CHECK-P9-NEXT: xvmuldp 6, 6, 0
; CHECK-P9-NEXT: stxv 2, 0(3)
; CHECK-P9-NEXT: stxv 6, 224(3) ; CHECK-P9-NEXT: stxv 6, 224(3)
; CHECK-P9-NEXT: addi 3, 3, 256 ; CHECK-P9-NEXT: addi 3, 3, 256
; CHECK-P9-NEXT: bdnz .LBB0_1 ; CHECK-P9-NEXT: bdnz .LBB0_1
; CHECK-P9-NEXT: # %bb.2: # %return.block ; CHECK-P9-NEXT: # %bb.2: # %return.block
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P9-NO-HEURISTIC-LABEL: test: ; CHECK-P9-NO-HEURISTIC-LABEL: test:
; CHECK-P9-NO-HEURISTIC: # %bb.0: # %entry ; CHECK-P9-NO-HEURISTIC: # %bb.0: # %entry
; CHECK-P9-NO-HEURISTIC-NEXT: ld 5, 0(5) ; CHECK-P9-NO-HEURISTIC-NEXT: ld 5, 0(5)
; CHECK-P9-NO-HEURISTIC-NEXT: addis 6, 2, scalars@toc@ha ; CHECK-P9-NO-HEURISTIC-NEXT: addis 6, 2, scalars@toc@ha
; CHECK-P9-NO-HEURISTIC-NEXT: addi 6, 6, scalars@toc@l ; CHECK-P9-NO-HEURISTIC-NEXT: addi 6, 6, scalars@toc@l
; CHECK-P9-NO-HEURISTIC-NEXT: rldicr 5, 5, 0, 58 ; CHECK-P9-NO-HEURISTIC-NEXT: rldicr 5, 5, 0, 58
; CHECK-P9-NO-HEURISTIC-NEXT: addi 6, 6, 16 ; CHECK-P9-NO-HEURISTIC-NEXT: addi 6, 6, 16
; CHECK-P9-NO-HEURISTIC-NEXT: addi 5, 5, -32 ; CHECK-P9-NO-HEURISTIC-NEXT: addi 5, 5, -32
; CHECK-P9-NO-HEURISTIC-NEXT: lxvdsx 0, 0, 6
; CHECK-P9-NO-HEURISTIC-NEXT: rldicl 5, 5, 59, 5 ; CHECK-P9-NO-HEURISTIC-NEXT: rldicl 5, 5, 59, 5
; CHECK-P9-NO-HEURISTIC-NEXT: addi 5, 5, 1 ; CHECK-P9-NO-HEURISTIC-NEXT: addi 5, 5, 1
; CHECK-P9-NO-HEURISTIC-NEXT: lxvdsx 0, 0, 6
; CHECK-P9-NO-HEURISTIC-NEXT: mtctr 5 ; CHECK-P9-NO-HEURISTIC-NEXT: mtctr 5
; CHECK-P9-NO-HEURISTIC-NEXT: .p2align 4 ; CHECK-P9-NO-HEURISTIC-NEXT: .p2align 4
; CHECK-P9-NO-HEURISTIC-NEXT: .LBB0_1: # %vector.body ; CHECK-P9-NO-HEURISTIC-NEXT: .LBB0_1: # %vector.body
; CHECK-P9-NO-HEURISTIC-NEXT: # ; CHECK-P9-NO-HEURISTIC-NEXT: #
; CHECK-P9-NO-HEURISTIC-NEXT: lxv 1, 16(4) ; CHECK-P9-NO-HEURISTIC-NEXT: lxv 1, 16(4)
; CHECK-P9-NO-HEURISTIC-NEXT: lxv 2, 0(4) ; CHECK-P9-NO-HEURISTIC-NEXT: lxv 2, 0(4)
; CHECK-P9-NO-HEURISTIC-NEXT: lxv 3, 48(4) ; CHECK-P9-NO-HEURISTIC-NEXT: lxv 3, 48(4)
; CHECK-P9-NO-HEURISTIC-NEXT: lxv 4, 32(4) ; CHECK-P9-NO-HEURISTIC-NEXT: lxv 4, 32(4)
; CHECK-P9-NO-HEURISTIC-NEXT: xvmuldp 2, 2, 0 ; CHECK-P9-NO-HEURISTIC-NEXT: xvmuldp 2, 2, 0
; CHECK-P9-NO-HEURISTIC-NEXT: lxv 5, 240(4) ; CHECK-P9-NO-HEURISTIC-NEXT: lxv 5, 240(4)
; CHECK-P9-NO-HEURISTIC-NEXT: lxv 6, 224(4) ; CHECK-P9-NO-HEURISTIC-NEXT: lxv 6, 224(4)
; CHECK-P9-NO-HEURISTIC-NEXT: xvmuldp 1, 1, 0 ; CHECK-P9-NO-HEURISTIC-NEXT: xvmuldp 1, 1, 0
; CHECK-P9-NO-HEURISTIC-NEXT: xvmuldp 4, 4, 0 ; CHECK-P9-NO-HEURISTIC-NEXT: xvmuldp 4, 4, 0
; CHECK-P9-NO-HEURISTIC-NEXT: xvmuldp 3, 3, 0 ; CHECK-P9-NO-HEURISTIC-NEXT: xvmuldp 3, 3, 0
; CHECK-P9-NO-HEURISTIC-NEXT: xvmuldp 6, 6, 0 ; CHECK-P9-NO-HEURISTIC-NEXT: xvmuldp 6, 6, 0
; CHECK-P9-NO-HEURISTIC-NEXT: xvmuldp 5, 5, 0 ; CHECK-P9-NO-HEURISTIC-NEXT: xvmuldp 5, 5, 0
; CHECK-P9-NO-HEURISTIC-NEXT: addi 4, 4, 256
; CHECK-P9-NO-HEURISTIC-NEXT: stxv 1, 16(3) ; CHECK-P9-NO-HEURISTIC-NEXT: stxv 1, 16(3)
; CHECK-P9-NO-HEURISTIC-NEXT: stxv 2, 0(3) ; CHECK-P9-NO-HEURISTIC-NEXT: stxv 2, 0(3)
; CHECK-P9-NO-HEURISTIC-NEXT: stxv 3, 48(3) ; CHECK-P9-NO-HEURISTIC-NEXT: stxv 3, 48(3)
; CHECK-P9-NO-HEURISTIC-NEXT: stxv 4, 32(3) ; CHECK-P9-NO-HEURISTIC-NEXT: stxv 4, 32(3)
; CHECK-P9-NO-HEURISTIC-NEXT: stxv 5, 240(3) ; CHECK-P9-NO-HEURISTIC-NEXT: stxv 5, 240(3)
; CHECK-P9-NO-HEURISTIC-NEXT: stxv 6, 224(3) ; CHECK-P9-NO-HEURISTIC-NEXT: stxv 6, 224(3)
; CHECK-P9-NO-HEURISTIC-NEXT: addi 4, 4, 256
; CHECK-P9-NO-HEURISTIC-NEXT: addi 3, 3, 256 ; CHECK-P9-NO-HEURISTIC-NEXT: addi 3, 3, 256
; CHECK-P9-NO-HEURISTIC-NEXT: bdnz .LBB0_1 ; CHECK-P9-NO-HEURISTIC-NEXT: bdnz .LBB0_1
; CHECK-P9-NO-HEURISTIC-NEXT: # %bb.2: # %return.block ; CHECK-P9-NO-HEURISTIC-NEXT: # %bb.2: # %return.block
; CHECK-P9-NO-HEURISTIC-NEXT: blr ; CHECK-P9-NO-HEURISTIC-NEXT: blr
entry: entry:
%x_rvo_based_addr_3 = getelementptr inbounds [0 x %_elem_type_of_x], [0 x %_elem_type_of_x]* %.x, i64 0, i64 -1 %x_rvo_based_addr_3 = getelementptr inbounds [0 x %_elem_type_of_x], [0 x %_elem_type_of_x]* %.x, i64 0, i64 -1
%a_rvo_based_addr_5 = getelementptr inbounds [0 x %_elem_type_of_a], [0 x %_elem_type_of_a]* %.a, i64 0, i64 -1 %a_rvo_based_addr_5 = getelementptr inbounds [0 x %_elem_type_of_a], [0 x %_elem_type_of_a]* %.a, i64 0, i64 -1
%_val_n_ = load i64, i64* %.n, align 8 %_val_n_ = load i64, i64* %.n, align 8
▲ Show 20 Lines • Show All 68 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/sms-cpy-1.ll

Show All 16 Lines
; CHECK-NEXT: li 3, 1 ; CHECK-NEXT: li 3, 1
; CHECK-NEXT: iselgt 3, 4, 3 ; CHECK-NEXT: iselgt 3, 4, 3
; CHECK-NEXT: li 4, 2 ; CHECK-NEXT: li 4, 2
; CHECK-NEXT: addi 3, 3, -1 ; CHECK-NEXT: addi 3, 3, -1
; CHECK-NEXT: cmpldi 3, 2 ; CHECK-NEXT: cmpldi 3, 2
; CHECK-NEXT: isellt 3, 3, 4 ; CHECK-NEXT: isellt 3, 3, 4
; CHECK-NEXT: li 4, 0 ; CHECK-NEXT: li 4, 0
; CHECK-NEXT: addi 3, 3, 1 ; CHECK-NEXT: addi 3, 3, 1
; CHECK-NEXT: mtctr 3
; CHECK-NEXT: li 3, 1
; CHECK-NEXT: li 7, -1 ; CHECK-NEXT: li 7, -1
; CHECK-NEXT: li 5, 0 ; CHECK-NEXT: li 5, 0
; CHECK-NEXT: mtctr 3
; CHECK-NEXT: li 3, 1
; CHECK-NEXT: lbz 5, 0(5) ; CHECK-NEXT: lbz 5, 0(5)
; CHECK-NEXT: bdz .LBB0_6 ; CHECK-NEXT: bdz .LBB0_6
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: addi 3, 3, 1 ; CHECK-NEXT: addi 3, 3, 1
; CHECK-NEXT: addi 8, 7, -1 ; CHECK-NEXT: addi 8, 7, -1
; CHECK-NEXT: xori 6, 5, 84 ; CHECK-NEXT: xori 6, 5, 84
; CHECK-NEXT: clrldi 5, 7, 32 ; CHECK-NEXT: clrldi 5, 7, 32
; CHECK-NEXT: lbz 5, 0(5) ; CHECK-NEXT: lbz 5, 0(5)
Show All 20 Lines
; CHECK-NEXT: .LBB0_4: ; CHECK-NEXT: .LBB0_4:
; CHECK-NEXT: add 4, 4, 7 ; CHECK-NEXT: add 4, 4, 7
; CHECK-NEXT: .LBB0_5: ; CHECK-NEXT: .LBB0_5:
; CHECK-NEXT: cntlzw 6, 6 ; CHECK-NEXT: cntlzw 6, 6
; CHECK-NEXT: srwi 6, 6, 5 ; CHECK-NEXT: srwi 6, 6, 5
; CHECK-NEXT: add 4, 4, 6 ; CHECK-NEXT: add 4, 4, 6
; CHECK-NEXT: .LBB0_6: ; CHECK-NEXT: .LBB0_6:
; CHECK-NEXT: xori 5, 5, 84 ; CHECK-NEXT: xori 5, 5, 84
; CHECK-NEXT: cntlzw 5, 5
; CHECK-NEXT: clrldi 3, 3, 32 ; CHECK-NEXT: clrldi 3, 3, 32
; CHECK-NEXT: li 7, 0
; CHECK-NEXT: li 8, 3
; CHECK-NEXT: std 3, 104(1) ; CHECK-NEXT: std 3, 104(1)
; CHECK-NEXT: cntlzw 5, 5
; CHECK-NEXT: addis 3, 2, .LC0@toc@ha ; CHECK-NEXT: addis 3, 2, .LC0@toc@ha
; CHECK-NEXT: li 10, 0
; CHECK-NEXT: ld 3, .LC0@toc@l(3) ; CHECK-NEXT: ld 3, .LC0@toc@l(3)
; CHECK-NEXT: li 7, 0
; CHECK-NEXT: li 8, 3
; CHECK-NEXT: srwi 5, 5, 5 ; CHECK-NEXT: srwi 5, 5, 5
; CHECK-NEXT: add 4, 4, 5 ; CHECK-NEXT: add 4, 4, 5
; CHECK-NEXT: li 5, 0 ; CHECK-NEXT: li 5, 0
; CHECK-NEXT: std 5, 120(1) ; CHECK-NEXT: std 5, 120(1)
; CHECK-NEXT: li 5, 3 ; CHECK-NEXT: li 5, 3
; CHECK-NEXT: std 5, 96(1)
; CHECK-NEXT: clrldi 6, 4, 32 ; CHECK-NEXT: clrldi 6, 4, 32
; CHECK-NEXT: li 4, 3 ; CHECK-NEXT: li 4, 3
; CHECK-NEXT: std 5, 96(1)
; CHECK-NEXT: li 5, 0 ; CHECK-NEXT: li 5, 0
; CHECK-NEXT: li 10, 0
; CHECK-NEXT: bl printf ; CHECK-NEXT: bl printf
; CHECK-NEXT: nop ; CHECK-NEXT: nop
%1 = load i32, i32* undef, align 4 %1 = load i32, i32* undef, align 4
%2 = add i32 %1, -1 %2 = add i32 %1, -1
%3 = zext i32 %2 to i64 %3 = zext i32 %2 to i64
%4 = zext i32 3 to i64 %4 = zext i32 3 to i64
br label %5 br label %5
Show All 24 Lines

llvm/test/CodeGen/PowerPC/sms-grp-order.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\ ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\
; RUN: -mcpu=pwr9 --ppc-enable-pipeliner | FileCheck %s ; RUN: -mcpu=pwr9 --ppc-enable-pipeliner | FileCheck %s
define void @lame_encode_buffer_interleaved() local_unnamed_addr { define void @lame_encode_buffer_interleaved() local_unnamed_addr {
; CHECK-LABEL: lame_encode_buffer_interleaved: ; CHECK-LABEL: lame_encode_buffer_interleaved:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lha 3, 0(3) ; CHECK-NEXT: lha 3, 0(3)
; CHECK-NEXT: li 5, 1 ; CHECK-NEXT: li 5, 1
; CHECK-NEXT: sldi 5, 5, 62
; CHECK-NEXT: lhz 4, 0(0) ; CHECK-NEXT: lhz 4, 0(0)
; CHECK-NEXT: sldi 5, 5, 62
; CHECK-NEXT: mtctr 5 ; CHECK-NEXT: mtctr 5
; CHECK-NEXT: srawi 3, 3, 1 ; CHECK-NEXT: srawi 3, 3, 1
; CHECK-NEXT: addze 3, 3 ; CHECK-NEXT: addze 3, 3
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_1: ; CHECK-NEXT: .LBB0_1:
; CHECK-NEXT: extsh 4, 4 ; CHECK-NEXT: extsh 4, 4
; CHECK-NEXT: srawi 4, 4, 1 ; CHECK-NEXT: srawi 4, 4, 1
; CHECK-NEXT: addze 4, 4 ; CHECK-NEXT: addze 4, 4
Show All 28 Lines

llvm/test/CodeGen/PowerPC/sms-phi-3.ll

Show All 15 Lines
; CHECK-NEXT: mr 30, 3 ; CHECK-NEXT: mr 30, 3
; CHECK-NEXT: bl malloc ; CHECK-NEXT: bl malloc
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: mr 29, 3 ; CHECK-NEXT: mr 29, 3
; CHECK-NEXT: bl malloc ; CHECK-NEXT: bl malloc
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi 7, 30, -4 ; CHECK-NEXT: addi 7, 30, -4
; CHECK-NEXT: mtctr 3 ; CHECK-NEXT: mtctr 3
; CHECK-NEXT: lwzu 8, 4(7)
; CHECK-NEXT: addi 4, 29, -8 ; CHECK-NEXT: addi 4, 29, -8
; CHECK-NEXT: li 5, 0 ; CHECK-NEXT: li 5, 0
; CHECK-NEXT: lwzu 8, 4(7)
; CHECK-NEXT: bdz .LBB0_5 ; CHECK-NEXT: bdz .LBB0_5
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: extswsli 6, 5, 5 ; CHECK-NEXT: extswsli 6, 5, 5
; CHECK-NEXT: add 5, 8, 5 ; CHECK-NEXT: add 5, 8, 5
; CHECK-NEXT: lwzu 8, 4(7) ; CHECK-NEXT: lwzu 8, 4(7)
; CHECK-NEXT: bdz .LBB0_4 ; CHECK-NEXT: bdz .LBB0_4
; CHECK-NEXT: # %bb.2: ; CHECK-NEXT: # %bb.2:
; CHECK-NEXT: add 6, 3, 6 ; CHECK-NEXT: add 6, 3, 6
▲ Show 20 Lines • Show All 51 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/sms-simple.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc < %s -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr9 --ppc-enable-pipeliner \ ; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr9 --ppc-enable-pipeliner \
; RUN: | FileCheck %s ; RUN: | FileCheck %s
@x = dso_local local_unnamed_addr global <{ i32, i32, i32, i32, [1020 x i32] }> <{ i32 1, i32 2, i32 3, i32 4, [1020 x i32] zeroinitializer }>, align 4 @x = dso_local local_unnamed_addr global <{ i32, i32, i32, i32, [1020 x i32] }> <{ i32 1, i32 2, i32 3, i32 4, [1020 x i32] zeroinitializer }>, align 4
@y = dso_local global [1024 x i32] zeroinitializer, align 4 @y = dso_local global [1024 x i32] zeroinitializer, align 4
define dso_local i32* @foo() local_unnamed_addr { define dso_local i32* @foo() local_unnamed_addr {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, x@toc@ha ; CHECK-NEXT: addis r5, r2, x@toc@ha
; CHECK-NEXT: addi r5, r5, x@toc@l
; CHECK-NEXT: addi r5, r5, -8
; CHECK-NEXT: addis r6, r2, y@toc@ha ; CHECK-NEXT: addis r6, r2, y@toc@ha
; CHECK-NEXT: li r7, 340 ; CHECK-NEXT: li r7, 340
; CHECK-NEXT: addi r5, r5, x@toc@l
; CHECK-NEXT: addi r5, r5, -8
; CHECK-NEXT: addi r3, r6, y@toc@l ; CHECK-NEXT: addi r3, r6, y@toc@l
; CHECK-NEXT: lwz r6, y@toc@l(r6) ; CHECK-NEXT: lwz r6, y@toc@l(r6)
; CHECK-NEXT: mtctr r7 ; CHECK-NEXT: mtctr r7
; CHECK-NEXT: addi r4, r3, -8
; CHECK-NEXT: lwzu r7, 12(r5) ; CHECK-NEXT: lwzu r7, 12(r5)
; CHECK-NEXT: maddld r6, r7, r7, r6 ; CHECK-NEXT: maddld r6, r7, r7, r6
; CHECK-NEXT: lwz r7, 4(r5) ; CHECK-NEXT: lwz r7, 4(r5)
; CHECK-NEXT: addi r4, r3, -8
; CHECK-NEXT: stwu r6, 12(r4) ; CHECK-NEXT: stwu r6, 12(r4)
; CHECK-NEXT: maddld r6, r7, r7, r6 ; CHECK-NEXT: maddld r6, r7, r7, r6
; CHECK-NEXT: lwz r7, 8(r5) ; CHECK-NEXT: lwz r7, 8(r5)
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_1: # %for.body ; CHECK-NEXT: .LBB0_1: # %for.body
; CHECK-NEXT: # ; CHECK-NEXT: #
; CHECK-NEXT: maddld r7, r7, r7, r6 ; CHECK-NEXT: maddld r7, r7, r7, r6
; CHECK-NEXT: lwzu r8, 12(r5) ; CHECK-NEXT: lwzu r8, 12(r5)
; CHECK-NEXT: maddld r8, r8, r8, r7
; CHECK-NEXT: stw r6, 4(r4) ; CHECK-NEXT: stw r6, 4(r4)
; CHECK-NEXT: lwz r6, 4(r5) ; CHECK-NEXT: lwz r6, 4(r5)
; CHECK-NEXT: maddld r6, r6, r6, r8 ; CHECK-NEXT: maddld r8, r8, r8, r7
; CHECK-NEXT: stw r7, 8(r4) ; CHECK-NEXT: stw r7, 8(r4)
; CHECK-NEXT: lwz r7, 8(r5) ; CHECK-NEXT: lwz r7, 8(r5)
; CHECK-NEXT: maddld r6, r6, r6, r8
; CHECK-NEXT: stwu r8, 12(r4) ; CHECK-NEXT: stwu r8, 12(r4)
; CHECK-NEXT: bdnz .LBB0_1 ; CHECK-NEXT: bdnz .LBB0_1
; CHECK-NEXT: # %bb.2: ; CHECK-NEXT: # %bb.2:
; CHECK-NEXT: maddld r5, r7, r7, r6 ; CHECK-NEXT: maddld r5, r7, r7, r6
; CHECK-NEXT: stw r6, 4(r4) ; CHECK-NEXT: stw r6, 4(r4)
; CHECK-NEXT: stw r5, 8(r4) ; CHECK-NEXT: stw r5, 8(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
Show All 33 Lines

llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \ ; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,P9LE ; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,P9LE
; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \ ; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,P9BE ; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,P9BE
; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \ ; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,P8LE ; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,P8LE
; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \ ; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,P8BE ; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,P8BE
define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) { define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) {
; P9LE-LABEL: fold_srem_vec_1: ; P9LE-LABEL: fold_srem_vec_1:
; P9LE: # %bb.0: ; P9LE: # %bb.0:
; P9LE-NEXT: li r3, 0 ; P9LE-NEXT: li r3, 0
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: lis r4, -21386 ; P9LE-NEXT: lis r4, -21386
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: ori r4, r4, 37253 ; P9LE-NEXT: ori r4, r4, 37253
; P9LE-NEXT: extsh r3, r3 ; P9LE-NEXT: extsh r3, r3
; P9LE-NEXT: mulhw r4, r3, r4 ; P9LE-NEXT: mulhw r4, r3, r4
; P9LE-NEXT: add r4, r4, r3 ; P9LE-NEXT: add r4, r4, r3
; P9LE-NEXT: srwi r5, r4, 31 ; P9LE-NEXT: srwi r5, r4, 31
; P9LE-NEXT: srawi r4, r4, 6 ; P9LE-NEXT: srawi r4, r4, 6
; P9LE-NEXT: add r4, r4, r5 ; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: mulli r4, r4, 95 ; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: sub r3, r3, r4 ; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: lis r4, 31710 ; P9LE-NEXT: lis r4, 31710
; P9LE-NEXT: mtvsrd v3, r3 ; P9LE-NEXT: mtvsrd v3, r3
; P9LE-NEXT: li r3, 2 ; P9LE-NEXT: li r3, 2
; P9LE-NEXT: ori r4, r4, 63421
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r3, r3 ; P9LE-NEXT: extsh r3, r3
; P9LE-NEXT: ori r4, r4, 63421
; P9LE-NEXT: mulhw r4, r3, r4 ; P9LE-NEXT: mulhw r4, r3, r4
; P9LE-NEXT: sub r4, r4, r3 ; P9LE-NEXT: sub r4, r4, r3
; P9LE-NEXT: srwi r5, r4, 31 ; P9LE-NEXT: srwi r5, r4, 31
; P9LE-NEXT: srawi r4, r4, 6 ; P9LE-NEXT: srawi r4, r4, 6
; P9LE-NEXT: add r4, r4, r5 ; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: mulli r4, r4, -124 ; P9LE-NEXT: mulli r4, r4, -124
; P9LE-NEXT: sub r3, r3, r4 ; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: lis r4, 21399 ; P9LE-NEXT: lis r4, 21399
; P9LE-NEXT: mtvsrd v4, r3 ; P9LE-NEXT: mtvsrd v4, r3
; P9LE-NEXT: li r3, 4 ; P9LE-NEXT: li r3, 4
; P9LE-NEXT: ori r4, r4, 33437
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: vmrghh v3, v4, v3
; P9LE-NEXT: extsh r3, r3 ; P9LE-NEXT: extsh r3, r3
; P9LE-NEXT: ori r4, r4, 33437
; P9LE-NEXT: mulhw r4, r3, r4 ; P9LE-NEXT: mulhw r4, r3, r4
; P9LE-NEXT: srwi r5, r4, 31 ; P9LE-NEXT: srwi r5, r4, 31
; P9LE-NEXT: srawi r4, r4, 5 ; P9LE-NEXT: srawi r4, r4, 5
; P9LE-NEXT: add r4, r4, r5 ; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: mulli r4, r4, 98 ; P9LE-NEXT: mulli r4, r4, 98
; P9LE-NEXT: sub r3, r3, r4 ; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: vmrghh v3, v4, v3 ; P9LE-NEXT: lis r4, -16728
; P9LE-NEXT: mtvsrd v4, r3 ; P9LE-NEXT: mtvsrd v4, r3
; P9LE-NEXT: li r3, 6 ; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: lis r4, -16728
; P9LE-NEXT: ori r4, r4, 63249 ; P9LE-NEXT: ori r4, r4, 63249
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r3, r3 ; P9LE-NEXT: extsh r3, r3
; P9LE-NEXT: mulhw r4, r3, r4 ; P9LE-NEXT: mulhw r4, r3, r4
; P9LE-NEXT: srwi r5, r4, 31 ; P9LE-NEXT: srwi r5, r4, 31
; P9LE-NEXT: srawi r4, r4, 8 ; P9LE-NEXT: srawi r4, r4, 8
; P9LE-NEXT: add r4, r4, r5 ; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: mulli r4, r4, -1003 ; P9LE-NEXT: mulli r4, r4, -1003
; P9LE-NEXT: sub r3, r3, r4 ; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: mtvsrd v2, r3 ; P9LE-NEXT: mtvsrd v2, r3
; P9LE-NEXT: vmrghh v2, v2, v4 ; P9LE-NEXT: vmrghh v2, v2, v4
; P9LE-NEXT: vmrglw v2, v2, v3 ; P9LE-NEXT: vmrglw v2, v2, v3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P9BE-LABEL: fold_srem_vec_1: ; P9BE-LABEL: fold_srem_vec_1:
; P9BE: # %bb.0: ; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 2 ; P9BE-NEXT: li r3, 2
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: lis r4, 31710 ; P9BE-NEXT: lis r4, 31710
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: ori r4, r4, 63421 ; P9BE-NEXT: ori r4, r4, 63421
; P9BE-NEXT: extsh r3, r3 ; P9BE-NEXT: extsh r3, r3
; P9BE-NEXT: mulhw r4, r3, r4 ; P9BE-NEXT: mulhw r4, r3, r4
; P9BE-NEXT: sub r4, r4, r3 ; P9BE-NEXT: sub r4, r4, r3
; P9BE-NEXT: srwi r5, r4, 31 ; P9BE-NEXT: srwi r5, r4, 31
; P9BE-NEXT: srawi r4, r4, 6 ; P9BE-NEXT: srawi r4, r4, 6
; P9BE-NEXT: add r4, r4, r5 ; P9BE-NEXT: add r4, r4, r5
; P9BE-NEXT: mulli r4, r4, -124 ; P9BE-NEXT: mulli r4, r4, -124
; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: sub r3, r3, r4
; P9BE-NEXT: lis r4, -21386 ; P9BE-NEXT: lis r4, -21386
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: ori r4, r4, 37253
; P9BE-NEXT: mtvsrd v3, r3 ; P9BE-NEXT: mtvsrd v3, r3
; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: li r3, 0
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: extsh r3, r3 ; P9BE-NEXT: extsh r3, r3
; P9BE-NEXT: ori r4, r4, 37253
; P9BE-NEXT: mulhw r4, r3, r4 ; P9BE-NEXT: mulhw r4, r3, r4
; P9BE-NEXT: add r4, r4, r3 ; P9BE-NEXT: add r4, r4, r3
; P9BE-NEXT: srwi r5, r4, 31 ; P9BE-NEXT: srwi r5, r4, 31
; P9BE-NEXT: srawi r4, r4, 6 ; P9BE-NEXT: srawi r4, r4, 6
; P9BE-NEXT: add r4, r4, r5 ; P9BE-NEXT: add r4, r4, r5
; P9BE-NEXT: mulli r4, r4, 95 ; P9BE-NEXT: mulli r4, r4, 95
; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: sub r3, r3, r4
; P9BE-NEXT: lis r4, -16728 ; P9BE-NEXT: lis r4, -16728
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: ori r4, r4, 63249
; P9BE-NEXT: mtvsrd v4, r3 ; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 6 ; P9BE-NEXT: li r3, 6
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: vmrghh v3, v4, v3
; P9BE-NEXT: extsh r3, r3 ; P9BE-NEXT: extsh r3, r3
; P9BE-NEXT: ori r4, r4, 63249
; P9BE-NEXT: mulhw r4, r3, r4 ; P9BE-NEXT: mulhw r4, r3, r4
; P9BE-NEXT: srwi r5, r4, 31 ; P9BE-NEXT: srwi r5, r4, 31
; P9BE-NEXT: srawi r4, r4, 8 ; P9BE-NEXT: srawi r4, r4, 8
; P9BE-NEXT: add r4, r4, r5 ; P9BE-NEXT: add r4, r4, r5
; P9BE-NEXT: mulli r4, r4, -1003 ; P9BE-NEXT: mulli r4, r4, -1003
; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: sub r3, r3, r4
; P9BE-NEXT: lis r4, 21399 ; P9BE-NEXT: lis r4, 21399
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: vmrghh v3, v4, v3 ; P9BE-NEXT: ori r4, r4, 33437
; P9BE-NEXT: mtvsrd v4, r3 ; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 4 ; P9BE-NEXT: li r3, 4
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: extsh r3, r3 ; P9BE-NEXT: extsh r3, r3
; P9BE-NEXT: ori r4, r4, 33437
; P9BE-NEXT: mulhw r4, r3, r4 ; P9BE-NEXT: mulhw r4, r3, r4
; P9BE-NEXT: srwi r5, r4, 31 ; P9BE-NEXT: srwi r5, r4, 31
; P9BE-NEXT: srawi r4, r4, 5 ; P9BE-NEXT: srawi r4, r4, 5
; P9BE-NEXT: add r4, r4, r5 ; P9BE-NEXT: add r4, r4, r5
; P9BE-NEXT: mulli r4, r4, 98 ; P9BE-NEXT: mulli r4, r4, 98
; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: sub r3, r3, r4
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v2, r3 ; P9BE-NEXT: mtvsrd v2, r3
▲ Show 20 Lines • Show All 116 Lines • ▼ Show 20 Lines; P8BE-NEXT: blr
%1 = srem <4 x i16> %x, <i16 95, i16 -124, i16 98, i16 -1003> %1 = srem <4 x i16> %x, <i16 95, i16 -124, i16 98, i16 -1003>
ret <4 x i16> %1 ret <4 x i16> %1
} }
define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) { define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) {
; P9LE-LABEL: fold_srem_vec_2: ; P9LE-LABEL: fold_srem_vec_2:
; P9LE: # %bb.0: ; P9LE: # %bb.0:
; P9LE-NEXT: li r3, 0 ; P9LE-NEXT: li r3, 0
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: lis r4, -21386 ; P9LE-NEXT: lis r4, -21386
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: ori r4, r4, 37253 ; P9LE-NEXT: ori r4, r4, 37253
; P9LE-NEXT: extsh r3, r3 ; P9LE-NEXT: extsh r3, r3
; P9LE-NEXT: mulhw r5, r3, r4 ; P9LE-NEXT: mulhw r5, r3, r4
; P9LE-NEXT: add r5, r5, r3 ; P9LE-NEXT: add r5, r5, r3
; P9LE-NEXT: srwi r6, r5, 31 ; P9LE-NEXT: srwi r6, r5, 31
; P9LE-NEXT: srawi r5, r5, 6 ; P9LE-NEXT: srawi r5, r5, 6
; P9LE-NEXT: add r5, r5, r6 ; P9LE-NEXT: add r5, r5, r6
; P9LE-NEXT: mulli r5, r5, 95 ; P9LE-NEXT: mulli r5, r5, 95
; P9LE-NEXT: sub r3, r3, r5 ; P9LE-NEXT: sub r3, r3, r5
; P9LE-NEXT: mtvsrd v3, r3 ; P9LE-NEXT: mtvsrd v3, r3
; P9LE-NEXT: li r3, 2 ; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r3, r3 ; P9LE-NEXT: extsh r3, r3
; P9LE-NEXT: mulhw r5, r3, r4 ; P9LE-NEXT: mulhw r5, r3, r4
; P9LE-NEXT: add r5, r5, r3 ; P9LE-NEXT: add r5, r5, r3
; P9LE-NEXT: srwi r6, r5, 31 ; P9LE-NEXT: srwi r6, r5, 31
; P9LE-NEXT: srawi r5, r5, 6 ; P9LE-NEXT: srawi r5, r5, 6
; P9LE-NEXT: add r5, r5, r6 ; P9LE-NEXT: add r5, r5, r6
; P9LE-NEXT: mulli r5, r5, 95 ; P9LE-NEXT: mulli r5, r5, 95
; P9LE-NEXT: sub r3, r3, r5 ; P9LE-NEXT: sub r3, r3, r5
; P9LE-NEXT: mtvsrd v4, r3 ; P9LE-NEXT: mtvsrd v4, r3
; P9LE-NEXT: li r3, 4 ; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: vmrghh v3, v4, v3
; P9LE-NEXT: extsh r3, r3 ; P9LE-NEXT: extsh r3, r3
; P9LE-NEXT: mulhw r5, r3, r4 ; P9LE-NEXT: mulhw r5, r3, r4
; P9LE-NEXT: add r5, r5, r3 ; P9LE-NEXT: add r5, r5, r3
; P9LE-NEXT: srwi r6, r5, 31 ; P9LE-NEXT: srwi r6, r5, 31
; P9LE-NEXT: srawi r5, r5, 6 ; P9LE-NEXT: srawi r5, r5, 6
; P9LE-NEXT: add r5, r5, r6 ; P9LE-NEXT: add r5, r5, r6
; P9LE-NEXT: mulli r5, r5, 95 ; P9LE-NEXT: mulli r5, r5, 95
; P9LE-NEXT: sub r3, r3, r5 ; P9LE-NEXT: sub r3, r3, r5
; P9LE-NEXT: vmrghh v3, v4, v3
; P9LE-NEXT: mtvsrd v4, r3 ; P9LE-NEXT: mtvsrd v4, r3
; P9LE-NEXT: li r3, 6 ; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r3, r3 ; P9LE-NEXT: extsh r3, r3
; P9LE-NEXT: mulhw r4, r3, r4 ; P9LE-NEXT: mulhw r4, r3, r4
; P9LE-NEXT: add r4, r4, r3 ; P9LE-NEXT: add r4, r4, r3
; P9LE-NEXT: srwi r5, r4, 31 ; P9LE-NEXT: srwi r5, r4, 31
; P9LE-NEXT: srawi r4, r4, 6 ; P9LE-NEXT: srawi r4, r4, 6
; P9LE-NEXT: add r4, r4, r5 ; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: mulli r4, r4, 95 ; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: sub r3, r3, r4 ; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: mtvsrd v2, r3 ; P9LE-NEXT: mtvsrd v2, r3
; P9LE-NEXT: vmrghh v2, v2, v4 ; P9LE-NEXT: vmrghh v2, v2, v4
; P9LE-NEXT: vmrglw v2, v2, v3 ; P9LE-NEXT: vmrglw v2, v2, v3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P9BE-LABEL: fold_srem_vec_2: ; P9BE-LABEL: fold_srem_vec_2:
; P9BE: # %bb.0: ; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 6 ; P9BE-NEXT: li r3, 6
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: lis r4, -21386 ; P9BE-NEXT: lis r4, -21386
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: ori r4, r4, 37253 ; P9BE-NEXT: ori r4, r4, 37253
; P9BE-NEXT: extsh r3, r3 ; P9BE-NEXT: extsh r3, r3
; P9BE-NEXT: mulhw r5, r3, r4 ; P9BE-NEXT: mulhw r5, r3, r4
; P9BE-NEXT: add r5, r5, r3 ; P9BE-NEXT: add r5, r5, r3
; P9BE-NEXT: srwi r6, r5, 31 ; P9BE-NEXT: srwi r6, r5, 31
; P9BE-NEXT: srawi r5, r5, 6 ; P9BE-NEXT: srawi r5, r5, 6
; P9BE-NEXT: add r5, r5, r6 ; P9BE-NEXT: add r5, r5, r6
; P9BE-NEXT: mulli r5, r5, 95 ; P9BE-NEXT: mulli r5, r5, 95
Show All 9 Lines
; P9BE-NEXT: srawi r5, r5, 6 ; P9BE-NEXT: srawi r5, r5, 6
; P9BE-NEXT: add r5, r5, r6 ; P9BE-NEXT: add r5, r5, r6
; P9BE-NEXT: mulli r5, r5, 95 ; P9BE-NEXT: mulli r5, r5, 95
; P9BE-NEXT: sub r3, r3, r5 ; P9BE-NEXT: sub r3, r3, r5
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v4, r3 ; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 2 ; P9BE-NEXT: li r3, 2
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: vmrghh v3, v4, v3
; P9BE-NEXT: extsh r3, r3 ; P9BE-NEXT: extsh r3, r3
; P9BE-NEXT: mulhw r5, r3, r4 ; P9BE-NEXT: mulhw r5, r3, r4
; P9BE-NEXT: add r5, r5, r3 ; P9BE-NEXT: add r5, r5, r3
; P9BE-NEXT: srwi r6, r5, 31 ; P9BE-NEXT: srwi r6, r5, 31
; P9BE-NEXT: srawi r5, r5, 6 ; P9BE-NEXT: srawi r5, r5, 6
; P9BE-NEXT: add r5, r5, r6 ; P9BE-NEXT: add r5, r5, r6
; P9BE-NEXT: mulli r5, r5, 95 ; P9BE-NEXT: mulli r5, r5, 95
; P9BE-NEXT: sub r3, r3, r5 ; P9BE-NEXT: sub r3, r3, r5
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: vmrghh v3, v4, v3
; P9BE-NEXT: mtvsrd v4, r3 ; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: li r3, 0
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: extsh r3, r3 ; P9BE-NEXT: extsh r3, r3
; P9BE-NEXT: mulhw r4, r3, r4 ; P9BE-NEXT: mulhw r4, r3, r4
; P9BE-NEXT: add r4, r4, r3 ; P9BE-NEXT: add r4, r4, r3
; P9BE-NEXT: srwi r5, r4, 31 ; P9BE-NEXT: srwi r5, r4, 31
; P9BE-NEXT: srawi r4, r4, 6 ; P9BE-NEXT: srawi r4, r4, 6
▲ Show 20 Lines • Show All 115 Lines • ▼ Show 20 Lines
} }
; Don't fold if we can combine srem with sdiv. ; Don't fold if we can combine srem with sdiv.
define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) { define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) {
; P9LE-LABEL: combine_srem_sdiv: ; P9LE-LABEL: combine_srem_sdiv:
; P9LE: # %bb.0: ; P9LE: # %bb.0:
; P9LE-NEXT: li r3, 0 ; P9LE-NEXT: li r3, 0
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: lis r4, -21386 ; P9LE-NEXT: lis r4, -21386
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: ori r4, r4, 37253 ; P9LE-NEXT: ori r4, r4, 37253
; P9LE-NEXT: extsh r3, r3 ; P9LE-NEXT: extsh r3, r3
; P9LE-NEXT: mulhw r5, r3, r4 ; P9LE-NEXT: mulhw r5, r3, r4
; P9LE-NEXT: add r5, r5, r3 ; P9LE-NEXT: add r5, r5, r3
; P9LE-NEXT: srwi r6, r5, 31 ; P9LE-NEXT: srwi r6, r5, 31
; P9LE-NEXT: srawi r5, r5, 6 ; P9LE-NEXT: srawi r5, r5, 6
; P9LE-NEXT: add r5, r5, r6 ; P9LE-NEXT: add r5, r5, r6
; P9LE-NEXT: mulli r6, r5, 95 ; P9LE-NEXT: mulli r6, r5, 95
; P9LE-NEXT: sub r3, r3, r6 ; P9LE-NEXT: sub r3, r3, r6
; P9LE-NEXT: mtvsrd v3, r3 ; P9LE-NEXT: mtvsrd v3, r3
; P9LE-NEXT: li r3, 2 ; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r6, r3 ; P9LE-NEXT: extsh r6, r3
; P9LE-NEXT: mulhw r7, r6, r4 ; P9LE-NEXT: mulhw r7, r6, r4
; P9LE-NEXT: add r6, r7, r6 ; P9LE-NEXT: add r6, r7, r6
; P9LE-NEXT: srwi r7, r6, 31 ; P9LE-NEXT: srwi r7, r6, 31
; P9LE-NEXT: srawi r6, r6, 6 ; P9LE-NEXT: srawi r6, r6, 6
; P9LE-NEXT: add r6, r6, r7 ; P9LE-NEXT: add r6, r6, r7
; P9LE-NEXT: mulli r7, r6, 95 ; P9LE-NEXT: mulli r7, r6, 95
; P9LE-NEXT: sub r3, r3, r7 ; P9LE-NEXT: sub r3, r3, r7
; P9LE-NEXT: mtvsrd v4, r3 ; P9LE-NEXT: mtvsrd v4, r3
; P9LE-NEXT: li r3, 4 ; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: vmrghh v3, v4, v3
; P9LE-NEXT: extsh r7, r3 ; P9LE-NEXT: extsh r7, r3
; P9LE-NEXT: mulhw r8, r7, r4 ; P9LE-NEXT: mulhw r8, r7, r4
; P9LE-NEXT: add r7, r8, r7 ; P9LE-NEXT: add r7, r8, r7
; P9LE-NEXT: srwi r8, r7, 31 ; P9LE-NEXT: srwi r8, r7, 31
; P9LE-NEXT: srawi r7, r7, 6 ; P9LE-NEXT: srawi r7, r7, 6
; P9LE-NEXT: add r7, r7, r8 ; P9LE-NEXT: add r7, r7, r8
; P9LE-NEXT: mulli r8, r7, 95 ; P9LE-NEXT: mulli r8, r7, 95
; P9LE-NEXT: sub r3, r3, r8 ; P9LE-NEXT: sub r3, r3, r8
; P9LE-NEXT: vmrghh v3, v4, v3
; P9LE-NEXT: mtvsrd v4, r3 ; P9LE-NEXT: mtvsrd v4, r3
; P9LE-NEXT: li r3, 6 ; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r8, r3 ; P9LE-NEXT: extsh r8, r3
; P9LE-NEXT: mulhw r4, r8, r4 ; P9LE-NEXT: mulhw r4, r8, r4
; P9LE-NEXT: add r4, r4, r8 ; P9LE-NEXT: add r4, r4, r8
; P9LE-NEXT: srwi r8, r4, 31 ; P9LE-NEXT: srwi r8, r4, 31
; P9LE-NEXT: srawi r4, r4, 6 ; P9LE-NEXT: srawi r4, r4, 6
; P9LE-NEXT: add r4, r4, r8 ; P9LE-NEXT: add r4, r4, r8
; P9LE-NEXT: mulli r8, r4, 95 ; P9LE-NEXT: mulli r8, r4, 95
; P9LE-NEXT: mtvsrd v5, r4
; P9LE-NEXT: sub r3, r3, r8 ; P9LE-NEXT: sub r3, r3, r8
; P9LE-NEXT: mtvsrd v2, r3 ; P9LE-NEXT: mtvsrd v2, r3
; P9LE-NEXT: vmrghh v2, v2, v4 ; P9LE-NEXT: vmrghh v2, v2, v4
; P9LE-NEXT: mtvsrd v4, r6 ; P9LE-NEXT: mtvsrd v4, r6
; P9LE-NEXT: vmrglw v2, v2, v3 ; P9LE-NEXT: vmrglw v2, v2, v3
; P9LE-NEXT: mtvsrd v3, r5 ; P9LE-NEXT: mtvsrd v3, r5
; P9LE-NEXT: vmrghh v3, v4, v3 ; P9LE-NEXT: vmrghh v3, v4, v3
; P9LE-NEXT: mtvsrd v4, r7 ; P9LE-NEXT: mtvsrd v4, r7
; P9LE-NEXT: mtvsrd v5, r4
; P9LE-NEXT: vmrghh v4, v5, v4 ; P9LE-NEXT: vmrghh v4, v5, v4
; P9LE-NEXT: vmrglw v3, v4, v3 ; P9LE-NEXT: vmrglw v3, v4, v3
; P9LE-NEXT: vadduhm v2, v2, v3 ; P9LE-NEXT: vadduhm v2, v2, v3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P9BE-LABEL: combine_srem_sdiv: ; P9BE-LABEL: combine_srem_sdiv:
; P9BE: # %bb.0: ; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 6 ; P9BE-NEXT: li r3, 6
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: lis r5, -21386 ; P9BE-NEXT: lis r5, -21386
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: ori r5, r5, 37253 ; P9BE-NEXT: ori r5, r5, 37253
; P9BE-NEXT: extsh r4, r3 ; P9BE-NEXT: extsh r4, r3
; P9BE-NEXT: mulhw r6, r4, r5 ; P9BE-NEXT: mulhw r6, r4, r5
; P9BE-NEXT: add r4, r6, r4 ; P9BE-NEXT: add r4, r6, r4
; P9BE-NEXT: srwi r6, r4, 31 ; P9BE-NEXT: srwi r6, r4, 31
; P9BE-NEXT: srawi r4, r4, 6 ; P9BE-NEXT: srawi r4, r4, 6
; P9BE-NEXT: add r4, r4, r6 ; P9BE-NEXT: add r4, r4, r6
; P9BE-NEXT: mulli r6, r4, 95 ; P9BE-NEXT: mulli r6, r4, 95
Show All 9 Lines
; P9BE-NEXT: srawi r6, r6, 6 ; P9BE-NEXT: srawi r6, r6, 6
; P9BE-NEXT: add r6, r6, r7 ; P9BE-NEXT: add r6, r6, r7
; P9BE-NEXT: mulli r7, r6, 95 ; P9BE-NEXT: mulli r7, r6, 95
; P9BE-NEXT: sub r3, r3, r7 ; P9BE-NEXT: sub r3, r3, r7
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v4, r3 ; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 2 ; P9BE-NEXT: li r3, 2
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: vmrghh v3, v4, v3
; P9BE-NEXT: extsh r7, r3 ; P9BE-NEXT: extsh r7, r3
; P9BE-NEXT: mulhw r8, r7, r5 ; P9BE-NEXT: mulhw r8, r7, r5
; P9BE-NEXT: add r7, r8, r7 ; P9BE-NEXT: add r7, r8, r7
; P9BE-NEXT: srwi r8, r7, 31 ; P9BE-NEXT: srwi r8, r7, 31
; P9BE-NEXT: srawi r7, r7, 6 ; P9BE-NEXT: srawi r7, r7, 6
; P9BE-NEXT: add r7, r7, r8 ; P9BE-NEXT: add r7, r7, r8
; P9BE-NEXT: mulli r8, r7, 95 ; P9BE-NEXT: mulli r8, r7, 95
; P9BE-NEXT: sub r3, r3, r8 ; P9BE-NEXT: sub r3, r3, r8
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: vmrghh v3, v4, v3
; P9BE-NEXT: mtvsrd v4, r3 ; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: li r3, 0
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: extsh r3, r3 ; P9BE-NEXT: extsh r3, r3
; P9BE-NEXT: mulhw r5, r3, r5 ; P9BE-NEXT: mulhw r5, r3, r5
; P9BE-NEXT: add r5, r5, r3 ; P9BE-NEXT: add r5, r5, r3
; P9BE-NEXT: srwi r8, r5, 31 ; P9BE-NEXT: srwi r8, r5, 31
; P9BE-NEXT: srawi r5, r5, 6 ; P9BE-NEXT: srawi r5, r5, 6
▲ Show 20 Lines • Show All 165 Lines • ▼ Show 20 Lines
; P9LE-NEXT: extsh r3, r3 ; P9LE-NEXT: extsh r3, r3
; P9LE-NEXT: srawi r4, r3, 5 ; P9LE-NEXT: srawi r4, r3, 5
; P9LE-NEXT: addze r4, r4 ; P9LE-NEXT: addze r4, r4
; P9LE-NEXT: slwi r4, r4, 5 ; P9LE-NEXT: slwi r4, r4, 5
; P9LE-NEXT: sub r3, r3, r4 ; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: lis r4, -21386 ; P9LE-NEXT: lis r4, -21386
; P9LE-NEXT: mtvsrd v4, r3 ; P9LE-NEXT: mtvsrd v4, r3
; P9LE-NEXT: li r3, 6 ; P9LE-NEXT: li r3, 6
; P9LE-NEXT: ori r4, r4, 37253
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: vmrghh v3, v4, v3
; P9LE-NEXT: extsh r3, r3 ; P9LE-NEXT: extsh r3, r3
; P9LE-NEXT: ori r4, r4, 37253
; P9LE-NEXT: mulhw r4, r3, r4 ; P9LE-NEXT: mulhw r4, r3, r4
; P9LE-NEXT: add r4, r4, r3 ; P9LE-NEXT: add r4, r4, r3
; P9LE-NEXT: srwi r5, r4, 31 ; P9LE-NEXT: srwi r5, r4, 31
; P9LE-NEXT: srawi r4, r4, 6 ; P9LE-NEXT: srawi r4, r4, 6
; P9LE-NEXT: add r4, r4, r5 ; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: mulli r4, r4, 95 ; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: sub r3, r3, r4 ; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: vmrghh v3, v4, v3
; P9LE-NEXT: mtvsrd v4, r3 ; P9LE-NEXT: mtvsrd v4, r3
; P9LE-NEXT: li r3, 4 ; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r3, r3 ; P9LE-NEXT: extsh r3, r3
; P9LE-NEXT: srawi r4, r3, 3 ; P9LE-NEXT: srawi r4, r3, 3
; P9LE-NEXT: addze r4, r4 ; P9LE-NEXT: addze r4, r4
; P9LE-NEXT: slwi r4, r4, 3 ; P9LE-NEXT: slwi r4, r4, 3
; P9LE-NEXT: sub r3, r3, r4 ; P9LE-NEXT: sub r3, r3, r4
Show All 17 Lines
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: extsh r3, r3 ; P9BE-NEXT: extsh r3, r3
; P9BE-NEXT: srawi r4, r3, 6 ; P9BE-NEXT: srawi r4, r3, 6
; P9BE-NEXT: addze r4, r4 ; P9BE-NEXT: addze r4, r4
; P9BE-NEXT: slwi r4, r4, 6 ; P9BE-NEXT: slwi r4, r4, 6
; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: sub r3, r3, r4
; P9BE-NEXT: lis r4, -21386 ; P9BE-NEXT: lis r4, -21386
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: ori r4, r4, 37253
; P9BE-NEXT: mtvsrd v4, r3 ; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 6 ; P9BE-NEXT: li r3, 6
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: vmrghh v3, v4, v3
; P9BE-NEXT: extsh r3, r3 ; P9BE-NEXT: extsh r3, r3
; P9BE-NEXT: ori r4, r4, 37253
; P9BE-NEXT: mulhw r4, r3, r4 ; P9BE-NEXT: mulhw r4, r3, r4
; P9BE-NEXT: add r4, r4, r3 ; P9BE-NEXT: add r4, r4, r3
; P9BE-NEXT: srwi r5, r4, 31 ; P9BE-NEXT: srwi r5, r4, 31
; P9BE-NEXT: srawi r4, r4, 6 ; P9BE-NEXT: srawi r4, r4, 6
; P9BE-NEXT: add r4, r4, r5 ; P9BE-NEXT: add r4, r4, r5
; P9BE-NEXT: mulli r4, r4, 95 ; P9BE-NEXT: mulli r4, r4, 95
; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: sub r3, r3, r4
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: vmrghh v3, v4, v3
; P9BE-NEXT: mtvsrd v4, r3 ; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 4 ; P9BE-NEXT: li r3, 4
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: extsh r3, r3 ; P9BE-NEXT: extsh r3, r3
; P9BE-NEXT: srawi r4, r3, 3 ; P9BE-NEXT: srawi r4, r3, 3
; P9BE-NEXT: addze r4, r4 ; P9BE-NEXT: addze r4, r4
; P9BE-NEXT: slwi r4, r4, 3 ; P9BE-NEXT: slwi r4, r4, 3
; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: sub r3, r3, r4
▲ Show 20 Lines • Show All 93 Lines • ▼ Show 20 Lines; P8BE-NEXT: blr
ret <4 x i16> %1 ret <4 x i16> %1
} }
; Don't fold if the divisor is one. ; Don't fold if the divisor is one.
define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) { define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {
; P9LE-LABEL: dont_fold_srem_one: ; P9LE-LABEL: dont_fold_srem_one:
; P9LE: # %bb.0: ; P9LE: # %bb.0:
; P9LE-NEXT: li r3, 2 ; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: lis r4, -14230 ; P9LE-NEXT: lis r4, -14230
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: ori r4, r4, 30865 ; P9LE-NEXT: ori r4, r4, 30865
; P9LE-NEXT: extsh r3, r3 ; P9LE-NEXT: extsh r3, r3
; P9LE-NEXT: mulhw r4, r3, r4 ; P9LE-NEXT: mulhw r4, r3, r4
; P9LE-NEXT: add r4, r4, r3 ; P9LE-NEXT: add r4, r4, r3
; P9LE-NEXT: srwi r5, r4, 31 ; P9LE-NEXT: srwi r5, r4, 31
; P9LE-NEXT: srawi r4, r4, 9 ; P9LE-NEXT: srawi r4, r4, 9
; P9LE-NEXT: add r4, r4, r5 ; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: mulli r4, r4, 654 ; P9LE-NEXT: mulli r4, r4, 654
; P9LE-NEXT: sub r3, r3, r4 ; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: lis r4, -19946 ; P9LE-NEXT: lis r4, -19946
; P9LE-NEXT: mtvsrd v3, r3 ; P9LE-NEXT: mtvsrd v3, r3
; P9LE-NEXT: li r3, 0 ; P9LE-NEXT: li r3, 0
; P9LE-NEXT: ori r4, r4, 17097
; P9LE-NEXT: mtvsrd v4, r3 ; P9LE-NEXT: mtvsrd v4, r3
; P9LE-NEXT: li r3, 4 ; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: vmrghh v3, v3, v4
; P9LE-NEXT: extsh r3, r3 ; P9LE-NEXT: extsh r3, r3
; P9LE-NEXT: ori r4, r4, 17097
; P9LE-NEXT: mulhw r4, r3, r4 ; P9LE-NEXT: mulhw r4, r3, r4
; P9LE-NEXT: add r4, r4, r3 ; P9LE-NEXT: add r4, r4, r3
; P9LE-NEXT: srwi r5, r4, 31 ; P9LE-NEXT: srwi r5, r4, 31
; P9LE-NEXT: srawi r4, r4, 4 ; P9LE-NEXT: srawi r4, r4, 4
; P9LE-NEXT: add r4, r4, r5 ; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: mulli r4, r4, 23 ; P9LE-NEXT: mulli r4, r4, 23
; P9LE-NEXT: sub r3, r3, r4 ; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: vmrghh v3, v3, v4 ; P9LE-NEXT: lis r4, 24749
; P9LE-NEXT: mtvsrd v4, r3 ; P9LE-NEXT: mtvsrd v4, r3
; P9LE-NEXT: li r3, 6 ; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: lis r4, 24749
; P9LE-NEXT: ori r4, r4, 47143 ; P9LE-NEXT: ori r4, r4, 47143
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r3, r3 ; P9LE-NEXT: extsh r3, r3
; P9LE-NEXT: mulhw r4, r3, r4 ; P9LE-NEXT: mulhw r4, r3, r4
; P9LE-NEXT: srwi r5, r4, 31 ; P9LE-NEXT: srwi r5, r4, 31
; P9LE-NEXT: srawi r4, r4, 11 ; P9LE-NEXT: srawi r4, r4, 11
; P9LE-NEXT: add r4, r4, r5 ; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: mulli r4, r4, 5423 ; P9LE-NEXT: mulli r4, r4, 5423
; P9LE-NEXT: sub r3, r3, r4 ; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: mtvsrd v2, r3 ; P9LE-NEXT: mtvsrd v2, r3
; P9LE-NEXT: vmrghh v2, v2, v4 ; P9LE-NEXT: vmrghh v2, v2, v4
; P9LE-NEXT: vmrglw v2, v2, v3 ; P9LE-NEXT: vmrglw v2, v2, v3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P9BE-LABEL: dont_fold_srem_one: ; P9BE-LABEL: dont_fold_srem_one:
; P9BE: # %bb.0: ; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 4 ; P9BE-NEXT: li r3, 4
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: lis r4, -19946 ; P9BE-NEXT: lis r4, -19946
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: ori r4, r4, 17097 ; P9BE-NEXT: ori r4, r4, 17097
; P9BE-NEXT: extsh r3, r3 ; P9BE-NEXT: extsh r3, r3
; P9BE-NEXT: mulhw r4, r3, r4 ; P9BE-NEXT: mulhw r4, r3, r4
; P9BE-NEXT: add r4, r4, r3 ; P9BE-NEXT: add r4, r4, r3
; P9BE-NEXT: srwi r5, r4, 31 ; P9BE-NEXT: srwi r5, r4, 31
; P9BE-NEXT: srawi r4, r4, 4 ; P9BE-NEXT: srawi r4, r4, 4
; P9BE-NEXT: add r4, r4, r5 ; P9BE-NEXT: add r4, r4, r5
; P9BE-NEXT: mulli r4, r4, 23 ; P9BE-NEXT: mulli r4, r4, 23
; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: sub r3, r3, r4
; P9BE-NEXT: lis r4, 24749 ; P9BE-NEXT: lis r4, 24749
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: ori r4, r4, 47143
; P9BE-NEXT: mtvsrd v3, r3 ; P9BE-NEXT: mtvsrd v3, r3
; P9BE-NEXT: li r3, 6 ; P9BE-NEXT: li r3, 6
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: extsh r3, r3 ; P9BE-NEXT: extsh r3, r3
; P9BE-NEXT: ori r4, r4, 47143
; P9BE-NEXT: mulhw r4, r3, r4 ; P9BE-NEXT: mulhw r4, r3, r4
; P9BE-NEXT: srwi r5, r4, 31 ; P9BE-NEXT: srwi r5, r4, 31
; P9BE-NEXT: srawi r4, r4, 11 ; P9BE-NEXT: srawi r4, r4, 11
; P9BE-NEXT: add r4, r4, r5 ; P9BE-NEXT: add r4, r4, r5
; P9BE-NEXT: mulli r4, r4, 5423 ; P9BE-NEXT: mulli r4, r4, 5423
; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: sub r3, r3, r4
; P9BE-NEXT: lis r4, -14230 ; P9BE-NEXT: lis r4, -14230
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: ori r4, r4, 30865
; P9BE-NEXT: mtvsrd v4, r3 ; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 2 ; P9BE-NEXT: li r3, 2
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: vmrghh v3, v3, v4
; P9BE-NEXT: extsh r3, r3 ; P9BE-NEXT: extsh r3, r3
; P9BE-NEXT: ori r4, r4, 30865
; P9BE-NEXT: mulhw r4, r3, r4 ; P9BE-NEXT: mulhw r4, r3, r4
; P9BE-NEXT: add r4, r4, r3 ; P9BE-NEXT: add r4, r4, r3
; P9BE-NEXT: srwi r5, r4, 31 ; P9BE-NEXT: srwi r5, r4, 31
; P9BE-NEXT: srawi r4, r4, 9 ; P9BE-NEXT: srawi r4, r4, 9
; P9BE-NEXT: add r4, r4, r5 ; P9BE-NEXT: add r4, r4, r5
; P9BE-NEXT: mulli r4, r4, 654 ; P9BE-NEXT: mulli r4, r4, 654
; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: sub r3, r3, r4
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v2, r3 ; P9BE-NEXT: mtvsrd v2, r3
; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: li r3, 0
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: vmrghh v3, v3, v4
; P9BE-NEXT: mtvsrd v4, r3 ; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: vmrghh v2, v4, v2 ; P9BE-NEXT: vmrghh v2, v4, v2
; P9BE-NEXT: vmrghw v2, v2, v3 ; P9BE-NEXT: vmrghw v2, v2, v3
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P8LE-LABEL: dont_fold_srem_one: ; P8LE-LABEL: dont_fold_srem_one:
; P8LE: # %bb.0: ; P8LE: # %bb.0:
; P8LE-NEXT: xxswapd vs0, v2 ; P8LE-NEXT: xxswapd vs0, v2
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines; P8BE-NEXT: blr
ret <4 x i16> %1 ret <4 x i16> %1
} }
; Don't fold if the divisor is 2^15. ; Don't fold if the divisor is 2^15.
define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) { define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
; P9LE-LABEL: dont_fold_urem_i16_smax: ; P9LE-LABEL: dont_fold_urem_i16_smax:
; P9LE: # %bb.0: ; P9LE: # %bb.0:
; P9LE-NEXT: li r3, 4 ; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: lis r4, -19946 ; P9LE-NEXT: lis r4, -19946
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: ori r4, r4, 17097 ; P9LE-NEXT: ori r4, r4, 17097
; P9LE-NEXT: extsh r3, r3 ; P9LE-NEXT: extsh r3, r3
; P9LE-NEXT: mulhw r4, r3, r4 ; P9LE-NEXT: mulhw r4, r3, r4
; P9LE-NEXT: add r4, r4, r3 ; P9LE-NEXT: add r4, r4, r3
; P9LE-NEXT: srwi r5, r4, 31 ; P9LE-NEXT: srwi r5, r4, 31
; P9LE-NEXT: srawi r4, r4, 4 ; P9LE-NEXT: srawi r4, r4, 4
; P9LE-NEXT: add r4, r4, r5 ; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: mulli r4, r4, 23 ; P9LE-NEXT: mulli r4, r4, 23
; P9LE-NEXT: sub r3, r3, r4 ; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: lis r4, 24749 ; P9LE-NEXT: lis r4, 24749
; P9LE-NEXT: mtvsrd v3, r3 ; P9LE-NEXT: mtvsrd v3, r3
; P9LE-NEXT: li r3, 6 ; P9LE-NEXT: li r3, 6
; P9LE-NEXT: ori r4, r4, 47143
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r3, r3 ; P9LE-NEXT: extsh r3, r3
; P9LE-NEXT: ori r4, r4, 47143
; P9LE-NEXT: mulhw r4, r3, r4 ; P9LE-NEXT: mulhw r4, r3, r4
; P9LE-NEXT: srwi r5, r4, 31 ; P9LE-NEXT: srwi r5, r4, 31
; P9LE-NEXT: srawi r4, r4, 11 ; P9LE-NEXT: srawi r4, r4, 11
; P9LE-NEXT: add r4, r4, r5 ; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: mulli r4, r4, 5423 ; P9LE-NEXT: mulli r4, r4, 5423
; P9LE-NEXT: sub r3, r3, r4 ; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: mtvsrd v4, r3 ; P9LE-NEXT: mtvsrd v4, r3
; P9LE-NEXT: li r3, 2 ; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: vmrghh v3, v4, v3
; P9LE-NEXT: extsh r3, r3 ; P9LE-NEXT: extsh r3, r3
; P9LE-NEXT: srawi r4, r3, 15 ; P9LE-NEXT: srawi r4, r3, 15
; P9LE-NEXT: addze r4, r4 ; P9LE-NEXT: addze r4, r4
; P9LE-NEXT: slwi r4, r4, 15 ; P9LE-NEXT: slwi r4, r4, 15
; P9LE-NEXT: sub r3, r3, r4 ; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: mtvsrd v2, r3 ; P9LE-NEXT: mtvsrd v2, r3
; P9LE-NEXT: li r3, 0 ; P9LE-NEXT: li r3, 0
; P9LE-NEXT: vmrghh v3, v4, v3
; P9LE-NEXT: mtvsrd v4, r3 ; P9LE-NEXT: mtvsrd v4, r3
; P9LE-NEXT: vmrghh v2, v2, v4 ; P9LE-NEXT: vmrghh v2, v2, v4
; P9LE-NEXT: vmrglw v2, v3, v2 ; P9LE-NEXT: vmrglw v2, v3, v2
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P9BE-LABEL: dont_fold_urem_i16_smax: ; P9BE-LABEL: dont_fold_urem_i16_smax:
; P9BE: # %bb.0: ; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 4 ; P9BE-NEXT: li r3, 4
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: lis r4, -19946 ; P9BE-NEXT: lis r4, -19946
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: ori r4, r4, 17097 ; P9BE-NEXT: ori r4, r4, 17097
; P9BE-NEXT: extsh r3, r3 ; P9BE-NEXT: extsh r3, r3
; P9BE-NEXT: mulhw r4, r3, r4 ; P9BE-NEXT: mulhw r4, r3, r4
; P9BE-NEXT: add r4, r4, r3 ; P9BE-NEXT: add r4, r4, r3
; P9BE-NEXT: srwi r5, r4, 31 ; P9BE-NEXT: srwi r5, r4, 31
; P9BE-NEXT: srawi r4, r4, 4 ; P9BE-NEXT: srawi r4, r4, 4
; P9BE-NEXT: add r4, r4, r5 ; P9BE-NEXT: add r4, r4, r5
; P9BE-NEXT: mulli r4, r4, 23 ; P9BE-NEXT: mulli r4, r4, 23
; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: sub r3, r3, r4
; P9BE-NEXT: lis r4, 24749 ; P9BE-NEXT: lis r4, 24749
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: ori r4, r4, 47143
; P9BE-NEXT: mtvsrd v3, r3 ; P9BE-NEXT: mtvsrd v3, r3
; P9BE-NEXT: li r3, 6 ; P9BE-NEXT: li r3, 6
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: extsh r3, r3 ; P9BE-NEXT: extsh r3, r3
; P9BE-NEXT: ori r4, r4, 47143
; P9BE-NEXT: mulhw r4, r3, r4 ; P9BE-NEXT: mulhw r4, r3, r4
; P9BE-NEXT: srwi r5, r4, 31 ; P9BE-NEXT: srwi r5, r4, 31
; P9BE-NEXT: srawi r4, r4, 11 ; P9BE-NEXT: srawi r4, r4, 11
; P9BE-NEXT: add r4, r4, r5 ; P9BE-NEXT: add r4, r4, r5
; P9BE-NEXT: mulli r4, r4, 5423 ; P9BE-NEXT: mulli r4, r4, 5423
; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: sub r3, r3, r4
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v4, r3 ; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 2 ; P9BE-NEXT: li r3, 2
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: vmrghh v3, v3, v4
; P9BE-NEXT: extsh r3, r3 ; P9BE-NEXT: extsh r3, r3
; P9BE-NEXT: srawi r4, r3, 15 ; P9BE-NEXT: srawi r4, r3, 15
; P9BE-NEXT: addze r4, r4 ; P9BE-NEXT: addze r4, r4
; P9BE-NEXT: slwi r4, r4, 15 ; P9BE-NEXT: slwi r4, r4, 15
; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: sub r3, r3, r4
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v2, r3 ; P9BE-NEXT: mtvsrd v2, r3
; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: li r3, 0
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: vmrghh v3, v3, v4
; P9BE-NEXT: mtvsrd v4, r3 ; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: vmrghh v2, v4, v2 ; P9BE-NEXT: vmrghh v2, v4, v2
; P9BE-NEXT: vmrghw v2, v2, v3 ; P9BE-NEXT: vmrghw v2, v2, v3
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P8LE-LABEL: dont_fold_urem_i16_smax: ; P8LE-LABEL: dont_fold_urem_i16_smax:
; P8LE: # %bb.0: ; P8LE: # %bb.0:
; P8LE-NEXT: xxswapd vs0, v2 ; P8LE-NEXT: xxswapd vs0, v2
▲ Show 20 Lines • Show All 82 Lines • ▼ Show 20 Lines; P8BE-NEXT: blr
ret <4 x i16> %1 ret <4 x i16> %1
} }
; Don't fold i64 srem. ; Don't fold i64 srem.
define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) { define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
; P9LE-LABEL: dont_fold_srem_i64: ; P9LE-LABEL: dont_fold_srem_i64:
; P9LE: # %bb.0: ; P9LE: # %bb.0:
; P9LE-NEXT: lis r4, 24749 ; P9LE-NEXT: lis r4, 24749
; P9LE-NEXT: mfvsrd r3, v3
; P9LE-NEXT: ori r4, r4, 47142 ; P9LE-NEXT: ori r4, r4, 47142
; P9LE-NEXT: sldi r4, r4, 32 ; P9LE-NEXT: sldi r4, r4, 32
; P9LE-NEXT: oris r4, r4, 58853 ; P9LE-NEXT: oris r4, r4, 58853
; P9LE-NEXT: mfvsrd r3, v3
; P9LE-NEXT: ori r4, r4, 6055 ; P9LE-NEXT: ori r4, r4, 6055
; P9LE-NEXT: mulhd r4, r3, r4 ; P9LE-NEXT: mulhd r4, r3, r4
; P9LE-NEXT: rldicl r5, r4, 1, 63 ; P9LE-NEXT: rldicl r5, r4, 1, 63
; P9LE-NEXT: sradi r4, r4, 11 ; P9LE-NEXT: sradi r4, r4, 11
; P9LE-NEXT: add r4, r4, r5 ; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: lis r5, -19946 ; P9LE-NEXT: lis r5, -19946
; P9LE-NEXT: mulli r4, r4, 5423 ; P9LE-NEXT: mulli r4, r4, 5423
; P9LE-NEXT: ori r5, r5, 17096 ; P9LE-NEXT: ori r5, r5, 17096
; P9LE-NEXT: sldi r5, r5, 32 ; P9LE-NEXT: sldi r5, r5, 32
; P9LE-NEXT: oris r5, r5, 22795 ; P9LE-NEXT: oris r5, r5, 22795
; P9LE-NEXT: sub r3, r3, r4 ; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: mfvsrld r4, v3 ; P9LE-NEXT: mfvsrld r4, v3
; P9LE-NEXT: ori r5, r5, 8549 ; P9LE-NEXT: ori r5, r5, 8549
; P9LE-NEXT: mulhd r5, r4, r5 ; P9LE-NEXT: mulhd r5, r4, r5
; P9LE-NEXT: add r5, r5, r4 ; P9LE-NEXT: add r5, r5, r4
; P9LE-NEXT: rldicl r6, r5, 1, 63 ; P9LE-NEXT: rldicl r6, r5, 1, 63
; P9LE-NEXT: sradi r5, r5, 4 ; P9LE-NEXT: sradi r5, r5, 4
; P9LE-NEXT: add r5, r5, r6 ; P9LE-NEXT: add r5, r5, r6
; P9LE-NEXT: mulli r5, r5, 23 ; P9LE-NEXT: mulli r5, r5, 23
; P9LE-NEXT: sub r4, r4, r5 ; P9LE-NEXT: sub r4, r4, r5
; P9LE-NEXT: mtvsrdd v3, r3, r4 ; P9LE-NEXT: mtvsrdd v3, r3, r4
; P9LE-NEXT: lis r4, 25653 ; P9LE-NEXT: lis r4, 25653
; P9LE-NEXT: mfvsrd r3, v2
; P9LE-NEXT: ori r4, r4, 15432 ; P9LE-NEXT: ori r4, r4, 15432
; P9LE-NEXT: sldi r4, r4, 32 ; P9LE-NEXT: sldi r4, r4, 32
; P9LE-NEXT: oris r4, r4, 1603 ; P9LE-NEXT: oris r4, r4, 1603
; P9LE-NEXT: mfvsrd r3, v2
; P9LE-NEXT: ori r4, r4, 21445 ; P9LE-NEXT: ori r4, r4, 21445
; P9LE-NEXT: mulhd r4, r3, r4 ; P9LE-NEXT: mulhd r4, r3, r4
; P9LE-NEXT: rldicl r5, r4, 1, 63 ; P9LE-NEXT: rldicl r5, r4, 1, 63
; P9LE-NEXT: sradi r4, r4, 8 ; P9LE-NEXT: sradi r4, r4, 8
; P9LE-NEXT: add r4, r4, r5 ; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: mulli r4, r4, 654 ; P9LE-NEXT: mulli r4, r4, 654
; P9LE-NEXT: sub r3, r3, r4 ; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: li r4, 0 ; P9LE-NEXT: li r4, 0
; P9LE-NEXT: mtvsrdd v2, r3, r4 ; P9LE-NEXT: mtvsrdd v2, r3, r4
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P9BE-LABEL: dont_fold_srem_i64: ; P9BE-LABEL: dont_fold_srem_i64:
; P9BE: # %bb.0: ; P9BE: # %bb.0:
; P9BE-NEXT: lis r4, 24749 ; P9BE-NEXT: lis r4, 24749
; P9BE-NEXT: mfvsrld r3, v3
; P9BE-NEXT: ori r4, r4, 47142 ; P9BE-NEXT: ori r4, r4, 47142
; P9BE-NEXT: sldi r4, r4, 32 ; P9BE-NEXT: sldi r4, r4, 32
; P9BE-NEXT: oris r4, r4, 58853 ; P9BE-NEXT: oris r4, r4, 58853
; P9BE-NEXT: mfvsrld r3, v3
; P9BE-NEXT: ori r4, r4, 6055 ; P9BE-NEXT: ori r4, r4, 6055
; P9BE-NEXT: mulhd r4, r3, r4 ; P9BE-NEXT: mulhd r4, r3, r4
; P9BE-NEXT: rldicl r5, r4, 1, 63 ; P9BE-NEXT: rldicl r5, r4, 1, 63
; P9BE-NEXT: sradi r4, r4, 11 ; P9BE-NEXT: sradi r4, r4, 11
; P9BE-NEXT: add r4, r4, r5 ; P9BE-NEXT: add r4, r4, r5
; P9BE-NEXT: lis r5, -19946 ; P9BE-NEXT: lis r5, -19946
; P9BE-NEXT: ori r5, r5, 17096 ; P9BE-NEXT: ori r5, r5, 17096
; P9BE-NEXT: mulli r4, r4, 5423 ; P9BE-NEXT: mulli r4, r4, 5423
; P9BE-NEXT: sldi r5, r5, 32 ; P9BE-NEXT: sldi r5, r5, 32
; P9BE-NEXT: oris r5, r5, 22795 ; P9BE-NEXT: oris r5, r5, 22795
; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: sub r3, r3, r4
; P9BE-NEXT: mfvsrd r4, v3 ; P9BE-NEXT: mfvsrd r4, v3
; P9BE-NEXT: ori r5, r5, 8549 ; P9BE-NEXT: ori r5, r5, 8549
; P9BE-NEXT: mulhd r5, r4, r5 ; P9BE-NEXT: mulhd r5, r4, r5
; P9BE-NEXT: add r5, r5, r4 ; P9BE-NEXT: add r5, r5, r4
; P9BE-NEXT: rldicl r6, r5, 1, 63 ; P9BE-NEXT: rldicl r6, r5, 1, 63
; P9BE-NEXT: sradi r5, r5, 4 ; P9BE-NEXT: sradi r5, r5, 4
; P9BE-NEXT: add r5, r5, r6 ; P9BE-NEXT: add r5, r5, r6
; P9BE-NEXT: mulli r5, r5, 23 ; P9BE-NEXT: mulli r5, r5, 23
; P9BE-NEXT: sub r4, r4, r5 ; P9BE-NEXT: sub r4, r4, r5
; P9BE-NEXT: mtvsrdd v3, r4, r3 ; P9BE-NEXT: mtvsrdd v3, r4, r3
; P9BE-NEXT: lis r4, 25653 ; P9BE-NEXT: lis r4, 25653
; P9BE-NEXT: mfvsrld r3, v2
; P9BE-NEXT: ori r4, r4, 15432 ; P9BE-NEXT: ori r4, r4, 15432
; P9BE-NEXT: sldi r4, r4, 32 ; P9BE-NEXT: sldi r4, r4, 32
; P9BE-NEXT: oris r4, r4, 1603 ; P9BE-NEXT: oris r4, r4, 1603
; P9BE-NEXT: mfvsrld r3, v2
; P9BE-NEXT: ori r4, r4, 21445 ; P9BE-NEXT: ori r4, r4, 21445
; P9BE-NEXT: mulhd r4, r3, r4 ; P9BE-NEXT: mulhd r4, r3, r4
; P9BE-NEXT: rldicl r5, r4, 1, 63 ; P9BE-NEXT: rldicl r5, r4, 1, 63
; P9BE-NEXT: sradi r4, r4, 8 ; P9BE-NEXT: sradi r4, r4, 8
; P9BE-NEXT: add r4, r4, r5 ; P9BE-NEXT: add r4, r4, r5
; P9BE-NEXT: mulli r4, r4, 654 ; P9BE-NEXT: mulli r4, r4, 654
; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: sub r3, r3, r4
; P9BE-NEXT: mtvsrdd v2, 0, r3 ; P9BE-NEXT: mtvsrdd v2, 0, r3
▲ Show 20 Lines • Show All 103 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/stack-clash-dynamic-alloca.ll

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
; ;
; CHECK-P9-LE-LABEL: foo: ; CHECK-P9-LE-LABEL: foo:
; CHECK-P9-LE: # %bb.0: ; CHECK-P9-LE: # %bb.0:
; CHECK-P9-LE-NEXT: std r31, -8(r1) ; CHECK-P9-LE-NEXT: std r31, -8(r1)
; CHECK-P9-LE-NEXT: stdu r1, -48(r1) ; CHECK-P9-LE-NEXT: stdu r1, -48(r1)
; CHECK-P9-LE-NEXT: rldic r3, r3, 2, 30 ; CHECK-P9-LE-NEXT: rldic r3, r3, 2, 30
; CHECK-P9-LE-NEXT: addi r3, r3, 15 ; CHECK-P9-LE-NEXT: addi r3, r3, 15
; CHECK-P9-LE-NEXT: li r6, -32768
; CHECK-P9-LE-NEXT: mr r31, r1
; CHECK-P9-LE-NEXT: addi r4, r31, 48
; CHECK-P9-LE-NEXT: rldicl r3, r3, 60, 4 ; CHECK-P9-LE-NEXT: rldicl r3, r3, 60, 4
; CHECK-P9-LE-NEXT: rldicl r3, r3, 4, 29 ; CHECK-P9-LE-NEXT: rldicl r3, r3, 4, 29
; CHECK-P9-LE-NEXT: neg r5, r3 ; CHECK-P9-LE-NEXT: neg r5, r3
; CHECK-P9-LE-NEXT: li r6, -32768
; CHECK-P9-LE-NEXT: divd r7, r5, r6 ; CHECK-P9-LE-NEXT: divd r7, r5, r6
; CHECK-P9-LE-NEXT: mulld r6, r7, r6
; CHECK-P9-LE-NEXT: mr r31, r1
; CHECK-P9-LE-NEXT: addi r4, r31, 48
; CHECK-P9-LE-NEXT: add r3, r1, r5 ; CHECK-P9-LE-NEXT: add r3, r1, r5
; CHECK-P9-LE-NEXT: mulld r6, r7, r6
; CHECK-P9-LE-NEXT: sub r5, r5, r6 ; CHECK-P9-LE-NEXT: sub r5, r5, r6
; CHECK-P9-LE-NEXT: stdux r4, r1, r5 ; CHECK-P9-LE-NEXT: stdux r4, r1, r5
; CHECK-P9-LE-NEXT: cmpd r1, r3 ; CHECK-P9-LE-NEXT: cmpd r1, r3
; CHECK-P9-LE-NEXT: beq cr0, .LBB0_2 ; CHECK-P9-LE-NEXT: beq cr0, .LBB0_2
; CHECK-P9-LE-NEXT: .LBB0_1: ; CHECK-P9-LE-NEXT: .LBB0_1:
; CHECK-P9-LE-NEXT: stdu r4, -32768(r1) ; CHECK-P9-LE-NEXT: stdu r4, -32768(r1)
; CHECK-P9-LE-NEXT: cmpd r1, r3 ; CHECK-P9-LE-NEXT: cmpd r1, r3
; CHECK-P9-LE-NEXT: bne cr0, .LBB0_1 ; CHECK-P9-LE-NEXT: bne cr0, .LBB0_1
; CHECK-P9-LE-NEXT: .LBB0_2: ; CHECK-P9-LE-NEXT: .LBB0_2:
; CHECK-P9-LE-NEXT: addi r3, r1, 32
; CHECK-P9-LE-NEXT: li r4, 1 ; CHECK-P9-LE-NEXT: li r4, 1
; CHECK-P9-LE-NEXT: addi r3, r1, 32
; CHECK-P9-LE-NEXT: stw r4, 4792(r3) ; CHECK-P9-LE-NEXT: stw r4, 4792(r3)
; CHECK-P9-LE-NEXT: lwz r3, 0(r3) ; CHECK-P9-LE-NEXT: lwz r3, 0(r3)
; CHECK-P9-LE-NEXT: ld r1, 0(r1) ; CHECK-P9-LE-NEXT: ld r1, 0(r1)
; CHECK-P9-LE-NEXT: ld r31, -8(r1) ; CHECK-P9-LE-NEXT: ld r31, -8(r1)
; CHECK-P9-LE-NEXT: blr ; CHECK-P9-LE-NEXT: blr
; ;
; CHECK-BE-LABEL: foo: ; CHECK-BE-LABEL: foo:
; CHECK-BE: # %bb.0: ; CHECK-BE: # %bb.0:
▲ Show 20 Lines • Show All 103 Lines • ▼ Show 20 Lines
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
; ;
; CHECK-P9-LE-LABEL: bar: ; CHECK-P9-LE-LABEL: bar:
; CHECK-P9-LE: # %bb.0: ; CHECK-P9-LE: # %bb.0:
; CHECK-P9-LE-NEXT: std r31, -8(r1) ; CHECK-P9-LE-NEXT: std r31, -8(r1)
; CHECK-P9-LE-NEXT: stdu r1, -48(r1) ; CHECK-P9-LE-NEXT: stdu r1, -48(r1)
; CHECK-P9-LE-NEXT: rldic r4, r3, 2, 30 ; CHECK-P9-LE-NEXT: rldic r4, r3, 2, 30
; CHECK-P9-LE-NEXT: addi r4, r4, 15 ; CHECK-P9-LE-NEXT: addi r4, r4, 15
; CHECK-P9-LE-NEXT: li r7, -4096
; CHECK-P9-LE-NEXT: mr r31, r1
; CHECK-P9-LE-NEXT: addi r5, r31, 48
; CHECK-P9-LE-NEXT: rldicl r4, r4, 60, 4 ; CHECK-P9-LE-NEXT: rldicl r4, r4, 60, 4
; CHECK-P9-LE-NEXT: rldicl r4, r4, 4, 29 ; CHECK-P9-LE-NEXT: rldicl r4, r4, 4, 29
; CHECK-P9-LE-NEXT: neg r6, r4 ; CHECK-P9-LE-NEXT: neg r6, r4
; CHECK-P9-LE-NEXT: li r7, -4096
; CHECK-P9-LE-NEXT: divd r8, r6, r7 ; CHECK-P9-LE-NEXT: divd r8, r6, r7
; CHECK-P9-LE-NEXT: mulld r7, r8, r7
; CHECK-P9-LE-NEXT: mr r31, r1
; CHECK-P9-LE-NEXT: addi r5, r31, 48
; CHECK-P9-LE-NEXT: add r4, r1, r6 ; CHECK-P9-LE-NEXT: add r4, r1, r6
; CHECK-P9-LE-NEXT: mulld r7, r8, r7
; CHECK-P9-LE-NEXT: sub r6, r6, r7 ; CHECK-P9-LE-NEXT: sub r6, r6, r7
; CHECK-P9-LE-NEXT: stdux r5, r1, r6 ; CHECK-P9-LE-NEXT: stdux r5, r1, r6
; CHECK-P9-LE-NEXT: cmpd r1, r4 ; CHECK-P9-LE-NEXT: cmpd r1, r4
; CHECK-P9-LE-NEXT: beq cr0, .LBB1_2 ; CHECK-P9-LE-NEXT: beq cr0, .LBB1_2
; CHECK-P9-LE-NEXT: .LBB1_1: ; CHECK-P9-LE-NEXT: .LBB1_1:
; CHECK-P9-LE-NEXT: stdu r5, -4096(r1) ; CHECK-P9-LE-NEXT: stdu r5, -4096(r1)
; CHECK-P9-LE-NEXT: cmpd r1, r4 ; CHECK-P9-LE-NEXT: cmpd r1, r4
; CHECK-P9-LE-NEXT: bne cr0, .LBB1_1 ; CHECK-P9-LE-NEXT: bne cr0, .LBB1_1
; CHECK-P9-LE-NEXT: .LBB1_2: ; CHECK-P9-LE-NEXT: .LBB1_2:
; CHECK-P9-LE-NEXT: addi r4, r1, 32
; CHECK-P9-LE-NEXT: extswsli r3, r3, 2 ; CHECK-P9-LE-NEXT: extswsli r3, r3, 2
; CHECK-P9-LE-NEXT: add r3, r4, r3
; CHECK-P9-LE-NEXT: li r5, 1 ; CHECK-P9-LE-NEXT: li r5, 1
; CHECK-P9-LE-NEXT: addi r4, r1, 32
; CHECK-P9-LE-NEXT: add r3, r4, r3
; CHECK-P9-LE-NEXT: stw r5, 4096(r3) ; CHECK-P9-LE-NEXT: stw r5, 4096(r3)
; CHECK-P9-LE-NEXT: lwz r3, 0(r4) ; CHECK-P9-LE-NEXT: lwz r3, 0(r4)
; CHECK-P9-LE-NEXT: ld r1, 0(r1) ; CHECK-P9-LE-NEXT: ld r1, 0(r1)
; CHECK-P9-LE-NEXT: ld r31, -8(r1) ; CHECK-P9-LE-NEXT: ld r31, -8(r1)
; CHECK-P9-LE-NEXT: blr ; CHECK-P9-LE-NEXT: blr
; ;
; CHECK-BE-LABEL: bar: ; CHECK-BE-LABEL: bar:
; CHECK-BE: # %bb.0: ; CHECK-BE: # %bb.0:
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; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
; ;
; CHECK-P9-LE-LABEL: f: ; CHECK-P9-LE-LABEL: f:
; CHECK-P9-LE: # %bb.0: ; CHECK-P9-LE: # %bb.0:
; CHECK-P9-LE-NEXT: std r31, -8(r1) ; CHECK-P9-LE-NEXT: std r31, -8(r1)
; CHECK-P9-LE-NEXT: stdu r1, -48(r1) ; CHECK-P9-LE-NEXT: stdu r1, -48(r1)
; CHECK-P9-LE-NEXT: rldic r3, r3, 2, 30 ; CHECK-P9-LE-NEXT: rldic r3, r3, 2, 30
; CHECK-P9-LE-NEXT: addi r3, r3, 15 ; CHECK-P9-LE-NEXT: addi r3, r3, 15
; CHECK-P9-LE-NEXT: rldicl r3, r3, 60, 4
; CHECK-P9-LE-NEXT: rldicl r3, r3, 4, 29
; CHECK-P9-LE-NEXT: lis r5, -1 ; CHECK-P9-LE-NEXT: lis r5, -1
; CHECK-P9-LE-NEXT: ori r5, r5, 0 ; CHECK-P9-LE-NEXT: ori r5, r5, 0
; CHECK-P9-LE-NEXT: neg r6, r3
; CHECK-P9-LE-NEXT: divd r7, r6, r5
; CHECK-P9-LE-NEXT: mulld r7, r7, r5
; CHECK-P9-LE-NEXT: mr r31, r1 ; CHECK-P9-LE-NEXT: mr r31, r1
; CHECK-P9-LE-NEXT: addi r4, r31, 48 ; CHECK-P9-LE-NEXT: addi r4, r31, 48
; CHECK-P9-LE-NEXT: rldicl r3, r3, 60, 4
; CHECK-P9-LE-NEXT: rldicl r3, r3, 4, 29
; CHECK-P9-LE-NEXT: neg r6, r3
; CHECK-P9-LE-NEXT: divd r7, r6, r5
; CHECK-P9-LE-NEXT: add r3, r1, r6 ; CHECK-P9-LE-NEXT: add r3, r1, r6
; CHECK-P9-LE-NEXT: mulld r7, r7, r5
; CHECK-P9-LE-NEXT: sub r6, r6, r7 ; CHECK-P9-LE-NEXT: sub r6, r6, r7
; CHECK-P9-LE-NEXT: stdux r4, r1, r6 ; CHECK-P9-LE-NEXT: stdux r4, r1, r6
; CHECK-P9-LE-NEXT: cmpd r1, r3 ; CHECK-P9-LE-NEXT: cmpd r1, r3
; CHECK-P9-LE-NEXT: beq cr0, .LBB2_2 ; CHECK-P9-LE-NEXT: beq cr0, .LBB2_2
; CHECK-P9-LE-NEXT: .LBB2_1: ; CHECK-P9-LE-NEXT: .LBB2_1:
; CHECK-P9-LE-NEXT: stdux r4, r1, r5 ; CHECK-P9-LE-NEXT: stdux r4, r1, r5
; CHECK-P9-LE-NEXT: cmpd r1, r3 ; CHECK-P9-LE-NEXT: cmpd r1, r3
; CHECK-P9-LE-NEXT: bne cr0, .LBB2_1 ; CHECK-P9-LE-NEXT: bne cr0, .LBB2_1
; CHECK-P9-LE-NEXT: .LBB2_2: ; CHECK-P9-LE-NEXT: .LBB2_2:
; CHECK-P9-LE-NEXT: addi r3, r1, 32
; CHECK-P9-LE-NEXT: li r4, 1 ; CHECK-P9-LE-NEXT: li r4, 1
; CHECK-P9-LE-NEXT: addi r3, r1, 32
; CHECK-P9-LE-NEXT: stw r4, 4792(r3) ; CHECK-P9-LE-NEXT: stw r4, 4792(r3)
; CHECK-P9-LE-NEXT: lwz r3, 0(r3) ; CHECK-P9-LE-NEXT: lwz r3, 0(r3)
; CHECK-P9-LE-NEXT: ld r1, 0(r1) ; CHECK-P9-LE-NEXT: ld r1, 0(r1)
; CHECK-P9-LE-NEXT: ld r31, -8(r1) ; CHECK-P9-LE-NEXT: ld r31, -8(r1)
; CHECK-P9-LE-NEXT: blr ; CHECK-P9-LE-NEXT: blr
; ;
; CHECK-BE-LABEL: f: ; CHECK-BE-LABEL: f:
; CHECK-BE: # %bb.0: ; CHECK-BE: # %bb.0:
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llvm/test/CodeGen/PowerPC/topdepthreduce-postra.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -run-pass=postmisched -o - %s | FileCheck %s
---
# Check that postmisched's TopDepthReduce heuristic moves the MULLD later
# because of the dependency on x5
name: test
body: |
bb.0:
; CHECK-LABEL: name: test
; CHECK: renamable $x5 = LD 0, killed renamable $x5 :: (load 8)
; CHECK: renamable $x4 = LD 0, killed renamable $x4 :: (load 8)
; CHECK: renamable $x5 = MULLD killed renamable $x5, renamable $x3
; CHECK: renamable $x3 = MADDLD8 killed renamable $x4, killed renamable $x3, killed renamable $x5
renamable $x5 = LD 0, killed renamable $x5 :: (load 8)
renamable $x5 = MULLD killed renamable $x5, renamable $x3
renamable $x4 = LD 0, killed renamable $x4 :: (load 8)
renamable $x3 = MADDLD8 killed renamable $x4, killed renamable $x3, killed renamable $x5
...

llvm/test/CodeGen/PowerPC/uint-to-fp-v4i32.ll

Show All 14 Lines
; P9BE-LABEL: test1: ; P9BE-LABEL: test1:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: li r3, 0
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: clrlwi r3, r3, 16 ; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: mtfprwz f0, r3 ; P9BE-NEXT: mtfprwz f0, r3
; P9BE-NEXT: li r3, 2 ; P9BE-NEXT: li r3, 2
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: xscvuxddp f0, f0
; P9BE-NEXT: clrlwi r3, r3, 16 ; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: mtfprwz f1, r3 ; P9BE-NEXT: mtfprwz f1, r3
; P9BE-NEXT: xscvuxddp f0, f0
; P9BE-NEXT: xscvuxddp f1, f1 ; P9BE-NEXT: xscvuxddp f1, f1
; P9BE-NEXT: xxmrghd v2, vs0, vs1 ; P9BE-NEXT: xxmrghd v2, vs0, vs1
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: test1: ; P9LE-LABEL: test1:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: li r3, 0 ; P9LE-NEXT: li r3, 0
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: clrlwi r3, r3, 16 ; P9LE-NEXT: clrlwi r3, r3, 16
; P9LE-NEXT: mtfprwz f0, r3 ; P9LE-NEXT: mtfprwz f0, r3
; P9LE-NEXT: li r3, 2 ; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: xscvuxddp f0, f0
; P9LE-NEXT: clrlwi r3, r3, 16 ; P9LE-NEXT: clrlwi r3, r3, 16
; P9LE-NEXT: mtfprwz f1, r3 ; P9LE-NEXT: mtfprwz f1, r3
; P9LE-NEXT: xscvuxddp f0, f0
; P9LE-NEXT: xscvuxddp f1, f1 ; P9LE-NEXT: xscvuxddp f1, f1
; P9LE-NEXT: xxmrghd v2, vs1, vs0 ; P9LE-NEXT: xxmrghd v2, vs1, vs0
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: test1: ; P8BE-LABEL: test1:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: mfvsrd r3, v2 ; P8BE-NEXT: mfvsrd r3, v2
; P8BE-NEXT: rldicl r4, r3, 16, 48 ; P8BE-NEXT: rldicl r4, r3, 16, 48
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llvm/test/CodeGen/PowerPC/unaligned-addressing-mode.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -ppc-convert-rr-to-ri=false -ppc-asm-full-reg-names < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -ppc-convert-rr-to-ri=false -ppc-asm-full-reg-names < %s | FileCheck %s
; ISEL matches address mode xaddr. ; ISEL matches address mode xaddr.
define i8 @test_xaddr(i8* %p) { define i8 @test_xaddr(i8* %p) {
; CHECK-LABEL: test_xaddr: ; CHECK-LABEL: test_xaddr:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li r4, 0 ; CHECK-NEXT: li r4, 0
; CHECK-NEXT: ori r4, r4, 40000
; CHECK-NEXT: std r3, -8(r1) ; CHECK-NEXT: std r3, -8(r1)
; CHECK-NEXT: ori r4, r4, 40000
; CHECK-NEXT: lbzx r3, r3, r4 ; CHECK-NEXT: lbzx r3, r3, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%p.addr = alloca i8*, align 8 %p.addr = alloca i8*, align 8
store i8* %p, i8** %p.addr, align 8 store i8* %p, i8** %p.addr, align 8
%0 = load i8*, i8** %p.addr, align 8 %0 = load i8*, i8** %p.addr, align 8
%add.ptr = getelementptr inbounds i8, i8* %0, i64 40000 %add.ptr = getelementptr inbounds i8, i8* %0, i64 40000
%1 = load i8, i8* %add.ptr, align 1 %1 = load i8, i8* %add.ptr, align 1
Show All 32 Linesentry:
ret <2 x double> %1 ret <2 x double> %1
} }
; ISEL matches address mode xoaddr. ; ISEL matches address mode xoaddr.
define void @test_xoaddr(i32* %arr, i32* %arrTo) { define void @test_xoaddr(i32* %arr, i32* %arrTo) {
; CHECK-LABEL: test_xoaddr: ; CHECK-LABEL: test_xoaddr:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi r3, r3, 8 ; CHECK-NEXT: addi r3, r3, 8
; CHECK-NEXT: lxvx vs0, 0, r3
; CHECK-NEXT: addi r4, r4, 4 ; CHECK-NEXT: addi r4, r4, 4
; CHECK-NEXT: lxvx vs0, 0, r3
; CHECK-NEXT: stxvx vs0, 0, r4 ; CHECK-NEXT: stxvx vs0, 0, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%arrayidx = getelementptr inbounds i32, i32* %arrTo, i64 1 %arrayidx = getelementptr inbounds i32, i32* %arrTo, i64 1
%0 = bitcast i32* %arrayidx to <4 x i32>* %0 = bitcast i32* %arrayidx to <4 x i32>*
%arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2
%1 = bitcast i32* %arrayidx1 to <4 x i32>* %1 = bitcast i32* %arrayidx1 to <4 x i32>*
%2 = load <4 x i32>, <4 x i32>* %1, align 8 %2 = load <4 x i32>, <4 x i32>* %1, align 8
store <4 x i32> %2, <4 x i32>* %0, align 8 store <4 x i32> %2, <4 x i32>* %0, align 8
ret void ret void
} }
; ISEL matches address mode xaddrX4 and generates LI which can be moved outside of ; ISEL matches address mode xaddrX4 and generates LI which can be moved outside of
; loop. ; loop.
define i64 @test_xaddrX4_loop(i8* %p) { define i64 @test_xaddrX4_loop(i8* %p) {
; CHECK-LABEL: test_xaddrX4_loop: ; CHECK-LABEL: test_xaddrX4_loop:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi r4, r3, -8 ; CHECK-NEXT: addi r4, r3, -8
; CHECK-NEXT: li r3, 8 ; CHECK-NEXT: li r3, 8
; CHECK-NEXT: li r5, 3
; CHECK-NEXT: mtctr r3 ; CHECK-NEXT: mtctr r3
; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: li r3, 0
; CHECK-NEXT: li r5, 3
; loop instruction number is changed from 5 to 4, so its align is changed from 5 to 4. ; loop instruction number is changed from 5 to 4, so its align is changed from 5 to 4.
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB4_1: # %for.body ; CHECK-NEXT: .LBB4_1: # %for.body
; CHECK: ldu r6, 8(r4) ; CHECK: ldu r6, 8(r4)
; CHECK-NEXT: ldx r7, r4, r5 ; CHECK-NEXT: ldx r7, r4, r5
; CHECK-NEXT: maddld r3, r7, r6, r3 ; CHECK-NEXT: maddld r3, r7, r6, r3
; CHECK-NEXT: bdnz .LBB4_1 ; CHECK-NEXT: bdnz .LBB4_1
; CHECK-NEXT: # %bb.2: # %for.end ; CHECK-NEXT: # %bb.2: # %for.end
Show All 24 Lines

llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \ ; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,P9LE ; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,P9LE
; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \ ; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,P9BE ; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,P9BE
; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \ ; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,P8LE ; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,P8LE
; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \ ; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,P8BE ; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,P8BE
define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) { define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) {
; P9LE-LABEL: fold_urem_vec_1: ; P9LE-LABEL: fold_urem_vec_1:
; P9LE: # %bb.0: ; P9LE: # %bb.0:
; P9LE-NEXT: li r3, 4 ; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: lis r4, 21399 ; P9LE-NEXT: lis r4, 21399
; P9LE-NEXT: lis r5, 8456
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: ori r4, r4, 33437 ; P9LE-NEXT: ori r4, r4, 33437
; P9LE-NEXT: ori r5, r5, 16913
; P9LE-NEXT: clrlwi r3, r3, 16 ; P9LE-NEXT: clrlwi r3, r3, 16
; P9LE-NEXT: mulhwu r4, r3, r4 ; P9LE-NEXT: mulhwu r4, r3, r4
; P9LE-NEXT: srwi r4, r4, 5 ; P9LE-NEXT: srwi r4, r4, 5
; P9LE-NEXT: mulli r4, r4, 98 ; P9LE-NEXT: mulli r4, r4, 98
; P9LE-NEXT: sub r3, r3, r4 ; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: lis r4, 16727 ; P9LE-NEXT: lis r4, 16727
; P9LE-NEXT: mtvsrd v3, r3 ; P9LE-NEXT: mtvsrd v3, r3
; P9LE-NEXT: li r3, 6 ; P9LE-NEXT: li r3, 6
; P9LE-NEXT: ori r4, r4, 2287
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: clrlwi r3, r3, 16 ; P9LE-NEXT: clrlwi r3, r3, 16
; P9LE-NEXT: ori r4, r4, 2287
; P9LE-NEXT: mulhwu r4, r3, r4 ; P9LE-NEXT: mulhwu r4, r3, r4
; P9LE-NEXT: srwi r4, r4, 8 ; P9LE-NEXT: srwi r4, r4, 8
; P9LE-NEXT: mulli r4, r4, 1003 ; P9LE-NEXT: mulli r4, r4, 1003
; P9LE-NEXT: sub r3, r3, r4 ; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: mtvsrd v4, r3 ; P9LE-NEXT: mtvsrd v4, r3
; P9LE-NEXT: li r3, 2 ; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: lis r5, 8456
; P9LE-NEXT: ori r5, r5, 16913
; P9LE-NEXT: vmrghh v3, v4, v3 ; P9LE-NEXT: vmrghh v3, v4, v3
; P9LE-NEXT: clrlwi r4, r3, 16 ; P9LE-NEXT: clrlwi r4, r3, 16
; P9LE-NEXT: rlwinm r3, r3, 30, 18, 31 ; P9LE-NEXT: rlwinm r3, r3, 30, 18, 31
; P9LE-NEXT: mulhwu r3, r3, r5 ; P9LE-NEXT: mulhwu r3, r3, r5
; P9LE-NEXT: srwi r3, r3, 2 ; P9LE-NEXT: srwi r3, r3, 2
; P9LE-NEXT: mulli r3, r3, 124 ; P9LE-NEXT: mulli r3, r3, 124
; P9LE-NEXT: sub r3, r4, r3 ; P9LE-NEXT: sub r3, r4, r3
; P9LE-NEXT: lis r4, 22765 ; P9LE-NEXT: lis r4, 22765
; P9LE-NEXT: mtvsrd v4, r3 ; P9LE-NEXT: mtvsrd v4, r3
; P9LE-NEXT: li r3, 0 ; P9LE-NEXT: li r3, 0
; P9LE-NEXT: ori r4, r4, 8969
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: clrlwi r3, r3, 16 ; P9LE-NEXT: clrlwi r3, r3, 16
; P9LE-NEXT: ori r4, r4, 8969
; P9LE-NEXT: mulhwu r4, r3, r4 ; P9LE-NEXT: mulhwu r4, r3, r4
; P9LE-NEXT: sub r5, r3, r4 ; P9LE-NEXT: sub r5, r3, r4
; P9LE-NEXT: srwi r5, r5, 1 ; P9LE-NEXT: srwi r5, r5, 1
; P9LE-NEXT: add r4, r5, r4 ; P9LE-NEXT: add r4, r5, r4
; P9LE-NEXT: srwi r4, r4, 6 ; P9LE-NEXT: srwi r4, r4, 6
; P9LE-NEXT: mulli r4, r4, 95 ; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: sub r3, r3, r4 ; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: mtvsrd v2, r3 ; P9LE-NEXT: mtvsrd v2, r3
; P9LE-NEXT: vmrghh v2, v4, v2 ; P9LE-NEXT: vmrghh v2, v4, v2
; P9LE-NEXT: vmrglw v2, v3, v2 ; P9LE-NEXT: vmrglw v2, v3, v2
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P9BE-LABEL: fold_urem_vec_1: ; P9BE-LABEL: fold_urem_vec_1:
; P9BE: # %bb.0: ; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 6 ; P9BE-NEXT: li r3, 6
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: lis r4, 16727 ; P9BE-NEXT: lis r4, 16727
; P9BE-NEXT: lis r5, 8456
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: ori r4, r4, 2287 ; P9BE-NEXT: ori r4, r4, 2287
; P9BE-NEXT: ori r5, r5, 16913
; P9BE-NEXT: clrlwi r3, r3, 16 ; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: mulhwu r4, r3, r4 ; P9BE-NEXT: mulhwu r4, r3, r4
; P9BE-NEXT: srwi r4, r4, 8 ; P9BE-NEXT: srwi r4, r4, 8
; P9BE-NEXT: mulli r4, r4, 1003 ; P9BE-NEXT: mulli r4, r4, 1003
; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: sub r3, r3, r4
; P9BE-NEXT: lis r4, 21399 ; P9BE-NEXT: lis r4, 21399
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: ori r4, r4, 33437
; P9BE-NEXT: mtvsrd v3, r3 ; P9BE-NEXT: mtvsrd v3, r3
; P9BE-NEXT: li r3, 4 ; P9BE-NEXT: li r3, 4
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: clrlwi r3, r3, 16 ; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: ori r4, r4, 33437
; P9BE-NEXT: mulhwu r4, r3, r4 ; P9BE-NEXT: mulhwu r4, r3, r4
; P9BE-NEXT: srwi r4, r4, 5 ; P9BE-NEXT: srwi r4, r4, 5
; P9BE-NEXT: mulli r4, r4, 98 ; P9BE-NEXT: mulli r4, r4, 98
; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: sub r3, r3, r4
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v4, r3 ; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 2 ; P9BE-NEXT: li r3, 2
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: lis r5, 8456
; P9BE-NEXT: ori r5, r5, 16913
; P9BE-NEXT: vmrghh v3, v4, v3 ; P9BE-NEXT: vmrghh v3, v4, v3
; P9BE-NEXT: clrlwi r4, r3, 16 ; P9BE-NEXT: clrlwi r4, r3, 16
; P9BE-NEXT: rlwinm r3, r3, 30, 18, 31 ; P9BE-NEXT: rlwinm r3, r3, 30, 18, 31
; P9BE-NEXT: mulhwu r3, r3, r5 ; P9BE-NEXT: mulhwu r3, r3, r5
; P9BE-NEXT: srwi r3, r3, 2 ; P9BE-NEXT: srwi r3, r3, 2
; P9BE-NEXT: mulli r3, r3, 124 ; P9BE-NEXT: mulli r3, r3, 124
; P9BE-NEXT: sub r3, r4, r3 ; P9BE-NEXT: sub r3, r4, r3
; P9BE-NEXT: lis r4, 22765 ; P9BE-NEXT: lis r4, 22765
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: ori r4, r4, 8969
; P9BE-NEXT: mtvsrd v4, r3 ; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: li r3, 0
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: clrlwi r3, r3, 16 ; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: ori r4, r4, 8969
; P9BE-NEXT: mulhwu r4, r3, r4 ; P9BE-NEXT: mulhwu r4, r3, r4
; P9BE-NEXT: sub r5, r3, r4 ; P9BE-NEXT: sub r5, r3, r4
; P9BE-NEXT: srwi r5, r5, 1 ; P9BE-NEXT: srwi r5, r5, 1
; P9BE-NEXT: add r4, r5, r4 ; P9BE-NEXT: add r4, r5, r4
; P9BE-NEXT: srwi r4, r4, 6 ; P9BE-NEXT: srwi r4, r4, 6
; P9BE-NEXT: mulli r4, r4, 95 ; P9BE-NEXT: mulli r4, r4, 95
; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: sub r3, r3, r4
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
▲ Show 20 Lines • Show All 105 Lines • ▼ Show 20 Lines; P8BE-NEXT: blr
%1 = urem <4 x i16> %x, <i16 95, i16 124, i16 98, i16 1003> %1 = urem <4 x i16> %x, <i16 95, i16 124, i16 98, i16 1003>
ret <4 x i16> %1 ret <4 x i16> %1
} }
define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) { define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) {
; P9LE-LABEL: fold_urem_vec_2: ; P9LE-LABEL: fold_urem_vec_2:
; P9LE: # %bb.0: ; P9LE: # %bb.0:
; P9LE-NEXT: li r3, 0 ; P9LE-NEXT: li r3, 0
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: lis r4, 22765 ; P9LE-NEXT: lis r4, 22765
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: ori r4, r4, 8969 ; P9LE-NEXT: ori r4, r4, 8969
; P9LE-NEXT: clrlwi r3, r3, 16 ; P9LE-NEXT: clrlwi r3, r3, 16
; P9LE-NEXT: mulhwu r5, r3, r4 ; P9LE-NEXT: mulhwu r5, r3, r4
; P9LE-NEXT: sub r6, r3, r5 ; P9LE-NEXT: sub r6, r3, r5
; P9LE-NEXT: srwi r6, r6, 1 ; P9LE-NEXT: srwi r6, r6, 1
; P9LE-NEXT: add r5, r6, r5 ; P9LE-NEXT: add r5, r6, r5
; P9LE-NEXT: srwi r5, r5, 6 ; P9LE-NEXT: srwi r5, r5, 6
; P9LE-NEXT: mulli r5, r5, 95 ; P9LE-NEXT: mulli r5, r5, 95
; P9LE-NEXT: sub r3, r3, r5 ; P9LE-NEXT: sub r3, r3, r5
; P9LE-NEXT: mtvsrd v3, r3 ; P9LE-NEXT: mtvsrd v3, r3
; P9LE-NEXT: li r3, 2 ; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: clrlwi r3, r3, 16 ; P9LE-NEXT: clrlwi r3, r3, 16
; P9LE-NEXT: mulhwu r5, r3, r4 ; P9LE-NEXT: mulhwu r5, r3, r4
; P9LE-NEXT: sub r6, r3, r5 ; P9LE-NEXT: sub r6, r3, r5
; P9LE-NEXT: srwi r6, r6, 1 ; P9LE-NEXT: srwi r6, r6, 1
; P9LE-NEXT: add r5, r6, r5 ; P9LE-NEXT: add r5, r6, r5
; P9LE-NEXT: srwi r5, r5, 6 ; P9LE-NEXT: srwi r5, r5, 6
; P9LE-NEXT: mulli r5, r5, 95 ; P9LE-NEXT: mulli r5, r5, 95
; P9LE-NEXT: sub r3, r3, r5 ; P9LE-NEXT: sub r3, r3, r5
; P9LE-NEXT: mtvsrd v4, r3 ; P9LE-NEXT: mtvsrd v4, r3
; P9LE-NEXT: li r3, 4 ; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: vmrghh v3, v4, v3
; P9LE-NEXT: clrlwi r3, r3, 16 ; P9LE-NEXT: clrlwi r3, r3, 16
; P9LE-NEXT: mulhwu r5, r3, r4 ; P9LE-NEXT: mulhwu r5, r3, r4
; P9LE-NEXT: sub r6, r3, r5 ; P9LE-NEXT: sub r6, r3, r5
; P9LE-NEXT: srwi r6, r6, 1 ; P9LE-NEXT: srwi r6, r6, 1
; P9LE-NEXT: add r5, r6, r5 ; P9LE-NEXT: add r5, r6, r5
; P9LE-NEXT: srwi r5, r5, 6 ; P9LE-NEXT: srwi r5, r5, 6
; P9LE-NEXT: mulli r5, r5, 95 ; P9LE-NEXT: mulli r5, r5, 95
; P9LE-NEXT: sub r3, r3, r5 ; P9LE-NEXT: sub r3, r3, r5
; P9LE-NEXT: vmrghh v3, v4, v3
; P9LE-NEXT: mtvsrd v4, r3 ; P9LE-NEXT: mtvsrd v4, r3
; P9LE-NEXT: li r3, 6 ; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: clrlwi r3, r3, 16 ; P9LE-NEXT: clrlwi r3, r3, 16
; P9LE-NEXT: mulhwu r4, r3, r4 ; P9LE-NEXT: mulhwu r4, r3, r4
; P9LE-NEXT: sub r5, r3, r4 ; P9LE-NEXT: sub r5, r3, r4
; P9LE-NEXT: srwi r5, r5, 1 ; P9LE-NEXT: srwi r5, r5, 1
; P9LE-NEXT: add r4, r5, r4 ; P9LE-NEXT: add r4, r5, r4
; P9LE-NEXT: srwi r4, r4, 6 ; P9LE-NEXT: srwi r4, r4, 6
; P9LE-NEXT: mulli r4, r4, 95 ; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: sub r3, r3, r4 ; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: mtvsrd v2, r3 ; P9LE-NEXT: mtvsrd v2, r3
; P9LE-NEXT: vmrghh v2, v2, v4 ; P9LE-NEXT: vmrghh v2, v2, v4
; P9LE-NEXT: vmrglw v2, v2, v3 ; P9LE-NEXT: vmrglw v2, v2, v3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P9BE-LABEL: fold_urem_vec_2: ; P9BE-LABEL: fold_urem_vec_2:
; P9BE: # %bb.0: ; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 6 ; P9BE-NEXT: li r3, 6
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: lis r4, 22765 ; P9BE-NEXT: lis r4, 22765
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: ori r4, r4, 8969 ; P9BE-NEXT: ori r4, r4, 8969
; P9BE-NEXT: clrlwi r3, r3, 16 ; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: mulhwu r5, r3, r4 ; P9BE-NEXT: mulhwu r5, r3, r4
; P9BE-NEXT: sub r6, r3, r5 ; P9BE-NEXT: sub r6, r3, r5
; P9BE-NEXT: srwi r6, r6, 1 ; P9BE-NEXT: srwi r6, r6, 1
; P9BE-NEXT: add r5, r6, r5 ; P9BE-NEXT: add r5, r6, r5
; P9BE-NEXT: srwi r5, r5, 6 ; P9BE-NEXT: srwi r5, r5, 6
; P9BE-NEXT: mulli r5, r5, 95 ; P9BE-NEXT: mulli r5, r5, 95
Show All 9 Lines
; P9BE-NEXT: add r5, r6, r5 ; P9BE-NEXT: add r5, r6, r5
; P9BE-NEXT: srwi r5, r5, 6 ; P9BE-NEXT: srwi r5, r5, 6
; P9BE-NEXT: mulli r5, r5, 95 ; P9BE-NEXT: mulli r5, r5, 95
; P9BE-NEXT: sub r3, r3, r5 ; P9BE-NEXT: sub r3, r3, r5
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v4, r3 ; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 2 ; P9BE-NEXT: li r3, 2
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: vmrghh v3, v4, v3
; P9BE-NEXT: clrlwi r3, r3, 16 ; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: mulhwu r5, r3, r4 ; P9BE-NEXT: mulhwu r5, r3, r4
; P9BE-NEXT: sub r6, r3, r5 ; P9BE-NEXT: sub r6, r3, r5
; P9BE-NEXT: srwi r6, r6, 1 ; P9BE-NEXT: srwi r6, r6, 1
; P9BE-NEXT: add r5, r6, r5 ; P9BE-NEXT: add r5, r6, r5
; P9BE-NEXT: srwi r5, r5, 6 ; P9BE-NEXT: srwi r5, r5, 6
; P9BE-NEXT: mulli r5, r5, 95 ; P9BE-NEXT: mulli r5, r5, 95
; P9BE-NEXT: sub r3, r3, r5 ; P9BE-NEXT: sub r3, r3, r5
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: vmrghh v3, v4, v3
; P9BE-NEXT: mtvsrd v4, r3 ; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: li r3, 0
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: clrlwi r3, r3, 16 ; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: mulhwu r4, r3, r4 ; P9BE-NEXT: mulhwu r4, r3, r4
; P9BE-NEXT: sub r5, r3, r4 ; P9BE-NEXT: sub r5, r3, r4
; P9BE-NEXT: srwi r5, r5, 1 ; P9BE-NEXT: srwi r5, r5, 1
; P9BE-NEXT: add r4, r5, r4 ; P9BE-NEXT: add r4, r5, r4
▲ Show 20 Lines • Show All 115 Lines • ▼ Show 20 Lines
} }
; Don't fold if we can combine urem with udiv. ; Don't fold if we can combine urem with udiv.
define <4 x i16> @combine_urem_udiv(<4 x i16> %x) { define <4 x i16> @combine_urem_udiv(<4 x i16> %x) {
; P9LE-LABEL: combine_urem_udiv: ; P9LE-LABEL: combine_urem_udiv:
; P9LE: # %bb.0: ; P9LE: # %bb.0:
; P9LE-NEXT: li r3, 0 ; P9LE-NEXT: li r3, 0
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: lis r4, 22765 ; P9LE-NEXT: lis r4, 22765
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: ori r4, r4, 8969 ; P9LE-NEXT: ori r4, r4, 8969
; P9LE-NEXT: clrlwi r3, r3, 16 ; P9LE-NEXT: clrlwi r3, r3, 16
; P9LE-NEXT: mulhwu r5, r3, r4 ; P9LE-NEXT: mulhwu r5, r3, r4
; P9LE-NEXT: sub r6, r3, r5 ; P9LE-NEXT: sub r6, r3, r5
; P9LE-NEXT: srwi r6, r6, 1 ; P9LE-NEXT: srwi r6, r6, 1
; P9LE-NEXT: add r5, r6, r5 ; P9LE-NEXT: add r5, r6, r5
; P9LE-NEXT: srwi r5, r5, 6 ; P9LE-NEXT: srwi r5, r5, 6
; P9LE-NEXT: mulli r6, r5, 95 ; P9LE-NEXT: mulli r6, r5, 95
; P9LE-NEXT: sub r3, r3, r6 ; P9LE-NEXT: sub r3, r3, r6
; P9LE-NEXT: mtvsrd v3, r3 ; P9LE-NEXT: mtvsrd v3, r3
; P9LE-NEXT: li r3, 2 ; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: clrlwi r6, r3, 16 ; P9LE-NEXT: clrlwi r6, r3, 16
; P9LE-NEXT: mulhwu r7, r6, r4 ; P9LE-NEXT: mulhwu r7, r6, r4
; P9LE-NEXT: sub r6, r6, r7 ; P9LE-NEXT: sub r6, r6, r7
; P9LE-NEXT: srwi r6, r6, 1 ; P9LE-NEXT: srwi r6, r6, 1
; P9LE-NEXT: add r6, r6, r7 ; P9LE-NEXT: add r6, r6, r7
; P9LE-NEXT: srwi r6, r6, 6 ; P9LE-NEXT: srwi r6, r6, 6
; P9LE-NEXT: mulli r7, r6, 95 ; P9LE-NEXT: mulli r7, r6, 95
; P9LE-NEXT: sub r3, r3, r7 ; P9LE-NEXT: sub r3, r3, r7
; P9LE-NEXT: mtvsrd v4, r3 ; P9LE-NEXT: mtvsrd v4, r3
; P9LE-NEXT: li r3, 4 ; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: vmrghh v3, v4, v3
; P9LE-NEXT: clrlwi r7, r3, 16 ; P9LE-NEXT: clrlwi r7, r3, 16
; P9LE-NEXT: mulhwu r8, r7, r4 ; P9LE-NEXT: mulhwu r8, r7, r4
; P9LE-NEXT: sub r7, r7, r8 ; P9LE-NEXT: sub r7, r7, r8
; P9LE-NEXT: srwi r7, r7, 1 ; P9LE-NEXT: srwi r7, r7, 1
; P9LE-NEXT: add r7, r7, r8 ; P9LE-NEXT: add r7, r7, r8
; P9LE-NEXT: srwi r7, r7, 6 ; P9LE-NEXT: srwi r7, r7, 6
; P9LE-NEXT: mulli r8, r7, 95 ; P9LE-NEXT: mulli r8, r7, 95
; P9LE-NEXT: sub r3, r3, r8 ; P9LE-NEXT: sub r3, r3, r8
; P9LE-NEXT: vmrghh v3, v4, v3
; P9LE-NEXT: mtvsrd v4, r3 ; P9LE-NEXT: mtvsrd v4, r3
; P9LE-NEXT: li r3, 6 ; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: clrlwi r8, r3, 16 ; P9LE-NEXT: clrlwi r8, r3, 16
; P9LE-NEXT: mulhwu r4, r8, r4 ; P9LE-NEXT: mulhwu r4, r8, r4
; P9LE-NEXT: sub r8, r8, r4 ; P9LE-NEXT: sub r8, r8, r4
; P9LE-NEXT: srwi r8, r8, 1 ; P9LE-NEXT: srwi r8, r8, 1
; P9LE-NEXT: add r4, r8, r4 ; P9LE-NEXT: add r4, r8, r4
; P9LE-NEXT: srwi r4, r4, 6 ; P9LE-NEXT: srwi r4, r4, 6
; P9LE-NEXT: mulli r8, r4, 95 ; P9LE-NEXT: mulli r8, r4, 95
; P9LE-NEXT: mtvsrd v5, r4
; P9LE-NEXT: sub r3, r3, r8 ; P9LE-NEXT: sub r3, r3, r8
; P9LE-NEXT: mtvsrd v2, r3 ; P9LE-NEXT: mtvsrd v2, r3
; P9LE-NEXT: vmrghh v2, v2, v4 ; P9LE-NEXT: vmrghh v2, v2, v4
; P9LE-NEXT: mtvsrd v4, r6 ; P9LE-NEXT: mtvsrd v4, r6
; P9LE-NEXT: vmrglw v2, v2, v3 ; P9LE-NEXT: vmrglw v2, v2, v3
; P9LE-NEXT: mtvsrd v3, r5 ; P9LE-NEXT: mtvsrd v3, r5
; P9LE-NEXT: vmrghh v3, v4, v3 ; P9LE-NEXT: vmrghh v3, v4, v3
; P9LE-NEXT: mtvsrd v4, r7 ; P9LE-NEXT: mtvsrd v4, r7
; P9LE-NEXT: mtvsrd v5, r4
; P9LE-NEXT: vmrghh v4, v5, v4 ; P9LE-NEXT: vmrghh v4, v5, v4
; P9LE-NEXT: vmrglw v3, v4, v3 ; P9LE-NEXT: vmrglw v3, v4, v3
; P9LE-NEXT: vadduhm v2, v2, v3 ; P9LE-NEXT: vadduhm v2, v2, v3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P9BE-LABEL: combine_urem_udiv: ; P9BE-LABEL: combine_urem_udiv:
; P9BE: # %bb.0: ; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 6 ; P9BE-NEXT: li r3, 6
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: lis r5, 22765 ; P9BE-NEXT: lis r5, 22765
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: ori r5, r5, 8969 ; P9BE-NEXT: ori r5, r5, 8969
; P9BE-NEXT: clrlwi r4, r3, 16 ; P9BE-NEXT: clrlwi r4, r3, 16
; P9BE-NEXT: mulhwu r6, r4, r5 ; P9BE-NEXT: mulhwu r6, r4, r5
; P9BE-NEXT: sub r4, r4, r6 ; P9BE-NEXT: sub r4, r4, r6
; P9BE-NEXT: srwi r4, r4, 1 ; P9BE-NEXT: srwi r4, r4, 1
; P9BE-NEXT: add r4, r4, r6 ; P9BE-NEXT: add r4, r4, r6
; P9BE-NEXT: srwi r4, r4, 6 ; P9BE-NEXT: srwi r4, r4, 6
; P9BE-NEXT: mulli r6, r4, 95 ; P9BE-NEXT: mulli r6, r4, 95
Show All 9 Lines
; P9BE-NEXT: add r6, r6, r7 ; P9BE-NEXT: add r6, r6, r7
; P9BE-NEXT: srwi r6, r6, 6 ; P9BE-NEXT: srwi r6, r6, 6
; P9BE-NEXT: mulli r7, r6, 95 ; P9BE-NEXT: mulli r7, r6, 95
; P9BE-NEXT: sub r3, r3, r7 ; P9BE-NEXT: sub r3, r3, r7
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v4, r3 ; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 2 ; P9BE-NEXT: li r3, 2
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: vmrghh v3, v4, v3
; P9BE-NEXT: clrlwi r7, r3, 16 ; P9BE-NEXT: clrlwi r7, r3, 16
; P9BE-NEXT: mulhwu r8, r7, r5 ; P9BE-NEXT: mulhwu r8, r7, r5
; P9BE-NEXT: sub r7, r7, r8 ; P9BE-NEXT: sub r7, r7, r8
; P9BE-NEXT: srwi r7, r7, 1 ; P9BE-NEXT: srwi r7, r7, 1
; P9BE-NEXT: add r7, r7, r8 ; P9BE-NEXT: add r7, r7, r8
; P9BE-NEXT: srwi r7, r7, 6 ; P9BE-NEXT: srwi r7, r7, 6
; P9BE-NEXT: mulli r8, r7, 95 ; P9BE-NEXT: mulli r8, r7, 95
; P9BE-NEXT: sub r3, r3, r8 ; P9BE-NEXT: sub r3, r3, r8
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: vmrghh v3, v4, v3
; P9BE-NEXT: mtvsrd v4, r3 ; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: li r3, 0
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: clrlwi r3, r3, 16 ; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: mulhwu r5, r3, r5 ; P9BE-NEXT: mulhwu r5, r3, r5
; P9BE-NEXT: sub r8, r3, r5 ; P9BE-NEXT: sub r8, r3, r5
; P9BE-NEXT: srwi r8, r8, 1 ; P9BE-NEXT: srwi r8, r8, 1
; P9BE-NEXT: add r5, r8, r5 ; P9BE-NEXT: add r5, r8, r5
▲ Show 20 Lines • Show All 150 Lines • ▼ Show 20 Lines; P8BE-NEXT: blr
ret <4 x i16> %3 ret <4 x i16> %3
} }
; Don't fold for divisors that are a power of two. ; Don't fold for divisors that are a power of two.
define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) { define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) {
; P9LE-LABEL: dont_fold_urem_power_of_two: ; P9LE-LABEL: dont_fold_urem_power_of_two:
; P9LE: # %bb.0: ; P9LE: # %bb.0:
; P9LE-NEXT: li r3, 0 ; P9LE-NEXT: li r3, 0
; P9LE-NEXT: lis r4, 22765
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: ori r4, r4, 8969
; P9LE-NEXT: clrlwi r3, r3, 26 ; P9LE-NEXT: clrlwi r3, r3, 26
; P9LE-NEXT: mtvsrd v3, r3 ; P9LE-NEXT: mtvsrd v3, r3
; P9LE-NEXT: li r3, 2 ; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: clrlwi r3, r3, 27 ; P9LE-NEXT: clrlwi r3, r3, 27
; P9LE-NEXT: mtvsrd v4, r3 ; P9LE-NEXT: mtvsrd v4, r3
; P9LE-NEXT: li r3, 6 ; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: lis r4, 22765
; P9LE-NEXT: ori r4, r4, 8969
; P9LE-NEXT: vmrghh v3, v4, v3 ; P9LE-NEXT: vmrghh v3, v4, v3
; P9LE-NEXT: clrlwi r3, r3, 16 ; P9LE-NEXT: clrlwi r3, r3, 16
; P9LE-NEXT: mulhwu r4, r3, r4 ; P9LE-NEXT: mulhwu r4, r3, r4
; P9LE-NEXT: sub r5, r3, r4 ; P9LE-NEXT: sub r5, r3, r4
; P9LE-NEXT: srwi r5, r5, 1 ; P9LE-NEXT: srwi r5, r5, 1
; P9LE-NEXT: add r4, r5, r4 ; P9LE-NEXT: add r4, r5, r4
; P9LE-NEXT: srwi r4, r4, 6 ; P9LE-NEXT: srwi r4, r4, 6
; P9LE-NEXT: mulli r4, r4, 95 ; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: sub r3, r3, r4 ; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: mtvsrd v4, r3 ; P9LE-NEXT: mtvsrd v4, r3
; P9LE-NEXT: li r3, 4 ; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: clrlwi r3, r3, 29 ; P9LE-NEXT: clrlwi r3, r3, 29
; P9LE-NEXT: mtvsrd v2, r3 ; P9LE-NEXT: mtvsrd v2, r3
; P9LE-NEXT: vmrghh v2, v4, v2 ; P9LE-NEXT: vmrghh v2, v4, v2
; P9LE-NEXT: vmrglw v2, v2, v3 ; P9LE-NEXT: vmrglw v2, v2, v3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P9BE-LABEL: dont_fold_urem_power_of_two: ; P9BE-LABEL: dont_fold_urem_power_of_two:
; P9BE: # %bb.0: ; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 2 ; P9BE-NEXT: li r3, 2
; P9BE-NEXT: lis r4, 22765
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: ori r4, r4, 8969
; P9BE-NEXT: clrlwi r3, r3, 27 ; P9BE-NEXT: clrlwi r3, r3, 27
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v3, r3 ; P9BE-NEXT: mtvsrd v3, r3
; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: li r3, 0
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: clrlwi r3, r3, 26 ; P9BE-NEXT: clrlwi r3, r3, 26
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v4, r3 ; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 6 ; P9BE-NEXT: li r3, 6
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: lis r4, 22765
; P9BE-NEXT: ori r4, r4, 8969
; P9BE-NEXT: vmrghh v3, v4, v3 ; P9BE-NEXT: vmrghh v3, v4, v3
; P9BE-NEXT: clrlwi r3, r3, 16 ; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: mulhwu r4, r3, r4 ; P9BE-NEXT: mulhwu r4, r3, r4
; P9BE-NEXT: sub r5, r3, r4 ; P9BE-NEXT: sub r5, r3, r4
; P9BE-NEXT: srwi r5, r5, 1 ; P9BE-NEXT: srwi r5, r5, 1
; P9BE-NEXT: add r4, r5, r4 ; P9BE-NEXT: add r4, r5, r4
; P9BE-NEXT: srwi r4, r4, 6 ; P9BE-NEXT: srwi r4, r4, 6
; P9BE-NEXT: mulli r4, r4, 95 ; P9BE-NEXT: mulli r4, r4, 95
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines; P8BE-NEXT: blr
ret <4 x i16> %1 ret <4 x i16> %1
} }
; Don't fold if the divisor is one. ; Don't fold if the divisor is one.
define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) { define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) {
; P9LE-LABEL: dont_fold_urem_one: ; P9LE-LABEL: dont_fold_urem_one:
; P9LE: # %bb.0: ; P9LE: # %bb.0:
; P9LE-NEXT: li r3, 4 ; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: lis r4, -19946 ; P9LE-NEXT: lis r4, -19946
; P9LE-NEXT: lis r5, -14230
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: ori r4, r4, 17097 ; P9LE-NEXT: ori r4, r4, 17097
; P9LE-NEXT: ori r5, r5, 30865
; P9LE-NEXT: clrlwi r3, r3, 16 ; P9LE-NEXT: clrlwi r3, r3, 16
; P9LE-NEXT: mulhwu r4, r3, r4 ; P9LE-NEXT: mulhwu r4, r3, r4
; P9LE-NEXT: srwi r4, r4, 4 ; P9LE-NEXT: srwi r4, r4, 4
; P9LE-NEXT: mulli r4, r4, 23 ; P9LE-NEXT: mulli r4, r4, 23
; P9LE-NEXT: sub r3, r3, r4 ; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: lis r4, 24749 ; P9LE-NEXT: lis r4, 24749
; P9LE-NEXT: mtvsrd v3, r3 ; P9LE-NEXT: mtvsrd v3, r3
; P9LE-NEXT: li r3, 6 ; P9LE-NEXT: li r3, 6
; P9LE-NEXT: ori r4, r4, 47143
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: clrlwi r3, r3, 16 ; P9LE-NEXT: clrlwi r3, r3, 16
; P9LE-NEXT: ori r4, r4, 47143
; P9LE-NEXT: mulhwu r4, r3, r4 ; P9LE-NEXT: mulhwu r4, r3, r4
; P9LE-NEXT: srwi r4, r4, 11 ; P9LE-NEXT: srwi r4, r4, 11
; P9LE-NEXT: mulli r4, r4, 5423 ; P9LE-NEXT: mulli r4, r4, 5423
; P9LE-NEXT: sub r3, r3, r4 ; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: mtvsrd v4, r3 ; P9LE-NEXT: mtvsrd v4, r3
; P9LE-NEXT: li r3, 2 ; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: lis r5, -14230
; P9LE-NEXT: ori r5, r5, 30865
; P9LE-NEXT: vmrghh v3, v4, v3 ; P9LE-NEXT: vmrghh v3, v4, v3
; P9LE-NEXT: clrlwi r4, r3, 16 ; P9LE-NEXT: clrlwi r4, r3, 16
; P9LE-NEXT: rlwinm r3, r3, 31, 17, 31 ; P9LE-NEXT: rlwinm r3, r3, 31, 17, 31
; P9LE-NEXT: mulhwu r3, r3, r5 ; P9LE-NEXT: mulhwu r3, r3, r5
; P9LE-NEXT: srwi r3, r3, 8 ; P9LE-NEXT: srwi r3, r3, 8
; P9LE-NEXT: mulli r3, r3, 654 ; P9LE-NEXT: mulli r3, r3, 654
; P9LE-NEXT: sub r3, r4, r3 ; P9LE-NEXT: sub r3, r4, r3
; P9LE-NEXT: mtvsrd v2, r3 ; P9LE-NEXT: mtvsrd v2, r3
; P9LE-NEXT: li r3, 0 ; P9LE-NEXT: li r3, 0
; P9LE-NEXT: mtvsrd v4, r3 ; P9LE-NEXT: mtvsrd v4, r3
; P9LE-NEXT: vmrghh v2, v2, v4 ; P9LE-NEXT: vmrghh v2, v2, v4
; P9LE-NEXT: vmrglw v2, v3, v2 ; P9LE-NEXT: vmrglw v2, v3, v2
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P9BE-LABEL: dont_fold_urem_one: ; P9BE-LABEL: dont_fold_urem_one:
; P9BE: # %bb.0: ; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 6 ; P9BE-NEXT: li r3, 6
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: lis r4, 24749 ; P9BE-NEXT: lis r4, 24749
; P9BE-NEXT: lis r5, -14230
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: ori r4, r4, 47143 ; P9BE-NEXT: ori r4, r4, 47143
; P9BE-NEXT: ori r5, r5, 30865
; P9BE-NEXT: clrlwi r3, r3, 16 ; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: mulhwu r4, r3, r4 ; P9BE-NEXT: mulhwu r4, r3, r4
; P9BE-NEXT: srwi r4, r4, 11 ; P9BE-NEXT: srwi r4, r4, 11
; P9BE-NEXT: mulli r4, r4, 5423 ; P9BE-NEXT: mulli r4, r4, 5423
; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: sub r3, r3, r4
; P9BE-NEXT: lis r4, -19946 ; P9BE-NEXT: lis r4, -19946
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: ori r4, r4, 17097
; P9BE-NEXT: mtvsrd v3, r3 ; P9BE-NEXT: mtvsrd v3, r3
; P9BE-NEXT: li r3, 4 ; P9BE-NEXT: li r3, 4
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: clrlwi r3, r3, 16 ; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: ori r4, r4, 17097
; P9BE-NEXT: mulhwu r4, r3, r4 ; P9BE-NEXT: mulhwu r4, r3, r4
; P9BE-NEXT: srwi r4, r4, 4 ; P9BE-NEXT: srwi r4, r4, 4
; P9BE-NEXT: mulli r4, r4, 23 ; P9BE-NEXT: mulli r4, r4, 23
; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: sub r3, r3, r4
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v4, r3 ; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 2 ; P9BE-NEXT: li r3, 2
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: lis r5, -14230
; P9BE-NEXT: ori r5, r5, 30865
; P9BE-NEXT: vmrghh v3, v4, v3 ; P9BE-NEXT: vmrghh v3, v4, v3
; P9BE-NEXT: clrlwi r4, r3, 16 ; P9BE-NEXT: clrlwi r4, r3, 16
; P9BE-NEXT: rlwinm r3, r3, 31, 17, 31 ; P9BE-NEXT: rlwinm r3, r3, 31, 17, 31
; P9BE-NEXT: mulhwu r3, r3, r5 ; P9BE-NEXT: mulhwu r3, r3, r5
; P9BE-NEXT: srwi r3, r3, 8 ; P9BE-NEXT: srwi r3, r3, 8
; P9BE-NEXT: mulli r3, r3, 654 ; P9BE-NEXT: mulli r3, r3, 654
; P9BE-NEXT: sub r3, r4, r3 ; P9BE-NEXT: sub r3, r4, r3
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Lines; CHECK-NEXT: blr
ret <4 x i16> %1 ret <4 x i16> %1
} }
; Don't fold i64 urem. ; Don't fold i64 urem.
define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) { define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) {
; P9LE-LABEL: dont_fold_urem_i64: ; P9LE-LABEL: dont_fold_urem_i64:
; P9LE: # %bb.0: ; P9LE: # %bb.0:
; P9LE-NEXT: lis r4, 25644 ; P9LE-NEXT: lis r4, 25644
; P9LE-NEXT: mfvsrld r3, v3
; P9LE-NEXT: ori r4, r4, 34192 ; P9LE-NEXT: ori r4, r4, 34192
; P9LE-NEXT: sldi r4, r4, 32 ; P9LE-NEXT: sldi r4, r4, 32
; P9LE-NEXT: oris r4, r4, 45590 ; P9LE-NEXT: oris r4, r4, 45590
; P9LE-NEXT: mfvsrld r3, v3
; P9LE-NEXT: ori r4, r4, 17097 ; P9LE-NEXT: ori r4, r4, 17097
; P9LE-NEXT: mulhdu r4, r3, r4 ; P9LE-NEXT: mulhdu r4, r3, r4
; P9LE-NEXT: sub r5, r3, r4 ; P9LE-NEXT: sub r5, r3, r4
; P9LE-NEXT: rldicl r5, r5, 63, 1 ; P9LE-NEXT: rldicl r5, r5, 63, 1
; P9LE-NEXT: add r4, r5, r4 ; P9LE-NEXT: add r4, r5, r4
; P9LE-NEXT: lis r5, -16037 ; P9LE-NEXT: lis r5, -16037
; P9LE-NEXT: rldicl r4, r4, 60, 4 ; P9LE-NEXT: rldicl r4, r4, 60, 4
; P9LE-NEXT: ori r5, r5, 28749 ; P9LE-NEXT: ori r5, r5, 28749
; P9LE-NEXT: mulli r4, r4, 23 ; P9LE-NEXT: mulli r4, r4, 23
; P9LE-NEXT: sldi r5, r5, 32 ; P9LE-NEXT: sldi r5, r5, 32
; P9LE-NEXT: oris r5, r5, 52170 ; P9LE-NEXT: oris r5, r5, 52170
; P9LE-NEXT: ori r5, r5, 12109 ; P9LE-NEXT: ori r5, r5, 12109
; P9LE-NEXT: sub r3, r3, r4 ; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: mfvsrd r4, v3 ; P9LE-NEXT: mfvsrd r4, v3
; P9LE-NEXT: mulhdu r5, r4, r5 ; P9LE-NEXT: mulhdu r5, r4, r5
; P9LE-NEXT: rldicl r5, r5, 52, 12 ; P9LE-NEXT: rldicl r5, r5, 52, 12
; P9LE-NEXT: mulli r5, r5, 5423 ; P9LE-NEXT: mulli r5, r5, 5423
; P9LE-NEXT: sub r4, r4, r5 ; P9LE-NEXT: sub r4, r4, r5
; P9LE-NEXT: lis r5, 25653 ; P9LE-NEXT: lis r5, 25653
; P9LE-NEXT: ori r5, r5, 15432 ; P9LE-NEXT: ori r5, r5, 15432
; P9LE-NEXT: sldi r5, r5, 32
; P9LE-NEXT: mtvsrdd v3, r4, r3 ; P9LE-NEXT: mtvsrdd v3, r4, r3
; P9LE-NEXT: mfvsrd r3, v2 ; P9LE-NEXT: mfvsrd r3, v2
; P9LE-NEXT: sldi r5, r5, 32
; P9LE-NEXT: rldicl r4, r3, 63, 1 ; P9LE-NEXT: rldicl r4, r3, 63, 1
; P9LE-NEXT: oris r5, r5, 1603 ; P9LE-NEXT: oris r5, r5, 1603
; P9LE-NEXT: ori r5, r5, 21445 ; P9LE-NEXT: ori r5, r5, 21445
; P9LE-NEXT: mulhdu r4, r4, r5 ; P9LE-NEXT: mulhdu r4, r4, r5
; P9LE-NEXT: rldicl r4, r4, 57, 7 ; P9LE-NEXT: rldicl r4, r4, 57, 7
; P9LE-NEXT: mulli r4, r4, 654 ; P9LE-NEXT: mulli r4, r4, 654
; P9LE-NEXT: sub r3, r3, r4 ; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: li r4, 0 ; P9LE-NEXT: li r4, 0
; P9LE-NEXT: mtvsrdd v2, r3, r4 ; P9LE-NEXT: mtvsrdd v2, r3, r4
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P9BE-LABEL: dont_fold_urem_i64: ; P9BE-LABEL: dont_fold_urem_i64:
; P9BE: # %bb.0: ; P9BE: # %bb.0:
; P9BE-NEXT: lis r4, 25644 ; P9BE-NEXT: lis r4, 25644
; P9BE-NEXT: mfvsrd r3, v3
; P9BE-NEXT: ori r4, r4, 34192 ; P9BE-NEXT: ori r4, r4, 34192
; P9BE-NEXT: sldi r4, r4, 32 ; P9BE-NEXT: sldi r4, r4, 32
; P9BE-NEXT: oris r4, r4, 45590 ; P9BE-NEXT: oris r4, r4, 45590
; P9BE-NEXT: mfvsrd r3, v3
; P9BE-NEXT: ori r4, r4, 17097 ; P9BE-NEXT: ori r4, r4, 17097
; P9BE-NEXT: mulhdu r4, r3, r4 ; P9BE-NEXT: mulhdu r4, r3, r4
; P9BE-NEXT: sub r5, r3, r4 ; P9BE-NEXT: sub r5, r3, r4
; P9BE-NEXT: rldicl r5, r5, 63, 1 ; P9BE-NEXT: rldicl r5, r5, 63, 1
; P9BE-NEXT: add r4, r5, r4 ; P9BE-NEXT: add r4, r5, r4
; P9BE-NEXT: lis r5, -16037 ; P9BE-NEXT: lis r5, -16037
; P9BE-NEXT: rldicl r4, r4, 60, 4 ; P9BE-NEXT: rldicl r4, r4, 60, 4
; P9BE-NEXT: mulli r4, r4, 23
; P9BE-NEXT: ori r5, r5, 28749 ; P9BE-NEXT: ori r5, r5, 28749
; P9BE-NEXT: mulli r4, r4, 23
; P9BE-NEXT: sldi r5, r5, 32 ; P9BE-NEXT: sldi r5, r5, 32
; P9BE-NEXT: oris r5, r5, 52170 ; P9BE-NEXT: oris r5, r5, 52170
; P9BE-NEXT: ori r5, r5, 12109 ; P9BE-NEXT: ori r5, r5, 12109
; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: sub r3, r3, r4
; P9BE-NEXT: mfvsrld r4, v3 ; P9BE-NEXT: mfvsrld r4, v3
; P9BE-NEXT: mulhdu r5, r4, r5 ; P9BE-NEXT: mulhdu r5, r4, r5
; P9BE-NEXT: rldicl r5, r5, 52, 12 ; P9BE-NEXT: rldicl r5, r5, 52, 12
; P9BE-NEXT: mulli r5, r5, 5423 ; P9BE-NEXT: mulli r5, r5, 5423
; P9BE-NEXT: sub r4, r4, r5 ; P9BE-NEXT: sub r4, r4, r5
; P9BE-NEXT: lis r5, 25653 ; P9BE-NEXT: lis r5, 25653
; P9BE-NEXT: ori r5, r5, 15432 ; P9BE-NEXT: ori r5, r5, 15432
; P9BE-NEXT: sldi r5, r5, 32
; P9BE-NEXT: mtvsrdd v3, r3, r4 ; P9BE-NEXT: mtvsrdd v3, r3, r4
; P9BE-NEXT: mfvsrld r3, v2 ; P9BE-NEXT: mfvsrld r3, v2
; P9BE-NEXT: sldi r5, r5, 32
; P9BE-NEXT: rldicl r4, r3, 63, 1 ; P9BE-NEXT: rldicl r4, r3, 63, 1
; P9BE-NEXT: oris r5, r5, 1603 ; P9BE-NEXT: oris r5, r5, 1603
; P9BE-NEXT: ori r5, r5, 21445 ; P9BE-NEXT: ori r5, r5, 21445
; P9BE-NEXT: mulhdu r4, r4, r5 ; P9BE-NEXT: mulhdu r4, r4, r5
; P9BE-NEXT: rldicl r4, r4, 57, 7 ; P9BE-NEXT: rldicl r4, r4, 57, 7
; P9BE-NEXT: mulli r4, r4, 654 ; P9BE-NEXT: mulli r4, r4, 654
; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: sub r3, r3, r4
; P9BE-NEXT: mtvsrdd v2, 0, r3 ; P9BE-NEXT: mtvsrdd v2, 0, r3
▲ Show 20 Lines • Show All 97 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/vavg.ll

Show First 20 Lines • Show All 132 Lines • ▼ Show 20 Linesentry:
%shr = ashr <16 x i8> %add1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> %shr = ashr <16 x i8> %add1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
ret <16 x i8> %shr ret <16 x i8> %shr
} }
define <8 x i16> @test_v8i16_sign_negative(<8 x i16> %m, <8 x i16> %n) { define <8 x i16> @test_v8i16_sign_negative(<8 x i16> %m, <8 x i16> %n) {
; CHECK-P9-LABEL: test_v8i16_sign_negative: ; CHECK-P9-LABEL: test_v8i16_sign_negative:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis 3, 2, .LCPI6_0@toc@ha ; CHECK-P9-NEXT: addis 3, 2, .LCPI6_0@toc@ha
; CHECK-P9-NEXT: addi 3, 3, .LCPI6_0@toc@l
; CHECK-P9-NEXT: vadduhm 2, 2, 3 ; CHECK-P9-NEXT: vadduhm 2, 2, 3
; CHECK-P9-NEXT: addi 3, 3, .LCPI6_0@toc@l
; CHECK-P9-NEXT: lxvx 35, 0, 3 ; CHECK-P9-NEXT: lxvx 35, 0, 3
; CHECK-P9-NEXT: vadduhm 2, 2, 3 ; CHECK-P9-NEXT: vadduhm 2, 2, 3
; CHECK-P9-NEXT: vspltish 3, 1 ; CHECK-P9-NEXT: vspltish 3, 1
; CHECK-P9-NEXT: vsrah 2, 2, 3 ; CHECK-P9-NEXT: vsrah 2, 2, 3
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LABEL: test_v8i16_sign_negative: ; CHECK-P8-LABEL: test_v8i16_sign_negative:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
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llvm/test/CodeGen/PowerPC/vec-bswap.ll

; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr9 \ ; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr9 \
; RUN: -verify-machineinstrs -ppc-asm-full-reg-names | FileCheck %s ; RUN: -verify-machineinstrs -ppc-asm-full-reg-names | FileCheck %s
define dso_local void @test(i32* %Arr, i32 signext %Len) { define dso_local void @test(i32* %Arr, i32 signext %Len) {
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: lxvx [[REG:vs[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}} ; CHECK: lxvx [[REG:vs[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}}
; CHECK-NEXT: xxbrw vs{{[0-9]+}}, [[REG]] ; CHECK-NOT: [[REG]]
; CHECK: xxbrw vs{{[0-9]+}}, [[REG]]
entry: entry:
%cmp1 = icmp slt i32 0, %Len %cmp1 = icmp slt i32 0, %Len
br i1 %cmp1, label %for.body.lr.ph, label %for.cond.cleanup br i1 %cmp1, label %for.body.lr.ph, label %for.cond.cleanup
for.body.lr.ph: ; preds = %entry for.body.lr.ph: ; preds = %entry
%min.iters.check = icmp ult i32 %Len, 4 %min.iters.check = icmp ult i32 %Len, 4
br i1 %min.iters.check, label %scalar.ph, label %vector.ph br i1 %min.iters.check, label %scalar.ph, label %vector.ph
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llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i16_elts.ll

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; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt: ; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xxsldwi vs1, v2, v2, 3 ; CHECK-P9-NEXT: xxsldwi vs1, v2, v2, 3
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd v2, r3 ; CHECK-P9-NEXT: mtvsrd v2, r3
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd v3, r3 ; CHECK-P9-NEXT: mtvsrd v3, r3
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: vmrghh v2, v3, v2 ; CHECK-P9-NEXT: vmrghh v2, v3, v2
; CHECK-P9-NEXT: vextuwrx r3, r3, v2 ; CHECK-P9-NEXT: vextuwrx r3, r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
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; CHECK-P8-NEXT: vmrghh v4, v4, v1 ; CHECK-P8-NEXT: vmrghh v4, v4, v1
; CHECK-P8-NEXT: vmrglw v3, v4, v5 ; CHECK-P8-NEXT: vmrglw v3, v4, v5
; CHECK-P8-NEXT: xxmrgld v2, v3, v2 ; CHECK-P8-NEXT: xxmrgld v2, v3, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs1, 0(r3) ; CHECK-P9-NEXT: lxv vs1, 0(r3)
; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: mffprwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: xxswapd vs2, vs1 ; CHECK-P9-NEXT: xxswapd vs2, vs1
; CHECK-P9-NEXT: mtvsrd v2, r3 ; CHECK-P9-NEXT: mtvsrd v2, r3
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mffprwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: xscvspdpn f2, vs1 ; CHECK-P9-NEXT: xscvspdpn f2, vs1
; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1 ; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1
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; CHECK-P9-NEXT: vmrghh v4, v4, v5 ; CHECK-P9-NEXT: vmrghh v4, v4, v5
; CHECK-P9-NEXT: vmrglw v3, v4, v3 ; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld v2, v3, v2 ; CHECK-P9-NEXT: xxmrgld v2, v3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt: ; CHECK-BE-LABEL: test8elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs1 ; CHECK-BE-NEXT: xxswapd vs2, vs1
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xscvspdpn f2, vs1 ; CHECK-BE-NEXT: xscvspdpn f2, vs1
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0 ; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
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; CHECK-P8-NEXT: stvx v2, 0, r3 ; CHECK-P8-NEXT: stvx v2, 0, r3
; CHECK-P8-NEXT: xxmrgld v3, v5, v4 ; CHECK-P8-NEXT: xxmrgld v3, v5, v4
; CHECK-P8-NEXT: stvx v3, r3, r5 ; CHECK-P8-NEXT: stvx v3, r3, r5
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs2, 0(r4) ; CHECK-P9-NEXT: lxv vs2, 0(r4)
; CHECK-P9-NEXT: lxv vs1, 16(r4)
; CHECK-P9-NEXT: lxv vs0, 32(r4)
; CHECK-P9-NEXT: xxsldwi vs3, vs2, vs2, 3 ; CHECK-P9-NEXT: xxsldwi vs3, vs2, vs2, 3
; CHECK-P9-NEXT: xxswapd vs4, vs2 ; CHECK-P9-NEXT: xxswapd vs4, vs2
; CHECK-P9-NEXT: xscvspdpn f5, vs2
; CHECK-P9-NEXT: xxsldwi vs2, vs2, vs2, 1
; CHECK-P9-NEXT: xxsldwi vs6, vs1, vs1, 3
; CHECK-P9-NEXT: xscvspdpn f3, vs3 ; CHECK-P9-NEXT: xscvspdpn f3, vs3
; CHECK-P9-NEXT: xscvspdpn f4, vs4 ; CHECK-P9-NEXT: xscvspdpn f4, vs4
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f3, f3 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: xscvdpsxws f4, f4 ; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: xscvspdpn f5, vs2
; CHECK-P9-NEXT: xxsldwi vs2, vs2, vs2, 1
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mffprwz r5, f3 ; CHECK-P9-NEXT: mffprwz r5, f3
; CHECK-P9-NEXT: lxv vs1, 16(r4)
; CHECK-P9-NEXT: xxsldwi vs6, vs1, vs1, 3
; CHECK-P9-NEXT: xxswapd vs3, vs1 ; CHECK-P9-NEXT: xxswapd vs3, vs1
; CHECK-P9-NEXT: mtvsrd v2, r5 ; CHECK-P9-NEXT: mtvsrd v2, r5
; CHECK-P9-NEXT: mffprwz r5, f4 ; CHECK-P9-NEXT: mffprwz r5, f4
; CHECK-P9-NEXT: xscvdpsxws f4, f5 ; CHECK-P9-NEXT: xscvdpsxws f4, f5
; CHECK-P9-NEXT: xscvspdpn f3, vs3 ; CHECK-P9-NEXT: xscvspdpn f3, vs3
; CHECK-P9-NEXT: mtvsrd v3, r5 ; CHECK-P9-NEXT: mtvsrd v3, r5
; CHECK-P9-NEXT: vmrghh v2, v3, v2 ; CHECK-P9-NEXT: vmrghh v2, v3, v2
; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: mffprwz r5, f4 ; CHECK-P9-NEXT: mffprwz r5, f4
; CHECK-P9-NEXT: xscvspdpn f4, vs6 ; CHECK-P9-NEXT: xscvspdpn f4, vs6
; CHECK-P9-NEXT: mtvsrd v3, r5 ; CHECK-P9-NEXT: mtvsrd v3, r5
; CHECK-P9-NEXT: mffprwz r5, f2 ; CHECK-P9-NEXT: mffprwz r5, f2
; CHECK-P9-NEXT: xscvspdpn f2, vs1 ; CHECK-P9-NEXT: xscvspdpn f2, vs1
; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1 ; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-P9-NEXT: xscvdpsxws f4, f4 ; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: lxv vs0, 32(r4)
; CHECK-P9-NEXT: mtvsrd v4, r5 ; CHECK-P9-NEXT: mtvsrd v4, r5
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: vmrghh v3, v3, v4 ; CHECK-P9-NEXT: vmrghh v3, v3, v4
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mffprwz r5, f4 ; CHECK-P9-NEXT: mffprwz r5, f4
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mtvsrd v4, r5 ; CHECK-P9-NEXT: mtvsrd v4, r5
; CHECK-P9-NEXT: mffprwz r5, f3 ; CHECK-P9-NEXT: mffprwz r5, f3
; CHECK-P9-NEXT: xxsldwi vs3, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi vs3, vs0, vs0, 3
; CHECK-P9-NEXT: mtvsrd v5, r5 ; CHECK-P9-NEXT: mtvsrd v5, r5
; CHECK-P9-NEXT: mffprwz r5, f2 ; CHECK-P9-NEXT: mffprwz r5, f2
; CHECK-P9-NEXT: xscvspdpn f2, vs3 ; CHECK-P9-NEXT: xscvspdpn f2, vs3
; CHECK-P9-NEXT: vmrghh v4, v5, v4 ; CHECK-P9-NEXT: vmrghh v4, v5, v4
; CHECK-P9-NEXT: mtvsrd v5, r5 ; CHECK-P9-NEXT: mtvsrd v5, r5
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; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mtvsrd v1, r5 ; CHECK-P9-NEXT: mtvsrd v1, r5
; CHECK-P9-NEXT: vmrghh v0, v1, v0 ; CHECK-P9-NEXT: vmrghh v0, v1, v0
; CHECK-P9-NEXT: mffprwz r4, f2 ; CHECK-P9-NEXT: mffprwz r4, f2
; CHECK-P9-NEXT: xxmrgld vs2, v3, v2 ; CHECK-P9-NEXT: xxmrgld vs2, v3, v2
; CHECK-P9-NEXT: mtvsrd v4, r4 ; CHECK-P9-NEXT: mtvsrd v4, r4
; CHECK-P9-NEXT: mffprwz r4, f0 ; CHECK-P9-NEXT: mffprwz r4, f0
; CHECK-P9-NEXT: xxsldwi vs0, vs1, vs1, 3 ; CHECK-P9-NEXT: xxsldwi vs0, vs1, vs1, 3
; CHECK-P9-NEXT: stxv vs2, 0(r3)
; CHECK-P9-NEXT: mtvsrd v2, r4 ; CHECK-P9-NEXT: mtvsrd v2, r4
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: vmrghh v2, v4, v2 ; CHECK-P9-NEXT: vmrghh v2, v4, v2
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: vmrglw v2, v2, v0 ; CHECK-P9-NEXT: vmrglw v2, v2, v0
; CHECK-P9-NEXT: mffprwz r4, f0 ; CHECK-P9-NEXT: mffprwz r4, f0
; CHECK-P9-NEXT: xxswapd vs0, vs1 ; CHECK-P9-NEXT: xxswapd vs0, vs1
; CHECK-P9-NEXT: mtvsrd v3, r4 ; CHECK-P9-NEXT: mtvsrd v3, r4
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; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r4, f0 ; CHECK-P9-NEXT: mffprwz r4, f0
; CHECK-P9-NEXT: mtvsrd v5, r4 ; CHECK-P9-NEXT: mtvsrd v5, r4
; CHECK-P9-NEXT: vmrghh v4, v4, v5 ; CHECK-P9-NEXT: vmrghh v4, v4, v5
; CHECK-P9-NEXT: vmrglw v3, v4, v3 ; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld vs0, v3, v2 ; CHECK-P9-NEXT: xxmrgld vs0, v3, v2
; CHECK-P9-NEXT: stxv vs0, 16(r3) ; CHECK-P9-NEXT: stxv vs0, 16(r3)
; CHECK-P9-NEXT: stxv vs2, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r4) ; CHECK-BE-NEXT: lxv vs1, 16(r4)
; CHECK-BE-NEXT: lxv vs0, 0(r4)
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xxswapd vs3, vs1 ; CHECK-BE-NEXT: xxswapd vs3, vs1
; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: mffprwz r5, f2
; CHECK-BE-NEXT: xscvspdpn f4, vs1 ; CHECK-BE-NEXT: xscvspdpn f4, vs1
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mffprwz r5, f2
; CHECK-BE-NEXT: xxsldwi vs2, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mtvsrd v2, r5 ; CHECK-BE-NEXT: mtvsrd v2, r5
; CHECK-BE-NEXT: mffprwz r5, f3 ; CHECK-BE-NEXT: mffprwz r5, f3
; CHECK-BE-NEXT: xscvdpsxws f3, f4 ; CHECK-BE-NEXT: xscvdpsxws f3, f4
; CHECK-BE-NEXT: lxv vs0, 0(r4)
; CHECK-BE-NEXT: xxsldwi vs2, vs0, vs0, 3
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mtvsrd v3, r5 ; CHECK-BE-NEXT: mtvsrd v3, r5
; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mffprwz r5, f3 ; CHECK-BE-NEXT: mffprwz r5, f3
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v3, r5 ; CHECK-BE-NEXT: mtvsrd v3, r5
; CHECK-BE-NEXT: mffprwz r5, f1 ; CHECK-BE-NEXT: mffprwz r5, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0 ; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r5 ; CHECK-BE-NEXT: mtvsrd v4, r5
; CHECK-BE-NEXT: mffprwz r5, f2 ; CHECK-BE-NEXT: mffprwz r5, f2
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: vmrghh v3, v3, v4 ; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: mtvsrd v4, r5 ; CHECK-BE-NEXT: mtvsrd v4, r5
Show All 10 Lines
; CHECK-BE-NEXT: mffprwz r5, f1 ; CHECK-BE-NEXT: mffprwz r5, f1
; CHECK-BE-NEXT: lxv vs1, 48(r4) ; CHECK-BE-NEXT: lxv vs1, 48(r4)
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v5, r5 ; CHECK-BE-NEXT: mtvsrd v5, r5
; CHECK-BE-NEXT: mffprwz r5, f0 ; CHECK-BE-NEXT: mffprwz r5, f0
; CHECK-BE-NEXT: lxv vs0, 32(r4) ; CHECK-BE-NEXT: lxv vs0, 32(r4)
; CHECK-BE-NEXT: xscvspdpn f5, vs1 ; CHECK-BE-NEXT: xscvspdpn f5, vs1
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvdpsxws f5, f5
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: xxswapd vs3, vs1 ; CHECK-BE-NEXT: xxswapd vs3, vs1
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: xscvdpsxws f5, f5
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mtvsrd v0, r5 ; CHECK-BE-NEXT: mtvsrd v0, r5
; CHECK-BE-NEXT: vmrghh v5, v5, v0
; CHECK-BE-NEXT: xscvspdpn f3, vs3 ; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: vmrghh v5, v5, v0
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: vmrghw v3, v5, v4
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghw v3, v5, v4
; CHECK-BE-NEXT: mffprwz r4, f5 ; CHECK-BE-NEXT: mffprwz r4, f5
; CHECK-BE-NEXT: xxmrghd vs4, v3, v2 ; CHECK-BE-NEXT: xxmrghd vs4, v3, v2
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v2, r4 ; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: mffprwz r4, f2 ; CHECK-BE-NEXT: mffprwz r4, f2
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: stxv vs4, 0(r3) ; CHECK-BE-NEXT: stxv vs4, 0(r3)
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v3, r4 ; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: mffprwz r4, f3 ; CHECK-BE-NEXT: mffprwz r4, f3
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v4, r4 ; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: mffprwz r4, f1 ; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghh v3, v4, v3 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghh v2, v2, v4 ; CHECK-BE-NEXT: vmrghh v2, v2, v4
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: vmrghw v2, v2, v3 ; CHECK-BE-NEXT: vmrghw v2, v2, v3
; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v3, r4 ; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mffprwz r4, f1 ; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v4, r4 ; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
Show All 36 Lines
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt_signed: ; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xxsldwi vs1, v2, v2, 3 ; CHECK-P9-NEXT: xxsldwi vs1, v2, v2, 3
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd v2, r3 ; CHECK-P9-NEXT: mtvsrd v2, r3
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd v3, r3 ; CHECK-P9-NEXT: mtvsrd v3, r3
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: vmrghh v2, v3, v2 ; CHECK-P9-NEXT: vmrghh v2, v3, v2
; CHECK-P9-NEXT: vextuwrx r3, r3, v2 ; CHECK-P9-NEXT: vextuwrx r3, r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
▲ Show 20 Lines • Show All 166 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: vmrghh v4, v4, v1 ; CHECK-P8-NEXT: vmrghh v4, v4, v1
; CHECK-P8-NEXT: vmrglw v3, v4, v5 ; CHECK-P8-NEXT: vmrglw v3, v4, v5
; CHECK-P8-NEXT: xxmrgld v2, v3, v2 ; CHECK-P8-NEXT: xxmrgld v2, v3, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs1, 0(r3) ; CHECK-P9-NEXT: lxv vs1, 0(r3)
; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: mffprwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: xxswapd vs2, vs1 ; CHECK-P9-NEXT: xxswapd vs2, vs1
; CHECK-P9-NEXT: mtvsrd v2, r3 ; CHECK-P9-NEXT: mtvsrd v2, r3
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mffprwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: xscvspdpn f2, vs1 ; CHECK-P9-NEXT: xscvspdpn f2, vs1
; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1 ; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1
Show All 31 Lines
; CHECK-P9-NEXT: vmrghh v4, v4, v5 ; CHECK-P9-NEXT: vmrghh v4, v4, v5
; CHECK-P9-NEXT: vmrglw v3, v4, v3 ; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld v2, v3, v2 ; CHECK-P9-NEXT: xxmrgld v2, v3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs1 ; CHECK-BE-NEXT: xxswapd vs2, vs1
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xscvspdpn f2, vs1 ; CHECK-BE-NEXT: xscvspdpn f2, vs1
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0 ; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
▲ Show 20 Lines • Show All 116 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stvx v2, 0, r3 ; CHECK-P8-NEXT: stvx v2, 0, r3
; CHECK-P8-NEXT: xxmrgld v3, v5, v4 ; CHECK-P8-NEXT: xxmrgld v3, v5, v4
; CHECK-P8-NEXT: stvx v3, r3, r5 ; CHECK-P8-NEXT: stvx v3, r3, r5
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs2, 0(r4) ; CHECK-P9-NEXT: lxv vs2, 0(r4)
; CHECK-P9-NEXT: lxv vs1, 16(r4)
; CHECK-P9-NEXT: lxv vs0, 32(r4)
; CHECK-P9-NEXT: xxsldwi vs3, vs2, vs2, 3 ; CHECK-P9-NEXT: xxsldwi vs3, vs2, vs2, 3
; CHECK-P9-NEXT: xxswapd vs4, vs2 ; CHECK-P9-NEXT: xxswapd vs4, vs2
; CHECK-P9-NEXT: xscvspdpn f5, vs2
; CHECK-P9-NEXT: xxsldwi vs2, vs2, vs2, 1
; CHECK-P9-NEXT: xxsldwi vs6, vs1, vs1, 3
; CHECK-P9-NEXT: xscvspdpn f3, vs3 ; CHECK-P9-NEXT: xscvspdpn f3, vs3
; CHECK-P9-NEXT: xscvspdpn f4, vs4 ; CHECK-P9-NEXT: xscvspdpn f4, vs4
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f3, f3 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: xscvdpsxws f4, f4 ; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: xscvspdpn f5, vs2
; CHECK-P9-NEXT: xxsldwi vs2, vs2, vs2, 1
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mffprwz r5, f3 ; CHECK-P9-NEXT: mffprwz r5, f3
; CHECK-P9-NEXT: lxv vs1, 16(r4)
; CHECK-P9-NEXT: xxsldwi vs6, vs1, vs1, 3
; CHECK-P9-NEXT: xxswapd vs3, vs1 ; CHECK-P9-NEXT: xxswapd vs3, vs1
; CHECK-P9-NEXT: mtvsrd v2, r5 ; CHECK-P9-NEXT: mtvsrd v2, r5
; CHECK-P9-NEXT: mffprwz r5, f4 ; CHECK-P9-NEXT: mffprwz r5, f4
; CHECK-P9-NEXT: xscvdpsxws f4, f5 ; CHECK-P9-NEXT: xscvdpsxws f4, f5
; CHECK-P9-NEXT: xscvspdpn f3, vs3 ; CHECK-P9-NEXT: xscvspdpn f3, vs3
; CHECK-P9-NEXT: mtvsrd v3, r5 ; CHECK-P9-NEXT: mtvsrd v3, r5
; CHECK-P9-NEXT: vmrghh v2, v3, v2 ; CHECK-P9-NEXT: vmrghh v2, v3, v2
; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: mffprwz r5, f4 ; CHECK-P9-NEXT: mffprwz r5, f4
; CHECK-P9-NEXT: xscvspdpn f4, vs6 ; CHECK-P9-NEXT: xscvspdpn f4, vs6
; CHECK-P9-NEXT: mtvsrd v3, r5 ; CHECK-P9-NEXT: mtvsrd v3, r5
; CHECK-P9-NEXT: mffprwz r5, f2 ; CHECK-P9-NEXT: mffprwz r5, f2
; CHECK-P9-NEXT: xscvspdpn f2, vs1 ; CHECK-P9-NEXT: xscvspdpn f2, vs1
; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1 ; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-P9-NEXT: xscvdpsxws f4, f4 ; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: lxv vs0, 32(r4)
; CHECK-P9-NEXT: mtvsrd v4, r5 ; CHECK-P9-NEXT: mtvsrd v4, r5
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: vmrghh v3, v3, v4 ; CHECK-P9-NEXT: vmrghh v3, v3, v4
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mffprwz r5, f4 ; CHECK-P9-NEXT: mffprwz r5, f4
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mtvsrd v4, r5 ; CHECK-P9-NEXT: mtvsrd v4, r5
; CHECK-P9-NEXT: mffprwz r5, f3 ; CHECK-P9-NEXT: mffprwz r5, f3
; CHECK-P9-NEXT: xxsldwi vs3, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi vs3, vs0, vs0, 3
; CHECK-P9-NEXT: mtvsrd v5, r5 ; CHECK-P9-NEXT: mtvsrd v5, r5
; CHECK-P9-NEXT: mffprwz r5, f2 ; CHECK-P9-NEXT: mffprwz r5, f2
; CHECK-P9-NEXT: xscvspdpn f2, vs3 ; CHECK-P9-NEXT: xscvspdpn f2, vs3
; CHECK-P9-NEXT: vmrghh v4, v5, v4 ; CHECK-P9-NEXT: vmrghh v4, v5, v4
; CHECK-P9-NEXT: mtvsrd v5, r5 ; CHECK-P9-NEXT: mtvsrd v5, r5
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; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mtvsrd v1, r5 ; CHECK-P9-NEXT: mtvsrd v1, r5
; CHECK-P9-NEXT: vmrghh v0, v1, v0 ; CHECK-P9-NEXT: vmrghh v0, v1, v0
; CHECK-P9-NEXT: mffprwz r4, f2 ; CHECK-P9-NEXT: mffprwz r4, f2
; CHECK-P9-NEXT: xxmrgld vs2, v3, v2 ; CHECK-P9-NEXT: xxmrgld vs2, v3, v2
; CHECK-P9-NEXT: mtvsrd v4, r4 ; CHECK-P9-NEXT: mtvsrd v4, r4
; CHECK-P9-NEXT: mffprwz r4, f0 ; CHECK-P9-NEXT: mffprwz r4, f0
; CHECK-P9-NEXT: xxsldwi vs0, vs1, vs1, 3 ; CHECK-P9-NEXT: xxsldwi vs0, vs1, vs1, 3
; CHECK-P9-NEXT: stxv vs2, 0(r3)
; CHECK-P9-NEXT: mtvsrd v2, r4 ; CHECK-P9-NEXT: mtvsrd v2, r4
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: vmrghh v2, v4, v2 ; CHECK-P9-NEXT: vmrghh v2, v4, v2
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: vmrglw v2, v2, v0 ; CHECK-P9-NEXT: vmrglw v2, v2, v0
; CHECK-P9-NEXT: mffprwz r4, f0 ; CHECK-P9-NEXT: mffprwz r4, f0
; CHECK-P9-NEXT: xxswapd vs0, vs1 ; CHECK-P9-NEXT: xxswapd vs0, vs1
; CHECK-P9-NEXT: mtvsrd v3, r4 ; CHECK-P9-NEXT: mtvsrd v3, r4
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; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r4, f0 ; CHECK-P9-NEXT: mffprwz r4, f0
; CHECK-P9-NEXT: mtvsrd v5, r4 ; CHECK-P9-NEXT: mtvsrd v5, r4
; CHECK-P9-NEXT: vmrghh v4, v4, v5 ; CHECK-P9-NEXT: vmrghh v4, v4, v5
; CHECK-P9-NEXT: vmrglw v3, v4, v3 ; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld vs0, v3, v2 ; CHECK-P9-NEXT: xxmrgld vs0, v3, v2
; CHECK-P9-NEXT: stxv vs0, 16(r3) ; CHECK-P9-NEXT: stxv vs0, 16(r3)
; CHECK-P9-NEXT: stxv vs2, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r4) ; CHECK-BE-NEXT: lxv vs1, 16(r4)
; CHECK-BE-NEXT: lxv vs0, 0(r4)
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xxswapd vs3, vs1 ; CHECK-BE-NEXT: xxswapd vs3, vs1
; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: mffprwz r5, f2
; CHECK-BE-NEXT: xscvspdpn f4, vs1 ; CHECK-BE-NEXT: xscvspdpn f4, vs1
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mffprwz r5, f2
; CHECK-BE-NEXT: xxsldwi vs2, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mtvsrd v2, r5 ; CHECK-BE-NEXT: mtvsrd v2, r5
; CHECK-BE-NEXT: mffprwz r5, f3 ; CHECK-BE-NEXT: mffprwz r5, f3
; CHECK-BE-NEXT: xscvdpsxws f3, f4 ; CHECK-BE-NEXT: xscvdpsxws f3, f4
; CHECK-BE-NEXT: lxv vs0, 0(r4)
; CHECK-BE-NEXT: xxsldwi vs2, vs0, vs0, 3
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mtvsrd v3, r5 ; CHECK-BE-NEXT: mtvsrd v3, r5
; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mffprwz r5, f3 ; CHECK-BE-NEXT: mffprwz r5, f3
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v3, r5 ; CHECK-BE-NEXT: mtvsrd v3, r5
; CHECK-BE-NEXT: mffprwz r5, f1 ; CHECK-BE-NEXT: mffprwz r5, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0 ; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r5 ; CHECK-BE-NEXT: mtvsrd v4, r5
; CHECK-BE-NEXT: mffprwz r5, f2 ; CHECK-BE-NEXT: mffprwz r5, f2
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: vmrghh v3, v3, v4 ; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: mtvsrd v4, r5 ; CHECK-BE-NEXT: mtvsrd v4, r5
Show All 10 Lines
; CHECK-BE-NEXT: mffprwz r5, f1 ; CHECK-BE-NEXT: mffprwz r5, f1
; CHECK-BE-NEXT: lxv vs1, 48(r4) ; CHECK-BE-NEXT: lxv vs1, 48(r4)
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v5, r5 ; CHECK-BE-NEXT: mtvsrd v5, r5
; CHECK-BE-NEXT: mffprwz r5, f0 ; CHECK-BE-NEXT: mffprwz r5, f0
; CHECK-BE-NEXT: lxv vs0, 32(r4) ; CHECK-BE-NEXT: lxv vs0, 32(r4)
; CHECK-BE-NEXT: xscvspdpn f5, vs1 ; CHECK-BE-NEXT: xscvspdpn f5, vs1
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvdpsxws f5, f5
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: xxswapd vs3, vs1 ; CHECK-BE-NEXT: xxswapd vs3, vs1
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: xscvdpsxws f5, f5
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mtvsrd v0, r5 ; CHECK-BE-NEXT: mtvsrd v0, r5
; CHECK-BE-NEXT: vmrghh v5, v5, v0
; CHECK-BE-NEXT: xscvspdpn f3, vs3 ; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: vmrghh v5, v5, v0
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: vmrghw v3, v5, v4
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghw v3, v5, v4
; CHECK-BE-NEXT: mffprwz r4, f5 ; CHECK-BE-NEXT: mffprwz r4, f5
; CHECK-BE-NEXT: xxmrghd vs4, v3, v2 ; CHECK-BE-NEXT: xxmrghd vs4, v3, v2
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v2, r4 ; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: mffprwz r4, f2 ; CHECK-BE-NEXT: mffprwz r4, f2
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: stxv vs4, 0(r3) ; CHECK-BE-NEXT: stxv vs4, 0(r3)
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v3, r4 ; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: mffprwz r4, f3 ; CHECK-BE-NEXT: mffprwz r4, f3
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v4, r4 ; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: mffprwz r4, f1 ; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghh v3, v4, v3 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghh v2, v2, v4 ; CHECK-BE-NEXT: vmrghh v2, v2, v4
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: vmrghw v2, v2, v3 ; CHECK-BE-NEXT: vmrghw v2, v2, v3
; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v3, r4 ; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mffprwz r4, f1 ; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v4, r4 ; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
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llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i8_elts.ll

Show All 31 Lines
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt: ; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xxsldwi vs1, v2, v2, 3 ; CHECK-P9-NEXT: xxsldwi vs1, v2, v2, 3
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd v2, r3 ; CHECK-P9-NEXT: mtvsrd v2, r3
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd v3, r3 ; CHECK-P9-NEXT: mtvsrd v3, r3
; CHECK-P9-NEXT: addi r3, r1, -2 ; CHECK-P9-NEXT: addi r3, r1, -2
; CHECK-P9-NEXT: vmrghb v2, v3, v2 ; CHECK-P9-NEXT: vmrghb v2, v3, v2
; CHECK-P9-NEXT: vsldoi v2, v2, v2, 8 ; CHECK-P9-NEXT: vsldoi v2, v2, v2, 8
; CHECK-P9-NEXT: stxsihx v2, 0, r3 ; CHECK-P9-NEXT: stxsihx v2, 0, r3
▲ Show 20 Lines • Show All 174 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mffprd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs1, 0(r3) ; CHECK-P9-NEXT: lxv vs1, 0(r3)
; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: mffprwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: xxswapd vs2, vs1 ; CHECK-P9-NEXT: xxswapd vs2, vs1
; CHECK-P9-NEXT: mtvsrd v2, r3 ; CHECK-P9-NEXT: mtvsrd v2, r3
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mffprwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: xscvspdpn f2, vs1 ; CHECK-P9-NEXT: xscvspdpn f2, vs1
; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1 ; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1
Show All 32 Lines
; CHECK-P9-NEXT: vmrglh v3, v4, v3 ; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt: ; CHECK-BE-LABEL: test8elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs1 ; CHECK-BE-NEXT: xxswapd vs2, vs1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xscvspdpn f2, vs1 ; CHECK-BE-NEXT: xscvspdpn f2, vs1
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghb v2, v3, v2 ; CHECK-BE-NEXT: vmrghb v2, v3, v2
; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0 ; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: vmrglw v2, v2, v3 ; CHECK-P8-NEXT: vmrglw v2, v2, v3
; CHECK-P8-NEXT: vmrglw v3, v5, v4 ; CHECK-P8-NEXT: vmrglw v3, v5, v4
; CHECK-P8-NEXT: xxmrgld v2, v3, v2 ; CHECK-P8-NEXT: xxmrgld v2, v3, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs3, 0(r3) ; CHECK-P9-NEXT: lxv vs3, 0(r3)
; CHECK-P9-NEXT: xxsldwi vs4, vs3, vs3, 3
; CHECK-P9-NEXT: xscvspdpn f4, vs4
; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: lxv vs0, 48(r3) ; CHECK-P9-NEXT: lxv vs0, 48(r3)
; CHECK-P9-NEXT: lxv vs1, 32(r3) ; CHECK-P9-NEXT: lxv vs1, 32(r3)
; CHECK-P9-NEXT: lxv vs2, 16(r3) ; CHECK-P9-NEXT: lxv vs2, 16(r3)
; CHECK-P9-NEXT: xxsldwi vs4, vs3, vs3, 3
; CHECK-P9-NEXT: xscvspdpn f4, vs4
; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: mffprwz r3, f4 ; CHECK-P9-NEXT: mffprwz r3, f4
; CHECK-P9-NEXT: xxswapd vs4, vs3 ; CHECK-P9-NEXT: xxswapd vs4, vs3
; CHECK-P9-NEXT: mtvsrd v2, r3 ; CHECK-P9-NEXT: mtvsrd v2, r3
; CHECK-P9-NEXT: xscvspdpn f4, vs4 ; CHECK-P9-NEXT: xscvspdpn f4, vs4
; CHECK-P9-NEXT: xscvdpsxws f4, f4 ; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: mffprwz r3, f4 ; CHECK-P9-NEXT: mffprwz r3, f4
; CHECK-P9-NEXT: xscvspdpn f4, vs3 ; CHECK-P9-NEXT: xscvspdpn f4, vs3
; CHECK-P9-NEXT: xxsldwi vs3, vs3, vs3, 1 ; CHECK-P9-NEXT: xxsldwi vs3, vs3, vs3, 1
▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines
; CHECK-P9-NEXT: vmrglh v4, v5, v4 ; CHECK-P9-NEXT: vmrglh v4, v5, v4
; CHECK-P9-NEXT: vmrglw v3, v4, v3 ; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld v2, v3, v2 ; CHECK-P9-NEXT: xxmrgld v2, v3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs3, 48(r3) ; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: xxsldwi vs4, vs3, vs3, 3
; CHECK-BE-NEXT: xscvspdpn f4, vs4
; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3) ; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxsldwi vs4, vs3, vs3, 3
; CHECK-BE-NEXT: xscvspdpn f4, vs4
; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: mffprwz r3, f4 ; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: xxswapd vs4, vs3 ; CHECK-BE-NEXT: xxswapd vs4, vs3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f4, vs4 ; CHECK-BE-NEXT: xscvspdpn f4, vs4
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: xscvdpsxws f4, f4 ; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: mffprwz r3, f4 ; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: xscvspdpn f4, vs3 ; CHECK-BE-NEXT: xscvspdpn f4, vs3
; CHECK-BE-NEXT: xxsldwi vs3, vs3, vs3, 1 ; CHECK-BE-NEXT: xxsldwi vs3, vs3, vs3, 1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f4, f4 ; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: xscvspdpn f3, vs3 ; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: vmrghb v2, v3, v2 ; CHECK-BE-NEXT: vmrghb v2, v3, v2
; CHECK-BE-NEXT: mffprwz r3, f4 ; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mffprwz r3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xxsldwi vs3, vs2, vs2, 3 ; CHECK-BE-NEXT: xxsldwi vs3, vs2, vs2, 3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f3, vs3 ; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mffprwz r3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xxswapd vs3, vs2 ; CHECK-BE-NEXT: xxswapd vs3, vs2
; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: mffprwz r3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xscvspdpn f3, vs2 ; CHECK-BE-NEXT: xscvspdpn f3, vs2
; CHECK-BE-NEXT: xxsldwi vs2, vs2, vs2, 1 ; CHECK-BE-NEXT: xxsldwi vs2, vs2, vs2, 1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: vmrghb v3, v4, v3 ; CHECK-BE-NEXT: vmrghb v3, v4, v3
; CHECK-BE-NEXT: mffprwz r3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mtvsrd v5, r3 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs1
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: vmrghb v4, v4, v5 ; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: vmrghh v3, v4, v3 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xscvspdpn f2, vs1 ; CHECK-BE-NEXT: xscvspdpn f2, vs1
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghb v3, v4, v3 ; CHECK-BE-NEXT: vmrghb v3, v4, v3
; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v5, r3 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0 ; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v3, v4, v3 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v5, r3 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
Show All 38 Lines
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt_signed: ; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xxsldwi vs1, v2, v2, 3 ; CHECK-P9-NEXT: xxsldwi vs1, v2, v2, 3
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd v2, r3 ; CHECK-P9-NEXT: mtvsrd v2, r3
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd v3, r3 ; CHECK-P9-NEXT: mtvsrd v3, r3
; CHECK-P9-NEXT: addi r3, r1, -2 ; CHECK-P9-NEXT: addi r3, r1, -2
; CHECK-P9-NEXT: vmrghb v2, v3, v2 ; CHECK-P9-NEXT: vmrghb v2, v3, v2
; CHECK-P9-NEXT: vsldoi v2, v2, v2, 8 ; CHECK-P9-NEXT: vsldoi v2, v2, v2, 8
; CHECK-P9-NEXT: stxsihx v2, 0, r3 ; CHECK-P9-NEXT: stxsihx v2, 0, r3
▲ Show 20 Lines • Show All 174 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mffprd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs1, 0(r3) ; CHECK-P9-NEXT: lxv vs1, 0(r3)
; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: mffprwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: xxswapd vs2, vs1 ; CHECK-P9-NEXT: xxswapd vs2, vs1
; CHECK-P9-NEXT: mtvsrd v2, r3 ; CHECK-P9-NEXT: mtvsrd v2, r3
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mffprwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: xscvspdpn f2, vs1 ; CHECK-P9-NEXT: xscvspdpn f2, vs1
; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1 ; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1
Show All 32 Lines
; CHECK-P9-NEXT: vmrglh v3, v4, v3 ; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs1 ; CHECK-BE-NEXT: xxswapd vs2, vs1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xscvspdpn f2, vs1 ; CHECK-BE-NEXT: xscvspdpn f2, vs1
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghb v2, v3, v2 ; CHECK-BE-NEXT: vmrghb v2, v3, v2
; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0 ; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: vmrglw v2, v2, v3 ; CHECK-P8-NEXT: vmrglw v2, v2, v3
; CHECK-P8-NEXT: vmrglw v3, v5, v4 ; CHECK-P8-NEXT: vmrglw v3, v5, v4
; CHECK-P8-NEXT: xxmrgld v2, v3, v2 ; CHECK-P8-NEXT: xxmrgld v2, v3, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs3, 0(r3) ; CHECK-P9-NEXT: lxv vs3, 0(r3)
; CHECK-P9-NEXT: xxsldwi vs4, vs3, vs3, 3
; CHECK-P9-NEXT: xscvspdpn f4, vs4
; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: lxv vs0, 48(r3) ; CHECK-P9-NEXT: lxv vs0, 48(r3)
; CHECK-P9-NEXT: lxv vs1, 32(r3) ; CHECK-P9-NEXT: lxv vs1, 32(r3)
; CHECK-P9-NEXT: lxv vs2, 16(r3) ; CHECK-P9-NEXT: lxv vs2, 16(r3)
; CHECK-P9-NEXT: xxsldwi vs4, vs3, vs3, 3
; CHECK-P9-NEXT: xscvspdpn f4, vs4
; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: mffprwz r3, f4 ; CHECK-P9-NEXT: mffprwz r3, f4
; CHECK-P9-NEXT: xxswapd vs4, vs3 ; CHECK-P9-NEXT: xxswapd vs4, vs3
; CHECK-P9-NEXT: mtvsrd v2, r3 ; CHECK-P9-NEXT: mtvsrd v2, r3
; CHECK-P9-NEXT: xscvspdpn f4, vs4 ; CHECK-P9-NEXT: xscvspdpn f4, vs4
; CHECK-P9-NEXT: xscvdpsxws f4, f4 ; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: mffprwz r3, f4 ; CHECK-P9-NEXT: mffprwz r3, f4
; CHECK-P9-NEXT: xscvspdpn f4, vs3 ; CHECK-P9-NEXT: xscvspdpn f4, vs3
; CHECK-P9-NEXT: xxsldwi vs3, vs3, vs3, 1 ; CHECK-P9-NEXT: xxsldwi vs3, vs3, vs3, 1
▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines
; CHECK-P9-NEXT: vmrglh v4, v5, v4 ; CHECK-P9-NEXT: vmrglh v4, v5, v4
; CHECK-P9-NEXT: vmrglw v3, v4, v3 ; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld v2, v3, v2 ; CHECK-P9-NEXT: xxmrgld v2, v3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs3, 48(r3) ; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: xxsldwi vs4, vs3, vs3, 3
; CHECK-BE-NEXT: xscvspdpn f4, vs4
; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3) ; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxsldwi vs4, vs3, vs3, 3
; CHECK-BE-NEXT: xscvspdpn f4, vs4
; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: mffprwz r3, f4 ; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: xxswapd vs4, vs3 ; CHECK-BE-NEXT: xxswapd vs4, vs3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f4, vs4 ; CHECK-BE-NEXT: xscvspdpn f4, vs4
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: xscvdpsxws f4, f4 ; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: mffprwz r3, f4 ; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: xscvspdpn f4, vs3 ; CHECK-BE-NEXT: xscvspdpn f4, vs3
; CHECK-BE-NEXT: xxsldwi vs3, vs3, vs3, 1 ; CHECK-BE-NEXT: xxsldwi vs3, vs3, vs3, 1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f4, f4 ; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: xscvspdpn f3, vs3 ; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: vmrghb v2, v3, v2 ; CHECK-BE-NEXT: vmrghb v2, v3, v2
; CHECK-BE-NEXT: mffprwz r3, f4 ; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mffprwz r3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xxsldwi vs3, vs2, vs2, 3 ; CHECK-BE-NEXT: xxsldwi vs3, vs2, vs2, 3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f3, vs3 ; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mffprwz r3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xxswapd vs3, vs2 ; CHECK-BE-NEXT: xxswapd vs3, vs2
; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: mffprwz r3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xscvspdpn f3, vs2 ; CHECK-BE-NEXT: xscvspdpn f3, vs2
; CHECK-BE-NEXT: xxsldwi vs2, vs2, vs2, 1 ; CHECK-BE-NEXT: xxsldwi vs2, vs2, vs2, 1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: vmrghb v3, v4, v3 ; CHECK-BE-NEXT: vmrghb v3, v4, v3
; CHECK-BE-NEXT: mffprwz r3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mtvsrd v5, r3 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs1
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: vmrghb v4, v4, v5 ; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: vmrghh v3, v4, v3 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xscvspdpn f2, vs1 ; CHECK-BE-NEXT: xscvspdpn f2, vs1
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghb v3, v4, v3 ; CHECK-BE-NEXT: vmrghb v3, v4, v3
; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v5, r3 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0 ; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v3, v4, v3 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v5, r3 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
Show All 17 Lines

llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll

Show First 20 Lines • Show All 83 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mffprd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt: ; CHECK-P9-LABEL: test4elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs1, 0(r3) ; CHECK-P9-NEXT: lxv vs1, 0(r3)
; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: xscvdpsxws f2, f1 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: xxswapd vs1, vs1 ; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: mffprwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd v2, r3 ; CHECK-P9-NEXT: mtvsrd v2, r3
; CHECK-P9-NEXT: mffprwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: xscvdpsxws f1, f0 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0 ; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: mtvsrd v3, r3 ; CHECK-P9-NEXT: mtvsrd v3, r3
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: vmrghh v2, v2, v3 ; CHECK-P9-NEXT: vmrghh v2, v2, v3
; CHECK-P9-NEXT: mffprwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd v3, r3 ; CHECK-P9-NEXT: mtvsrd v3, r3
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd v4, r3 ; CHECK-P9-NEXT: mtvsrd v4, r3
; CHECK-P9-NEXT: vmrghh v3, v3, v4 ; CHECK-P9-NEXT: vmrghh v3, v3, v4
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt: ; CHECK-BE-LABEL: test4elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: xscvdpsxws f2, f1 ; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1 ; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0 ; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0 ; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: vmrglw v3, v5, v4 ; CHECK-P8-NEXT: vmrglw v3, v5, v4
; CHECK-P8-NEXT: xxmrgld v2, v3, v2 ; CHECK-P8-NEXT: xxmrgld v2, v3, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs3, 0(r3) ; CHECK-P9-NEXT: lxv vs3, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f4, f3
; CHECK-P9-NEXT: xxswapd vs3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: lxv vs2, 16(r3) ; CHECK-P9-NEXT: lxv vs2, 16(r3)
; CHECK-P9-NEXT: lxv vs0, 48(r3) ; CHECK-P9-NEXT: lxv vs0, 48(r3)
; CHECK-P9-NEXT: lxv vs1, 32(r3) ; CHECK-P9-NEXT: lxv vs1, 32(r3)
; CHECK-P9-NEXT: xscvdpsxws f4, f3
; CHECK-P9-NEXT: xxswapd vs3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: mffprwz r3, f4 ; CHECK-P9-NEXT: mffprwz r3, f4
; CHECK-P9-NEXT: mtvsrd v2, r3 ; CHECK-P9-NEXT: mtvsrd v2, r3
; CHECK-P9-NEXT: mffprwz r3, f3 ; CHECK-P9-NEXT: mffprwz r3, f3
; CHECK-P9-NEXT: xscvdpsxws f3, f2 ; CHECK-P9-NEXT: xscvdpsxws f3, f2
; CHECK-P9-NEXT: xxswapd vs2, vs2 ; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: mtvsrd v3, r3 ; CHECK-P9-NEXT: mtvsrd v3, r3
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: vmrghh v2, v2, v3 ; CHECK-P9-NEXT: vmrghh v2, v2, v3
Show All 21 Lines
; CHECK-P9-NEXT: vmrghh v4, v4, v5 ; CHECK-P9-NEXT: vmrghh v4, v4, v5
; CHECK-P9-NEXT: vmrglw v3, v4, v3 ; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld v2, v3, v2 ; CHECK-P9-NEXT: xxmrgld v2, v3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt: ; CHECK-BE-LABEL: test8elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs3, 48(r3) ; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: xscvdpsxws f4, f3
; CHECK-BE-NEXT: xxswapd vs3, vs3
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: lxv vs2, 32(r3) ; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: xscvdpsxws f4, f3
; CHECK-BE-NEXT: xxswapd vs3, vs3
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: mffprwz r3, f4 ; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mffprwz r3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xscvdpsxws f3, f2 ; CHECK-BE-NEXT: xscvdpsxws f3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs2 ; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
▲ Show 20 Lines • Show All 128 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stvx v3, r3, r5 ; CHECK-P8-NEXT: stvx v3, r3, r5
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs3, 0(r4) ; CHECK-P9-NEXT: lxv vs3, 0(r4)
; CHECK-P9-NEXT: lxv vs2, 16(r4) ; CHECK-P9-NEXT: lxv vs2, 16(r4)
; CHECK-P9-NEXT: lxv vs1, 32(r4) ; CHECK-P9-NEXT: lxv vs1, 32(r4)
; CHECK-P9-NEXT: xscvdpsxws f4, f3
; CHECK-P9-NEXT: lxv vs0, 48(r4) ; CHECK-P9-NEXT: lxv vs0, 48(r4)
; CHECK-P9-NEXT: xscvdpsxws f4, f3
; CHECK-P9-NEXT: xscvdpsxws f5, f2 ; CHECK-P9-NEXT: xscvdpsxws f5, f2
; CHECK-P9-NEXT: xscvdpsxws f6, f1 ; CHECK-P9-NEXT: xscvdpsxws f6, f1
; CHECK-P9-NEXT: xxswapd vs3, vs3 ; CHECK-P9-NEXT: xxswapd vs3, vs3
; CHECK-P9-NEXT: xscvdpsxws f7, f0 ; CHECK-P9-NEXT: xscvdpsxws f7, f0
; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xxswapd vs0, vs0 ; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r5, f4
; CHECK-P9-NEXT: xscvdpsxws f3, f3 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r5, f4
; CHECK-P9-NEXT: mtvsrd v2, r5 ; CHECK-P9-NEXT: mtvsrd v2, r5
; CHECK-P9-NEXT: mffprwz r5, f5 ; CHECK-P9-NEXT: mffprwz r5, f5
; CHECK-P9-NEXT: mtvsrd v3, r5 ; CHECK-P9-NEXT: mtvsrd v3, r5
; CHECK-P9-NEXT: mffprwz r5, f6 ; CHECK-P9-NEXT: mffprwz r5, f6
; CHECK-P9-NEXT: mtvsrd v4, r5 ; CHECK-P9-NEXT: mtvsrd v4, r5
; CHECK-P9-NEXT: mffprwz r5, f7 ; CHECK-P9-NEXT: mffprwz r5, f7
; CHECK-P9-NEXT: mtvsrd v5, r5 ; CHECK-P9-NEXT: mtvsrd v5, r5
; CHECK-P9-NEXT: mffprwz r5, f3 ; CHECK-P9-NEXT: mffprwz r5, f3
; CHECK-P9-NEXT: lxv vs3, 64(r4) ; CHECK-P9-NEXT: lxv vs3, 64(r4)
; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mtvsrd v0, r5 ; CHECK-P9-NEXT: mtvsrd v0, r5
; CHECK-P9-NEXT: mffprwz r5, f2 ; CHECK-P9-NEXT: mffprwz r5, f2
; CHECK-P9-NEXT: lxv vs2, 80(r4) ; CHECK-P9-NEXT: lxv vs2, 80(r4)
; CHECK-P9-NEXT: vmrghh v2, v2, v0 ; CHECK-P9-NEXT: vmrghh v2, v2, v0
; CHECK-P9-NEXT: mtvsrd v0, r5 ; CHECK-P9-NEXT: mtvsrd v0, r5
; CHECK-P9-NEXT: mffprwz r5, f1 ; CHECK-P9-NEXT: mffprwz r5, f1
; CHECK-P9-NEXT: lxv vs1, 96(r4) ; CHECK-P9-NEXT: lxv vs1, 96(r4)
; CHECK-P9-NEXT: xscvdpsxws f4, f3 ; CHECK-P9-NEXT: xscvdpsxws f4, f3
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; CHECK-P9-NEXT: vmrglw v3, v4, v3 ; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld vs0, v3, v2 ; CHECK-P9-NEXT: xxmrgld vs0, v3, v2
; CHECK-P9-NEXT: stxv vs0, 16(r3) ; CHECK-P9-NEXT: stxv vs0, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs4, 48(r4) ; CHECK-BE-NEXT: lxv vs4, 48(r4)
; CHECK-BE-NEXT: lxv vs3, 32(r4)
; CHECK-BE-NEXT: lxv vs2, 16(r4)
; CHECK-BE-NEXT: lxv vs1, 0(r4)
; CHECK-BE-NEXT: xscvdpsxws f5, f4 ; CHECK-BE-NEXT: xscvdpsxws f5, f4
; CHECK-BE-NEXT: xxswapd vs4, vs4 ; CHECK-BE-NEXT: xxswapd vs4, vs4
; CHECK-BE-NEXT: lxv vs3, 32(r4)
; CHECK-BE-NEXT: xscvdpsxws f6, f3 ; CHECK-BE-NEXT: xscvdpsxws f6, f3
; CHECK-BE-NEXT: xxswapd vs3, vs3 ; CHECK-BE-NEXT: xxswapd vs3, vs3
; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: mffprwz r5, f5
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: lxv vs2, 16(r4)
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: xscvdpsxws f7, f2 ; CHECK-BE-NEXT: xscvdpsxws f7, f2
; CHECK-BE-NEXT: lxv vs0, 112(r4)
; CHECK-BE-NEXT: xxswapd vs2, vs2 ; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mffprwz r5, f5
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v2, r5 ; CHECK-BE-NEXT: mtvsrd v2, r5
; CHECK-BE-NEXT: mffprwz r5, f4 ; CHECK-BE-NEXT: mffprwz r5, f4
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: lxv vs1, 0(r4)
; CHECK-BE-NEXT: xscvdpsxws f4, f1 ; CHECK-BE-NEXT: xscvdpsxws f4, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1 ; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v3, r5 ; CHECK-BE-NEXT: mtvsrd v3, r5
; CHECK-BE-NEXT: mffprwz r5, f6 ; CHECK-BE-NEXT: mffprwz r5, f6
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: lxv vs0, 112(r4)
; CHECK-BE-NEXT: vmrghh v2, v2, v3 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
; CHECK-BE-NEXT: mtvsrd v3, r5 ; CHECK-BE-NEXT: mtvsrd v3, r5
; CHECK-BE-NEXT: mffprwz r5, f3 ; CHECK-BE-NEXT: mffprwz r5, f3
; CHECK-BE-NEXT: xscvdpsxws f3, f0 ; CHECK-BE-NEXT: xscvdpsxws f3, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0 ; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r5 ; CHECK-BE-NEXT: mtvsrd v4, r5
Show All 15 Lines
; CHECK-BE-NEXT: mffprwz r5, f1 ; CHECK-BE-NEXT: mffprwz r5, f1
; CHECK-BE-NEXT: lxv vs1, 80(r4) ; CHECK-BE-NEXT: lxv vs1, 80(r4)
; CHECK-BE-NEXT: xscvdpsxws f3, f2 ; CHECK-BE-NEXT: xscvdpsxws f3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs2 ; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: vmrghh v4, v4, v1 ; CHECK-BE-NEXT: vmrghh v4, v4, v1
; CHECK-BE-NEXT: mtvsrd v1, r5 ; CHECK-BE-NEXT: mtvsrd v1, r5
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: vmrghh v5, v5, v1
; CHECK-BE-NEXT: mffprwz r5, f0 ; CHECK-BE-NEXT: mffprwz r5, f0
; CHECK-BE-NEXT: lxv vs0, 64(r4) ; CHECK-BE-NEXT: lxv vs0, 64(r4)
; CHECK-BE-NEXT: vmrghh v5, v5, v1
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mffprwz r4, f3 ; CHECK-BE-NEXT: mffprwz r4, f3
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: mtvsrd v1, r5
; CHECK-BE-NEXT: vmrghw v3, v5, v4 ; CHECK-BE-NEXT: vmrghw v3, v5, v4
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: vmrghh v0, v0, v1
; CHECK-BE-NEXT: xxmrghd vs3, v3, v2 ; CHECK-BE-NEXT: xxmrghd vs3, v3, v2
; CHECK-BE-NEXT: mtvsrd v2, r4 ; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: mffprwz r4, f2 ; CHECK-BE-NEXT: mffprwz r4, f2
; CHECK-BE-NEXT: xscvdpsxws f2, f1 ; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1 ; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: stxv vs3, 0(r3)
; CHECK-BE-NEXT: mtvsrd v3, r4 ; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: vmrghh v2, v2, v3 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
; CHECK-BE-NEXT: mffprwz r4, f2 ; CHECK-BE-NEXT: mffprwz r4, f2
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: vmrghw v2, v2, v0
; CHECK-BE-NEXT: mtvsrd v3, r4 ; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: mffprwz r4, f1 ; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0 ; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0 ; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r4 ; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: vmrghh v3, v3, v4 ; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: mffprwz r4, f1 ; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v4, r4 ; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: mffprwz r4, f0 ; CHECK-BE-NEXT: mffprwz r4, f0
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v1, r5
; CHECK-BE-NEXT: vmrghh v0, v0, v1
; CHECK-BE-NEXT: vmrghw v2, v2, v0
; CHECK-BE-NEXT: stxv vs3, 0(r3)
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v5, r4 ; CHECK-BE-NEXT: mtvsrd v5, r4
; CHECK-BE-NEXT: vmrghh v4, v4, v5 ; CHECK-BE-NEXT: vmrghh v4, v4, v5
; CHECK-BE-NEXT: vmrghw v3, v4, v3 ; CHECK-BE-NEXT: vmrghw v3, v4, v3
; CHECK-BE-NEXT: xxmrghd vs0, v3, v2 ; CHECK-BE-NEXT: xxmrghd vs0, v3, v2
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mffprd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt_signed: ; CHECK-P9-LABEL: test4elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs1, 0(r3) ; CHECK-P9-NEXT: lxv vs1, 0(r3)
; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: xscvdpsxws f2, f1 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: xxswapd vs1, vs1 ; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: mffprwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd v2, r3 ; CHECK-P9-NEXT: mtvsrd v2, r3
; CHECK-P9-NEXT: mffprwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: xscvdpsxws f1, f0 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0 ; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: mtvsrd v3, r3 ; CHECK-P9-NEXT: mtvsrd v3, r3
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: vmrghh v2, v2, v3 ; CHECK-P9-NEXT: vmrghh v2, v2, v3
; CHECK-P9-NEXT: mffprwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd v3, r3 ; CHECK-P9-NEXT: mtvsrd v3, r3
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd v4, r3 ; CHECK-P9-NEXT: mtvsrd v4, r3
; CHECK-P9-NEXT: vmrghh v3, v3, v4 ; CHECK-P9-NEXT: vmrghh v3, v3, v4
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt_signed: ; CHECK-BE-LABEL: test4elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: xscvdpsxws f2, f1 ; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1 ; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0 ; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0 ; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: vmrglw v3, v5, v4 ; CHECK-P8-NEXT: vmrglw v3, v5, v4
; CHECK-P8-NEXT: xxmrgld v2, v3, v2 ; CHECK-P8-NEXT: xxmrgld v2, v3, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs3, 0(r3) ; CHECK-P9-NEXT: lxv vs3, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f4, f3
; CHECK-P9-NEXT: xxswapd vs3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: lxv vs2, 16(r3) ; CHECK-P9-NEXT: lxv vs2, 16(r3)
; CHECK-P9-NEXT: lxv vs0, 48(r3) ; CHECK-P9-NEXT: lxv vs0, 48(r3)
; CHECK-P9-NEXT: lxv vs1, 32(r3) ; CHECK-P9-NEXT: lxv vs1, 32(r3)
; CHECK-P9-NEXT: xscvdpsxws f4, f3
; CHECK-P9-NEXT: xxswapd vs3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: mffprwz r3, f4 ; CHECK-P9-NEXT: mffprwz r3, f4
; CHECK-P9-NEXT: mtvsrd v2, r3 ; CHECK-P9-NEXT: mtvsrd v2, r3
; CHECK-P9-NEXT: mffprwz r3, f3 ; CHECK-P9-NEXT: mffprwz r3, f3
; CHECK-P9-NEXT: xscvdpsxws f3, f2 ; CHECK-P9-NEXT: xscvdpsxws f3, f2
; CHECK-P9-NEXT: xxswapd vs2, vs2 ; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: mtvsrd v3, r3 ; CHECK-P9-NEXT: mtvsrd v3, r3
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: vmrghh v2, v2, v3 ; CHECK-P9-NEXT: vmrghh v2, v2, v3
Show All 21 Lines
; CHECK-P9-NEXT: vmrghh v4, v4, v5 ; CHECK-P9-NEXT: vmrghh v4, v4, v5
; CHECK-P9-NEXT: vmrglw v3, v4, v3 ; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld v2, v3, v2 ; CHECK-P9-NEXT: xxmrgld v2, v3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs3, 48(r3) ; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: xscvdpsxws f4, f3
; CHECK-BE-NEXT: xxswapd vs3, vs3
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: lxv vs2, 32(r3) ; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: xscvdpsxws f4, f3
; CHECK-BE-NEXT: xxswapd vs3, vs3
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: mffprwz r3, f4 ; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mffprwz r3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xscvdpsxws f3, f2 ; CHECK-BE-NEXT: xscvdpsxws f3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs2 ; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
▲ Show 20 Lines • Show All 128 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stvx v3, r3, r5 ; CHECK-P8-NEXT: stvx v3, r3, r5
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs3, 0(r4) ; CHECK-P9-NEXT: lxv vs3, 0(r4)
; CHECK-P9-NEXT: lxv vs2, 16(r4) ; CHECK-P9-NEXT: lxv vs2, 16(r4)
; CHECK-P9-NEXT: lxv vs1, 32(r4) ; CHECK-P9-NEXT: lxv vs1, 32(r4)
; CHECK-P9-NEXT: xscvdpsxws f4, f3
; CHECK-P9-NEXT: lxv vs0, 48(r4) ; CHECK-P9-NEXT: lxv vs0, 48(r4)
; CHECK-P9-NEXT: xscvdpsxws f4, f3
; CHECK-P9-NEXT: xscvdpsxws f5, f2 ; CHECK-P9-NEXT: xscvdpsxws f5, f2
; CHECK-P9-NEXT: xscvdpsxws f6, f1 ; CHECK-P9-NEXT: xscvdpsxws f6, f1
; CHECK-P9-NEXT: xxswapd vs3, vs3 ; CHECK-P9-NEXT: xxswapd vs3, vs3
; CHECK-P9-NEXT: xscvdpsxws f7, f0 ; CHECK-P9-NEXT: xscvdpsxws f7, f0
; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xxswapd vs0, vs0 ; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r5, f4
; CHECK-P9-NEXT: xscvdpsxws f3, f3 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r5, f4
; CHECK-P9-NEXT: mtvsrd v2, r5 ; CHECK-P9-NEXT: mtvsrd v2, r5
; CHECK-P9-NEXT: mffprwz r5, f5 ; CHECK-P9-NEXT: mffprwz r5, f5
; CHECK-P9-NEXT: mtvsrd v3, r5 ; CHECK-P9-NEXT: mtvsrd v3, r5
; CHECK-P9-NEXT: mffprwz r5, f6 ; CHECK-P9-NEXT: mffprwz r5, f6
; CHECK-P9-NEXT: mtvsrd v4, r5 ; CHECK-P9-NEXT: mtvsrd v4, r5
; CHECK-P9-NEXT: mffprwz r5, f7 ; CHECK-P9-NEXT: mffprwz r5, f7
; CHECK-P9-NEXT: mtvsrd v5, r5 ; CHECK-P9-NEXT: mtvsrd v5, r5
; CHECK-P9-NEXT: mffprwz r5, f3 ; CHECK-P9-NEXT: mffprwz r5, f3
; CHECK-P9-NEXT: lxv vs3, 64(r4) ; CHECK-P9-NEXT: lxv vs3, 64(r4)
; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mtvsrd v0, r5 ; CHECK-P9-NEXT: mtvsrd v0, r5
; CHECK-P9-NEXT: mffprwz r5, f2 ; CHECK-P9-NEXT: mffprwz r5, f2
; CHECK-P9-NEXT: lxv vs2, 80(r4) ; CHECK-P9-NEXT: lxv vs2, 80(r4)
; CHECK-P9-NEXT: vmrghh v2, v2, v0 ; CHECK-P9-NEXT: vmrghh v2, v2, v0
; CHECK-P9-NEXT: mtvsrd v0, r5 ; CHECK-P9-NEXT: mtvsrd v0, r5
; CHECK-P9-NEXT: mffprwz r5, f1 ; CHECK-P9-NEXT: mffprwz r5, f1
; CHECK-P9-NEXT: lxv vs1, 96(r4) ; CHECK-P9-NEXT: lxv vs1, 96(r4)
; CHECK-P9-NEXT: xscvdpsxws f4, f3 ; CHECK-P9-NEXT: xscvdpsxws f4, f3
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK-P9-NEXT: vmrglw v3, v4, v3 ; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld vs0, v3, v2 ; CHECK-P9-NEXT: xxmrgld vs0, v3, v2
; CHECK-P9-NEXT: stxv vs0, 16(r3) ; CHECK-P9-NEXT: stxv vs0, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs4, 48(r4) ; CHECK-BE-NEXT: lxv vs4, 48(r4)
; CHECK-BE-NEXT: lxv vs3, 32(r4)
; CHECK-BE-NEXT: lxv vs2, 16(r4)
; CHECK-BE-NEXT: lxv vs1, 0(r4)
; CHECK-BE-NEXT: xscvdpsxws f5, f4 ; CHECK-BE-NEXT: xscvdpsxws f5, f4
; CHECK-BE-NEXT: xxswapd vs4, vs4 ; CHECK-BE-NEXT: xxswapd vs4, vs4
; CHECK-BE-NEXT: lxv vs3, 32(r4)
; CHECK-BE-NEXT: xscvdpsxws f6, f3 ; CHECK-BE-NEXT: xscvdpsxws f6, f3
; CHECK-BE-NEXT: xxswapd vs3, vs3 ; CHECK-BE-NEXT: xxswapd vs3, vs3
; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: mffprwz r5, f5
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: lxv vs2, 16(r4)
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: xscvdpsxws f7, f2 ; CHECK-BE-NEXT: xscvdpsxws f7, f2
; CHECK-BE-NEXT: lxv vs0, 112(r4)
; CHECK-BE-NEXT: xxswapd vs2, vs2 ; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mffprwz r5, f5
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v2, r5 ; CHECK-BE-NEXT: mtvsrd v2, r5
; CHECK-BE-NEXT: mffprwz r5, f4 ; CHECK-BE-NEXT: mffprwz r5, f4
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: lxv vs1, 0(r4)
; CHECK-BE-NEXT: xscvdpsxws f4, f1 ; CHECK-BE-NEXT: xscvdpsxws f4, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1 ; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v3, r5 ; CHECK-BE-NEXT: mtvsrd v3, r5
; CHECK-BE-NEXT: mffprwz r5, f6 ; CHECK-BE-NEXT: mffprwz r5, f6
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: lxv vs0, 112(r4)
; CHECK-BE-NEXT: vmrghh v2, v2, v3 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
; CHECK-BE-NEXT: mtvsrd v3, r5 ; CHECK-BE-NEXT: mtvsrd v3, r5
; CHECK-BE-NEXT: mffprwz r5, f3 ; CHECK-BE-NEXT: mffprwz r5, f3
; CHECK-BE-NEXT: xscvdpsxws f3, f0 ; CHECK-BE-NEXT: xscvdpsxws f3, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0 ; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r5 ; CHECK-BE-NEXT: mtvsrd v4, r5
Show All 15 Lines
; CHECK-BE-NEXT: mffprwz r5, f1 ; CHECK-BE-NEXT: mffprwz r5, f1
; CHECK-BE-NEXT: lxv vs1, 80(r4) ; CHECK-BE-NEXT: lxv vs1, 80(r4)
; CHECK-BE-NEXT: xscvdpsxws f3, f2 ; CHECK-BE-NEXT: xscvdpsxws f3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs2 ; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: vmrghh v4, v4, v1 ; CHECK-BE-NEXT: vmrghh v4, v4, v1
; CHECK-BE-NEXT: mtvsrd v1, r5 ; CHECK-BE-NEXT: mtvsrd v1, r5
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: vmrghh v5, v5, v1
; CHECK-BE-NEXT: mffprwz r5, f0 ; CHECK-BE-NEXT: mffprwz r5, f0
; CHECK-BE-NEXT: lxv vs0, 64(r4) ; CHECK-BE-NEXT: lxv vs0, 64(r4)
; CHECK-BE-NEXT: vmrghh v5, v5, v1
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mffprwz r4, f3 ; CHECK-BE-NEXT: mffprwz r4, f3
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: mtvsrd v1, r5
; CHECK-BE-NEXT: vmrghw v3, v5, v4 ; CHECK-BE-NEXT: vmrghw v3, v5, v4
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: vmrghh v0, v0, v1
; CHECK-BE-NEXT: xxmrghd vs3, v3, v2 ; CHECK-BE-NEXT: xxmrghd vs3, v3, v2
; CHECK-BE-NEXT: mtvsrd v2, r4 ; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: mffprwz r4, f2 ; CHECK-BE-NEXT: mffprwz r4, f2
; CHECK-BE-NEXT: xscvdpsxws f2, f1 ; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1 ; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: stxv vs3, 0(r3)
; CHECK-BE-NEXT: mtvsrd v3, r4 ; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: vmrghh v2, v2, v3 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
; CHECK-BE-NEXT: mffprwz r4, f2 ; CHECK-BE-NEXT: mffprwz r4, f2
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: vmrghw v2, v2, v0
; CHECK-BE-NEXT: mtvsrd v3, r4 ; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: mffprwz r4, f1 ; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0 ; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0 ; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r4 ; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: vmrghh v3, v3, v4 ; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: mffprwz r4, f1 ; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v4, r4 ; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: mffprwz r4, f0 ; CHECK-BE-NEXT: mffprwz r4, f0
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v1, r5
; CHECK-BE-NEXT: vmrghh v0, v0, v1
; CHECK-BE-NEXT: vmrghw v2, v2, v0
; CHECK-BE-NEXT: stxv vs3, 0(r3)
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v5, r4 ; CHECK-BE-NEXT: mtvsrd v5, r4
; CHECK-BE-NEXT: vmrghh v4, v4, v5 ; CHECK-BE-NEXT: vmrghh v4, v4, v5
; CHECK-BE-NEXT: vmrghw v3, v4, v3 ; CHECK-BE-NEXT: vmrghw v3, v4, v3
; CHECK-BE-NEXT: xxmrghd vs0, v3, v2 ; CHECK-BE-NEXT: xxmrghd vs0, v3, v2
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x double>, <16 x double>* %0, align 128 %a = load <16 x double>, <16 x double>* %0, align 128
%1 = fptosi <16 x double> %a to <16 x i16> %1 = fptosi <16 x double> %a to <16 x i16>
store <16 x i16> %1, <16 x i16>* %agg.result, align 32 store <16 x i16> %1, <16 x i16>* %agg.result, align 32
ret void ret void
} }

llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll

Show First 20 Lines • Show All 123 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stvx v2, r3, r5 ; CHECK-P8-NEXT: stvx v2, r3, r5
; CHECK-P8-NEXT: stvx v3, 0, r3 ; CHECK-P8-NEXT: stvx v3, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs2, 0(r4) ; CHECK-P9-NEXT: lxv vs2, 0(r4)
; CHECK-P9-NEXT: lxv vs3, 16(r4) ; CHECK-P9-NEXT: lxv vs3, 16(r4)
; CHECK-P9-NEXT: xxmrgld vs4, vs3, vs2
; CHECK-P9-NEXT: xxmrghd vs2, vs3, vs2
; CHECK-P9-NEXT: lxv vs0, 32(r4) ; CHECK-P9-NEXT: lxv vs0, 32(r4)
; CHECK-P9-NEXT: lxv vs1, 48(r4) ; CHECK-P9-NEXT: lxv vs1, 48(r4)
; CHECK-P9-NEXT: xxmrgld vs4, vs3, vs2
; CHECK-P9-NEXT: xxmrghd vs2, vs3, vs2
; CHECK-P9-NEXT: xvcvdpuxws v2, vs4 ; CHECK-P9-NEXT: xvcvdpuxws v2, vs4
; CHECK-P9-NEXT: xvcvdpuxws v3, vs2 ; CHECK-P9-NEXT: xvcvdpuxws v3, vs2
; CHECK-P9-NEXT: xxmrgld vs2, vs1, vs0 ; CHECK-P9-NEXT: xxmrgld vs2, vs1, vs0
; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0 ; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-P9-NEXT: xvcvdpuxws v4, vs0 ; CHECK-P9-NEXT: xvcvdpuxws v4, vs0
; CHECK-P9-NEXT: vmrgew v2, v3, v2 ; CHECK-P9-NEXT: vmrgew v2, v3, v2
; CHECK-P9-NEXT: xvcvdpuxws v3, vs2 ; CHECK-P9-NEXT: xvcvdpuxws v3, vs2
; CHECK-P9-NEXT: stxv v2, 0(r3) ; CHECK-P9-NEXT: stxv v2, 0(r3)
; CHECK-P9-NEXT: vmrgew v3, v4, v3 ; CHECK-P9-NEXT: vmrgew v3, v4, v3
; CHECK-P9-NEXT: stxv v3, 16(r3) ; CHECK-P9-NEXT: stxv v3, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt: ; CHECK-BE-LABEL: test8elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs2, 16(r4) ; CHECK-BE-NEXT: lxv vs2, 16(r4)
; CHECK-BE-NEXT: lxv vs3, 0(r4) ; CHECK-BE-NEXT: lxv vs3, 0(r4)
; CHECK-BE-NEXT: xxmrgld vs4, vs3, vs2
; CHECK-BE-NEXT: xxmrghd vs2, vs3, vs2
; CHECK-BE-NEXT: lxv vs0, 48(r4) ; CHECK-BE-NEXT: lxv vs0, 48(r4)
; CHECK-BE-NEXT: lxv vs1, 32(r4) ; CHECK-BE-NEXT: lxv vs1, 32(r4)
; CHECK-BE-NEXT: xxmrgld vs4, vs3, vs2
; CHECK-BE-NEXT: xxmrghd vs2, vs3, vs2
; CHECK-BE-NEXT: xvcvdpuxws v2, vs4 ; CHECK-BE-NEXT: xvcvdpuxws v2, vs4
; CHECK-BE-NEXT: xvcvdpuxws v3, vs2 ; CHECK-BE-NEXT: xvcvdpuxws v3, vs2
; CHECK-BE-NEXT: xxmrgld vs2, vs1, vs0 ; CHECK-BE-NEXT: xxmrgld vs2, vs1, vs0
; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0 ; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-BE-NEXT: xvcvdpuxws v4, vs0 ; CHECK-BE-NEXT: xvcvdpuxws v4, vs0
; CHECK-BE-NEXT: vmrgew v2, v3, v2 ; CHECK-BE-NEXT: vmrgew v2, v3, v2
; CHECK-BE-NEXT: xvcvdpuxws v3, vs2 ; CHECK-BE-NEXT: xvcvdpuxws v3, vs2
; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: stxv v2, 0(r3)
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stvx v4, r3, r6 ; CHECK-P8-NEXT: stvx v4, r3, r6
; CHECK-P8-NEXT: stvx v5, 0, r3 ; CHECK-P8-NEXT: stvx v5, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs6, 0(r4) ; CHECK-P9-NEXT: lxv vs6, 0(r4)
; CHECK-P9-NEXT: lxv vs7, 16(r4) ; CHECK-P9-NEXT: lxv vs7, 16(r4)
; CHECK-P9-NEXT: xxmrgld vs8, vs7, vs6
; CHECK-P9-NEXT: xxmrghd vs6, vs7, vs6
; CHECK-P9-NEXT: lxv vs4, 32(r4) ; CHECK-P9-NEXT: lxv vs4, 32(r4)
; CHECK-P9-NEXT: lxv vs5, 48(r4) ; CHECK-P9-NEXT: lxv vs5, 48(r4)
; CHECK-P9-NEXT: xxmrgld vs8, vs7, vs6
; CHECK-P9-NEXT: xxmrghd vs6, vs7, vs6
; CHECK-P9-NEXT: xxmrgld vs7, vs5, vs4 ; CHECK-P9-NEXT: xxmrgld vs7, vs5, vs4
; CHECK-P9-NEXT: xxmrghd vs4, vs5, vs4 ; CHECK-P9-NEXT: xxmrghd vs4, vs5, vs4
; CHECK-P9-NEXT: xvcvdpuxws v2, vs8
; CHECK-P9-NEXT: xvcvdpuxws v3, vs6
; CHECK-P9-NEXT: lxv vs2, 64(r4) ; CHECK-P9-NEXT: lxv vs2, 64(r4)
; CHECK-P9-NEXT: lxv vs3, 80(r4) ; CHECK-P9-NEXT: lxv vs3, 80(r4)
; CHECK-P9-NEXT: lxv vs0, 96(r4)
; CHECK-P9-NEXT: lxv vs1, 112(r4)
; CHECK-P9-NEXT: xvcvdpuxws v2, vs8
; CHECK-P9-NEXT: xvcvdpuxws v3, vs6
; CHECK-P9-NEXT: xvcvdpuxws v4, vs7 ; CHECK-P9-NEXT: xvcvdpuxws v4, vs7
; CHECK-P9-NEXT: vmrgew v2, v3, v2 ; CHECK-P9-NEXT: vmrgew v2, v3, v2
; CHECK-P9-NEXT: xvcvdpuxws v3, vs4 ; CHECK-P9-NEXT: xvcvdpuxws v3, vs4
; CHECK-P9-NEXT: xxmrgld vs4, vs3, vs2 ; CHECK-P9-NEXT: xxmrgld vs4, vs3, vs2
; CHECK-P9-NEXT: xxmrghd vs2, vs3, vs2 ; CHECK-P9-NEXT: xxmrghd vs2, vs3, vs2
; CHECK-P9-NEXT: lxv vs0, 96(r4)
; CHECK-P9-NEXT: lxv vs1, 112(r4)
; CHECK-P9-NEXT: stxv v2, 0(r3) ; CHECK-P9-NEXT: stxv v2, 0(r3)
; CHECK-P9-NEXT: xvcvdpuxws v5, vs2 ; CHECK-P9-NEXT: xvcvdpuxws v5, vs2
; CHECK-P9-NEXT: xxmrgld vs2, vs1, vs0 ; CHECK-P9-NEXT: xxmrgld vs2, vs1, vs0
; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0 ; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-P9-NEXT: xvcvdpuxws v0, vs0 ; CHECK-P9-NEXT: xvcvdpuxws v0, vs0
; CHECK-P9-NEXT: vmrgew v3, v3, v4 ; CHECK-P9-NEXT: vmrgew v3, v3, v4
; CHECK-P9-NEXT: xvcvdpuxws v4, vs4 ; CHECK-P9-NEXT: xvcvdpuxws v4, vs4
; CHECK-P9-NEXT: stxv v3, 16(r3) ; CHECK-P9-NEXT: stxv v3, 16(r3)
; CHECK-P9-NEXT: vmrgew v4, v5, v4 ; CHECK-P9-NEXT: vmrgew v4, v5, v4
; CHECK-P9-NEXT: stxv v4, 32(r3) ; CHECK-P9-NEXT: stxv v4, 32(r3)
; CHECK-P9-NEXT: xvcvdpuxws v5, vs2 ; CHECK-P9-NEXT: xvcvdpuxws v5, vs2
; CHECK-P9-NEXT: vmrgew v5, v0, v5 ; CHECK-P9-NEXT: vmrgew v5, v0, v5
; CHECK-P9-NEXT: stxv v5, 48(r3) ; CHECK-P9-NEXT: stxv v5, 48(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs6, 16(r4) ; CHECK-BE-NEXT: lxv vs6, 16(r4)
; CHECK-BE-NEXT: lxv vs7, 0(r4) ; CHECK-BE-NEXT: lxv vs7, 0(r4)
; CHECK-BE-NEXT: xxmrgld vs8, vs7, vs6
; CHECK-BE-NEXT: xxmrghd vs6, vs7, vs6
; CHECK-BE-NEXT: lxv vs4, 48(r4) ; CHECK-BE-NEXT: lxv vs4, 48(r4)
; CHECK-BE-NEXT: lxv vs5, 32(r4) ; CHECK-BE-NEXT: lxv vs5, 32(r4)
; CHECK-BE-NEXT: xxmrgld vs8, vs7, vs6
; CHECK-BE-NEXT: xxmrghd vs6, vs7, vs6
; CHECK-BE-NEXT: xxmrgld vs7, vs5, vs4 ; CHECK-BE-NEXT: xxmrgld vs7, vs5, vs4
; CHECK-BE-NEXT: xxmrghd vs4, vs5, vs4 ; CHECK-BE-NEXT: xxmrghd vs4, vs5, vs4
; CHECK-BE-NEXT: xvcvdpuxws v2, vs8
; CHECK-BE-NEXT: xvcvdpuxws v3, vs6
; CHECK-BE-NEXT: lxv vs2, 80(r4) ; CHECK-BE-NEXT: lxv vs2, 80(r4)
; CHECK-BE-NEXT: lxv vs3, 64(r4) ; CHECK-BE-NEXT: lxv vs3, 64(r4)
; CHECK-BE-NEXT: lxv vs0, 112(r4)
; CHECK-BE-NEXT: lxv vs1, 96(r4)
; CHECK-BE-NEXT: xvcvdpuxws v2, vs8
; CHECK-BE-NEXT: xvcvdpuxws v3, vs6
; CHECK-BE-NEXT: xvcvdpuxws v4, vs7 ; CHECK-BE-NEXT: xvcvdpuxws v4, vs7
; CHECK-BE-NEXT: vmrgew v2, v3, v2 ; CHECK-BE-NEXT: vmrgew v2, v3, v2
; CHECK-BE-NEXT: xvcvdpuxws v3, vs4 ; CHECK-BE-NEXT: xvcvdpuxws v3, vs4
; CHECK-BE-NEXT: xxmrgld vs4, vs3, vs2 ; CHECK-BE-NEXT: xxmrgld vs4, vs3, vs2
; CHECK-BE-NEXT: xxmrghd vs2, vs3, vs2 ; CHECK-BE-NEXT: xxmrghd vs2, vs3, vs2
; CHECK-BE-NEXT: lxv vs0, 112(r4)
; CHECK-BE-NEXT: lxv vs1, 96(r4)
; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: xvcvdpuxws v5, vs2 ; CHECK-BE-NEXT: xvcvdpuxws v5, vs2
; CHECK-BE-NEXT: xxmrgld vs2, vs1, vs0 ; CHECK-BE-NEXT: xxmrgld vs2, vs1, vs0
; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0 ; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-BE-NEXT: xvcvdpuxws v0, vs0 ; CHECK-BE-NEXT: xvcvdpuxws v0, vs0
; CHECK-BE-NEXT: vmrgew v3, v3, v4 ; CHECK-BE-NEXT: vmrgew v3, v3, v4
; CHECK-BE-NEXT: xvcvdpuxws v4, vs4 ; CHECK-BE-NEXT: xvcvdpuxws v4, vs4
; CHECK-BE-NEXT: stxv v3, 16(r3) ; CHECK-BE-NEXT: stxv v3, 16(r3)
▲ Show 20 Lines • Show All 125 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stvx v2, r3, r5 ; CHECK-P8-NEXT: stvx v2, r3, r5
; CHECK-P8-NEXT: stvx v3, 0, r3 ; CHECK-P8-NEXT: stvx v3, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs2, 0(r4) ; CHECK-P9-NEXT: lxv vs2, 0(r4)
; CHECK-P9-NEXT: lxv vs3, 16(r4) ; CHECK-P9-NEXT: lxv vs3, 16(r4)
; CHECK-P9-NEXT: xxmrgld vs4, vs3, vs2
; CHECK-P9-NEXT: xxmrghd vs2, vs3, vs2
; CHECK-P9-NEXT: lxv vs0, 32(r4) ; CHECK-P9-NEXT: lxv vs0, 32(r4)
; CHECK-P9-NEXT: lxv vs1, 48(r4) ; CHECK-P9-NEXT: lxv vs1, 48(r4)
; CHECK-P9-NEXT: xxmrgld vs4, vs3, vs2
; CHECK-P9-NEXT: xxmrghd vs2, vs3, vs2
; CHECK-P9-NEXT: xvcvdpsxws v2, vs4 ; CHECK-P9-NEXT: xvcvdpsxws v2, vs4
; CHECK-P9-NEXT: xvcvdpsxws v3, vs2 ; CHECK-P9-NEXT: xvcvdpsxws v3, vs2
; CHECK-P9-NEXT: xxmrgld vs2, vs1, vs0 ; CHECK-P9-NEXT: xxmrgld vs2, vs1, vs0
; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0 ; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-P9-NEXT: xvcvdpsxws v4, vs0 ; CHECK-P9-NEXT: xvcvdpsxws v4, vs0
; CHECK-P9-NEXT: vmrgew v2, v3, v2 ; CHECK-P9-NEXT: vmrgew v2, v3, v2
; CHECK-P9-NEXT: xvcvdpsxws v3, vs2 ; CHECK-P9-NEXT: xvcvdpsxws v3, vs2
; CHECK-P9-NEXT: stxv v2, 0(r3) ; CHECK-P9-NEXT: stxv v2, 0(r3)
; CHECK-P9-NEXT: vmrgew v3, v4, v3 ; CHECK-P9-NEXT: vmrgew v3, v4, v3
; CHECK-P9-NEXT: stxv v3, 16(r3) ; CHECK-P9-NEXT: stxv v3, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs2, 16(r4) ; CHECK-BE-NEXT: lxv vs2, 16(r4)
; CHECK-BE-NEXT: lxv vs3, 0(r4) ; CHECK-BE-NEXT: lxv vs3, 0(r4)
; CHECK-BE-NEXT: xxmrgld vs4, vs3, vs2
; CHECK-BE-NEXT: xxmrghd vs2, vs3, vs2
; CHECK-BE-NEXT: lxv vs0, 48(r4) ; CHECK-BE-NEXT: lxv vs0, 48(r4)
; CHECK-BE-NEXT: lxv vs1, 32(r4) ; CHECK-BE-NEXT: lxv vs1, 32(r4)
; CHECK-BE-NEXT: xxmrgld vs4, vs3, vs2
; CHECK-BE-NEXT: xxmrghd vs2, vs3, vs2
; CHECK-BE-NEXT: xvcvdpsxws v2, vs4 ; CHECK-BE-NEXT: xvcvdpsxws v2, vs4
; CHECK-BE-NEXT: xvcvdpsxws v3, vs2 ; CHECK-BE-NEXT: xvcvdpsxws v3, vs2
; CHECK-BE-NEXT: xxmrgld vs2, vs1, vs0 ; CHECK-BE-NEXT: xxmrgld vs2, vs1, vs0
; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0 ; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-BE-NEXT: xvcvdpsxws v4, vs0 ; CHECK-BE-NEXT: xvcvdpsxws v4, vs0
; CHECK-BE-NEXT: vmrgew v2, v3, v2 ; CHECK-BE-NEXT: vmrgew v2, v3, v2
; CHECK-BE-NEXT: xvcvdpsxws v3, vs2 ; CHECK-BE-NEXT: xvcvdpsxws v3, vs2
; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: stxv v2, 0(r3)
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; CHECK-P8-NEXT: stvx v4, r3, r6 ; CHECK-P8-NEXT: stvx v4, r3, r6
; CHECK-P8-NEXT: stvx v5, 0, r3 ; CHECK-P8-NEXT: stvx v5, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs6, 0(r4) ; CHECK-P9-NEXT: lxv vs6, 0(r4)
; CHECK-P9-NEXT: lxv vs7, 16(r4) ; CHECK-P9-NEXT: lxv vs7, 16(r4)
; CHECK-P9-NEXT: xxmrgld vs8, vs7, vs6
; CHECK-P9-NEXT: xxmrghd vs6, vs7, vs6
; CHECK-P9-NEXT: lxv vs4, 32(r4) ; CHECK-P9-NEXT: lxv vs4, 32(r4)
; CHECK-P9-NEXT: lxv vs5, 48(r4) ; CHECK-P9-NEXT: lxv vs5, 48(r4)
; CHECK-P9-NEXT: xxmrgld vs8, vs7, vs6
; CHECK-P9-NEXT: xxmrghd vs6, vs7, vs6
; CHECK-P9-NEXT: xxmrgld vs7, vs5, vs4 ; CHECK-P9-NEXT: xxmrgld vs7, vs5, vs4
; CHECK-P9-NEXT: xxmrghd vs4, vs5, vs4 ; CHECK-P9-NEXT: xxmrghd vs4, vs5, vs4
; CHECK-P9-NEXT: xvcvdpsxws v2, vs8
; CHECK-P9-NEXT: xvcvdpsxws v3, vs6
; CHECK-P9-NEXT: lxv vs2, 64(r4) ; CHECK-P9-NEXT: lxv vs2, 64(r4)
; CHECK-P9-NEXT: lxv vs3, 80(r4) ; CHECK-P9-NEXT: lxv vs3, 80(r4)
; CHECK-P9-NEXT: lxv vs0, 96(r4)
; CHECK-P9-NEXT: lxv vs1, 112(r4)
; CHECK-P9-NEXT: xvcvdpsxws v2, vs8
; CHECK-P9-NEXT: xvcvdpsxws v3, vs6
; CHECK-P9-NEXT: xvcvdpsxws v4, vs7 ; CHECK-P9-NEXT: xvcvdpsxws v4, vs7
; CHECK-P9-NEXT: vmrgew v2, v3, v2 ; CHECK-P9-NEXT: vmrgew v2, v3, v2
; CHECK-P9-NEXT: xvcvdpsxws v3, vs4 ; CHECK-P9-NEXT: xvcvdpsxws v3, vs4
; CHECK-P9-NEXT: xxmrgld vs4, vs3, vs2 ; CHECK-P9-NEXT: xxmrgld vs4, vs3, vs2
; CHECK-P9-NEXT: xxmrghd vs2, vs3, vs2 ; CHECK-P9-NEXT: xxmrghd vs2, vs3, vs2
; CHECK-P9-NEXT: lxv vs0, 96(r4)
; CHECK-P9-NEXT: lxv vs1, 112(r4)
; CHECK-P9-NEXT: stxv v2, 0(r3) ; CHECK-P9-NEXT: stxv v2, 0(r3)
; CHECK-P9-NEXT: xvcvdpsxws v5, vs2 ; CHECK-P9-NEXT: xvcvdpsxws v5, vs2
; CHECK-P9-NEXT: xxmrgld vs2, vs1, vs0 ; CHECK-P9-NEXT: xxmrgld vs2, vs1, vs0
; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0 ; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-P9-NEXT: xvcvdpsxws v0, vs0 ; CHECK-P9-NEXT: xvcvdpsxws v0, vs0
; CHECK-P9-NEXT: vmrgew v3, v3, v4 ; CHECK-P9-NEXT: vmrgew v3, v3, v4
; CHECK-P9-NEXT: xvcvdpsxws v4, vs4 ; CHECK-P9-NEXT: xvcvdpsxws v4, vs4
; CHECK-P9-NEXT: stxv v3, 16(r3) ; CHECK-P9-NEXT: stxv v3, 16(r3)
; CHECK-P9-NEXT: vmrgew v4, v5, v4 ; CHECK-P9-NEXT: vmrgew v4, v5, v4
; CHECK-P9-NEXT: stxv v4, 32(r3) ; CHECK-P9-NEXT: stxv v4, 32(r3)
; CHECK-P9-NEXT: xvcvdpsxws v5, vs2 ; CHECK-P9-NEXT: xvcvdpsxws v5, vs2
; CHECK-P9-NEXT: vmrgew v5, v0, v5 ; CHECK-P9-NEXT: vmrgew v5, v0, v5
; CHECK-P9-NEXT: stxv v5, 48(r3) ; CHECK-P9-NEXT: stxv v5, 48(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs6, 16(r4) ; CHECK-BE-NEXT: lxv vs6, 16(r4)
; CHECK-BE-NEXT: lxv vs7, 0(r4) ; CHECK-BE-NEXT: lxv vs7, 0(r4)
; CHECK-BE-NEXT: xxmrgld vs8, vs7, vs6
; CHECK-BE-NEXT: xxmrghd vs6, vs7, vs6
; CHECK-BE-NEXT: lxv vs4, 48(r4) ; CHECK-BE-NEXT: lxv vs4, 48(r4)
; CHECK-BE-NEXT: lxv vs5, 32(r4) ; CHECK-BE-NEXT: lxv vs5, 32(r4)
; CHECK-BE-NEXT: xxmrgld vs8, vs7, vs6
; CHECK-BE-NEXT: xxmrghd vs6, vs7, vs6
; CHECK-BE-NEXT: xxmrgld vs7, vs5, vs4 ; CHECK-BE-NEXT: xxmrgld vs7, vs5, vs4
; CHECK-BE-NEXT: xxmrghd vs4, vs5, vs4 ; CHECK-BE-NEXT: xxmrghd vs4, vs5, vs4
; CHECK-BE-NEXT: xvcvdpsxws v2, vs8
; CHECK-BE-NEXT: xvcvdpsxws v3, vs6
; CHECK-BE-NEXT: lxv vs2, 80(r4) ; CHECK-BE-NEXT: lxv vs2, 80(r4)
; CHECK-BE-NEXT: lxv vs3, 64(r4) ; CHECK-BE-NEXT: lxv vs3, 64(r4)
; CHECK-BE-NEXT: lxv vs0, 112(r4)
; CHECK-BE-NEXT: lxv vs1, 96(r4)
; CHECK-BE-NEXT: xvcvdpsxws v2, vs8
; CHECK-BE-NEXT: xvcvdpsxws v3, vs6
; CHECK-BE-NEXT: xvcvdpsxws v4, vs7 ; CHECK-BE-NEXT: xvcvdpsxws v4, vs7
; CHECK-BE-NEXT: vmrgew v2, v3, v2 ; CHECK-BE-NEXT: vmrgew v2, v3, v2
; CHECK-BE-NEXT: xvcvdpsxws v3, vs4 ; CHECK-BE-NEXT: xvcvdpsxws v3, vs4
; CHECK-BE-NEXT: xxmrgld vs4, vs3, vs2 ; CHECK-BE-NEXT: xxmrgld vs4, vs3, vs2
; CHECK-BE-NEXT: xxmrghd vs2, vs3, vs2 ; CHECK-BE-NEXT: xxmrghd vs2, vs3, vs2
; CHECK-BE-NEXT: lxv vs0, 112(r4)
; CHECK-BE-NEXT: lxv vs1, 96(r4)
; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: xvcvdpsxws v5, vs2 ; CHECK-BE-NEXT: xvcvdpsxws v5, vs2
; CHECK-BE-NEXT: xxmrgld vs2, vs1, vs0 ; CHECK-BE-NEXT: xxmrgld vs2, vs1, vs0
; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0 ; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-BE-NEXT: xvcvdpsxws v0, vs0 ; CHECK-BE-NEXT: xvcvdpsxws v0, vs0
; CHECK-BE-NEXT: vmrgew v3, v3, v4 ; CHECK-BE-NEXT: vmrgew v3, v3, v4
; CHECK-BE-NEXT: xvcvdpsxws v4, vs4 ; CHECK-BE-NEXT: xvcvdpsxws v4, vs4
; CHECK-BE-NEXT: stxv v3, 16(r3) ; CHECK-BE-NEXT: stxv v3, 16(r3)
Show All 12 Lines

llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i8_elts.ll

Show First 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: vmrglh v2, v3, v2 ; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mffprwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt: ; CHECK-P9-LABEL: test4elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs1, 0(r3) ; CHECK-P9-NEXT: lxv vs1, 0(r3)
; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: xscvdpsxws f2, f1 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: xxswapd vs1, vs1 ; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: mffprwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd v2, r3 ; CHECK-P9-NEXT: mtvsrd v2, r3
; CHECK-P9-NEXT: mffprwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: xscvdpsxws f1, f0 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0 ; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: mtvsrd v3, r3 ; CHECK-P9-NEXT: mtvsrd v3, r3
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: vmrghb v2, v2, v3 ; CHECK-P9-NEXT: vmrghb v2, v2, v3
; CHECK-P9-NEXT: mffprwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd v3, r3 ; CHECK-P9-NEXT: mtvsrd v3, r3
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd v4, r3 ; CHECK-P9-NEXT: mtvsrd v4, r3
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: vmrghb v3, v3, v4 ; CHECK-P9-NEXT: vmrghb v3, v3, v4
; CHECK-P9-NEXT: vmrglh v2, v3, v2 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: vextuwrx r3, r3, v2 ; CHECK-P9-NEXT: vextuwrx r3, r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt: ; CHECK-BE-LABEL: test4elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: xscvdpsxws f2, f1 ; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1 ; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0 ; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0 ; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mffprd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs3, 0(r3) ; CHECK-P9-NEXT: lxv vs3, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f4, f3
; CHECK-P9-NEXT: xxswapd vs3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: lxv vs2, 16(r3) ; CHECK-P9-NEXT: lxv vs2, 16(r3)
; CHECK-P9-NEXT: lxv vs0, 48(r3) ; CHECK-P9-NEXT: lxv vs0, 48(r3)
; CHECK-P9-NEXT: lxv vs1, 32(r3) ; CHECK-P9-NEXT: lxv vs1, 32(r3)
; CHECK-P9-NEXT: xscvdpsxws f4, f3
; CHECK-P9-NEXT: xxswapd vs3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: mffprwz r3, f4 ; CHECK-P9-NEXT: mffprwz r3, f4
; CHECK-P9-NEXT: mtvsrd v2, r3 ; CHECK-P9-NEXT: mtvsrd v2, r3
; CHECK-P9-NEXT: mffprwz r3, f3 ; CHECK-P9-NEXT: mffprwz r3, f3
; CHECK-P9-NEXT: xscvdpsxws f3, f2 ; CHECK-P9-NEXT: xscvdpsxws f3, f2
; CHECK-P9-NEXT: xxswapd vs2, vs2 ; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: mtvsrd v3, r3 ; CHECK-P9-NEXT: mtvsrd v3, r3
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: vmrghb v2, v2, v3 ; CHECK-P9-NEXT: vmrghb v2, v2, v3
Show All 22 Lines
; CHECK-P9-NEXT: vmrglh v3, v4, v3 ; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt: ; CHECK-BE-LABEL: test8elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs3, 48(r3) ; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: xscvdpsxws f4, f3
; CHECK-BE-NEXT: xxswapd vs3, vs3
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: lxv vs2, 32(r3) ; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: xscvdpsxws f4, f3
; CHECK-BE-NEXT: xxswapd vs3, vs3
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: mffprwz r3, f4 ; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mffprwz r3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xscvdpsxws f3, f2 ; CHECK-BE-NEXT: xscvdpsxws f3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs2 ; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
▲ Show 20 Lines • Show All 127 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: vmrglw v4, v5, v4 ; CHECK-P8-NEXT: vmrglw v4, v5, v4
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxmrgld v2, v2, v4 ; CHECK-P8-NEXT: xxmrgld v2, v2, v4
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs7, 0(r3) ; CHECK-P9-NEXT: lxv vs7, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f8, f7
; CHECK-P9-NEXT: xxswapd vs7, vs7
; CHECK-P9-NEXT: xscvdpsxws f7, f7
; CHECK-P9-NEXT: lxv vs6, 16(r3) ; CHECK-P9-NEXT: lxv vs6, 16(r3)
; CHECK-P9-NEXT: lxv vs0, 112(r3) ; CHECK-P9-NEXT: lxv vs0, 112(r3)
; CHECK-P9-NEXT: lxv vs1, 96(r3) ; CHECK-P9-NEXT: lxv vs1, 96(r3)
; CHECK-P9-NEXT: xscvdpsxws f8, f7
; CHECK-P9-NEXT: xxswapd vs7, vs7
; CHECK-P9-NEXT: lxv vs2, 80(r3) ; CHECK-P9-NEXT: lxv vs2, 80(r3)
; CHECK-P9-NEXT: lxv vs3, 64(r3) ; CHECK-P9-NEXT: lxv vs3, 64(r3)
; CHECK-P9-NEXT: lxv vs4, 48(r3) ; CHECK-P9-NEXT: lxv vs4, 48(r3)
; CHECK-P9-NEXT: lxv vs5, 32(r3) ; CHECK-P9-NEXT: lxv vs5, 32(r3)
; CHECK-P9-NEXT: xscvdpsxws f7, f7
; CHECK-P9-NEXT: mffprwz r3, f8 ; CHECK-P9-NEXT: mffprwz r3, f8
; CHECK-P9-NEXT: mtvsrd v2, r3 ; CHECK-P9-NEXT: mtvsrd v2, r3
; CHECK-P9-NEXT: mffprwz r3, f7 ; CHECK-P9-NEXT: mffprwz r3, f7
; CHECK-P9-NEXT: xscvdpsxws f7, f6 ; CHECK-P9-NEXT: xscvdpsxws f7, f6
; CHECK-P9-NEXT: xxswapd vs6, vs6 ; CHECK-P9-NEXT: xxswapd vs6, vs6
; CHECK-P9-NEXT: mtvsrd v3, r3 ; CHECK-P9-NEXT: mtvsrd v3, r3
; CHECK-P9-NEXT: xscvdpsxws f6, f6 ; CHECK-P9-NEXT: xscvdpsxws f6, f6
; CHECK-P9-NEXT: vmrghb v2, v2, v3 ; CHECK-P9-NEXT: vmrghb v2, v2, v3
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; CHECK-P9-NEXT: vmrglh v4, v5, v4 ; CHECK-P9-NEXT: vmrglh v4, v5, v4
; CHECK-P9-NEXT: vmrglw v3, v4, v3 ; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld v2, v3, v2 ; CHECK-P9-NEXT: xxmrgld v2, v3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs7, 112(r3) ; CHECK-BE-NEXT: lxv vs7, 112(r3)
; CHECK-BE-NEXT: xscvdpsxws f8, f7
; CHECK-BE-NEXT: xxswapd vs7, vs7
; CHECK-BE-NEXT: xscvdpsxws f7, f7
; CHECK-BE-NEXT: lxv vs6, 96(r3) ; CHECK-BE-NEXT: lxv vs6, 96(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: xscvdpsxws f8, f7
; CHECK-BE-NEXT: xxswapd vs7, vs7
; CHECK-BE-NEXT: lxv vs2, 32(r3) ; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3) ; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs4, 64(r3) ; CHECK-BE-NEXT: lxv vs4, 64(r3)
; CHECK-BE-NEXT: lxv vs5, 80(r3) ; CHECK-BE-NEXT: lxv vs5, 80(r3)
; CHECK-BE-NEXT: xscvdpsxws f7, f7
; CHECK-BE-NEXT: mffprwz r3, f8 ; CHECK-BE-NEXT: mffprwz r3, f8
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mffprwz r3, f7 ; CHECK-BE-NEXT: mffprwz r3, f7
; CHECK-BE-NEXT: xscvdpsxws f7, f6 ; CHECK-BE-NEXT: xscvdpsxws f7, f6
; CHECK-BE-NEXT: xxswapd vs6, vs6 ; CHECK-BE-NEXT: xxswapd vs6, vs6
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f6, f6 ; CHECK-BE-NEXT: xscvdpsxws f6, f6
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; CHECK-P8-NEXT: vmrglh v2, v3, v2 ; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mffprwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt_signed: ; CHECK-P9-LABEL: test4elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs1, 0(r3) ; CHECK-P9-NEXT: lxv vs1, 0(r3)
; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: xscvdpsxws f2, f1 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: xxswapd vs1, vs1 ; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: mffprwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd v2, r3 ; CHECK-P9-NEXT: mtvsrd v2, r3
; CHECK-P9-NEXT: mffprwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: xscvdpsxws f1, f0 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0 ; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: mtvsrd v3, r3 ; CHECK-P9-NEXT: mtvsrd v3, r3
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: vmrghb v2, v2, v3 ; CHECK-P9-NEXT: vmrghb v2, v2, v3
; CHECK-P9-NEXT: mffprwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd v3, r3 ; CHECK-P9-NEXT: mtvsrd v3, r3
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd v4, r3 ; CHECK-P9-NEXT: mtvsrd v4, r3
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: vmrghb v3, v3, v4 ; CHECK-P9-NEXT: vmrghb v3, v3, v4
; CHECK-P9-NEXT: vmrglh v2, v3, v2 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: vextuwrx r3, r3, v2 ; CHECK-P9-NEXT: vextuwrx r3, r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt_signed: ; CHECK-BE-LABEL: test4elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: xscvdpsxws f2, f1 ; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1 ; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0 ; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0 ; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
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; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mffprd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs3, 0(r3) ; CHECK-P9-NEXT: lxv vs3, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f4, f3
; CHECK-P9-NEXT: xxswapd vs3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: lxv vs2, 16(r3) ; CHECK-P9-NEXT: lxv vs2, 16(r3)
; CHECK-P9-NEXT: lxv vs0, 48(r3) ; CHECK-P9-NEXT: lxv vs0, 48(r3)
; CHECK-P9-NEXT: lxv vs1, 32(r3) ; CHECK-P9-NEXT: lxv vs1, 32(r3)
; CHECK-P9-NEXT: xscvdpsxws f4, f3
; CHECK-P9-NEXT: xxswapd vs3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: mffprwz r3, f4 ; CHECK-P9-NEXT: mffprwz r3, f4
; CHECK-P9-NEXT: mtvsrd v2, r3 ; CHECK-P9-NEXT: mtvsrd v2, r3
; CHECK-P9-NEXT: mffprwz r3, f3 ; CHECK-P9-NEXT: mffprwz r3, f3
; CHECK-P9-NEXT: xscvdpsxws f3, f2 ; CHECK-P9-NEXT: xscvdpsxws f3, f2
; CHECK-P9-NEXT: xxswapd vs2, vs2 ; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: mtvsrd v3, r3 ; CHECK-P9-NEXT: mtvsrd v3, r3
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: vmrghb v2, v2, v3 ; CHECK-P9-NEXT: vmrghb v2, v2, v3
Show All 22 Lines
; CHECK-P9-NEXT: vmrglh v3, v4, v3 ; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs3, 48(r3) ; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: xscvdpsxws f4, f3
; CHECK-BE-NEXT: xxswapd vs3, vs3
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: lxv vs2, 32(r3) ; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: xscvdpsxws f4, f3
; CHECK-BE-NEXT: xxswapd vs3, vs3
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: mffprwz r3, f4 ; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mffprwz r3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xscvdpsxws f3, f2 ; CHECK-BE-NEXT: xscvdpsxws f3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs2 ; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
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; CHECK-P8-NEXT: vmrglw v4, v5, v4 ; CHECK-P8-NEXT: vmrglw v4, v5, v4
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxmrgld v2, v2, v4 ; CHECK-P8-NEXT: xxmrgld v2, v2, v4
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs7, 0(r3) ; CHECK-P9-NEXT: lxv vs7, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f8, f7
; CHECK-P9-NEXT: xxswapd vs7, vs7
; CHECK-P9-NEXT: xscvdpsxws f7, f7
; CHECK-P9-NEXT: lxv vs6, 16(r3) ; CHECK-P9-NEXT: lxv vs6, 16(r3)
; CHECK-P9-NEXT: lxv vs0, 112(r3) ; CHECK-P9-NEXT: lxv vs0, 112(r3)
; CHECK-P9-NEXT: lxv vs1, 96(r3) ; CHECK-P9-NEXT: lxv vs1, 96(r3)
; CHECK-P9-NEXT: xscvdpsxws f8, f7
; CHECK-P9-NEXT: xxswapd vs7, vs7
; CHECK-P9-NEXT: lxv vs2, 80(r3) ; CHECK-P9-NEXT: lxv vs2, 80(r3)
; CHECK-P9-NEXT: lxv vs3, 64(r3) ; CHECK-P9-NEXT: lxv vs3, 64(r3)
; CHECK-P9-NEXT: lxv vs4, 48(r3) ; CHECK-P9-NEXT: lxv vs4, 48(r3)
; CHECK-P9-NEXT: lxv vs5, 32(r3) ; CHECK-P9-NEXT: lxv vs5, 32(r3)
; CHECK-P9-NEXT: xscvdpsxws f7, f7
; CHECK-P9-NEXT: mffprwz r3, f8 ; CHECK-P9-NEXT: mffprwz r3, f8
; CHECK-P9-NEXT: mtvsrd v2, r3 ; CHECK-P9-NEXT: mtvsrd v2, r3
; CHECK-P9-NEXT: mffprwz r3, f7 ; CHECK-P9-NEXT: mffprwz r3, f7
; CHECK-P9-NEXT: xscvdpsxws f7, f6 ; CHECK-P9-NEXT: xscvdpsxws f7, f6
; CHECK-P9-NEXT: xxswapd vs6, vs6 ; CHECK-P9-NEXT: xxswapd vs6, vs6
; CHECK-P9-NEXT: mtvsrd v3, r3 ; CHECK-P9-NEXT: mtvsrd v3, r3
; CHECK-P9-NEXT: xscvdpsxws f6, f6 ; CHECK-P9-NEXT: xscvdpsxws f6, f6
; CHECK-P9-NEXT: vmrghb v2, v2, v3 ; CHECK-P9-NEXT: vmrghb v2, v2, v3
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; CHECK-P9-NEXT: vmrglh v4, v5, v4 ; CHECK-P9-NEXT: vmrglh v4, v5, v4
; CHECK-P9-NEXT: vmrglw v3, v4, v3 ; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld v2, v3, v2 ; CHECK-P9-NEXT: xxmrgld v2, v3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs7, 112(r3) ; CHECK-BE-NEXT: lxv vs7, 112(r3)
; CHECK-BE-NEXT: xscvdpsxws f8, f7
; CHECK-BE-NEXT: xxswapd vs7, vs7
; CHECK-BE-NEXT: xscvdpsxws f7, f7
; CHECK-BE-NEXT: lxv vs6, 96(r3) ; CHECK-BE-NEXT: lxv vs6, 96(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: xscvdpsxws f8, f7
; CHECK-BE-NEXT: xxswapd vs7, vs7
; CHECK-BE-NEXT: lxv vs2, 32(r3) ; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3) ; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs4, 64(r3) ; CHECK-BE-NEXT: lxv vs4, 64(r3)
; CHECK-BE-NEXT: lxv vs5, 80(r3) ; CHECK-BE-NEXT: lxv vs5, 80(r3)
; CHECK-BE-NEXT: xscvdpsxws f7, f7
; CHECK-BE-NEXT: mffprwz r3, f8 ; CHECK-BE-NEXT: mffprwz r3, f8
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mffprwz r3, f7 ; CHECK-BE-NEXT: mffprwz r3, f7
; CHECK-BE-NEXT: xscvdpsxws f7, f6 ; CHECK-BE-NEXT: xscvdpsxws f7, f6
; CHECK-BE-NEXT: xxswapd vs6, vs6 ; CHECK-BE-NEXT: xxswapd vs6, vs6
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f6, f6 ; CHECK-BE-NEXT: xscvdpsxws f6, f6
▲ Show 20 Lines • Show All 82 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll

Show All 34 Lines
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrws v2, r3 ; CHECK-P9-NEXT: mtvsrws v2, r3
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: vextuhrx r3, r3, v2 ; CHECK-P9-NEXT: vextuhrx r3, r3, v2
; CHECK-P9-NEXT: clrlwi r3, r3, 16 ; CHECK-P9-NEXT: clrlwi r3, r3, 16
; CHECK-P9-NEXT: mtfprwz f0, r3 ; CHECK-P9-NEXT: mtfprwz f0, r3
; CHECK-P9-NEXT: li r3, 2 ; CHECK-P9-NEXT: li r3, 2
; CHECK-P9-NEXT: xscvuxdsp f0, f0 ; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: vextuhrx r3, r3, v2 ; CHECK-P9-NEXT: vextuhrx r3, r3, v2
; CHECK-P9-NEXT: clrlwi r3, r3, 16 ; CHECK-P9-NEXT: clrlwi r3, r3, 16
; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3
; CHECK-P9-NEXT: mtfprwz f0, r3 ; CHECK-P9-NEXT: mtfprwz f0, r3
; CHECK-P9-NEXT: xscvuxdsp f0, f0 ; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: xscvdpspn vs0, f0 ; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-P9-NEXT: vmrghw v2, v2, v3 ; CHECK-P9-NEXT: vmrghw v2, v2, v3
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
Show All 39 Lines
; CHECK-P9-NEXT: vmrghh v2, v3, v2 ; CHECK-P9-NEXT: vmrghh v2, v3, v2
; CHECK-P9-NEXT: xvcvuxwsp v2, v2 ; CHECK-P9-NEXT: xvcvuxwsp v2, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt: ; CHECK-BE-LABEL: test4elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l ; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r3 ; CHECK-BE-NEXT: lxvx v3, 0, r3
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: vperm v2, v2, v4, v3 ; CHECK-BE-NEXT: vperm v2, v2, v4, v3
; CHECK-BE-NEXT: xvcvuxwsp v2, v2 ; CHECK-BE-NEXT: xvcvuxwsp v2, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <4 x i16> %0 = bitcast i64 %a.coerce to <4 x i16>
%1 = uitofp <4 x i16> %0 to <4 x float> %1 = uitofp <4 x i16> %0 to <4 x float>
ret <4 x float> %1 ret <4 x float> %1
} }
Show All 20 Lines
; CHECK-P9-NEXT: xvcvuxwsp vs1, v2 ; CHECK-P9-NEXT: xvcvuxwsp vs1, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt: ; CHECK-BE-LABEL: test8elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: vperm v3, v2, v4, v3
; CHECK-BE-NEXT: xvcvuxwsp vs0, v3 ; CHECK-BE-NEXT: xvcvuxwsp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: vperm v2, v4, v2, v3
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: xvcvuxwsp vs1, v2 ; CHECK-BE-NEXT: xvcvuxwsp vs1, v2
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; CHECK-P8-NEXT: stvx v3, r3, r5 ; CHECK-P8-NEXT: stvx v3, r3, r5
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v2, 16(r4) ; CHECK-P9-NEXT: lxv v2, 16(r4)
; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; CHECK-P9-NEXT: xxlxor v5, v5, v5
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l
; CHECK-P9-NEXT: lxvx v4, 0, r4 ; CHECK-P9-NEXT: lxvx v4, 0, r4
; CHECK-P9-NEXT: xxlxor v5, v5, v5
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l
; CHECK-P9-NEXT: vperm v0, v5, v3, v4 ; CHECK-P9-NEXT: vperm v0, v5, v3, v4
; CHECK-P9-NEXT: xvcvuxwsp vs0, v0 ; CHECK-P9-NEXT: xvcvuxwsp vs0, v0
; CHECK-P9-NEXT: lxvx v0, 0, r4 ; CHECK-P9-NEXT: lxvx v0, 0, r4
; CHECK-P9-NEXT: vperm v3, v5, v3, v0 ; CHECK-P9-NEXT: vperm v3, v5, v3, v0
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: xvcvuxwsp vs1, v3 ; CHECK-P9-NEXT: xvcvuxwsp vs1, v3
; CHECK-P9-NEXT: vperm v3, v5, v2, v4 ; CHECK-P9-NEXT: vperm v3, v5, v2, v4
; CHECK-P9-NEXT: vperm v2, v5, v2, v0 ; CHECK-P9-NEXT: vperm v2, v5, v2, v0
; CHECK-P9-NEXT: xvcvuxwsp vs2, v3 ; CHECK-P9-NEXT: xvcvuxwsp vs2, v3
; CHECK-P9-NEXT: xvcvuxwsp vs3, v2 ; CHECK-P9-NEXT: xvcvuxwsp vs3, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v2, 16(r4) ; CHECK-BE-NEXT: lxv v2, 16(r4)
; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; CHECK-BE-NEXT: xxlxor v5, v5, v5
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l
; CHECK-BE-NEXT: lxvx v4, 0, r4 ; CHECK-BE-NEXT: lxvx v4, 0, r4
; CHECK-BE-NEXT: xxlxor v5, v5, v5
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l
; CHECK-BE-NEXT: vperm v0, v3, v5, v4 ; CHECK-BE-NEXT: vperm v0, v3, v5, v4
; CHECK-BE-NEXT: xvcvuxwsp vs0, v0 ; CHECK-BE-NEXT: xvcvuxwsp vs0, v0
; CHECK-BE-NEXT: lxvx v0, 0, r4 ; CHECK-BE-NEXT: lxvx v0, 0, r4
; CHECK-BE-NEXT: vperm v3, v5, v3, v0 ; CHECK-BE-NEXT: vperm v3, v5, v3, v0
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: xvcvuxwsp vs1, v3 ; CHECK-BE-NEXT: xvcvuxwsp vs1, v3
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; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrws v2, r3 ; CHECK-P9-NEXT: mtvsrws v2, r3
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: vextuhrx r3, r3, v2 ; CHECK-P9-NEXT: vextuhrx r3, r3, v2
; CHECK-P9-NEXT: extsh r3, r3 ; CHECK-P9-NEXT: extsh r3, r3
; CHECK-P9-NEXT: mtfprwa f0, r3 ; CHECK-P9-NEXT: mtfprwa f0, r3
; CHECK-P9-NEXT: li r3, 2 ; CHECK-P9-NEXT: li r3, 2
; CHECK-P9-NEXT: xscvsxdsp f0, f0 ; CHECK-P9-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: vextuhrx r3, r3, v2 ; CHECK-P9-NEXT: vextuhrx r3, r3, v2
; CHECK-P9-NEXT: extsh r3, r3 ; CHECK-P9-NEXT: extsh r3, r3
; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3
; CHECK-P9-NEXT: mtfprwa f0, r3 ; CHECK-P9-NEXT: mtfprwa f0, r3
; CHECK-P9-NEXT: xscvsxdsp f0, f0 ; CHECK-P9-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: xscvdpspn vs0, f0 ; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-P9-NEXT: vmrghw v2, v2, v3 ; CHECK-P9-NEXT: vmrghw v2, v2, v3
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
; CHECK-P9-NEXT: xvcvsxwsp vs1, v2 ; CHECK-P9-NEXT: xvcvsxwsp vs1, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: vmrghh v2, v2, v2 ; CHECK-BE-NEXT: vmrghh v2, v2, v2
; CHECK-BE-NEXT: vextsh2w v3, v3 ; CHECK-BE-NEXT: vextsh2w v3, v3
; CHECK-BE-NEXT: vextsh2w v2, v2 ; CHECK-BE-NEXT: vextsh2w v2, v2
; CHECK-BE-NEXT: xvcvsxwsp vs0, v3 ; CHECK-BE-NEXT: xvcvsxwsp vs0, v3
; CHECK-BE-NEXT: xvcvsxwsp vs1, v2 ; CHECK-BE-NEXT: xvcvsxwsp vs1, v2
; CHECK-BE-NEXT: stxv vs1, 0(r3) ; CHECK-BE-NEXT: stxv vs1, 0(r3)
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3)
Show All 38 Lines
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: lxv v2, 16(r4) ; CHECK-P9-NEXT: lxv v2, 16(r4)
; CHECK-P9-NEXT: vmrglh v4, v3, v3 ; CHECK-P9-NEXT: vmrglh v4, v3, v3
; CHECK-P9-NEXT: vmrghh v3, v3, v3 ; CHECK-P9-NEXT: vmrghh v3, v3, v3
; CHECK-P9-NEXT: vextsh2w v3, v3 ; CHECK-P9-NEXT: vextsh2w v3, v3
; CHECK-P9-NEXT: vextsh2w v4, v4
; CHECK-P9-NEXT: xvcvsxwsp vs1, v3 ; CHECK-P9-NEXT: xvcvsxwsp vs1, v3
; CHECK-P9-NEXT: vmrglh v3, v2, v2 ; CHECK-P9-NEXT: vmrglh v3, v2, v2
; CHECK-P9-NEXT: vmrghh v2, v2, v2 ; CHECK-P9-NEXT: vmrghh v2, v2, v2
; CHECK-P9-NEXT: vextsh2w v4, v4
; CHECK-P9-NEXT: xvcvsxwsp vs0, v4 ; CHECK-P9-NEXT: xvcvsxwsp vs0, v4
; CHECK-P9-NEXT: vextsh2w v3, v3 ; CHECK-P9-NEXT: vextsh2w v3, v3
; CHECK-P9-NEXT: vextsh2w v2, v2 ; CHECK-P9-NEXT: vextsh2w v2, v2
; CHECK-P9-NEXT: xvcvsxwsp vs2, v3 ; CHECK-P9-NEXT: xvcvsxwsp vs2, v3
; CHECK-P9-NEXT: xvcvsxwsp vs3, v2 ; CHECK-P9-NEXT: xvcvsxwsp vs3, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v2, 16(r4) ; CHECK-BE-NEXT: lxv v2, 16(r4)
; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha
; CHECK-BE-NEXT: xxlxor v5, v5, v5
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l
; CHECK-BE-NEXT: lxvx v4, 0, r4 ; CHECK-BE-NEXT: lxvx v4, 0, r4
; CHECK-BE-NEXT: xxlxor v5, v5, v5
; CHECK-BE-NEXT: vperm v0, v5, v3, v4 ; CHECK-BE-NEXT: vperm v0, v5, v3, v4
; CHECK-BE-NEXT: vperm v4, v5, v2, v4 ; CHECK-BE-NEXT: vperm v4, v5, v2, v4
; CHECK-BE-NEXT: vmrghh v3, v3, v3 ; CHECK-BE-NEXT: vmrghh v3, v3, v3
; CHECK-BE-NEXT: vmrghh v2, v2, v2 ; CHECK-BE-NEXT: vmrghh v2, v2, v2
; CHECK-BE-NEXT: vextsh2w v0, v0 ; CHECK-BE-NEXT: vextsh2w v0, v0
; CHECK-BE-NEXT: vextsh2w v4, v4 ; CHECK-BE-NEXT: vextsh2w v4, v4
; CHECK-BE-NEXT: vextsh2w v3, v3 ; CHECK-BE-NEXT: vextsh2w v3, v3
; CHECK-BE-NEXT: vextsh2w v2, v2 ; CHECK-BE-NEXT: vextsh2w v2, v2
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llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll

Show All 19 Lines
; CHECK-P8-NEXT: vperm v2, v4, v2, v3 ; CHECK-P8-NEXT: vperm v2, v4, v2, v3
; CHECK-P8-NEXT: xvcvuxddp v2, v2 ; CHECK-P8-NEXT: xvcvuxddp v2, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt: ; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrws v2, r3 ; CHECK-P9-NEXT: mtvsrws v2, r3
; CHECK-P9-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI0_0@toc@ha
; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addi r3, r3, .LCPI0_0@toc@l ; CHECK-P9-NEXT: addi r3, r3, .LCPI0_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r3 ; CHECK-P9-NEXT: lxvx v3, 0, r3
; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: xvcvuxddp v2, v2 ; CHECK-P9-NEXT: xvcvuxddp v2, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt: ; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrws v2, r3 ; CHECK-BE-NEXT: mtvsrws v2, r3
; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l ; CHECK-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r3 ; CHECK-BE-NEXT: lxvx v3, 0, r3
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: vperm v2, v2, v4, v3 ; CHECK-BE-NEXT: vperm v2, v2, v4, v3
; CHECK-BE-NEXT: xvcvuxddp v2, v2 ; CHECK-BE-NEXT: xvcvuxddp v2, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i32 %a.coerce to <2 x i16> %0 = bitcast i32 %a.coerce to <2 x i16>
%1 = uitofp <2 x i16> %0 to <2 x double> %1 = uitofp <2 x i16> %0 to <2 x double>
ret <2 x double> %1 ret <2 x double> %1
} }
Show All 19 Lines
; CHECK-P8-NEXT: stxvd2x vs1, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt: ; CHECK-P9-LABEL: test4elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd v2, r4 ; CHECK-P9-NEXT: mtvsrd v2, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0@toc@ha
; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addis r4, r2, .LCPI1_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI1_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_1@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: xvcvuxddp vs0, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: xvcvuxddp vs1, v2 ; CHECK-P9-NEXT: xvcvuxddp vs1, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt: ; CHECK-BE-LABEL: test4elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd v2, r4 ; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI1_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addis r4, r2, .LCPI1_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI1_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_1@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: vperm v3, v2, v4, v3
; CHECK-BE-NEXT: xvcvuxddp vs0, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: vperm v2, v4, v2, v3
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: xvcvuxddp vs1, v2 ; CHECK-BE-NEXT: xvcvuxddp vs1, v2
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stxvd2x vs1, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
; CHECK-P8-NEXT: stxvd2x vs3, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: xvcvuxddp vs0, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI2_2@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_2@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI2_2@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_2@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
Show All 10 Lines
; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: xvcvuxddp vs3, v2 ; CHECK-P9-NEXT: xvcvuxddp vs3, v2
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt: ; CHECK-BE-LABEL: test8elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: vperm v3, v2, v4, v3
; CHECK-BE-NEXT: xvcvuxddp vs0, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI2_2@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_2@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI2_2@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_2@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
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; CHECK-P8-NEXT: stxvd2x vs3, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs3, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v2, 16(r4) ; CHECK-P9-NEXT: lxv v2, 16(r4)
; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; CHECK-P9-NEXT: xxlxor v5, v5, v5
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l
; CHECK-P9-NEXT: lxvx v4, 0, r4 ; CHECK-P9-NEXT: lxvx v4, 0, r4
; CHECK-P9-NEXT: xxlxor v5, v5, v5
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l
; CHECK-P9-NEXT: vperm v0, v5, v3, v4 ; CHECK-P9-NEXT: vperm v0, v5, v3, v4
; CHECK-P9-NEXT: xvcvuxddp vs0, v0 ; CHECK-P9-NEXT: xvcvuxddp vs0, v0
; CHECK-P9-NEXT: lxvx v0, 0, r4 ; CHECK-P9-NEXT: lxvx v0, 0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l
; CHECK-P9-NEXT: vperm v1, v5, v3, v0 ; CHECK-P9-NEXT: vperm v1, v5, v3, v0
Show All 24 Lines
; CHECK-P9-NEXT: stxv vs6, 96(r3) ; CHECK-P9-NEXT: stxv vs6, 96(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v2, 16(r4) ; CHECK-BE-NEXT: lxv v2, 16(r4)
; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; CHECK-BE-NEXT: xxlxor v5, v5, v5
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l
; CHECK-BE-NEXT: lxvx v4, 0, r4 ; CHECK-BE-NEXT: lxvx v4, 0, r4
; CHECK-BE-NEXT: xxlxor v5, v5, v5
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l
; CHECK-BE-NEXT: vperm v0, v3, v5, v4 ; CHECK-BE-NEXT: vperm v0, v3, v5, v4
; CHECK-BE-NEXT: xvcvuxddp vs0, v0 ; CHECK-BE-NEXT: xvcvuxddp vs0, v0
; CHECK-BE-NEXT: lxvx v0, 0, r4 ; CHECK-BE-NEXT: lxvx v0, 0, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l
; CHECK-BE-NEXT: vperm v1, v5, v3, v0 ; CHECK-BE-NEXT: vperm v1, v5, v3, v0
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; CHECK-P9-NEXT: xvcvsxddp vs1, v2 ; CHECK-P9-NEXT: xvcvsxddp vs1, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt_signed: ; CHECK-BE-LABEL: test4elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd v2, r4 ; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha
; CHECK-BE-NEXT: xxlxor v3, v3, v3
; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0@toc@l
; CHECK-BE-NEXT: lxvx v4, 0, r4 ; CHECK-BE-NEXT: lxvx v4, 0, r4
; CHECK-BE-NEXT: xxlxor v3, v3, v3
; CHECK-BE-NEXT: vperm v3, v3, v2, v4
; CHECK-BE-NEXT: addis r4, r2, .LCPI5_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_1@toc@ha
; CHECK-BE-NEXT: vextsh2d v3, v3
; CHECK-BE-NEXT: addi r4, r4, .LCPI5_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_1@toc@l
; CHECK-BE-NEXT: vperm v3, v3, v2, v4
; CHECK-BE-NEXT: vextsh2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs0, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs1, v2 ; CHECK-BE-NEXT: xvcvsxddp vs1, v2
; CHECK-BE-NEXT: stxv vs1, 0(r3) ; CHECK-BE-NEXT: stxv vs1, 0(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
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; CHECK-P9-NEXT: vextsh2d v2, v2 ; CHECK-P9-NEXT: vextsh2d v2, v2
; CHECK-P9-NEXT: xvcvsxddp vs3, v2 ; CHECK-P9-NEXT: xvcvsxddp vs3, v2
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: vextsh2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs0, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_2@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_2@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_2@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_2@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: vextsh2d v3, v3
▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stxvd2x vs0, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
; CHECK-P8-NEXT: stxvd2x vs2, r3, r6 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r6
; CHECK-P8-NEXT: stxvd2x vs3, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs3, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r5, r2, .LCPI7_0@toc@ha ; CHECK-P9-NEXT: addis r5, r2, .LCPI7_0@toc@ha
; CHECK-P9-NEXT: addi r5, r5, .LCPI7_0@toc@l
; CHECK-P9-NEXT: lxv v2, 0(r4) ; CHECK-P9-NEXT: lxv v2, 0(r4)
; CHECK-P9-NEXT: addi r5, r5, .LCPI7_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r5 ; CHECK-P9-NEXT: lxvx v3, 0, r5
; CHECK-P9-NEXT: addis r5, r2, .LCPI7_1@toc@ha ; CHECK-P9-NEXT: addis r5, r2, .LCPI7_1@toc@ha
; CHECK-P9-NEXT: addi r5, r5, .LCPI7_1@toc@l ; CHECK-P9-NEXT: addi r5, r5, .LCPI7_1@toc@l
; CHECK-P9-NEXT: lxvx v5, 0, r5 ; CHECK-P9-NEXT: lxvx v5, 0, r5
; CHECK-P9-NEXT: addis r5, r2, .LCPI7_2@toc@ha ; CHECK-P9-NEXT: addis r5, r2, .LCPI7_2@toc@ha
; CHECK-P9-NEXT: vperm v4, v2, v2, v3 ; CHECK-P9-NEXT: vperm v4, v2, v2, v3
; CHECK-P9-NEXT: addi r5, r5, .LCPI7_2@toc@l ; CHECK-P9-NEXT: addi r5, r5, .LCPI7_2@toc@l
; CHECK-P9-NEXT: vextsh2d v4, v4 ; CHECK-P9-NEXT: vextsh2d v4, v4
; CHECK-P9-NEXT: lxvx v0, 0, r5 ; CHECK-P9-NEXT: lxvx v0, 0, r5
; CHECK-P9-NEXT: addis r5, r2, .LCPI7_3@toc@ha ; CHECK-P9-NEXT: addis r5, r2, .LCPI7_3@toc@ha
; CHECK-P9-NEXT: xvcvsxddp vs0, v4 ; CHECK-P9-NEXT: xvcvsxddp vs0, v4
; CHECK-P9-NEXT: vperm v4, v2, v2, v5 ; CHECK-P9-NEXT: vperm v4, v2, v2, v5
; CHECK-P9-NEXT: addi r5, r5, .LCPI7_3@toc@l ; CHECK-P9-NEXT: addi r5, r5, .LCPI7_3@toc@l
; CHECK-P9-NEXT: lxvx v1, 0, r5 ; CHECK-P9-NEXT: lxvx v1, 0, r5
; CHECK-P9-NEXT: vextsh2d v4, v4 ; CHECK-P9-NEXT: vextsh2d v4, v4
; CHECK-P9-NEXT: xvcvsxddp vs1, v4 ; CHECK-P9-NEXT: xvcvsxddp vs1, v4
; CHECK-P9-NEXT: vperm v4, v2, v2, v0 ; CHECK-P9-NEXT: vperm v4, v2, v2, v0
; CHECK-P9-NEXT: vperm v2, v2, v2, v1 ; CHECK-P9-NEXT: vperm v2, v2, v2, v1
; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: vextsh2d v4, v4 ; CHECK-P9-NEXT: vextsh2d v4, v4
; CHECK-P9-NEXT: xvcvsxddp vs2, v4 ; CHECK-P9-NEXT: xvcvsxddp vs2, v4
; CHECK-P9-NEXT: lxv v4, 16(r4) ; CHECK-P9-NEXT: lxv v4, 16(r4)
; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: vextsh2d v2, v2 ; CHECK-P9-NEXT: vextsh2d v2, v2
; CHECK-P9-NEXT: xvcvsxddp vs3, v2 ; CHECK-P9-NEXT: xvcvsxddp vs3, v2
; CHECK-P9-NEXT: vperm v2, v4, v4, v3 ; CHECK-P9-NEXT: vperm v2, v4, v4, v3
; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: vextsh2d v2, v2 ; CHECK-P9-NEXT: vextsh2d v2, v2
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: xvcvsxddp vs4, v2 ; CHECK-P9-NEXT: xvcvsxddp vs4, v2
; CHECK-P9-NEXT: vperm v2, v4, v4, v5 ; CHECK-P9-NEXT: vperm v2, v4, v4, v5
; CHECK-P9-NEXT: vextsh2d v2, v2 ; CHECK-P9-NEXT: vextsh2d v2, v2
; CHECK-P9-NEXT: xvcvsxddp vs5, v2 ; CHECK-P9-NEXT: xvcvsxddp vs5, v2
; CHECK-P9-NEXT: vperm v2, v4, v4, v0 ; CHECK-P9-NEXT: vperm v2, v4, v4, v0
; CHECK-P9-NEXT: stxv vs4, 64(r3) ; CHECK-P9-NEXT: stxv vs4, 64(r3)
; CHECK-P9-NEXT: vextsh2d v2, v2 ; CHECK-P9-NEXT: vextsh2d v2, v2
; CHECK-P9-NEXT: xvcvsxddp vs6, v2 ; CHECK-P9-NEXT: xvcvsxddp vs6, v2
; CHECK-P9-NEXT: vperm v2, v4, v4, v1 ; CHECK-P9-NEXT: vperm v2, v4, v4, v1
; CHECK-P9-NEXT: stxv vs5, 80(r3) ; CHECK-P9-NEXT: stxv vs5, 80(r3)
; CHECK-P9-NEXT: stxv vs6, 96(r3)
; CHECK-P9-NEXT: vextsh2d v2, v2 ; CHECK-P9-NEXT: vextsh2d v2, v2
; CHECK-P9-NEXT: xvcvsxddp vs7, v2 ; CHECK-P9-NEXT: xvcvsxddp vs7, v2
; CHECK-P9-NEXT: stxv vs6, 96(r3)
; CHECK-P9-NEXT: stxv vs7, 112(r3) ; CHECK-P9-NEXT: stxv vs7, 112(r3)
; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LCPI7_0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LCPI7_0@toc@ha
; CHECK-BE-NEXT: addi r5, r5, .LCPI7_0@toc@l
; CHECK-BE-NEXT: lxvx v2, 0, r5
; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: lxv v4, 0(r4)
; CHECK-BE-NEXT: lxv v1, 16(r4) ; CHECK-BE-NEXT: lxv v1, 16(r4)
; CHECK-BE-NEXT: xxlxor v5, v5, v5
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha
; CHECK-BE-NEXT: addi r5, r5, .LCPI7_0@toc@l
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l
; CHECK-BE-NEXT: lxvx v2, 0, r5
; CHECK-BE-NEXT: addis r5, r2, .LCPI7_1@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LCPI7_1@toc@ha
; CHECK-BE-NEXT: addi r5, r5, .LCPI7_1@toc@l ; CHECK-BE-NEXT: addi r5, r5, .LCPI7_1@toc@l
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha
; CHECK-BE-NEXT: xxlxor v5, v5, v5
; CHECK-BE-NEXT: vperm v0, v5, v4, v2
; CHECK-BE-NEXT: lxvx v3, 0, r5 ; CHECK-BE-NEXT: lxvx v3, 0, r5
; CHECK-BE-NEXT: vperm v0, v5, v4, v2
; CHECK-BE-NEXT: vperm v2, v5, v1, v2 ; CHECK-BE-NEXT: vperm v2, v5, v1, v2
; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l
; CHECK-BE-NEXT: vextsh2d v0, v0 ; CHECK-BE-NEXT: vextsh2d v0, v0
; CHECK-BE-NEXT: xvcvsxddp vs2, v2 ; CHECK-BE-NEXT: xvcvsxddp vs2, v2
; CHECK-BE-NEXT: vperm v2, v5, v1, v3 ; CHECK-BE-NEXT: vperm v2, v5, v1, v3
; CHECK-BE-NEXT: xvcvsxddp vs0, v0
; CHECK-BE-NEXT: vperm v0, v5, v4, v3
; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: stxv vs2, 80(r3) ; CHECK-BE-NEXT: vextsh2d v0, v0
; CHECK-BE-NEXT: xvcvsxddp vs3, v2 ; CHECK-BE-NEXT: xvcvsxddp vs3, v2
; CHECK-BE-NEXT: lxvx v2, 0, r4 ; CHECK-BE-NEXT: lxvx v2, 0, r4
; CHECK-BE-NEXT: xvcvsxddp vs0, v0
; CHECK-BE-NEXT: vperm v0, v5, v4, v3
; CHECK-BE-NEXT: vperm v3, v4, v4, v2
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha
; CHECK-BE-NEXT: vextsh2d v0, v0
; CHECK-BE-NEXT: xvcvsxddp vs1, v0 ; CHECK-BE-NEXT: xvcvsxddp vs1, v0
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l
; CHECK-BE-NEXT: stxv vs2, 80(r3)
; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: vperm v3, v4, v4, v2
; CHECK-BE-NEXT: vperm v2, v1, v1, v2
; CHECK-BE-NEXT: stxv vs3, 112(r3)
; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: stxv vs1, 48(r3)
; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: vextsh2d v3, v3
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l ; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs4, v3 ; CHECK-BE-NEXT: xvcvsxddp vs4, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: vperm v2, v1, v1, v2
; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs6, v2 ; CHECK-BE-NEXT: xvcvsxddp vs6, v2
; CHECK-BE-NEXT: vperm v2, v1, v1, v3
; CHECK-BE-NEXT: vperm v4, v4, v4, v3 ; CHECK-BE-NEXT: vperm v4, v4, v4, v3
; CHECK-BE-NEXT: vperm v2, v1, v1, v3
; CHECK-BE-NEXT: stxv vs6, 64(r3)
; CHECK-BE-NEXT: stxv vs4, 0(r3)
; CHECK-BE-NEXT: vextsh2d v4, v4 ; CHECK-BE-NEXT: vextsh2d v4, v4
; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs7, v2
; CHECK-BE-NEXT: xvcvsxddp vs5, v4 ; CHECK-BE-NEXT: xvcvsxddp vs5, v4
; CHECK-BE-NEXT: stxv vs3, 112(r3) ; CHECK-BE-NEXT: xvcvsxddp vs7, v2
; CHECK-BE-NEXT: stxv vs6, 64(r3)
; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: stxv vs4, 0(r3)
; CHECK-BE-NEXT: stxv vs7, 96(r3) ; CHECK-BE-NEXT: stxv vs7, 96(r3)
; CHECK-BE-NEXT: stxv vs5, 32(r3) ; CHECK-BE-NEXT: stxv vs5, 32(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x i16>, <16 x i16>* %0, align 32 %a = load <16 x i16>, <16 x i16>* %0, align 32
%1 = sitofp <16 x i16> %a to <16 x double> %1 = sitofp <16 x i16> %a to <16 x double>
store <16 x double> %1, <16 x double>* %agg.result, align 128 store <16 x double> %1, <16 x double>* %agg.result, align 128
ret void ret void
} }

llvm/test/CodeGen/PowerPC/vec_conv_i32_to_fp64_elts.ll

Show First 20 Lines • Show All 100 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stxvd2x vs0, r3, r6 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r6
; CHECK-P8-NEXT: stxvd2x vs3, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r5
; CHECK-P8-NEXT: stxvd2x vs2, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs2, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs1, 0(r4) ; CHECK-P9-NEXT: lxv vs1, 0(r4)
; CHECK-P9-NEXT: xxmrglw v2, vs1, vs1
; CHECK-P9-NEXT: lxv vs0, 16(r4) ; CHECK-P9-NEXT: lxv vs0, 16(r4)
; CHECK-P9-NEXT: xxmrglw v2, vs1, vs1
; CHECK-P9-NEXT: xvcvuxwdp vs2, v2 ; CHECK-P9-NEXT: xvcvuxwdp vs2, v2
; CHECK-P9-NEXT: xxmrghw v2, vs1, vs1 ; CHECK-P9-NEXT: xxmrghw v2, vs1, vs1
; CHECK-P9-NEXT: xvcvuxwdp vs1, v2 ; CHECK-P9-NEXT: xvcvuxwdp vs1, v2
; CHECK-P9-NEXT: xxmrglw v2, vs0, vs0 ; CHECK-P9-NEXT: xxmrglw v2, vs0, vs0
; CHECK-P9-NEXT: xvcvuxwdp vs3, v2 ; CHECK-P9-NEXT: xvcvuxwdp vs3, v2
; CHECK-P9-NEXT: xxmrghw v2, vs0, vs0 ; CHECK-P9-NEXT: xxmrghw v2, vs0, vs0
; CHECK-P9-NEXT: stxv vs2, 0(r3) ; CHECK-P9-NEXT: stxv vs2, 0(r3)
; CHECK-P9-NEXT: xvcvuxwdp vs0, v2 ; CHECK-P9-NEXT: xvcvuxwdp vs0, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs3, 32(r3) ; CHECK-P9-NEXT: stxv vs3, 32(r3)
; CHECK-P9-NEXT: stxv vs0, 48(r3) ; CHECK-P9-NEXT: stxv vs0, 48(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt: ; CHECK-BE-LABEL: test8elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 0(r4) ; CHECK-BE-NEXT: lxv vs1, 0(r4)
; CHECK-BE-NEXT: xxmrghw v2, vs1, vs1
; CHECK-BE-NEXT: lxv vs0, 16(r4) ; CHECK-BE-NEXT: lxv vs0, 16(r4)
; CHECK-BE-NEXT: xxmrghw v2, vs1, vs1
; CHECK-BE-NEXT: xvcvuxwdp vs2, v2 ; CHECK-BE-NEXT: xvcvuxwdp vs2, v2
; CHECK-BE-NEXT: xxmrglw v2, vs1, vs1 ; CHECK-BE-NEXT: xxmrglw v2, vs1, vs1
; CHECK-BE-NEXT: xvcvuxwdp vs1, v2 ; CHECK-BE-NEXT: xvcvuxwdp vs1, v2
; CHECK-BE-NEXT: xxmrghw v2, vs0, vs0 ; CHECK-BE-NEXT: xxmrghw v2, vs0, vs0
; CHECK-BE-NEXT: xvcvuxwdp vs3, v2 ; CHECK-BE-NEXT: xvcvuxwdp vs3, v2
; CHECK-BE-NEXT: xxmrglw v2, vs0, vs0 ; CHECK-BE-NEXT: xxmrglw v2, vs0, vs0
; CHECK-BE-NEXT: stxv vs2, 0(r3) ; CHECK-BE-NEXT: stxv vs2, 0(r3)
; CHECK-BE-NEXT: xvcvuxwdp vs0, v2 ; CHECK-BE-NEXT: xvcvuxwdp vs0, v2
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stxvd2x vs0, r3, r7 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r7
; CHECK-P8-NEXT: stxvd2x vs3, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r5
; CHECK-P8-NEXT: stxvd2x vs5, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs5, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 0(r4) ; CHECK-P9-NEXT: lxv vs0, 0(r4)
; CHECK-P9-NEXT: xxmrglw v2, vs0, vs0
; CHECK-P9-NEXT: lxv vs2, 16(r4) ; CHECK-P9-NEXT: lxv vs2, 16(r4)
; CHECK-P9-NEXT: lxv vs5, 32(r4)
; CHECK-P9-NEXT: lxv vs4, 48(r4) ; CHECK-P9-NEXT: lxv vs4, 48(r4)
; CHECK-P9-NEXT: xxmrglw v2, vs0, vs0
; CHECK-P9-NEXT: xvcvuxwdp vs1, v2 ; CHECK-P9-NEXT: xvcvuxwdp vs1, v2
; CHECK-P9-NEXT: xxmrghw v2, vs0, vs0 ; CHECK-P9-NEXT: xxmrghw v2, vs0, vs0
; CHECK-P9-NEXT: lxv vs5, 32(r4)
; CHECK-P9-NEXT: xvcvuxwdp vs0, v2 ; CHECK-P9-NEXT: xvcvuxwdp vs0, v2
; CHECK-P9-NEXT: xxmrglw v2, vs2, vs2 ; CHECK-P9-NEXT: xxmrglw v2, vs2, vs2
; CHECK-P9-NEXT: xvcvuxwdp vs3, v2 ; CHECK-P9-NEXT: xvcvuxwdp vs3, v2
; CHECK-P9-NEXT: xxmrghw v2, vs2, vs2 ; CHECK-P9-NEXT: xxmrghw v2, vs2, vs2
; CHECK-P9-NEXT: stxv vs1, 0(r3) ; CHECK-P9-NEXT: stxv vs1, 0(r3)
; CHECK-P9-NEXT: stxv vs0, 16(r3) ; CHECK-P9-NEXT: stxv vs0, 16(r3)
; CHECK-P9-NEXT: xvcvuxwdp vs2, v2 ; CHECK-P9-NEXT: xvcvuxwdp vs2, v2
; CHECK-P9-NEXT: xxmrglw v2, vs5, vs5 ; CHECK-P9-NEXT: xxmrglw v2, vs5, vs5
Show All 10 Lines
; CHECK-P9-NEXT: xvcvuxwdp vs4, v2 ; CHECK-P9-NEXT: xvcvuxwdp vs4, v2
; CHECK-P9-NEXT: stxv vs7, 96(r3) ; CHECK-P9-NEXT: stxv vs7, 96(r3)
; CHECK-P9-NEXT: stxv vs4, 112(r3) ; CHECK-P9-NEXT: stxv vs4, 112(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs0, 0(r4) ; CHECK-BE-NEXT: lxv vs0, 0(r4)
; CHECK-BE-NEXT: xxmrghw v2, vs0, vs0
; CHECK-BE-NEXT: lxv vs2, 16(r4) ; CHECK-BE-NEXT: lxv vs2, 16(r4)
; CHECK-BE-NEXT: lxv vs5, 32(r4)
; CHECK-BE-NEXT: lxv vs4, 48(r4) ; CHECK-BE-NEXT: lxv vs4, 48(r4)
; CHECK-BE-NEXT: xxmrghw v2, vs0, vs0
; CHECK-BE-NEXT: xvcvuxwdp vs1, v2 ; CHECK-BE-NEXT: xvcvuxwdp vs1, v2
; CHECK-BE-NEXT: xxmrglw v2, vs0, vs0 ; CHECK-BE-NEXT: xxmrglw v2, vs0, vs0
; CHECK-BE-NEXT: lxv vs5, 32(r4)
; CHECK-BE-NEXT: xvcvuxwdp vs0, v2 ; CHECK-BE-NEXT: xvcvuxwdp vs0, v2
; CHECK-BE-NEXT: xxmrghw v2, vs2, vs2 ; CHECK-BE-NEXT: xxmrghw v2, vs2, vs2
; CHECK-BE-NEXT: xvcvuxwdp vs3, v2 ; CHECK-BE-NEXT: xvcvuxwdp vs3, v2
; CHECK-BE-NEXT: xxmrglw v2, vs2, vs2 ; CHECK-BE-NEXT: xxmrglw v2, vs2, vs2
; CHECK-BE-NEXT: stxv vs1, 0(r3) ; CHECK-BE-NEXT: stxv vs1, 0(r3)
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: xvcvuxwdp vs2, v2 ; CHECK-BE-NEXT: xvcvuxwdp vs2, v2
; CHECK-BE-NEXT: xxmrghw v2, vs5, vs5 ; CHECK-BE-NEXT: xxmrghw v2, vs5, vs5
▲ Show 20 Lines • Show All 110 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stxvd2x vs0, r3, r6 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r6
; CHECK-P8-NEXT: stxvd2x vs3, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r5
; CHECK-P8-NEXT: stxvd2x vs2, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs2, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs1, 0(r4) ; CHECK-P9-NEXT: lxv vs1, 0(r4)
; CHECK-P9-NEXT: xxmrglw v2, vs1, vs1
; CHECK-P9-NEXT: lxv vs0, 16(r4) ; CHECK-P9-NEXT: lxv vs0, 16(r4)
; CHECK-P9-NEXT: xxmrglw v2, vs1, vs1
; CHECK-P9-NEXT: xvcvsxwdp vs2, v2 ; CHECK-P9-NEXT: xvcvsxwdp vs2, v2
; CHECK-P9-NEXT: xxmrghw v2, vs1, vs1 ; CHECK-P9-NEXT: xxmrghw v2, vs1, vs1
; CHECK-P9-NEXT: xvcvsxwdp vs1, v2 ; CHECK-P9-NEXT: xvcvsxwdp vs1, v2
; CHECK-P9-NEXT: xxmrglw v2, vs0, vs0 ; CHECK-P9-NEXT: xxmrglw v2, vs0, vs0
; CHECK-P9-NEXT: xvcvsxwdp vs3, v2 ; CHECK-P9-NEXT: xvcvsxwdp vs3, v2
; CHECK-P9-NEXT: xxmrghw v2, vs0, vs0 ; CHECK-P9-NEXT: xxmrghw v2, vs0, vs0
; CHECK-P9-NEXT: stxv vs2, 0(r3) ; CHECK-P9-NEXT: stxv vs2, 0(r3)
; CHECK-P9-NEXT: xvcvsxwdp vs0, v2 ; CHECK-P9-NEXT: xvcvsxwdp vs0, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs3, 32(r3) ; CHECK-P9-NEXT: stxv vs3, 32(r3)
; CHECK-P9-NEXT: stxv vs0, 48(r3) ; CHECK-P9-NEXT: stxv vs0, 48(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 0(r4) ; CHECK-BE-NEXT: lxv vs1, 0(r4)
; CHECK-BE-NEXT: xxmrghw v2, vs1, vs1
; CHECK-BE-NEXT: lxv vs0, 16(r4) ; CHECK-BE-NEXT: lxv vs0, 16(r4)
; CHECK-BE-NEXT: xxmrghw v2, vs1, vs1
; CHECK-BE-NEXT: xvcvsxwdp vs2, v2 ; CHECK-BE-NEXT: xvcvsxwdp vs2, v2
; CHECK-BE-NEXT: xxmrglw v2, vs1, vs1 ; CHECK-BE-NEXT: xxmrglw v2, vs1, vs1
; CHECK-BE-NEXT: xvcvsxwdp vs1, v2 ; CHECK-BE-NEXT: xvcvsxwdp vs1, v2
; CHECK-BE-NEXT: xxmrghw v2, vs0, vs0 ; CHECK-BE-NEXT: xxmrghw v2, vs0, vs0
; CHECK-BE-NEXT: xvcvsxwdp vs3, v2 ; CHECK-BE-NEXT: xvcvsxwdp vs3, v2
; CHECK-BE-NEXT: xxmrglw v2, vs0, vs0 ; CHECK-BE-NEXT: xxmrglw v2, vs0, vs0
; CHECK-BE-NEXT: stxv vs2, 0(r3) ; CHECK-BE-NEXT: stxv vs2, 0(r3)
; CHECK-BE-NEXT: xvcvsxwdp vs0, v2 ; CHECK-BE-NEXT: xvcvsxwdp vs0, v2
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stxvd2x vs0, r3, r7 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r7
; CHECK-P8-NEXT: stxvd2x vs3, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r5
; CHECK-P8-NEXT: stxvd2x vs5, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs5, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 0(r4) ; CHECK-P9-NEXT: lxv vs0, 0(r4)
; CHECK-P9-NEXT: xxmrglw v2, vs0, vs0
; CHECK-P9-NEXT: lxv vs2, 16(r4) ; CHECK-P9-NEXT: lxv vs2, 16(r4)
; CHECK-P9-NEXT: lxv vs5, 32(r4)
; CHECK-P9-NEXT: lxv vs4, 48(r4) ; CHECK-P9-NEXT: lxv vs4, 48(r4)
; CHECK-P9-NEXT: xxmrglw v2, vs0, vs0
; CHECK-P9-NEXT: xvcvsxwdp vs1, v2 ; CHECK-P9-NEXT: xvcvsxwdp vs1, v2
; CHECK-P9-NEXT: xxmrghw v2, vs0, vs0 ; CHECK-P9-NEXT: xxmrghw v2, vs0, vs0
; CHECK-P9-NEXT: lxv vs5, 32(r4)
; CHECK-P9-NEXT: xvcvsxwdp vs0, v2 ; CHECK-P9-NEXT: xvcvsxwdp vs0, v2
; CHECK-P9-NEXT: xxmrglw v2, vs2, vs2 ; CHECK-P9-NEXT: xxmrglw v2, vs2, vs2
; CHECK-P9-NEXT: xvcvsxwdp vs3, v2 ; CHECK-P9-NEXT: xvcvsxwdp vs3, v2
; CHECK-P9-NEXT: xxmrghw v2, vs2, vs2 ; CHECK-P9-NEXT: xxmrghw v2, vs2, vs2
; CHECK-P9-NEXT: stxv vs1, 0(r3) ; CHECK-P9-NEXT: stxv vs1, 0(r3)
; CHECK-P9-NEXT: stxv vs0, 16(r3) ; CHECK-P9-NEXT: stxv vs0, 16(r3)
; CHECK-P9-NEXT: xvcvsxwdp vs2, v2 ; CHECK-P9-NEXT: xvcvsxwdp vs2, v2
; CHECK-P9-NEXT: xxmrglw v2, vs5, vs5 ; CHECK-P9-NEXT: xxmrglw v2, vs5, vs5
Show All 10 Lines
; CHECK-P9-NEXT: xvcvsxwdp vs4, v2 ; CHECK-P9-NEXT: xvcvsxwdp vs4, v2
; CHECK-P9-NEXT: stxv vs7, 96(r3) ; CHECK-P9-NEXT: stxv vs7, 96(r3)
; CHECK-P9-NEXT: stxv vs4, 112(r3) ; CHECK-P9-NEXT: stxv vs4, 112(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs0, 0(r4) ; CHECK-BE-NEXT: lxv vs0, 0(r4)
; CHECK-BE-NEXT: xxmrghw v2, vs0, vs0
; CHECK-BE-NEXT: lxv vs2, 16(r4) ; CHECK-BE-NEXT: lxv vs2, 16(r4)
; CHECK-BE-NEXT: lxv vs5, 32(r4)
; CHECK-BE-NEXT: lxv vs4, 48(r4) ; CHECK-BE-NEXT: lxv vs4, 48(r4)
; CHECK-BE-NEXT: xxmrghw v2, vs0, vs0
; CHECK-BE-NEXT: xvcvsxwdp vs1, v2 ; CHECK-BE-NEXT: xvcvsxwdp vs1, v2
; CHECK-BE-NEXT: xxmrglw v2, vs0, vs0 ; CHECK-BE-NEXT: xxmrglw v2, vs0, vs0
; CHECK-BE-NEXT: lxv vs5, 32(r4)
; CHECK-BE-NEXT: xvcvsxwdp vs0, v2 ; CHECK-BE-NEXT: xvcvsxwdp vs0, v2
; CHECK-BE-NEXT: xxmrghw v2, vs2, vs2 ; CHECK-BE-NEXT: xxmrghw v2, vs2, vs2
; CHECK-BE-NEXT: xvcvsxwdp vs3, v2 ; CHECK-BE-NEXT: xvcvsxwdp vs3, v2
; CHECK-BE-NEXT: xxmrglw v2, vs2, vs2 ; CHECK-BE-NEXT: xxmrglw v2, vs2, vs2
; CHECK-BE-NEXT: stxv vs1, 0(r3) ; CHECK-BE-NEXT: stxv vs1, 0(r3)
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: xvcvsxwdp vs2, v2 ; CHECK-BE-NEXT: xvcvsxwdp vs2, v2
; CHECK-BE-NEXT: xxmrghw v2, vs5, vs5 ; CHECK-BE-NEXT: xxmrghw v2, vs5, vs5
Show All 20 Lines

llvm/test/CodeGen/PowerPC/vec_conv_i64_to_fp32_elts.ll

Show First 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 3 ; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 3
; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-P8-NEXT: vpkudum v2, v2, v3 ; CHECK-P8-NEXT: vpkudum v2, v2, v3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt: ; CHECK-P9-LABEL: test4elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v3, 0(r3) ; CHECK-P9-NEXT: lxv v3, 0(r3)
; CHECK-P9-NEXT: xvcvuxdsp vs0, v3
; CHECK-P9-NEXT: lxv v2, 16(r3) ; CHECK-P9-NEXT: lxv v2, 16(r3)
; CHECK-P9-NEXT: xvcvuxdsp vs0, v3
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvuxdsp vs0, v2 ; CHECK-P9-NEXT: xvcvuxdsp vs0, v2
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-P9-NEXT: vpkudum v2, v2, v3 ; CHECK-P9-NEXT: vpkudum v2, v2, v3
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt: ; CHECK-BE-LABEL: test4elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v3, 16(r3) ; CHECK-BE-NEXT: lxv v3, 16(r3)
; CHECK-BE-NEXT: xvcvuxdsp vs0, v3
; CHECK-BE-NEXT: lxv v2, 0(r3) ; CHECK-BE-NEXT: lxv v2, 0(r3)
; CHECK-BE-NEXT: xvcvuxdsp vs0, v3
; CHECK-BE-NEXT: xxsldwi v3, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi v3, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvuxdsp vs0, v2 ; CHECK-BE-NEXT: xvcvuxdsp vs0, v2
; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-BE-NEXT: vpkudum v2, v2, v3 ; CHECK-BE-NEXT: vpkudum v2, v2, v3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <4 x i64>, <4 x i64>* %0, align 32 %a = load <4 x i64>, <4 x i64>* %0, align 32
%1 = uitofp <4 x i64> %a to <4 x float> %1 = uitofp <4 x i64> %a to <4 x float>
Show All 26 Lines
; CHECK-P8-NEXT: vpkudum v3, v4, v5 ; CHECK-P8-NEXT: vpkudum v3, v4, v5
; CHECK-P8-NEXT: stvx v2, r3, r5 ; CHECK-P8-NEXT: stvx v2, r3, r5
; CHECK-P8-NEXT: stvx v3, 0, r3 ; CHECK-P8-NEXT: stvx v3, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v5, 0(r4) ; CHECK-P9-NEXT: lxv v5, 0(r4)
; CHECK-P9-NEXT: xvcvuxdsp vs0, v5
; CHECK-P9-NEXT: lxv v4, 16(r4) ; CHECK-P9-NEXT: lxv v4, 16(r4)
; CHECK-P9-NEXT: lxv v3, 32(r4)
; CHECK-P9-NEXT: lxv v2, 48(r4)
; CHECK-P9-NEXT: xvcvuxdsp vs0, v5
; CHECK-P9-NEXT: xxsldwi v5, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v5, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvuxdsp vs0, v4 ; CHECK-P9-NEXT: xvcvuxdsp vs0, v4
; CHECK-P9-NEXT: lxv v3, 32(r4)
; CHECK-P9-NEXT: xxsldwi v4, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v4, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvuxdsp vs0, v3 ; CHECK-P9-NEXT: xvcvuxdsp vs0, v3
; CHECK-P9-NEXT: lxv v2, 48(r4)
; CHECK-P9-NEXT: vpkudum v3, v4, v5 ; CHECK-P9-NEXT: vpkudum v3, v4, v5
; CHECK-P9-NEXT: stxv v3, 0(r3) ; CHECK-P9-NEXT: stxv v3, 0(r3)
; CHECK-P9-NEXT: xxsldwi v4, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v4, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvuxdsp vs0, v2 ; CHECK-P9-NEXT: xvcvuxdsp vs0, v2
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-P9-NEXT: vpkudum v2, v2, v4 ; CHECK-P9-NEXT: vpkudum v2, v2, v4
; CHECK-P9-NEXT: stxv v2, 16(r3) ; CHECK-P9-NEXT: stxv v2, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt: ; CHECK-BE-LABEL: test8elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v5, 16(r4) ; CHECK-BE-NEXT: lxv v5, 16(r4)
; CHECK-BE-NEXT: xvcvuxdsp vs0, v5
; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: lxv v4, 0(r4)
; CHECK-BE-NEXT: lxv v3, 48(r4)
; CHECK-BE-NEXT: lxv v2, 32(r4)
; CHECK-BE-NEXT: xvcvuxdsp vs0, v5
; CHECK-BE-NEXT: xxsldwi v5, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi v5, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvuxdsp vs0, v4 ; CHECK-BE-NEXT: xvcvuxdsp vs0, v4
; CHECK-BE-NEXT: lxv v3, 48(r4)
; CHECK-BE-NEXT: xxsldwi v4, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi v4, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvuxdsp vs0, v3 ; CHECK-BE-NEXT: xvcvuxdsp vs0, v3
; CHECK-BE-NEXT: lxv v2, 32(r4)
; CHECK-BE-NEXT: vpkudum v3, v4, v5 ; CHECK-BE-NEXT: vpkudum v3, v4, v5
; CHECK-BE-NEXT: stxv v3, 0(r3) ; CHECK-BE-NEXT: stxv v3, 0(r3)
; CHECK-BE-NEXT: xxsldwi v4, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi v4, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvuxdsp vs0, v2 ; CHECK-BE-NEXT: xvcvuxdsp vs0, v2
; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-BE-NEXT: vpkudum v2, v2, v4 ; CHECK-BE-NEXT: vpkudum v2, v2, v4
; CHECK-BE-NEXT: stxv v2, 16(r3) ; CHECK-BE-NEXT: stxv v2, 16(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stvx v3, r3, r5 ; CHECK-P8-NEXT: stvx v3, r3, r5
; CHECK-P8-NEXT: stvx v4, r3, r6 ; CHECK-P8-NEXT: stvx v4, r3, r6
; CHECK-P8-NEXT: stvx v5, 0, r3 ; CHECK-P8-NEXT: stvx v5, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v7, 0(r4) ; CHECK-P9-NEXT: lxv v7, 0(r4)
; CHECK-P9-NEXT: xvcvuxdsp vs0, v7
; CHECK-P9-NEXT: lxv v6, 16(r4) ; CHECK-P9-NEXT: lxv v6, 16(r4)
; CHECK-P9-NEXT: lxv v1, 32(r4)
; CHECK-P9-NEXT: lxv v0, 48(r4)
; CHECK-P9-NEXT: xvcvuxdsp vs0, v7
; CHECK-P9-NEXT: lxv v5, 64(r4)
; CHECK-P9-NEXT: lxv v4, 80(r4)
; CHECK-P9-NEXT: lxv v3, 96(r4)
; CHECK-P9-NEXT: lxv v2, 112(r4)
; CHECK-P9-NEXT: xxsldwi v7, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v7, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvuxdsp vs0, v6 ; CHECK-P9-NEXT: xvcvuxdsp vs0, v6
; CHECK-P9-NEXT: lxv v1, 32(r4)
; CHECK-P9-NEXT: xxsldwi v6, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v6, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvuxdsp vs0, v1 ; CHECK-P9-NEXT: xvcvuxdsp vs0, v1
; CHECK-P9-NEXT: lxv v0, 48(r4)
; CHECK-P9-NEXT: vpkudum v1, v6, v7 ; CHECK-P9-NEXT: vpkudum v1, v6, v7
; CHECK-P9-NEXT: stxv v1, 0(r3)
; CHECK-P9-NEXT: xxsldwi v6, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v6, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvuxdsp vs0, v0 ; CHECK-P9-NEXT: xvcvuxdsp vs0, v0
; CHECK-P9-NEXT: lxv v5, 64(r4)
; CHECK-P9-NEXT: stxv v1, 0(r3)
; CHECK-P9-NEXT: xxsldwi v0, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v0, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvuxdsp vs0, v5 ; CHECK-P9-NEXT: xvcvuxdsp vs0, v5
; CHECK-P9-NEXT: lxv v4, 80(r4)
; CHECK-P9-NEXT: vpkudum v0, v0, v6 ; CHECK-P9-NEXT: vpkudum v0, v0, v6
; CHECK-P9-NEXT: stxv v0, 16(r3) ; CHECK-P9-NEXT: stxv v0, 16(r3)
; CHECK-P9-NEXT: xxsldwi v5, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v5, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvuxdsp vs0, v4 ; CHECK-P9-NEXT: xvcvuxdsp vs0, v4
; CHECK-P9-NEXT: lxv v3, 96(r4)
; CHECK-P9-NEXT: xxsldwi v4, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v4, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvuxdsp vs0, v3 ; CHECK-P9-NEXT: xvcvuxdsp vs0, v3
; CHECK-P9-NEXT: lxv v2, 112(r4)
; CHECK-P9-NEXT: vpkudum v4, v4, v5 ; CHECK-P9-NEXT: vpkudum v4, v4, v5
; CHECK-P9-NEXT: stxv v4, 32(r3) ; CHECK-P9-NEXT: stxv v4, 32(r3)
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvuxdsp vs0, v2 ; CHECK-P9-NEXT: xvcvuxdsp vs0, v2
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-P9-NEXT: vpkudum v2, v2, v3 ; CHECK-P9-NEXT: vpkudum v2, v2, v3
; CHECK-P9-NEXT: stxv v2, 48(r3) ; CHECK-P9-NEXT: stxv v2, 48(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v7, 16(r4) ; CHECK-BE-NEXT: lxv v7, 16(r4)
; CHECK-BE-NEXT: xvcvuxdsp vs0, v7
; CHECK-BE-NEXT: lxv v6, 0(r4) ; CHECK-BE-NEXT: lxv v6, 0(r4)
; CHECK-BE-NEXT: lxv v1, 48(r4)
; CHECK-BE-NEXT: lxv v0, 32(r4)
; CHECK-BE-NEXT: xvcvuxdsp vs0, v7
; CHECK-BE-NEXT: lxv v5, 80(r4)
; CHECK-BE-NEXT: lxv v4, 64(r4)
; CHECK-BE-NEXT: lxv v3, 112(r4)
; CHECK-BE-NEXT: lxv v2, 96(r4)
; CHECK-BE-NEXT: xxsldwi v7, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi v7, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvuxdsp vs0, v6 ; CHECK-BE-NEXT: xvcvuxdsp vs0, v6
; CHECK-BE-NEXT: lxv v1, 48(r4)
; CHECK-BE-NEXT: xxsldwi v6, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi v6, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvuxdsp vs0, v1 ; CHECK-BE-NEXT: xvcvuxdsp vs0, v1
; CHECK-BE-NEXT: lxv v0, 32(r4)
; CHECK-BE-NEXT: vpkudum v1, v6, v7 ; CHECK-BE-NEXT: vpkudum v1, v6, v7
; CHECK-BE-NEXT: stxv v1, 0(r3)
; CHECK-BE-NEXT: xxsldwi v6, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi v6, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvuxdsp vs0, v0 ; CHECK-BE-NEXT: xvcvuxdsp vs0, v0
; CHECK-BE-NEXT: lxv v5, 80(r4)
; CHECK-BE-NEXT: stxv v1, 0(r3)
; CHECK-BE-NEXT: xxsldwi v0, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi v0, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvuxdsp vs0, v5 ; CHECK-BE-NEXT: xvcvuxdsp vs0, v5
; CHECK-BE-NEXT: lxv v4, 64(r4)
; CHECK-BE-NEXT: vpkudum v0, v0, v6 ; CHECK-BE-NEXT: vpkudum v0, v0, v6
; CHECK-BE-NEXT: stxv v0, 16(r3) ; CHECK-BE-NEXT: stxv v0, 16(r3)
; CHECK-BE-NEXT: xxsldwi v5, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi v5, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvuxdsp vs0, v4 ; CHECK-BE-NEXT: xvcvuxdsp vs0, v4
; CHECK-BE-NEXT: lxv v3, 112(r4)
; CHECK-BE-NEXT: xxsldwi v4, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi v4, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvuxdsp vs0, v3 ; CHECK-BE-NEXT: xvcvuxdsp vs0, v3
; CHECK-BE-NEXT: lxv v2, 96(r4)
; CHECK-BE-NEXT: vpkudum v4, v4, v5 ; CHECK-BE-NEXT: vpkudum v4, v4, v5
; CHECK-BE-NEXT: stxv v4, 32(r3) ; CHECK-BE-NEXT: stxv v4, 32(r3)
; CHECK-BE-NEXT: xxsldwi v3, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi v3, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvuxdsp vs0, v2 ; CHECK-BE-NEXT: xvcvuxdsp vs0, v2
; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-BE-NEXT: vpkudum v2, v2, v3 ; CHECK-BE-NEXT: vpkudum v2, v2, v3
; CHECK-BE-NEXT: stxv v2, 48(r3) ; CHECK-BE-NEXT: stxv v2, 48(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 3 ; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 3
; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-P8-NEXT: vpkudum v2, v2, v3 ; CHECK-P8-NEXT: vpkudum v2, v2, v3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt_signed: ; CHECK-P9-LABEL: test4elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v3, 0(r3) ; CHECK-P9-NEXT: lxv v3, 0(r3)
; CHECK-P9-NEXT: xvcvsxdsp vs0, v3
; CHECK-P9-NEXT: lxv v2, 16(r3) ; CHECK-P9-NEXT: lxv v2, 16(r3)
; CHECK-P9-NEXT: xvcvsxdsp vs0, v3
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvsxdsp vs0, v2 ; CHECK-P9-NEXT: xvcvsxdsp vs0, v2
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-P9-NEXT: vpkudum v2, v2, v3 ; CHECK-P9-NEXT: vpkudum v2, v2, v3
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt_signed: ; CHECK-BE-LABEL: test4elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v3, 16(r3) ; CHECK-BE-NEXT: lxv v3, 16(r3)
; CHECK-BE-NEXT: xvcvsxdsp vs0, v3
; CHECK-BE-NEXT: lxv v2, 0(r3) ; CHECK-BE-NEXT: lxv v2, 0(r3)
; CHECK-BE-NEXT: xvcvsxdsp vs0, v3
; CHECK-BE-NEXT: xxsldwi v3, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi v3, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvsxdsp vs0, v2 ; CHECK-BE-NEXT: xvcvsxdsp vs0, v2
; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-BE-NEXT: vpkudum v2, v2, v3 ; CHECK-BE-NEXT: vpkudum v2, v2, v3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <4 x i64>, <4 x i64>* %0, align 32 %a = load <4 x i64>, <4 x i64>* %0, align 32
%1 = sitofp <4 x i64> %a to <4 x float> %1 = sitofp <4 x i64> %a to <4 x float>
Show All 26 Lines
; CHECK-P8-NEXT: vpkudum v3, v4, v5 ; CHECK-P8-NEXT: vpkudum v3, v4, v5
; CHECK-P8-NEXT: stvx v2, r3, r5 ; CHECK-P8-NEXT: stvx v2, r3, r5
; CHECK-P8-NEXT: stvx v3, 0, r3 ; CHECK-P8-NEXT: stvx v3, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v5, 0(r4) ; CHECK-P9-NEXT: lxv v5, 0(r4)
; CHECK-P9-NEXT: xvcvsxdsp vs0, v5
; CHECK-P9-NEXT: lxv v4, 16(r4) ; CHECK-P9-NEXT: lxv v4, 16(r4)
; CHECK-P9-NEXT: lxv v3, 32(r4)
; CHECK-P9-NEXT: lxv v2, 48(r4)
; CHECK-P9-NEXT: xvcvsxdsp vs0, v5
; CHECK-P9-NEXT: xxsldwi v5, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v5, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvsxdsp vs0, v4 ; CHECK-P9-NEXT: xvcvsxdsp vs0, v4
; CHECK-P9-NEXT: lxv v3, 32(r4)
; CHECK-P9-NEXT: xxsldwi v4, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v4, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvsxdsp vs0, v3 ; CHECK-P9-NEXT: xvcvsxdsp vs0, v3
; CHECK-P9-NEXT: lxv v2, 48(r4)
; CHECK-P9-NEXT: vpkudum v3, v4, v5 ; CHECK-P9-NEXT: vpkudum v3, v4, v5
; CHECK-P9-NEXT: stxv v3, 0(r3) ; CHECK-P9-NEXT: stxv v3, 0(r3)
; CHECK-P9-NEXT: xxsldwi v4, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v4, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvsxdsp vs0, v2 ; CHECK-P9-NEXT: xvcvsxdsp vs0, v2
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-P9-NEXT: vpkudum v2, v2, v4 ; CHECK-P9-NEXT: vpkudum v2, v2, v4
; CHECK-P9-NEXT: stxv v2, 16(r3) ; CHECK-P9-NEXT: stxv v2, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v5, 16(r4) ; CHECK-BE-NEXT: lxv v5, 16(r4)
; CHECK-BE-NEXT: xvcvsxdsp vs0, v5
; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: lxv v4, 0(r4)
; CHECK-BE-NEXT: lxv v3, 48(r4)
; CHECK-BE-NEXT: lxv v2, 32(r4)
; CHECK-BE-NEXT: xvcvsxdsp vs0, v5
; CHECK-BE-NEXT: xxsldwi v5, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi v5, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvsxdsp vs0, v4 ; CHECK-BE-NEXT: xvcvsxdsp vs0, v4
; CHECK-BE-NEXT: lxv v3, 48(r4)
; CHECK-BE-NEXT: xxsldwi v4, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi v4, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvsxdsp vs0, v3 ; CHECK-BE-NEXT: xvcvsxdsp vs0, v3
; CHECK-BE-NEXT: lxv v2, 32(r4)
; CHECK-BE-NEXT: vpkudum v3, v4, v5 ; CHECK-BE-NEXT: vpkudum v3, v4, v5
; CHECK-BE-NEXT: stxv v3, 0(r3) ; CHECK-BE-NEXT: stxv v3, 0(r3)
; CHECK-BE-NEXT: xxsldwi v4, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi v4, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvsxdsp vs0, v2 ; CHECK-BE-NEXT: xvcvsxdsp vs0, v2
; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-BE-NEXT: vpkudum v2, v2, v4 ; CHECK-BE-NEXT: vpkudum v2, v2, v4
; CHECK-BE-NEXT: stxv v2, 16(r3) ; CHECK-BE-NEXT: stxv v2, 16(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stvx v3, r3, r5 ; CHECK-P8-NEXT: stvx v3, r3, r5
; CHECK-P8-NEXT: stvx v4, r3, r6 ; CHECK-P8-NEXT: stvx v4, r3, r6
; CHECK-P8-NEXT: stvx v5, 0, r3 ; CHECK-P8-NEXT: stvx v5, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v7, 0(r4) ; CHECK-P9-NEXT: lxv v7, 0(r4)
; CHECK-P9-NEXT: xvcvsxdsp vs0, v7
; CHECK-P9-NEXT: lxv v6, 16(r4) ; CHECK-P9-NEXT: lxv v6, 16(r4)
; CHECK-P9-NEXT: lxv v1, 32(r4)
; CHECK-P9-NEXT: lxv v0, 48(r4)
; CHECK-P9-NEXT: xvcvsxdsp vs0, v7
; CHECK-P9-NEXT: lxv v5, 64(r4)
; CHECK-P9-NEXT: lxv v4, 80(r4)
; CHECK-P9-NEXT: lxv v3, 96(r4)
; CHECK-P9-NEXT: lxv v2, 112(r4)
; CHECK-P9-NEXT: xxsldwi v7, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v7, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvsxdsp vs0, v6 ; CHECK-P9-NEXT: xvcvsxdsp vs0, v6
; CHECK-P9-NEXT: lxv v1, 32(r4)
; CHECK-P9-NEXT: xxsldwi v6, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v6, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvsxdsp vs0, v1 ; CHECK-P9-NEXT: xvcvsxdsp vs0, v1
; CHECK-P9-NEXT: lxv v0, 48(r4)
; CHECK-P9-NEXT: vpkudum v1, v6, v7 ; CHECK-P9-NEXT: vpkudum v1, v6, v7
; CHECK-P9-NEXT: stxv v1, 0(r3)
; CHECK-P9-NEXT: xxsldwi v6, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v6, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvsxdsp vs0, v0 ; CHECK-P9-NEXT: xvcvsxdsp vs0, v0
; CHECK-P9-NEXT: lxv v5, 64(r4)
; CHECK-P9-NEXT: stxv v1, 0(r3)
; CHECK-P9-NEXT: xxsldwi v0, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v0, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvsxdsp vs0, v5 ; CHECK-P9-NEXT: xvcvsxdsp vs0, v5
; CHECK-P9-NEXT: lxv v4, 80(r4)
; CHECK-P9-NEXT: vpkudum v0, v0, v6 ; CHECK-P9-NEXT: vpkudum v0, v0, v6
; CHECK-P9-NEXT: stxv v0, 16(r3) ; CHECK-P9-NEXT: stxv v0, 16(r3)
; CHECK-P9-NEXT: xxsldwi v5, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v5, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvsxdsp vs0, v4 ; CHECK-P9-NEXT: xvcvsxdsp vs0, v4
; CHECK-P9-NEXT: lxv v3, 96(r4)
; CHECK-P9-NEXT: xxsldwi v4, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v4, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvsxdsp vs0, v3 ; CHECK-P9-NEXT: xvcvsxdsp vs0, v3
; CHECK-P9-NEXT: lxv v2, 112(r4)
; CHECK-P9-NEXT: vpkudum v4, v4, v5 ; CHECK-P9-NEXT: vpkudum v4, v4, v5
; CHECK-P9-NEXT: stxv v4, 32(r3) ; CHECK-P9-NEXT: stxv v4, 32(r3)
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvsxdsp vs0, v2 ; CHECK-P9-NEXT: xvcvsxdsp vs0, v2
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-P9-NEXT: vpkudum v2, v2, v3 ; CHECK-P9-NEXT: vpkudum v2, v2, v3
; CHECK-P9-NEXT: stxv v2, 48(r3) ; CHECK-P9-NEXT: stxv v2, 48(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v7, 16(r4) ; CHECK-BE-NEXT: lxv v7, 16(r4)
; CHECK-BE-NEXT: xvcvsxdsp vs0, v7
; CHECK-BE-NEXT: lxv v6, 0(r4) ; CHECK-BE-NEXT: lxv v6, 0(r4)
; CHECK-BE-NEXT: lxv v1, 48(r4)
; CHECK-BE-NEXT: lxv v0, 32(r4)
; CHECK-BE-NEXT: xvcvsxdsp vs0, v7
; CHECK-BE-NEXT: lxv v5, 80(r4)
; CHECK-BE-NEXT: lxv v4, 64(r4)
; CHECK-BE-NEXT: lxv v3, 112(r4)
; CHECK-BE-NEXT: lxv v2, 96(r4)
; CHECK-BE-NEXT: xxsldwi v7, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi v7, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvsxdsp vs0, v6 ; CHECK-BE-NEXT: xvcvsxdsp vs0, v6
; CHECK-BE-NEXT: lxv v1, 48(r4)
; CHECK-BE-NEXT: xxsldwi v6, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi v6, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvsxdsp vs0, v1 ; CHECK-BE-NEXT: xvcvsxdsp vs0, v1
; CHECK-BE-NEXT: lxv v0, 32(r4)
; CHECK-BE-NEXT: vpkudum v1, v6, v7 ; CHECK-BE-NEXT: vpkudum v1, v6, v7
; CHECK-BE-NEXT: stxv v1, 0(r3)
; CHECK-BE-NEXT: xxsldwi v6, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi v6, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvsxdsp vs0, v0 ; CHECK-BE-NEXT: xvcvsxdsp vs0, v0
; CHECK-BE-NEXT: lxv v5, 80(r4)
; CHECK-BE-NEXT: stxv v1, 0(r3)
; CHECK-BE-NEXT: xxsldwi v0, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi v0, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvsxdsp vs0, v5 ; CHECK-BE-NEXT: xvcvsxdsp vs0, v5
; CHECK-BE-NEXT: lxv v4, 64(r4)
; CHECK-BE-NEXT: vpkudum v0, v0, v6 ; CHECK-BE-NEXT: vpkudum v0, v0, v6
; CHECK-BE-NEXT: stxv v0, 16(r3) ; CHECK-BE-NEXT: stxv v0, 16(r3)
; CHECK-BE-NEXT: xxsldwi v5, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi v5, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvsxdsp vs0, v4 ; CHECK-BE-NEXT: xvcvsxdsp vs0, v4
; CHECK-BE-NEXT: lxv v3, 112(r4)
; CHECK-BE-NEXT: xxsldwi v4, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi v4, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvsxdsp vs0, v3 ; CHECK-BE-NEXT: xvcvsxdsp vs0, v3
; CHECK-BE-NEXT: lxv v2, 96(r4)
; CHECK-BE-NEXT: vpkudum v4, v4, v5 ; CHECK-BE-NEXT: vpkudum v4, v4, v5
; CHECK-BE-NEXT: stxv v4, 32(r3) ; CHECK-BE-NEXT: stxv v4, 32(r3)
; CHECK-BE-NEXT: xxsldwi v3, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi v3, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvsxdsp vs0, v2 ; CHECK-BE-NEXT: xvcvsxdsp vs0, v2
; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-BE-NEXT: vpkudum v2, v2, v3 ; CHECK-BE-NEXT: vpkudum v2, v2, v3
; CHECK-BE-NEXT: stxv v2, 48(r3) ; CHECK-BE-NEXT: stxv v2, 48(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x i64>, <16 x i64>* %0, align 128 %a = load <16 x i64>, <16 x i64>* %0, align 128
%1 = sitofp <16 x i64> %a to <16 x float> %1 = sitofp <16 x i64> %a to <16 x float>
store <16 x float> %1, <16 x float>* %agg.result, align 64 store <16 x float> %1, <16 x float>* %agg.result, align 64
ret void ret void
} }

llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll

Show All 34 Lines
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrws v2, r3 ; CHECK-P9-NEXT: mtvsrws v2, r3
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: vextubrx r3, r3, v2 ; CHECK-P9-NEXT: vextubrx r3, r3, v2
; CHECK-P9-NEXT: clrlwi r3, r3, 24 ; CHECK-P9-NEXT: clrlwi r3, r3, 24
; CHECK-P9-NEXT: mtfprwz f0, r3 ; CHECK-P9-NEXT: mtfprwz f0, r3
; CHECK-P9-NEXT: li r3, 1 ; CHECK-P9-NEXT: li r3, 1
; CHECK-P9-NEXT: xscvuxdsp f0, f0 ; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: vextubrx r3, r3, v2 ; CHECK-P9-NEXT: vextubrx r3, r3, v2
; CHECK-P9-NEXT: clrlwi r3, r3, 24 ; CHECK-P9-NEXT: clrlwi r3, r3, 24
; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3
; CHECK-P9-NEXT: mtfprwz f0, r3 ; CHECK-P9-NEXT: mtfprwz f0, r3
; CHECK-P9-NEXT: xscvuxdsp f0, f0 ; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: xscvdpspn vs0, f0 ; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-P9-NEXT: vmrghw v2, v2, v3 ; CHECK-P9-NEXT: vmrghw v2, v2, v3
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
Show All 34 Lines
; CHECK-P8-NEXT: vperm v2, v4, v2, v3 ; CHECK-P8-NEXT: vperm v2, v4, v2, v3
; CHECK-P8-NEXT: xvcvuxwsp v2, v2 ; CHECK-P8-NEXT: xvcvuxwsp v2, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt: ; CHECK-P9-LABEL: test4elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrws v2, r3 ; CHECK-P9-NEXT: mtvsrws v2, r3
; CHECK-P9-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI1_0@toc@ha
; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addi r3, r3, .LCPI1_0@toc@l ; CHECK-P9-NEXT: addi r3, r3, .LCPI1_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r3 ; CHECK-P9-NEXT: lxvx v3, 0, r3
; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: xvcvuxwsp v2, v2 ; CHECK-P9-NEXT: xvcvuxwsp v2, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt: ; CHECK-BE-LABEL: test4elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrws v2, r3 ; CHECK-BE-NEXT: mtvsrws v2, r3
; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l ; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r3 ; CHECK-BE-NEXT: lxvx v3, 0, r3
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: vperm v2, v2, v4, v3 ; CHECK-BE-NEXT: vperm v2, v2, v4, v3
; CHECK-BE-NEXT: xvcvuxwsp v2, v2 ; CHECK-BE-NEXT: xvcvuxwsp v2, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i32 %a.coerce to <4 x i8> %0 = bitcast i32 %a.coerce to <4 x i8>
%1 = uitofp <4 x i8> %0 to <4 x float> %1 = uitofp <4 x i8> %0 to <4 x float>
ret <4 x float> %1 ret <4 x float> %1
} }
Show All 17 Lines
; CHECK-P8-NEXT: stvx v3, 0, r3 ; CHECK-P8-NEXT: stvx v3, 0, r3
; CHECK-P8-NEXT: stvx v2, r3, r4 ; CHECK-P8-NEXT: stvx v2, r3, r4
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd v2, r4 ; CHECK-P9-NEXT: mtvsrd v2, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: xvcvuxwsp vs0, v3 ; CHECK-P9-NEXT: xvcvuxwsp vs0, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: xvcvuxwsp vs1, v2 ; CHECK-P9-NEXT: xvcvuxwsp vs1, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt: ; CHECK-BE-LABEL: test8elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd v2, r4 ; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: vperm v3, v2, v4, v3
; CHECK-BE-NEXT: xvcvuxwsp vs0, v3 ; CHECK-BE-NEXT: xvcvuxwsp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: vperm v2, v4, v2, v3
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: xvcvuxwsp vs1, v2 ; CHECK-BE-NEXT: xvcvuxwsp vs1, v2
Show All 37 Lines
; CHECK-P8-NEXT: stvx v5, r3, r4 ; CHECK-P8-NEXT: stvx v5, r3, r4
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: stvx v2, r3, r4 ; CHECK-P8-NEXT: stvx v2, r3, r4
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: xvcvuxwsp vs0, v3 ; CHECK-P9-NEXT: xvcvuxwsp vs0, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
Show All 10 Lines
; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: xvcvuxwsp vs3, v2 ; CHECK-P9-NEXT: xvcvuxwsp vs3, v2
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: vperm v3, v2, v4, v3
; CHECK-BE-NEXT: xvcvuxwsp vs0, v3 ; CHECK-BE-NEXT: xvcvuxwsp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrws v2, r3 ; CHECK-P9-NEXT: mtvsrws v2, r3
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: vextubrx r3, r3, v2 ; CHECK-P9-NEXT: vextubrx r3, r3, v2
; CHECK-P9-NEXT: extsb r3, r3 ; CHECK-P9-NEXT: extsb r3, r3
; CHECK-P9-NEXT: mtfprwa f0, r3 ; CHECK-P9-NEXT: mtfprwa f0, r3
; CHECK-P9-NEXT: li r3, 1 ; CHECK-P9-NEXT: li r3, 1
; CHECK-P9-NEXT: xscvsxdsp f0, f0 ; CHECK-P9-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: vextubrx r3, r3, v2 ; CHECK-P9-NEXT: vextubrx r3, r3, v2
; CHECK-P9-NEXT: extsb r3, r3 ; CHECK-P9-NEXT: extsb r3, r3
; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3
; CHECK-P9-NEXT: mtfprwa f0, r3 ; CHECK-P9-NEXT: mtfprwa f0, r3
; CHECK-P9-NEXT: xscvsxdsp f0, f0 ; CHECK-P9-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: xscvdpspn vs0, f0 ; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-P9-NEXT: vmrghw v2, v2, v3 ; CHECK-P9-NEXT: vmrghw v2, v2, v3
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
▲ Show 20 Lines • Show All 108 Lines • ▼ Show 20 Lines
; CHECK-P9-NEXT: xvcvsxwsp vs1, v2 ; CHECK-P9-NEXT: xvcvsxwsp vs1, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd v2, r4 ; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha
; CHECK-BE-NEXT: xxlxor v3, v3, v3
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l
; CHECK-BE-NEXT: lxvx v4, 0, r4 ; CHECK-BE-NEXT: lxvx v4, 0, r4
; CHECK-BE-NEXT: xxlxor v3, v3, v3
; CHECK-BE-NEXT: vperm v3, v3, v2, v4
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha
; CHECK-BE-NEXT: vextsb2w v3, v3
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l
; CHECK-BE-NEXT: vperm v3, v3, v2, v4
; CHECK-BE-NEXT: vextsb2w v3, v3
; CHECK-BE-NEXT: xvcvsxwsp vs0, v3 ; CHECK-BE-NEXT: xvcvsxwsp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: vextsb2w v2, v2 ; CHECK-BE-NEXT: vextsb2w v2, v2
; CHECK-BE-NEXT: xvcvsxwsp vs1, v2 ; CHECK-BE-NEXT: xvcvsxwsp vs1, v2
; CHECK-BE-NEXT: stxv vs1, 0(r3) ; CHECK-BE-NEXT: stxv vs1, 0(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
; CHECK-P9-NEXT: vextsb2w v2, v2 ; CHECK-P9-NEXT: vextsb2w v2, v2
; CHECK-P9-NEXT: xvcvsxwsp vs3, v2 ; CHECK-P9-NEXT: xvcvsxwsp vs3, v2
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_1@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: vextsb2w v3, v3 ; CHECK-BE-NEXT: vextsb2w v3, v3
; CHECK-BE-NEXT: xvcvsxwsp vs0, v3 ; CHECK-BE-NEXT: xvcvsxwsp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: vextsb2w v3, v3 ; CHECK-BE-NEXT: vextsb2w v3, v3
Show All 20 Lines

llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll

Show All 19 Lines
; CHECK-P8-NEXT: vperm v2, v4, v2, v3 ; CHECK-P8-NEXT: vperm v2, v4, v2, v3
; CHECK-P8-NEXT: xvcvuxddp v2, v2 ; CHECK-P8-NEXT: xvcvuxddp v2, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt: ; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrws v2, r3 ; CHECK-P9-NEXT: mtvsrws v2, r3
; CHECK-P9-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI0_0@toc@ha
; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addi r3, r3, .LCPI0_0@toc@l ; CHECK-P9-NEXT: addi r3, r3, .LCPI0_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r3 ; CHECK-P9-NEXT: lxvx v3, 0, r3
; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: xvcvuxddp v2, v2 ; CHECK-P9-NEXT: xvcvuxddp v2, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt: ; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrws v2, r3 ; CHECK-BE-NEXT: mtvsrws v2, r3
; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l ; CHECK-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r3 ; CHECK-BE-NEXT: lxvx v3, 0, r3
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: vperm v2, v2, v4, v3 ; CHECK-BE-NEXT: vperm v2, v2, v4, v3
; CHECK-BE-NEXT: xvcvuxddp v2, v2 ; CHECK-BE-NEXT: xvcvuxddp v2, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i16 %a.coerce to <2 x i8> %0 = bitcast i16 %a.coerce to <2 x i8>
%1 = uitofp <2 x i8> %0 to <2 x double> %1 = uitofp <2 x i8> %0 to <2 x double>
ret <2 x double> %1 ret <2 x double> %1
} }
Show All 19 Lines
; CHECK-P8-NEXT: stxvd2x vs1, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt: ; CHECK-P9-LABEL: test4elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrws v2, r4 ; CHECK-P9-NEXT: mtvsrws v2, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0@toc@ha
; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addis r4, r2, .LCPI1_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI1_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_1@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: xvcvuxddp vs0, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: xvcvuxddp vs1, v2 ; CHECK-P9-NEXT: xvcvuxddp vs1, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt: ; CHECK-BE-LABEL: test4elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrws v2, r4 ; CHECK-BE-NEXT: mtvsrws v2, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI1_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addis r4, r2, .LCPI1_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI1_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_1@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: vperm v3, v2, v4, v3
; CHECK-BE-NEXT: xvcvuxddp vs0, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: vperm v2, v4, v2, v3
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: xvcvuxddp vs1, v2 ; CHECK-BE-NEXT: xvcvuxddp vs1, v2
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stxvd2x vs3, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd v2, r4 ; CHECK-P9-NEXT: mtvsrd v2, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: xvcvuxddp vs0, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI2_2@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_2@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI2_2@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_2@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
Show All 11 Lines
; CHECK-P9-NEXT: xvcvuxddp vs3, v2 ; CHECK-P9-NEXT: xvcvuxddp vs3, v2
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt: ; CHECK-BE-LABEL: test8elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd v2, r4 ; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: vperm v3, v2, v4, v3
; CHECK-BE-NEXT: xvcvuxddp vs0, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI2_2@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_2@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI2_2@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_2@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stxvd2x vs0, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
; CHECK-P8-NEXT: stxvd2x vs2, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
; CHECK-P8-NEXT: stxvd2x vs3, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs3, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: xvcvuxddp vs0, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
Show All 34 Lines
; CHECK-P9-NEXT: stxv vs6, 96(r3) ; CHECK-P9-NEXT: stxv vs6, 96(r3)
; CHECK-P9-NEXT: xvcvuxddp vs7, v2 ; CHECK-P9-NEXT: xvcvuxddp vs7, v2
; CHECK-P9-NEXT: stxv vs7, 112(r3) ; CHECK-P9-NEXT: stxv vs7, 112(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: vperm v3, v2, v4, v3
; CHECK-BE-NEXT: xvcvuxddp vs0, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
▲ Show 20 Lines • Show All 132 Lines • ▼ Show 20 Lines
; CHECK-P9-NEXT: xvcvsxddp vs1, v2 ; CHECK-P9-NEXT: xvcvsxddp vs1, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt_signed: ; CHECK-BE-LABEL: test4elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrws v2, r4 ; CHECK-BE-NEXT: mtvsrws v2, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha
; CHECK-BE-NEXT: xxlxor v3, v3, v3
; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0@toc@l
; CHECK-BE-NEXT: lxvx v4, 0, r4 ; CHECK-BE-NEXT: lxvx v4, 0, r4
; CHECK-BE-NEXT: xxlxor v3, v3, v3
; CHECK-BE-NEXT: vperm v3, v3, v2, v4
; CHECK-BE-NEXT: addis r4, r2, .LCPI5_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_1@toc@ha
; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: addi r4, r4, .LCPI5_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_1@toc@l
; CHECK-BE-NEXT: vperm v3, v3, v2, v4
; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs0, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: vextsb2d v2, v2 ; CHECK-BE-NEXT: vextsb2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs1, v2 ; CHECK-BE-NEXT: xvcvsxddp vs1, v2
; CHECK-BE-NEXT: stxv vs1, 0(r3) ; CHECK-BE-NEXT: stxv vs1, 0(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
; CHECK-P9-NEXT: xvcvsxddp vs3, v2 ; CHECK-P9-NEXT: xvcvsxddp vs3, v2
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd v2, r4 ; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha
; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs0, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_2@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_2@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_2@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_2@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs1, v3 ; CHECK-BE-NEXT: xvcvsxddp vs1, v3
▲ Show 20 Lines • Show All 164 Lines • ▼ Show 20 Lines
; CHECK-P9-NEXT: vextsb2d v2, v2 ; CHECK-P9-NEXT: vextsb2d v2, v2
; CHECK-P9-NEXT: xvcvsxddp vs7, v2 ; CHECK-P9-NEXT: xvcvsxddp vs7, v2
; CHECK-P9-NEXT: stxv vs7, 112(r3) ; CHECK-P9-NEXT: stxv vs7, 112(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha
; CHECK-BE-NEXT: xxlxor v3, v3, v3
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l
; CHECK-BE-NEXT: lxvx v4, 0, r4 ; CHECK-BE-NEXT: lxvx v4, 0, r4
; CHECK-BE-NEXT: xxlxor v3, v3, v3
; CHECK-BE-NEXT: vperm v4, v3, v2, v4
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_1@toc@l
; CHECK-BE-NEXT: vperm v4, v3, v2, v4
; CHECK-BE-NEXT: vextsb2d v4, v4 ; CHECK-BE-NEXT: vextsb2d v4, v4
; CHECK-BE-NEXT: xvcvsxddp vs0, v4 ; CHECK-BE-NEXT: xvcvsxddp vs0, v4
; CHECK-BE-NEXT: lxvx v4, 0, r4 ; CHECK-BE-NEXT: lxvx v4, 0, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l
; CHECK-BE-NEXT: vperm v4, v3, v2, v4 ; CHECK-BE-NEXT: vperm v4, v3, v2, v4
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: vextsb2d v4, v4 ; CHECK-BE-NEXT: vextsb2d v4, v4
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llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll

Show First 20 Lines • Show All 299 Lines • ▼ Show 20 Lines
; PC64LE9-NEXT: addis 3, 2, .LCPI6_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI6_1@toc@ha
; PC64LE9-NEXT: lfs 31, .LCPI6_1@toc@l(3) ; PC64LE9-NEXT: lfs 31, .LCPI6_1@toc@l(3)
; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: fmr 2, 31
; PC64LE9-NEXT: bl fmod ; PC64LE9-NEXT: bl fmod
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI6_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI6_2@toc@ha
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfs 1, .LCPI6_2@toc@l(3)
; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: fmr 2, 31
; PC64LE9-NEXT: lfs 1, .LCPI6_2@toc@l(3)
; PC64LE9-NEXT: bl fmod ; PC64LE9-NEXT: bl fmod
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: xxmrghd 34, 1, 0 ; PC64LE9-NEXT: xxmrghd 34, 1, 0
; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: addi 1, 1, 64
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
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; PC64LE9-NEXT: lfs 1, .LCPI7_0@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI7_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI7_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI7_1@toc@ha
; PC64LE9-NEXT: lfs 31, .LCPI7_1@toc@l(3) ; PC64LE9-NEXT: lfs 31, .LCPI7_1@toc@l(3)
; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: fmr 2, 31
; PC64LE9-NEXT: bl fmodf ; PC64LE9-NEXT: bl fmodf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI7_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI7_2@toc@ha
; PC64LE9-NEXT: fmr 30, 1 ; PC64LE9-NEXT: fmr 30, 1
; PC64LE9-NEXT: lfs 1, .LCPI7_2@toc@l(3)
; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: fmr 2, 31
; PC64LE9-NEXT: lfs 1, .LCPI7_2@toc@l(3)
; PC64LE9-NEXT: bl fmodf ; PC64LE9-NEXT: bl fmodf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI7_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI7_3@toc@ha
; PC64LE9-NEXT: fmr 29, 1 ; PC64LE9-NEXT: fmr 29, 1
; PC64LE9-NEXT: lfs 1, .LCPI7_3@toc@l(3)
; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: fmr 2, 31
; PC64LE9-NEXT: lfs 1, .LCPI7_3@toc@l(3)
; PC64LE9-NEXT: bl fmodf ; PC64LE9-NEXT: bl fmodf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: addis 3, 2, .LCPI7_4@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI7_4@toc@l
; PC64LE9-NEXT: lxvx 36, 0, 3
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 29 ; PC64LE9-NEXT: xscvdpspn 0, 29
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xscvdpspn 0, 30
; PC64LE9-NEXT: addis 3, 2, .LCPI7_4@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI7_4@toc@l
; PC64LE9-NEXT: lxvx 36, 0, 3
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 3, 2, 4 ; PC64LE9-NEXT: vperm 2, 3, 2, 4
; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: addi 1, 1, 64
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
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; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_frem_v3f64: ; PC64LE9-LABEL: constrained_vector_frem_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -80(1) ; PC64LE9-NEXT: stdu 1, -80(1)
; PC64LE9-NEXT: addis 3, 2, .LCPI8_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI8_0@toc@ha
; PC64LE9-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfs 1, .LCPI8_0@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI8_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI8_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI8_1@toc@ha
; PC64LE9-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE9-NEXT: lfs 31, .LCPI8_1@toc@l(3) ; PC64LE9-NEXT: lfs 31, .LCPI8_1@toc@l(3)
; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: fmr 2, 31
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: bl fmod ; PC64LE9-NEXT: bl fmod
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI8_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI8_2@toc@ha
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfs 1, .LCPI8_2@toc@l(3)
; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: fmr 2, 31
; PC64LE9-NEXT: lfs 1, .LCPI8_2@toc@l(3)
; PC64LE9-NEXT: bl fmod ; PC64LE9-NEXT: bl fmod
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload
; PC64LE9-NEXT: addis 3, 2, .LCPI8_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI8_3@toc@ha
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: fmr 2, 31
; PC64LE9-NEXT: xxmrghd 63, 1, 0 ; PC64LE9-NEXT: xxmrghd 63, 1, 0
; PC64LE9-NEXT: lfs 1, .LCPI8_3@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI8_3@toc@l(3)
; PC64LE9-NEXT: fmr 2, 31
; PC64LE9-NEXT: bl fmod ; PC64LE9-NEXT: bl fmod
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: fmr 3, 1 ; PC64LE9-NEXT: fmr 3, 1
; PC64LE9-NEXT: xxswapd 1, 63 ; PC64LE9-NEXT: xxswapd 1, 63
; PC64LE9-NEXT: xscpsgndp 2, 63, 63 ; PC64LE9-NEXT: xscpsgndp 2, 63, 63
; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload ; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload
; PC64LE9-NEXT: lfd 31, 72(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, 72(1) # 8-byte Folded Reload
; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1
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; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_frem_v4f64: ; PC64LE9-LABEL: constrained_vector_frem_v4f64:
; PC64LE9: # %bb.0: ; PC64LE9: # %bb.0:
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -80(1) ; PC64LE9-NEXT: stdu 1, -80(1)
; PC64LE9-NEXT: addis 3, 2, .LCPI9_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI9_0@toc@ha
; PC64LE9-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfs 1, .LCPI9_0@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI9_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI9_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI9_1@toc@ha
; PC64LE9-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE9-NEXT: lfs 31, .LCPI9_1@toc@l(3) ; PC64LE9-NEXT: lfs 31, .LCPI9_1@toc@l(3)
; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: fmr 2, 31
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: bl fmod ; PC64LE9-NEXT: bl fmod
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI9_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI9_2@toc@ha
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfs 1, .LCPI9_2@toc@l(3)
; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: fmr 2, 31
; PC64LE9-NEXT: lfs 1, .LCPI9_2@toc@l(3)
; PC64LE9-NEXT: bl fmod ; PC64LE9-NEXT: bl fmod
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload
; PC64LE9-NEXT: addis 3, 2, .LCPI9_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI9_3@toc@ha
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: fmr 2, 31
; PC64LE9-NEXT: xxmrghd 63, 1, 0 ; PC64LE9-NEXT: xxmrghd 63, 1, 0
; PC64LE9-NEXT: lfs 1, .LCPI9_3@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI9_3@toc@l(3)
; PC64LE9-NEXT: fmr 2, 31
; PC64LE9-NEXT: bl fmod ; PC64LE9-NEXT: bl fmod
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI9_4@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI9_4@toc@ha
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfs 1, .LCPI9_4@toc@l(3)
; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: fmr 2, 31
; PC64LE9-NEXT: lfs 1, .LCPI9_4@toc@l(3)
; PC64LE9-NEXT: bl fmod ; PC64LE9-NEXT: bl fmod
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload
; PC64LE9-NEXT: vmr 2, 31 ; PC64LE9-NEXT: vmr 2, 31
; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload ; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload
; PC64LE9-NEXT: lfd 31, 72(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, 72(1) # 8-byte Folded Reload
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: xxmrghd 35, 1, 0 ; PC64LE9-NEXT: xxmrghd 35, 1, 0
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; PC64LE-NEXT: vmrghw 2, 3, 2 ; PC64LE-NEXT: vmrghw 2, 3, 2
; PC64LE-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE-NEXT: vperm 2, 3, 2, 4 ; PC64LE-NEXT: vperm 2, 3, 2, 4
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fadd_v3f32: ; PC64LE9-LABEL: constrained_vector_fadd_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI17_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI17_0@toc@ha
; PC64LE9-NEXT: xxlxor 1, 1, 1
; PC64LE9-NEXT: lfs 0, .LCPI17_0@toc@l(3) ; PC64LE9-NEXT: lfs 0, .LCPI17_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI17_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI17_1@toc@ha
; PC64LE9-NEXT: lfs 2, .LCPI17_1@toc@l(3) ; PC64LE9-NEXT: lfs 2, .LCPI17_1@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI17_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI17_2@toc@ha
; PC64LE9-NEXT: xsaddsp 2, 0, 2
; PC64LE9-NEXT: lfs 3, .LCPI17_2@toc@l(3) ; PC64LE9-NEXT: lfs 3, .LCPI17_2@toc@l(3)
; PC64LE9-NEXT: xxlxor 1, 1, 1 ; PC64LE9-NEXT: addis 3, 2, .LCPI17_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI17_3@toc@l
; PC64LE9-NEXT: xsaddsp 1, 0, 1 ; PC64LE9-NEXT: xsaddsp 1, 0, 1
; PC64LE9-NEXT: lxvx 36, 0, 3
; PC64LE9-NEXT: xsaddsp 2, 0, 2
; PC64LE9-NEXT: xsaddsp 0, 0, 3 ; PC64LE9-NEXT: xsaddsp 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xscvdpspn 0, 0
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 2 ; PC64LE9-NEXT: xscvdpspn 0, 2
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: addis 3, 2, .LCPI17_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI17_3@toc@l
; PC64LE9-NEXT: lxvx 36, 0, 3
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 3, 2, 4 ; PC64LE9-NEXT: vperm 2, 3, 2, 4
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%add = call <3 x float> @llvm.experimental.constrained.fadd.v3f32( %add = call <3 x float> @llvm.experimental.constrained.fadd.v3f32(
<3 x float> <float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, <3 x float> <float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000,
float 0xFFFFFFFFE0000000>, float 0xFFFFFFFFE0000000>,
Show All 22 Lines
; PC64LE-NEXT: xxswapd 1, 2 ; PC64LE-NEXT: xxswapd 1, 2
; PC64LE-NEXT: # kill: def $f2 killed $f2 killed $vsl2 ; PC64LE-NEXT: # kill: def $f2 killed $f2 killed $vsl2
; PC64LE-NEXT: # kill: def $f1 killed $f1 killed $vsl1 ; PC64LE-NEXT: # kill: def $f1 killed $f1 killed $vsl1
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fadd_v3f64: ; PC64LE9-LABEL: constrained_vector_fadd_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI18_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI18_0@toc@ha
; PC64LE9-NEXT: xxlxor 1, 1, 1
; PC64LE9-NEXT: lfd 0, .LCPI18_0@toc@l(3) ; PC64LE9-NEXT: lfd 0, .LCPI18_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI18_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI18_1@toc@ha
; PC64LE9-NEXT: xxlxor 1, 1, 1
; PC64LE9-NEXT: addi 3, 3, .LCPI18_1@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI18_1@toc@l
; PC64LE9-NEXT: xsadddp 3, 0, 1 ; PC64LE9-NEXT: xsadddp 3, 0, 1
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxvx 0, 0, 3
; PC64LE9-NEXT: addis 3, 2, .LCPI18_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI18_2@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI18_2@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI18_2@toc@l
; PC64LE9-NEXT: lxvx 1, 0, 3 ; PC64LE9-NEXT: lxvx 1, 0, 3
; PC64LE9-NEXT: xvadddp 2, 1, 0 ; PC64LE9-NEXT: xvadddp 2, 1, 0
; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: xxswapd 1, 2
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; PC64LE-NEXT: vmrghw 2, 3, 2 ; PC64LE-NEXT: vmrghw 2, 3, 2
; PC64LE-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE-NEXT: vperm 2, 3, 2, 4 ; PC64LE-NEXT: vperm 2, 3, 2, 4
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fsub_v3f32: ; PC64LE9-LABEL: constrained_vector_fsub_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI22_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI22_0@toc@ha
; PC64LE9-NEXT: xxlxor 1, 1, 1
; PC64LE9-NEXT: lfs 0, .LCPI22_0@toc@l(3) ; PC64LE9-NEXT: lfs 0, .LCPI22_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI22_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI22_1@toc@ha
; PC64LE9-NEXT: lfs 2, .LCPI22_1@toc@l(3) ; PC64LE9-NEXT: lfs 2, .LCPI22_1@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI22_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI22_2@toc@ha
; PC64LE9-NEXT: xssubsp 2, 0, 2
; PC64LE9-NEXT: lfs 3, .LCPI22_2@toc@l(3) ; PC64LE9-NEXT: lfs 3, .LCPI22_2@toc@l(3)
; PC64LE9-NEXT: xxlxor 1, 1, 1 ; PC64LE9-NEXT: addis 3, 2, .LCPI22_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI22_3@toc@l
; PC64LE9-NEXT: xssubsp 1, 0, 1 ; PC64LE9-NEXT: xssubsp 1, 0, 1
; PC64LE9-NEXT: lxvx 36, 0, 3
; PC64LE9-NEXT: xssubsp 2, 0, 2
; PC64LE9-NEXT: xssubsp 0, 0, 3 ; PC64LE9-NEXT: xssubsp 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xscvdpspn 0, 0
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 2 ; PC64LE9-NEXT: xscvdpspn 0, 2
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: addis 3, 2, .LCPI22_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI22_3@toc@l
; PC64LE9-NEXT: lxvx 36, 0, 3
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 3, 2, 4 ; PC64LE9-NEXT: vperm 2, 3, 2, 4
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%sub = call <3 x float> @llvm.experimental.constrained.fsub.v3f32( %sub = call <3 x float> @llvm.experimental.constrained.fsub.v3f32(
<3 x float> <float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, <3 x float> <float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000,
float 0xFFFFFFFFE0000000>, float 0xFFFFFFFFE0000000>,
Show All 22 Lines
; PC64LE-NEXT: xxswapd 1, 2 ; PC64LE-NEXT: xxswapd 1, 2
; PC64LE-NEXT: # kill: def $f2 killed $f2 killed $vsl2 ; PC64LE-NEXT: # kill: def $f2 killed $f2 killed $vsl2
; PC64LE-NEXT: # kill: def $f1 killed $f1 killed $vsl1 ; PC64LE-NEXT: # kill: def $f1 killed $f1 killed $vsl1
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fsub_v3f64: ; PC64LE9-LABEL: constrained_vector_fsub_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI23_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI23_0@toc@ha
; PC64LE9-NEXT: xxlxor 1, 1, 1
; PC64LE9-NEXT: lfd 0, .LCPI23_0@toc@l(3) ; PC64LE9-NEXT: lfd 0, .LCPI23_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI23_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI23_1@toc@ha
; PC64LE9-NEXT: xxlxor 1, 1, 1
; PC64LE9-NEXT: addi 3, 3, .LCPI23_1@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI23_1@toc@l
; PC64LE9-NEXT: xssubdp 3, 0, 1 ; PC64LE9-NEXT: xssubdp 3, 0, 1
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxvx 0, 0, 3
; PC64LE9-NEXT: addis 3, 2, .LCPI23_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI23_2@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI23_2@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI23_2@toc@l
; PC64LE9-NEXT: lxvx 1, 0, 3 ; PC64LE9-NEXT: lxvx 1, 0, 3
; PC64LE9-NEXT: xvsubdp 2, 1, 0 ; PC64LE9-NEXT: xvsubdp 2, 1, 0
; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: xxswapd 1, 2
▲ Show 20 Lines • Show All 313 Lines • ▼ Show 20 Lines
; PC64LE9-NEXT: addis 3, 2, .LCPI31_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI31_1@toc@ha
; PC64LE9-NEXT: lfs 31, .LCPI31_1@toc@l(3) ; PC64LE9-NEXT: lfs 31, .LCPI31_1@toc@l(3)
; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: fmr 2, 31
; PC64LE9-NEXT: bl pow ; PC64LE9-NEXT: bl pow
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI31_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI31_2@toc@ha
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfd 1, .LCPI31_2@toc@l(3)
; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: fmr 2, 31
; PC64LE9-NEXT: lfd 1, .LCPI31_2@toc@l(3)
; PC64LE9-NEXT: bl pow ; PC64LE9-NEXT: bl pow
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: xxmrghd 34, 1, 0 ; PC64LE9-NEXT: xxmrghd 34, 1, 0
; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: addi 1, 1, 64
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
; PC64LE9-NEXT: lfs 1, .LCPI32_0@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI32_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI32_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI32_1@toc@ha
; PC64LE9-NEXT: lfs 31, .LCPI32_1@toc@l(3) ; PC64LE9-NEXT: lfs 31, .LCPI32_1@toc@l(3)
; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: fmr 2, 31
; PC64LE9-NEXT: bl powf ; PC64LE9-NEXT: bl powf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI32_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI32_2@toc@ha
; PC64LE9-NEXT: fmr 30, 1 ; PC64LE9-NEXT: fmr 30, 1
; PC64LE9-NEXT: lfs 1, .LCPI32_2@toc@l(3)
; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: fmr 2, 31
; PC64LE9-NEXT: lfs 1, .LCPI32_2@toc@l(3)
; PC64LE9-NEXT: bl powf ; PC64LE9-NEXT: bl powf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI32_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI32_3@toc@ha
; PC64LE9-NEXT: fmr 29, 1 ; PC64LE9-NEXT: fmr 29, 1
; PC64LE9-NEXT: lfs 1, .LCPI32_3@toc@l(3)
; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: fmr 2, 31
; PC64LE9-NEXT: lfs 1, .LCPI32_3@toc@l(3)
; PC64LE9-NEXT: bl powf ; PC64LE9-NEXT: bl powf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: addis 3, 2, .LCPI32_4@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI32_4@toc@l
; PC64LE9-NEXT: lxvx 36, 0, 3
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 29 ; PC64LE9-NEXT: xscvdpspn 0, 29
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xscvdpspn 0, 30
; PC64LE9-NEXT: addis 3, 2, .LCPI32_4@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI32_4@toc@l
; PC64LE9-NEXT: lxvx 36, 0, 3
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 3, 2, 4 ; PC64LE9-NEXT: vperm 2, 3, 2, 4
; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: addi 1, 1, 64
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_pow_v3f64: ; PC64LE9-LABEL: constrained_vector_pow_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -80(1) ; PC64LE9-NEXT: stdu 1, -80(1)
; PC64LE9-NEXT: addis 3, 2, .LCPI33_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI33_0@toc@ha
; PC64LE9-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfs 1, .LCPI33_0@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI33_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI33_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI33_1@toc@ha
; PC64LE9-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE9-NEXT: lfs 31, .LCPI33_1@toc@l(3) ; PC64LE9-NEXT: lfs 31, .LCPI33_1@toc@l(3)
; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: fmr 2, 31
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: bl pow ; PC64LE9-NEXT: bl pow
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI33_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI33_2@toc@ha
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfd 1, .LCPI33_2@toc@l(3)
; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: fmr 2, 31
; PC64LE9-NEXT: lfd 1, .LCPI33_2@toc@l(3)
; PC64LE9-NEXT: bl pow ; PC64LE9-NEXT: bl pow
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload
; PC64LE9-NEXT: addis 3, 2, .LCPI33_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI33_3@toc@ha
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: fmr 2, 31
; PC64LE9-NEXT: xxmrghd 63, 1, 0 ; PC64LE9-NEXT: xxmrghd 63, 1, 0
; PC64LE9-NEXT: lfd 1, .LCPI33_3@toc@l(3) ; PC64LE9-NEXT: lfd 1, .LCPI33_3@toc@l(3)
; PC64LE9-NEXT: fmr 2, 31
; PC64LE9-NEXT: bl pow ; PC64LE9-NEXT: bl pow
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: fmr 3, 1 ; PC64LE9-NEXT: fmr 3, 1
; PC64LE9-NEXT: xxswapd 1, 63 ; PC64LE9-NEXT: xxswapd 1, 63
; PC64LE9-NEXT: xscpsgndp 2, 63, 63 ; PC64LE9-NEXT: xscpsgndp 2, 63, 63
; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload ; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload
; PC64LE9-NEXT: lfd 31, 72(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, 72(1) # 8-byte Folded Reload
; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_pow_v4f64: ; PC64LE9-LABEL: constrained_vector_pow_v4f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -80(1) ; PC64LE9-NEXT: stdu 1, -80(1)
; PC64LE9-NEXT: addis 3, 2, .LCPI34_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI34_0@toc@ha
; PC64LE9-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfd 1, .LCPI34_0@toc@l(3) ; PC64LE9-NEXT: lfd 1, .LCPI34_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI34_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI34_1@toc@ha
; PC64LE9-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE9-NEXT: lfs 31, .LCPI34_1@toc@l(3) ; PC64LE9-NEXT: lfs 31, .LCPI34_1@toc@l(3)
; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: fmr 2, 31
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: bl pow ; PC64LE9-NEXT: bl pow
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI34_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI34_2@toc@ha
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfd 1, .LCPI34_2@toc@l(3)
; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: fmr 2, 31
; PC64LE9-NEXT: lfd 1, .LCPI34_2@toc@l(3)
; PC64LE9-NEXT: bl pow ; PC64LE9-NEXT: bl pow
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload
; PC64LE9-NEXT: addis 3, 2, .LCPI34_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI34_3@toc@ha
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: fmr 2, 31
; PC64LE9-NEXT: xxmrghd 63, 1, 0 ; PC64LE9-NEXT: xxmrghd 63, 1, 0
; PC64LE9-NEXT: lfd 1, .LCPI34_3@toc@l(3) ; PC64LE9-NEXT: lfd 1, .LCPI34_3@toc@l(3)
; PC64LE9-NEXT: fmr 2, 31
; PC64LE9-NEXT: bl pow ; PC64LE9-NEXT: bl pow
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI34_4@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI34_4@toc@ha
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfd 1, .LCPI34_4@toc@l(3)
; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: fmr 2, 31
; PC64LE9-NEXT: lfd 1, .LCPI34_4@toc@l(3)
; PC64LE9-NEXT: bl pow ; PC64LE9-NEXT: bl pow
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload
; PC64LE9-NEXT: vmr 2, 31 ; PC64LE9-NEXT: vmr 2, 31
; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload ; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload
; PC64LE9-NEXT: lfd 31, 72(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, 72(1) # 8-byte Folded Reload
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: xxmrghd 35, 1, 0 ; PC64LE9-NEXT: xxmrghd 35, 1, 0
Show All 29 Lines
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_powi_v1f32: ; PC64LE9-LABEL: constrained_vector_powi_v1f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: addis 3, 2, .LCPI35_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI35_0@toc@ha
; PC64LE9-NEXT: lfs 1, .LCPI35_0@toc@l(3)
; PC64LE9-NEXT: li 4, 3 ; PC64LE9-NEXT: li 4, 3
; PC64LE9-NEXT: lfs 1, .LCPI35_0@toc@l(3)
; PC64LE9-NEXT: bl __powisf2 ; PC64LE9-NEXT: bl __powisf2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%powi = call <1 x float> @llvm.experimental.constrained.powi.v1f32( %powi = call <1 x float> @llvm.experimental.constrained.powi.v1f32(
Show All 33 Lines
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_powi_v2f64: ; PC64LE9-LABEL: constrained_vector_powi_v2f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -48(1) ; PC64LE9-NEXT: stdu 1, -48(1)
; PC64LE9-NEXT: addis 3, 2, .LCPI36_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI36_0@toc@ha
; PC64LE9-NEXT: lfd 1, .LCPI36_0@toc@l(3)
; PC64LE9-NEXT: li 4, 3 ; PC64LE9-NEXT: li 4, 3
; PC64LE9-NEXT: lfd 1, .LCPI36_0@toc@l(3)
; PC64LE9-NEXT: bl __powidf2 ; PC64LE9-NEXT: bl __powidf2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI36_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI36_1@toc@ha
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfd 1, .LCPI36_1@toc@l(3)
; PC64LE9-NEXT: li 4, 3 ; PC64LE9-NEXT: li 4, 3
; PC64LE9-NEXT: lfd 1, .LCPI36_1@toc@l(3)
; PC64LE9-NEXT: bl __powidf2 ; PC64LE9-NEXT: bl __powidf2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: xxmrghd 34, 1, 0 ; PC64LE9-NEXT: xxmrghd 34, 1, 0
; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: addi 1, 1, 48
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
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; PC64LE9-LABEL: constrained_vector_powi_v3f32: ; PC64LE9-LABEL: constrained_vector_powi_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -48(1) ; PC64LE9-NEXT: stdu 1, -48(1)
; PC64LE9-NEXT: addis 3, 2, .LCPI37_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI37_0@toc@ha
; PC64LE9-NEXT: lfs 1, .LCPI37_0@toc@l(3)
; PC64LE9-NEXT: li 4, 3 ; PC64LE9-NEXT: li 4, 3
; PC64LE9-NEXT: lfs 1, .LCPI37_0@toc@l(3)
; PC64LE9-NEXT: bl __powisf2 ; PC64LE9-NEXT: bl __powisf2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI37_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI37_1@toc@ha
; PC64LE9-NEXT: fmr 31, 1 ; PC64LE9-NEXT: fmr 31, 1
; PC64LE9-NEXT: lfs 1, .LCPI37_1@toc@l(3)
; PC64LE9-NEXT: li 4, 3 ; PC64LE9-NEXT: li 4, 3
; PC64LE9-NEXT: lfs 1, .LCPI37_1@toc@l(3)
; PC64LE9-NEXT: bl __powisf2 ; PC64LE9-NEXT: bl __powisf2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI37_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI37_2@toc@ha
; PC64LE9-NEXT: fmr 30, 1 ; PC64LE9-NEXT: fmr 30, 1
; PC64LE9-NEXT: lfs 1, .LCPI37_2@toc@l(3)
; PC64LE9-NEXT: li 4, 3 ; PC64LE9-NEXT: li 4, 3
; PC64LE9-NEXT: lfs 1, .LCPI37_2@toc@l(3)
; PC64LE9-NEXT: bl __powisf2 ; PC64LE9-NEXT: bl __powisf2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: addis 3, 2, .LCPI37_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI37_3@toc@l
; PC64LE9-NEXT: lxvx 36, 0, 3
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xscvdpspn 0, 30
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: xscvdpspn 0, 31
; PC64LE9-NEXT: addis 3, 2, .LCPI37_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI37_3@toc@l
; PC64LE9-NEXT: lxvx 36, 0, 3
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 3, 2, 4 ; PC64LE9-NEXT: vperm 2, 3, 2, 4
; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: addi 1, 1, 48
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
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; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_powi_v3f64: ; PC64LE9-LABEL: constrained_vector_powi_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: addis 3, 2, .LCPI38_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI38_0@toc@ha
; PC64LE9-NEXT: lfd 1, .LCPI38_0@toc@l(3)
; PC64LE9-NEXT: li 4, 3 ; PC64LE9-NEXT: li 4, 3
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfd 1, .LCPI38_0@toc@l(3)
; PC64LE9-NEXT: bl __powidf2 ; PC64LE9-NEXT: bl __powidf2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI38_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI38_1@toc@ha
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfs 1, .LCPI38_1@toc@l(3)
; PC64LE9-NEXT: li 4, 3 ; PC64LE9-NEXT: li 4, 3
; PC64LE9-NEXT: lfs 1, .LCPI38_1@toc@l(3)
; PC64LE9-NEXT: bl __powidf2 ; PC64LE9-NEXT: bl __powidf2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload
; PC64LE9-NEXT: addis 3, 2, .LCPI38_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI38_2@toc@ha
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: li 4, 3
; PC64LE9-NEXT: xxmrghd 63, 0, 1 ; PC64LE9-NEXT: xxmrghd 63, 0, 1
; PC64LE9-NEXT: lfd 1, .LCPI38_2@toc@l(3) ; PC64LE9-NEXT: lfd 1, .LCPI38_2@toc@l(3)
; PC64LE9-NEXT: li 4, 3
; PC64LE9-NEXT: bl __powidf2 ; PC64LE9-NEXT: bl __powidf2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: fmr 3, 1 ; PC64LE9-NEXT: fmr 3, 1
; PC64LE9-NEXT: xxswapd 1, 63 ; PC64LE9-NEXT: xxswapd 1, 63
; PC64LE9-NEXT: xscpsgndp 2, 63, 63 ; PC64LE9-NEXT: xscpsgndp 2, 63, 63
; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload ; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload
; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1
; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: addi 1, 1, 64
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; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_powi_v4f64: ; PC64LE9-LABEL: constrained_vector_powi_v4f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: addis 3, 2, .LCPI39_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI39_0@toc@ha
; PC64LE9-NEXT: lfd 1, .LCPI39_0@toc@l(3)
; PC64LE9-NEXT: li 4, 3 ; PC64LE9-NEXT: li 4, 3
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfd 1, .LCPI39_0@toc@l(3)
; PC64LE9-NEXT: bl __powidf2 ; PC64LE9-NEXT: bl __powidf2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI39_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI39_1@toc@ha
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfd 1, .LCPI39_1@toc@l(3)
; PC64LE9-NEXT: li 4, 3 ; PC64LE9-NEXT: li 4, 3
; PC64LE9-NEXT: lfd 1, .LCPI39_1@toc@l(3)
; PC64LE9-NEXT: bl __powidf2 ; PC64LE9-NEXT: bl __powidf2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload
; PC64LE9-NEXT: addis 3, 2, .LCPI39_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI39_2@toc@ha
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: li 4, 3
; PC64LE9-NEXT: xxmrghd 63, 1, 0 ; PC64LE9-NEXT: xxmrghd 63, 1, 0
; PC64LE9-NEXT: lfd 1, .LCPI39_2@toc@l(3) ; PC64LE9-NEXT: lfd 1, .LCPI39_2@toc@l(3)
; PC64LE9-NEXT: li 4, 3
; PC64LE9-NEXT: bl __powidf2 ; PC64LE9-NEXT: bl __powidf2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI39_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI39_3@toc@ha
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfd 1, .LCPI39_3@toc@l(3)
; PC64LE9-NEXT: li 4, 3 ; PC64LE9-NEXT: li 4, 3
; PC64LE9-NEXT: lfd 1, .LCPI39_3@toc@l(3)
; PC64LE9-NEXT: bl __powidf2 ; PC64LE9-NEXT: bl __powidf2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload
; PC64LE9-NEXT: vmr 2, 31 ; PC64LE9-NEXT: vmr 2, 31
; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload ; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: xxmrghd 35, 1, 0 ; PC64LE9-NEXT: xxmrghd 35, 1, 0
; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: addi 1, 1, 64
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; PC64LE9-NEXT: bl sinf ; PC64LE9-NEXT: bl sinf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI42_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI42_2@toc@ha
; PC64LE9-NEXT: fmr 30, 1 ; PC64LE9-NEXT: fmr 30, 1
; PC64LE9-NEXT: lfs 1, .LCPI42_2@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI42_2@toc@l(3)
; PC64LE9-NEXT: bl sinf ; PC64LE9-NEXT: bl sinf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: addis 3, 2, .LCPI42_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI42_3@toc@l
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xscvdpspn 0, 30
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: xscvdpspn 0, 31
; PC64LE9-NEXT: addis 3, 2, .LCPI42_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI42_3@toc@l
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxvx 35, 0, 3
; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: addi 1, 1, 48
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
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; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_sin_v3f64: ; PC64LE9-LABEL: constrained_vector_sin_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: addis 3, 2, .LCPI43_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI43_0@toc@ha
; PC64LE9-NEXT: lfd 1, .LCPI43_0@toc@l(3)
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfd 1, .LCPI43_0@toc@l(3)
; PC64LE9-NEXT: bl sin ; PC64LE9-NEXT: bl sin
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI43_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI43_1@toc@ha
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfs 1, .LCPI43_1@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI43_1@toc@l(3)
; PC64LE9-NEXT: bl sin ; PC64LE9-NEXT: bl sin
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
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; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_sin_v4f64: ; PC64LE9-LABEL: constrained_vector_sin_v4f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: addis 3, 2, .LCPI44_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI44_0@toc@ha
; PC64LE9-NEXT: lfd 1, .LCPI44_0@toc@l(3)
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfd 1, .LCPI44_0@toc@l(3)
; PC64LE9-NEXT: bl sin ; PC64LE9-NEXT: bl sin
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI44_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI44_1@toc@ha
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfd 1, .LCPI44_1@toc@l(3) ; PC64LE9-NEXT: lfd 1, .LCPI44_1@toc@l(3)
; PC64LE9-NEXT: bl sin ; PC64LE9-NEXT: bl sin
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
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; PC64LE9-NEXT: bl cosf ; PC64LE9-NEXT: bl cosf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI47_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI47_2@toc@ha
; PC64LE9-NEXT: fmr 30, 1 ; PC64LE9-NEXT: fmr 30, 1
; PC64LE9-NEXT: lfs 1, .LCPI47_2@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI47_2@toc@l(3)
; PC64LE9-NEXT: bl cosf ; PC64LE9-NEXT: bl cosf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: addis 3, 2, .LCPI47_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI47_3@toc@l
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xscvdpspn 0, 30
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: xscvdpspn 0, 31
; PC64LE9-NEXT: addis 3, 2, .LCPI47_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI47_3@toc@l
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxvx 35, 0, 3
; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: addi 1, 1, 48
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
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; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_cos_v3f64: ; PC64LE9-LABEL: constrained_vector_cos_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: addis 3, 2, .LCPI48_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI48_0@toc@ha
; PC64LE9-NEXT: lfd 1, .LCPI48_0@toc@l(3)
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfd 1, .LCPI48_0@toc@l(3)
; PC64LE9-NEXT: bl cos ; PC64LE9-NEXT: bl cos
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI48_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI48_1@toc@ha
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfs 1, .LCPI48_1@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI48_1@toc@l(3)
; PC64LE9-NEXT: bl cos ; PC64LE9-NEXT: bl cos
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_cos_v4f64: ; PC64LE9-LABEL: constrained_vector_cos_v4f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: addis 3, 2, .LCPI49_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI49_0@toc@ha
; PC64LE9-NEXT: lfd 1, .LCPI49_0@toc@l(3)
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfd 1, .LCPI49_0@toc@l(3)
; PC64LE9-NEXT: bl cos ; PC64LE9-NEXT: bl cos
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI49_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI49_1@toc@ha
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfd 1, .LCPI49_1@toc@l(3) ; PC64LE9-NEXT: lfd 1, .LCPI49_1@toc@l(3)
; PC64LE9-NEXT: bl cos ; PC64LE9-NEXT: bl cos
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
▲ Show 20 Lines • Show All 177 Lines • ▼ Show 20 Lines
; PC64LE9-NEXT: bl expf ; PC64LE9-NEXT: bl expf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI52_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI52_2@toc@ha
; PC64LE9-NEXT: fmr 30, 1 ; PC64LE9-NEXT: fmr 30, 1
; PC64LE9-NEXT: lfs 1, .LCPI52_2@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI52_2@toc@l(3)
; PC64LE9-NEXT: bl expf ; PC64LE9-NEXT: bl expf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: addis 3, 2, .LCPI52_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI52_3@toc@l
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xscvdpspn 0, 30
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: xscvdpspn 0, 31
; PC64LE9-NEXT: addis 3, 2, .LCPI52_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI52_3@toc@l
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxvx 35, 0, 3
; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: addi 1, 1, 48
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_exp_v3f64: ; PC64LE9-LABEL: constrained_vector_exp_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: addis 3, 2, .LCPI53_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI53_0@toc@ha
; PC64LE9-NEXT: lfd 1, .LCPI53_0@toc@l(3)
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfd 1, .LCPI53_0@toc@l(3)
; PC64LE9-NEXT: bl exp ; PC64LE9-NEXT: bl exp
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI53_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI53_1@toc@ha
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfs 1, .LCPI53_1@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI53_1@toc@l(3)
; PC64LE9-NEXT: bl exp ; PC64LE9-NEXT: bl exp
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_exp_v4f64: ; PC64LE9-LABEL: constrained_vector_exp_v4f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: addis 3, 2, .LCPI54_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI54_0@toc@ha
; PC64LE9-NEXT: lfd 1, .LCPI54_0@toc@l(3)
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfd 1, .LCPI54_0@toc@l(3)
; PC64LE9-NEXT: bl exp ; PC64LE9-NEXT: bl exp
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI54_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI54_1@toc@ha
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfd 1, .LCPI54_1@toc@l(3) ; PC64LE9-NEXT: lfd 1, .LCPI54_1@toc@l(3)
; PC64LE9-NEXT: bl exp ; PC64LE9-NEXT: bl exp
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
▲ Show 20 Lines • Show All 177 Lines • ▼ Show 20 Lines
; PC64LE9-NEXT: bl exp2f ; PC64LE9-NEXT: bl exp2f
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI57_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI57_2@toc@ha
; PC64LE9-NEXT: fmr 30, 1 ; PC64LE9-NEXT: fmr 30, 1
; PC64LE9-NEXT: lfs 1, .LCPI57_2@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI57_2@toc@l(3)
; PC64LE9-NEXT: bl exp2f ; PC64LE9-NEXT: bl exp2f
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: addis 3, 2, .LCPI57_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI57_3@toc@l
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xscvdpspn 0, 30
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: xscvdpspn 0, 31
; PC64LE9-NEXT: addis 3, 2, .LCPI57_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI57_3@toc@l
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxvx 35, 0, 3
; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: addi 1, 1, 48
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_exp2_v3f64: ; PC64LE9-LABEL: constrained_vector_exp2_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: addis 3, 2, .LCPI58_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI58_0@toc@ha
; PC64LE9-NEXT: lfd 1, .LCPI58_0@toc@l(3)
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfd 1, .LCPI58_0@toc@l(3)
; PC64LE9-NEXT: bl exp2 ; PC64LE9-NEXT: bl exp2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI58_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI58_1@toc@ha
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfs 1, .LCPI58_1@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI58_1@toc@l(3)
; PC64LE9-NEXT: bl exp2 ; PC64LE9-NEXT: bl exp2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_exp2_v4f64: ; PC64LE9-LABEL: constrained_vector_exp2_v4f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: addis 3, 2, .LCPI59_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI59_0@toc@ha
; PC64LE9-NEXT: lfd 1, .LCPI59_0@toc@l(3)
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfd 1, .LCPI59_0@toc@l(3)
; PC64LE9-NEXT: bl exp2 ; PC64LE9-NEXT: bl exp2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI59_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI59_1@toc@ha
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfd 1, .LCPI59_1@toc@l(3) ; PC64LE9-NEXT: lfd 1, .LCPI59_1@toc@l(3)
; PC64LE9-NEXT: bl exp2 ; PC64LE9-NEXT: bl exp2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
▲ Show 20 Lines • Show All 177 Lines • ▼ Show 20 Lines
; PC64LE9-NEXT: bl logf ; PC64LE9-NEXT: bl logf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI62_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI62_2@toc@ha
; PC64LE9-NEXT: fmr 30, 1 ; PC64LE9-NEXT: fmr 30, 1
; PC64LE9-NEXT: lfs 1, .LCPI62_2@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI62_2@toc@l(3)
; PC64LE9-NEXT: bl logf ; PC64LE9-NEXT: bl logf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: addis 3, 2, .LCPI62_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI62_3@toc@l
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xscvdpspn 0, 30
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: xscvdpspn 0, 31
; PC64LE9-NEXT: addis 3, 2, .LCPI62_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI62_3@toc@l
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxvx 35, 0, 3
; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: addi 1, 1, 48
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_log_v3f64: ; PC64LE9-LABEL: constrained_vector_log_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: addis 3, 2, .LCPI63_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI63_0@toc@ha
; PC64LE9-NEXT: lfd 1, .LCPI63_0@toc@l(3)
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfd 1, .LCPI63_0@toc@l(3)
; PC64LE9-NEXT: bl log ; PC64LE9-NEXT: bl log
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI63_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI63_1@toc@ha
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfs 1, .LCPI63_1@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI63_1@toc@l(3)
; PC64LE9-NEXT: bl log ; PC64LE9-NEXT: bl log
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_log_v4f64: ; PC64LE9-LABEL: constrained_vector_log_v4f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: addis 3, 2, .LCPI64_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI64_0@toc@ha
; PC64LE9-NEXT: lfd 1, .LCPI64_0@toc@l(3)
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfd 1, .LCPI64_0@toc@l(3)
; PC64LE9-NEXT: bl log ; PC64LE9-NEXT: bl log
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI64_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI64_1@toc@ha
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfd 1, .LCPI64_1@toc@l(3) ; PC64LE9-NEXT: lfd 1, .LCPI64_1@toc@l(3)
; PC64LE9-NEXT: bl log ; PC64LE9-NEXT: bl log
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
▲ Show 20 Lines • Show All 177 Lines • ▼ Show 20 Lines
; PC64LE9-NEXT: bl log10f ; PC64LE9-NEXT: bl log10f
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI67_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI67_2@toc@ha
; PC64LE9-NEXT: fmr 30, 1 ; PC64LE9-NEXT: fmr 30, 1
; PC64LE9-NEXT: lfs 1, .LCPI67_2@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI67_2@toc@l(3)
; PC64LE9-NEXT: bl log10f ; PC64LE9-NEXT: bl log10f
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: addis 3, 2, .LCPI67_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI67_3@toc@l
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xscvdpspn 0, 30
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: xscvdpspn 0, 31
; PC64LE9-NEXT: addis 3, 2, .LCPI67_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI67_3@toc@l
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxvx 35, 0, 3
; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: addi 1, 1, 48
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_log10_v3f64: ; PC64LE9-LABEL: constrained_vector_log10_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: addis 3, 2, .LCPI68_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI68_0@toc@ha
; PC64LE9-NEXT: lfd 1, .LCPI68_0@toc@l(3)
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfd 1, .LCPI68_0@toc@l(3)
; PC64LE9-NEXT: bl log10 ; PC64LE9-NEXT: bl log10
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI68_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI68_1@toc@ha
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfs 1, .LCPI68_1@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI68_1@toc@l(3)
; PC64LE9-NEXT: bl log10 ; PC64LE9-NEXT: bl log10
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_log10_v4f64: ; PC64LE9-LABEL: constrained_vector_log10_v4f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: addis 3, 2, .LCPI69_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI69_0@toc@ha
; PC64LE9-NEXT: lfd 1, .LCPI69_0@toc@l(3)
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfd 1, .LCPI69_0@toc@l(3)
; PC64LE9-NEXT: bl log10 ; PC64LE9-NEXT: bl log10
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI69_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI69_1@toc@ha
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfd 1, .LCPI69_1@toc@l(3) ; PC64LE9-NEXT: lfd 1, .LCPI69_1@toc@l(3)
; PC64LE9-NEXT: bl log10 ; PC64LE9-NEXT: bl log10
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
▲ Show 20 Lines • Show All 177 Lines • ▼ Show 20 Lines
; PC64LE9-NEXT: bl log2f ; PC64LE9-NEXT: bl log2f
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI72_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI72_2@toc@ha
; PC64LE9-NEXT: fmr 30, 1 ; PC64LE9-NEXT: fmr 30, 1
; PC64LE9-NEXT: lfs 1, .LCPI72_2@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI72_2@toc@l(3)
; PC64LE9-NEXT: bl log2f ; PC64LE9-NEXT: bl log2f
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: addis 3, 2, .LCPI72_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI72_3@toc@l
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xscvdpspn 0, 30
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: xscvdpspn 0, 31
; PC64LE9-NEXT: addis 3, 2, .LCPI72_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI72_3@toc@l
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxvx 35, 0, 3
; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: addi 1, 1, 48
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_log2_v3f64: ; PC64LE9-LABEL: constrained_vector_log2_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: addis 3, 2, .LCPI73_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI73_0@toc@ha
; PC64LE9-NEXT: lfd 1, .LCPI73_0@toc@l(3)
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfd 1, .LCPI73_0@toc@l(3)
; PC64LE9-NEXT: bl log2 ; PC64LE9-NEXT: bl log2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI73_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI73_1@toc@ha
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfs 1, .LCPI73_1@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI73_1@toc@l(3)
; PC64LE9-NEXT: bl log2 ; PC64LE9-NEXT: bl log2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_log2_v4f64: ; PC64LE9-LABEL: constrained_vector_log2_v4f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: addis 3, 2, .LCPI74_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI74_0@toc@ha
; PC64LE9-NEXT: lfd 1, .LCPI74_0@toc@l(3)
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfd 1, .LCPI74_0@toc@l(3)
; PC64LE9-NEXT: bl log2 ; PC64LE9-NEXT: bl log2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI74_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI74_1@toc@ha
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 1, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: lfd 1, .LCPI74_1@toc@l(3) ; PC64LE9-NEXT: lfd 1, .LCPI74_1@toc@l(3)
; PC64LE9-NEXT: bl log2 ; PC64LE9-NEXT: bl log2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
▲ Show 20 Lines • Show All 321 Lines • ▼ Show 20 Lines
; PC64LE9-NEXT: bl nearbyintf ; PC64LE9-NEXT: bl nearbyintf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI82_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI82_2@toc@ha
; PC64LE9-NEXT: fmr 30, 1 ; PC64LE9-NEXT: fmr 30, 1
; PC64LE9-NEXT: lfs 1, .LCPI82_2@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI82_2@toc@l(3)
; PC64LE9-NEXT: bl nearbyintf ; PC64LE9-NEXT: bl nearbyintf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: addis 3, 2, .LCPI82_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI82_3@toc@l
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xscvdpspn 0, 30
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: xscvdpspn 0, 31
; PC64LE9-NEXT: addis 3, 2, .LCPI82_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI82_3@toc@l
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxvx 35, 0, 3
; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: addi 1, 1, 48
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
▲ Show 20 Lines • Show All 216 Lines • ▼ Show 20 Lines
; PC64LE9-NEXT: addis 3, 2, .LCPI87_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI87_2@toc@ha
; PC64LE9-NEXT: fmr 30, 1 ; PC64LE9-NEXT: fmr 30, 1
; PC64LE9-NEXT: lfs 1, .LCPI87_2@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI87_2@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI87_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI87_3@toc@ha
; PC64LE9-NEXT: lfs 2, .LCPI87_3@toc@l(3) ; PC64LE9-NEXT: lfs 2, .LCPI87_3@toc@l(3)
; PC64LE9-NEXT: bl fmaxf ; PC64LE9-NEXT: bl fmaxf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI87_4@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI87_4@toc@ha
; PC64LE9-NEXT: lfs 2, .LCPI87_4@toc@l(3)
; PC64LE9-NEXT: fmr 29, 1 ; PC64LE9-NEXT: fmr 29, 1
; PC64LE9-NEXT: fmr 1, 31 ; PC64LE9-NEXT: fmr 1, 31
; PC64LE9-NEXT: lfs 2, .LCPI87_4@toc@l(3)
; PC64LE9-NEXT: bl fmaxf ; PC64LE9-NEXT: bl fmaxf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: addis 3, 2, .LCPI87_5@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI87_5@toc@l
; PC64LE9-NEXT: lxvx 36, 0, 3
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 29 ; PC64LE9-NEXT: xscvdpspn 0, 29
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xscvdpspn 0, 30
; PC64LE9-NEXT: addis 3, 2, .LCPI87_5@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI87_5@toc@l
; PC64LE9-NEXT: lxvx 36, 0, 3
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 3, 2, 4 ; PC64LE9-NEXT: vperm 2, 3, 2, 4
; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: addi 1, 1, 64
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: addis 3, 2, .LCPI88_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI88_0@toc@ha
; PC64LE9-NEXT: lfs 1, .LCPI88_0@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI88_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI88_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI88_1@toc@ha
; PC64LE9-NEXT: lfs 2, .LCPI88_1@toc@l(3) ; PC64LE9-NEXT: lfs 2, .LCPI88_1@toc@l(3)
; PC64LE9-NEXT: bl fmax ; PC64LE9-NEXT: bl fmax
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI88_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI88_2@toc@ha
; PC64LE9-NEXT: fmr 3, 1
; PC64LE9-NEXT: addi 3, 3, .LCPI88_2@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI88_2@toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxvx 0, 0, 3
; PC64LE9-NEXT: addis 3, 2, .LCPI88_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI88_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI88_3@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI88_3@toc@l
; PC64LE9-NEXT: fmr 3, 1
; PC64LE9-NEXT: lxvx 1, 0, 3 ; PC64LE9-NEXT: lxvx 1, 0, 3
; PC64LE9-NEXT: xvmaxdp 2, 1, 0 ; PC64LE9-NEXT: xvmaxdp 2, 1, 0
; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: xxswapd 1, 2
; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1
; PC64LE9-NEXT: # kill: def $f2 killed $f2 killed $vsl2 ; PC64LE9-NEXT: # kill: def $f2 killed $f2 killed $vsl2
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
▲ Show 20 Lines • Show All 193 Lines • ▼ Show 20 Lines
; PC64LE9-NEXT: addis 3, 2, .LCPI92_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI92_2@toc@ha
; PC64LE9-NEXT: fmr 30, 1 ; PC64LE9-NEXT: fmr 30, 1
; PC64LE9-NEXT: lfs 1, .LCPI92_2@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI92_2@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI92_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI92_3@toc@ha
; PC64LE9-NEXT: lfs 2, .LCPI92_3@toc@l(3) ; PC64LE9-NEXT: lfs 2, .LCPI92_3@toc@l(3)
; PC64LE9-NEXT: bl fminf ; PC64LE9-NEXT: bl fminf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI92_4@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI92_4@toc@ha
; PC64LE9-NEXT: lfs 2, .LCPI92_4@toc@l(3)
; PC64LE9-NEXT: fmr 29, 1 ; PC64LE9-NEXT: fmr 29, 1
; PC64LE9-NEXT: fmr 1, 31 ; PC64LE9-NEXT: fmr 1, 31
; PC64LE9-NEXT: lfs 2, .LCPI92_4@toc@l(3)
; PC64LE9-NEXT: bl fminf ; PC64LE9-NEXT: bl fminf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: addis 3, 2, .LCPI92_5@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI92_5@toc@l
; PC64LE9-NEXT: lxvx 36, 0, 3
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 29 ; PC64LE9-NEXT: xscvdpspn 0, 29
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xscvdpspn 0, 30
; PC64LE9-NEXT: addis 3, 2, .LCPI92_5@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI92_5@toc@l
; PC64LE9-NEXT: lxvx 36, 0, 3
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 3, 2, 4 ; PC64LE9-NEXT: vperm 2, 3, 2, 4
; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: addi 1, 1, 64
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: addis 3, 2, .LCPI93_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI93_0@toc@ha
; PC64LE9-NEXT: lfs 1, .LCPI93_0@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI93_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI93_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI93_1@toc@ha
; PC64LE9-NEXT: lfs 2, .LCPI93_1@toc@l(3) ; PC64LE9-NEXT: lfs 2, .LCPI93_1@toc@l(3)
; PC64LE9-NEXT: bl fmin ; PC64LE9-NEXT: bl fmin
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI93_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI93_2@toc@ha
; PC64LE9-NEXT: fmr 3, 1
; PC64LE9-NEXT: addi 3, 3, .LCPI93_2@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI93_2@toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxvx 0, 0, 3
; PC64LE9-NEXT: addis 3, 2, .LCPI93_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI93_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI93_3@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI93_3@toc@l
; PC64LE9-NEXT: fmr 3, 1
; PC64LE9-NEXT: lxvx 1, 0, 3 ; PC64LE9-NEXT: lxvx 1, 0, 3
; PC64LE9-NEXT: xvmindp 2, 1, 0 ; PC64LE9-NEXT: xvmindp 2, 1, 0
; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: xxswapd 1, 2
; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1
; PC64LE9-NEXT: # kill: def $f2 killed $f2 killed $vsl2 ; PC64LE9-NEXT: # kill: def $f2 killed $f2 killed $vsl2
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
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llvm/test/CodeGen/X86/testb-je-fusion.ll

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; BRANCHFUSION_POSTRA-NEXT: # %bb.1: # %if.then ; BRANCHFUSION_POSTRA-NEXT: # %bb.1: # %if.then
; BRANCHFUSION_POSTRA-NEXT: movl $1, %eax ; BRANCHFUSION_POSTRA-NEXT: movl $1, %eax
; BRANCHFUSION_POSTRA-NEXT: .LBB2_2: # %if.end ; BRANCHFUSION_POSTRA-NEXT: .LBB2_2: # %if.end
; BRANCHFUSION_POSTRA-NEXT: retq ; BRANCHFUSION_POSTRA-NEXT: retq
; ;
; NOFUSION_MISCHEDPOSTRA-LABEL: macrofuse_alu_je: ; NOFUSION_MISCHEDPOSTRA-LABEL: macrofuse_alu_je:
; NOFUSION_MISCHEDPOSTRA: # %bb.0: # %entry ; NOFUSION_MISCHEDPOSTRA: # %bb.0: # %entry
; NOFUSION_MISCHEDPOSTRA-NEXT: movl %edi, %eax ; NOFUSION_MISCHEDPOSTRA-NEXT: movl %edi, %eax
; NOFUSION_MISCHEDPOSTRA-NEXT: addl $-512, %eax # imm = 0xFE00
; NOFUSION_MISCHEDPOSTRA-NEXT: movb $1, (%rsi) ; NOFUSION_MISCHEDPOSTRA-NEXT: movb $1, (%rsi)
; NOFUSION_MISCHEDPOSTRA-NEXT: addl $-512, %eax # imm = 0xFE00
; NOFUSION_MISCHEDPOSTRA-NEXT: je .LBB2_2 ; NOFUSION_MISCHEDPOSTRA-NEXT: je .LBB2_2
; NOFUSION_MISCHEDPOSTRA-NEXT: # %bb.1: # %if.then ; NOFUSION_MISCHEDPOSTRA-NEXT: # %bb.1: # %if.then
; NOFUSION_MISCHEDPOSTRA-NEXT: movl $1, %eax ; NOFUSION_MISCHEDPOSTRA-NEXT: movl $1, %eax
; NOFUSION_MISCHEDPOSTRA-NEXT: .LBB2_2: # %if.end ; NOFUSION_MISCHEDPOSTRA-NEXT: .LBB2_2: # %if.end
; NOFUSION_MISCHEDPOSTRA-NEXT: retq ; NOFUSION_MISCHEDPOSTRA-NEXT: retq
; ;
; BRANCHFUSIONONLY_MISCHEDPOSTRA-LABEL: macrofuse_alu_je: ; BRANCHFUSIONONLY_MISCHEDPOSTRA-LABEL: macrofuse_alu_je:
; BRANCHFUSIONONLY_MISCHEDPOSTRA: # %bb.0: # %entry ; BRANCHFUSIONONLY_MISCHEDPOSTRA: # %bb.0: # %entry
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: movl %edi, %eax ; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: movl %edi, %eax
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: addl $-512, %eax # imm = 0xFE00
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: movb $1, (%rsi) ; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: movb $1, (%rsi)
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: addl $-512, %eax # imm = 0xFE00
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: je .LBB2_2 ; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: je .LBB2_2
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: # %bb.1: # %if.then ; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: # %bb.1: # %if.then
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: movl $1, %eax ; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: movl $1, %eax
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: .LBB2_2: # %if.end ; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: .LBB2_2: # %if.end
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: retq ; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: retq
; ;
; MACROFUSION_MISCHEDPOSTRA-LABEL: macrofuse_alu_je: ; MACROFUSION_MISCHEDPOSTRA-LABEL: macrofuse_alu_je:
; MACROFUSION_MISCHEDPOSTRA: # %bb.0: # %entry ; MACROFUSION_MISCHEDPOSTRA: # %bb.0: # %entry
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; BRANCHFUSION_POSTRA-NEXT: # %bb.1: # %if.then ; BRANCHFUSION_POSTRA-NEXT: # %bb.1: # %if.then
; BRANCHFUSION_POSTRA-NEXT: movl $1, %eax ; BRANCHFUSION_POSTRA-NEXT: movl $1, %eax
; BRANCHFUSION_POSTRA-NEXT: .LBB3_2: # %if.end ; BRANCHFUSION_POSTRA-NEXT: .LBB3_2: # %if.end
; BRANCHFUSION_POSTRA-NEXT: retq ; BRANCHFUSION_POSTRA-NEXT: retq
; ;
; NOFUSION_MISCHEDPOSTRA-LABEL: macrofuse_dec_je: ; NOFUSION_MISCHEDPOSTRA-LABEL: macrofuse_dec_je:
; NOFUSION_MISCHEDPOSTRA: # %bb.0: # %entry ; NOFUSION_MISCHEDPOSTRA: # %bb.0: # %entry
; NOFUSION_MISCHEDPOSTRA-NEXT: movl %edi, %eax ; NOFUSION_MISCHEDPOSTRA-NEXT: movl %edi, %eax
; NOFUSION_MISCHEDPOSTRA-NEXT: decl %eax
; NOFUSION_MISCHEDPOSTRA-NEXT: movb $1, (%rsi) ; NOFUSION_MISCHEDPOSTRA-NEXT: movb $1, (%rsi)
; NOFUSION_MISCHEDPOSTRA-NEXT: decl %eax
; NOFUSION_MISCHEDPOSTRA-NEXT: je .LBB3_2 ; NOFUSION_MISCHEDPOSTRA-NEXT: je .LBB3_2
; NOFUSION_MISCHEDPOSTRA-NEXT: # %bb.1: # %if.then ; NOFUSION_MISCHEDPOSTRA-NEXT: # %bb.1: # %if.then
; NOFUSION_MISCHEDPOSTRA-NEXT: movl $1, %eax ; NOFUSION_MISCHEDPOSTRA-NEXT: movl $1, %eax
; NOFUSION_MISCHEDPOSTRA-NEXT: .LBB3_2: # %if.end ; NOFUSION_MISCHEDPOSTRA-NEXT: .LBB3_2: # %if.end
; NOFUSION_MISCHEDPOSTRA-NEXT: retq ; NOFUSION_MISCHEDPOSTRA-NEXT: retq
; ;
; BRANCHFUSIONONLY_MISCHEDPOSTRA-LABEL: macrofuse_dec_je: ; BRANCHFUSIONONLY_MISCHEDPOSTRA-LABEL: macrofuse_dec_je:
; BRANCHFUSIONONLY_MISCHEDPOSTRA: # %bb.0: # %entry ; BRANCHFUSIONONLY_MISCHEDPOSTRA: # %bb.0: # %entry
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: movl %edi, %eax ; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: movl %edi, %eax
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: decl %eax
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: movb $1, (%rsi) ; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: movb $1, (%rsi)
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: decl %eax
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: je .LBB3_2 ; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: je .LBB3_2
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: # %bb.1: # %if.then ; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: # %bb.1: # %if.then
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: movl $1, %eax ; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: movl $1, %eax
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: .LBB3_2: # %if.end ; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: .LBB3_2: # %if.end
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: retq ; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: retq
; ;
; MACROFUSION_MISCHEDPOSTRA-LABEL: macrofuse_dec_je: ; MACROFUSION_MISCHEDPOSTRA-LABEL: macrofuse_dec_je:
; MACROFUSION_MISCHEDPOSTRA: # %bb.0: # %entry ; MACROFUSION_MISCHEDPOSTRA: # %bb.0: # %entry
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llvm/test/CodeGen/X86/topdepthreduce-postra.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64 -enable-post-misched -run-pass=postmisched -o - %s | FileCheck %s
---
# Check that postmisched's TopDepthReduce heuristic moves the DEC32r later
# because of the dependency on eax
name: test
body: |
bb.0:
; CHECK-LABEL: name: test
; CHECK: $eax = MOV32rr killed $edi
; CHECK: MOV8mi killed renamable $rsi, 1, $noreg, 0, $noreg, 1 :: (store 1)
; CHECK: renamable $eax = DEC32r killed renamable $eax, implicit-def $eflags
$eax = MOV32rr $edi
renamable $eax = DEC32r killed renamable $eax, implicit-def $eflags
MOV8mi killed renamable $rsi, 1, $noreg, 0, $noreg, 1 :: (store 1)
...