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Differential D72307

[X86] Directly emit a BROADCAST_LOAD from constant pool in lowerUINT_TO_FP_vXi32 to avoid double loads seen in D71971
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Authored by craig.topper on Jan 6 2020, 3:15 PM.

Details

Reviewers
RKSimon
spatel
Commits
rG98c54fb1feba: [X86] Directly emit a BROADCAST_LOAD from constant pool in…
Summary

By directly emitting the constants as a constant pool load we seem to avoid the build_vector/extract_subvector combines that resulted in the duplicate loads we had before.

Diff Detail

Event Timeline

craig.topper created this revision.Jan 6 2020, 3:15 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 6 2020, 3:15 PM
Herald added a subscriber: hiraditya. · View Herald Transcript
RKSimon added inline comments.Jan 7 2020, 12:58 AM
llvm/lib/Target/X86/X86ISelLowering.cpp
19175

Could we avoid all this by using X86ISD::FOR instead?

RKSimon added inline comments.Jan 7 2020, 3:44 AM
llvm/lib/Target/X86/X86ISelLowering.cpp
19175

Turns out - no we can't, but this still seems a hacky way to fix this.

craig.topper marked an inline comment as done.Jan 9 2020, 6:12 PM
craig.topper added inline comments.
llvm/lib/Target/X86/X86ISelLowering.cpp
19175

I admit this is hacky. But its not the only place we are directly emitting loads pool operations during int->fp conversion. See also LowerUINT_TO_FP_i64, LowerUINT_TO_FP, and SelectionDAGLegalize::ExpandLegalINT_TO_FP

RKSimon accepted this revision.Jan 14 2020, 5:16 AM

OK - LGTM

This revision is now accepted and ready to land.Jan 14 2020, 5:16 AM
Closed by commit rG98c54fb1feba: [X86] Directly emit a BROADCAST_LOAD from constant pool in… (authored by craig.topper). · Explain WhyJan 14 2020, 10:53 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
X86/
14 lines
test/
CodeGen/
X86/
2 lines
48 lines
2 lines

Diff 238040

llvm/lib/Target/X86/X86ISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 19,152 Lines • ▼ Show 20 Lines if (Subtarget.hasAVX512()) {
if (IsStrict) if (IsStrict)
return DAG.getMergeValues({Res, Chain}, DL); return DAG.getMergeValues({Res, Chain}, DL);
return Res; return Res;
} }
if (Subtarget.hasAVX() && VecIntVT == MVT::v4i32 && if (Subtarget.hasAVX() && VecIntVT == MVT::v4i32 &&
Op->getSimpleValueType(0) == MVT::v4f64) { Op->getSimpleValueType(0) == MVT::v4f64) {
SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i64, V); SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i64, V);
SDValue VBias = Constant *Bias = ConstantFP::get(
DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), DL, MVT::v4f64); *DAG.getContext(),
APFloat(APFloat::IEEEdouble(), APInt(64, 0x4330000000000000ULL)));
auto PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
SDValue CPIdx = DAG.getConstantPool(Bias, PtrVT, /*Alignment*/ 8);
SDVTList Tys = DAG.getVTList(MVT::v4f64, MVT::Other);
SDValue Ops[] = {DAG.getEntryNode(), CPIdx};
SDValue VBias = DAG.getMemIntrinsicNode(
X86ISD::VBROADCAST_LOAD, DL, Tys, Ops, MVT::f64,
MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
/*Alignment*/ 8, MachineMemOperand::MOLoad);
SDValue Or = DAG.getNode(ISD::OR, DL, MVT::v4i64, ZExtIn, SDValue Or = DAG.getNode(ISD::OR, DL, MVT::v4i64, ZExtIn,
DAG.getBitcast(MVT::v4i64, VBias)); DAG.getBitcast(MVT::v4i64, VBias));
Or = DAG.getBitcast(MVT::v4f64, Or); Or = DAG.getBitcast(MVT::v4f64, Or);
RKSimonUnsubmitted
Not Done
ReplyInline Actions

Could we avoid all this by using X86ISD::FOR instead?

RKSimon: Could we avoid all this by using X86ISD::FOR instead?
RKSimonUnsubmitted
Not Done
ReplyInline Actions

Turns out - no we can't, but this still seems a hacky way to fix this.

RKSimon: Turns out - no we can't, but this still seems a hacky way to fix this.
craig.topperAuthorUnsubmitted
Done
ReplyInline Actions

I admit this is hacky. But its not the only place we are directly emitting loads pool operations during int->fp conversion. See also LowerUINT_TO_FP_i64, LowerUINT_TO_FP, and SelectionDAGLegalize::ExpandLegalINT_TO_FP

craig.topper: I admit this is hacky. But its not the only place we are directly emitting loads pool…
if (IsStrict) if (IsStrict)
return DAG.getNode(ISD::STRICT_FSUB, DL, {MVT::v4f64, MVT::Other}, return DAG.getNode(ISD::STRICT_FSUB, DL, {MVT::v4f64, MVT::Other},
{Op.getOperand(0), Or, VBias}); {Op.getOperand(0), Or, VBias});
return DAG.getNode(ISD::FSUB, DL, MVT::v4f64, Or, VBias); return DAG.getNode(ISD::FSUB, DL, MVT::v4f64, Or, VBias);
} }
// The algorithm is the following: // The algorithm is the following:
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llvm/test/CodeGen/X86/vec-strict-inttofp-256.ll

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define <4 x double> @uitofp_v4i32_v4f64(<4 x i32> %x) #0 { define <4 x double> @uitofp_v4i32_v4f64(<4 x i32> %x) #0 {
; AVX1-LABEL: uitofp_v4i32_v4f64: ; AVX1-LABEL: uitofp_v4i32_v4f64:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm1 = xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm1 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero ; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: vmovapd {{.*#+}} ymm1 = [4.503599627370496E+15,4.503599627370496E+15,4.503599627370496E+15,4.503599627370496E+15] ; AVX1-NEXT: vbroadcastsd {{.*#+}} ymm1 = [4.503599627370496E+15,4.503599627370496E+15,4.503599627370496E+15,4.503599627370496E+15]
; AVX1-NEXT: vorpd %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vorpd %ymm1, %ymm0, %ymm0
; AVX1-NEXT: vsubpd %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vsubpd %ymm1, %ymm0, %ymm0
; AVX1-NEXT: ret{{[l|q]}} ; AVX1-NEXT: ret{{[l|q]}}
; ;
; AVX2-LABEL: uitofp_v4i32_v4f64: ; AVX2-LABEL: uitofp_v4i32_v4f64:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero ; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [4.503599627370496E+15,4.503599627370496E+15,4.503599627370496E+15,4.503599627370496E+15] ; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [4.503599627370496E+15,4.503599627370496E+15,4.503599627370496E+15,4.503599627370496E+15]
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llvm/test/CodeGen/X86/vec_int_to_fp.ll

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; SSE41-LABEL: uitofp_4i32_to_2f64: ; SSE41-LABEL: uitofp_4i32_to_2f64:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: pmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero ; SSE41-NEXT: pmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [4.503599627370496E+15,4.503599627370496E+15] ; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [4.503599627370496E+15,4.503599627370496E+15]
; SSE41-NEXT: por %xmm1, %xmm0 ; SSE41-NEXT: por %xmm1, %xmm0
; SSE41-NEXT: subpd %xmm1, %xmm0 ; SSE41-NEXT: subpd %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; VEX-LABEL: uitofp_4i32_to_2f64: ; AVX1-LABEL: uitofp_4i32_to_2f64:
; VEX: # %bb.0: ; AVX1: # %bb.0:
; VEX-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero ; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; VEX-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0 ; AVX1-NEXT: vmovddup {{.*#+}} xmm1 = [4.503599627370496E+15,4.503599627370496E+15]
; VEX-NEXT: vsubpd {{.*}}(%rip), %xmm0, %xmm0 ; AVX1-NEXT: # xmm1 = mem[0,0]
; VEX-NEXT: retq ; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vsubpd %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: uitofp_4i32_to_2f64:
; AVX2: # %bb.0:
; AVX2-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX2-NEXT: vpbroadcastq {{.*#+}} xmm1 = [4.503599627370496E+15,4.503599627370496E+15]
; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vsubpd %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
; ;
; AVX512F-LABEL: uitofp_4i32_to_2f64: ; AVX512F-LABEL: uitofp_4i32_to_2f64:
; AVX512F: # %bb.0: ; AVX512F: # %bb.0:
; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0 ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX512F-NEXT: vcvtudq2pd %ymm0, %zmm0 ; AVX512F-NEXT: vcvtudq2pd %ymm0, %zmm0
; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
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; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: uitofp_4i32_to_4f64: ; AVX1-LABEL: uitofp_4i32_to_4f64:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm1 = xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm1 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero ; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: vmovapd {{.*#+}} ymm1 = [4.503599627370496E+15,4.503599627370496E+15,4.503599627370496E+15,4.503599627370496E+15] ; AVX1-NEXT: vbroadcastsd {{.*#+}} ymm1 = [4.503599627370496E+15,4.503599627370496E+15,4.503599627370496E+15,4.503599627370496E+15]
; AVX1-NEXT: vorpd %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vorpd %ymm1, %ymm0, %ymm0
; AVX1-NEXT: vsubpd %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vsubpd %ymm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: uitofp_4i32_to_4f64: ; AVX2-LABEL: uitofp_4i32_to_4f64:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero ; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [4.503599627370496E+15,4.503599627370496E+15,4.503599627370496E+15,4.503599627370496E+15] ; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [4.503599627370496E+15,4.503599627370496E+15,4.503599627370496E+15,4.503599627370496E+15]
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; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [4.503599627370496E+15,4.503599627370496E+15] ; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [4.503599627370496E+15,4.503599627370496E+15]
; SSE41-NEXT: por %xmm1, %xmm0 ; SSE41-NEXT: por %xmm1, %xmm0
; SSE41-NEXT: subpd %xmm1, %xmm0 ; SSE41-NEXT: subpd %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: uitofp_load_4i32_to_2f64_2: ; AVX1-LABEL: uitofp_load_4i32_to_2f64_2:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero ; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero
; AVX1-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0 ; AVX1-NEXT: vmovddup {{.*#+}} xmm1 = [4.503599627370496E+15,4.503599627370496E+15]
; AVX1-NEXT: vsubpd {{.*}}(%rip), %xmm0, %xmm0 ; AVX1-NEXT: # xmm1 = mem[0,0]
; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vsubpd %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: uitofp_load_4i32_to_2f64_2: ; AVX2-LABEL: uitofp_load_4i32_to_2f64_2:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero ; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
; AVX2-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0 ; AVX2-NEXT: vpbroadcastq {{.*#+}} xmm1 = [4.503599627370496E+15,4.503599627370496E+15]
; AVX2-NEXT: vsubpd {{.*}}(%rip), %xmm0, %xmm0 ; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vsubpd %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512F-LABEL: uitofp_load_4i32_to_2f64_2: ; AVX512F-LABEL: uitofp_load_4i32_to_2f64_2:
; AVX512F: # %bb.0: ; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovaps (%rdi), %xmm0 ; AVX512F-NEXT: vmovaps (%rdi), %xmm0
; AVX512F-NEXT: vcvtudq2pd %ymm0, %zmm0 ; AVX512F-NEXT: vcvtudq2pd %ymm0, %zmm0
; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
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; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [4.503599627370496E+15,4.503599627370496E+15] ; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [4.503599627370496E+15,4.503599627370496E+15]
; SSE41-NEXT: por %xmm1, %xmm0 ; SSE41-NEXT: por %xmm1, %xmm0
; SSE41-NEXT: subpd %xmm1, %xmm0 ; SSE41-NEXT: subpd %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: uitofp_volatile_load_4i32_to_2f64_2: ; AVX1-LABEL: uitofp_volatile_load_4i32_to_2f64_2:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero ; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero
; AVX1-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0 ; AVX1-NEXT: vmovddup {{.*#+}} xmm1 = [4.503599627370496E+15,4.503599627370496E+15]
; AVX1-NEXT: vsubpd {{.*}}(%rip), %xmm0, %xmm0 ; AVX1-NEXT: # xmm1 = mem[0,0]
; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vsubpd %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: uitofp_volatile_load_4i32_to_2f64_2: ; AVX2-LABEL: uitofp_volatile_load_4i32_to_2f64_2:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero ; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
; AVX2-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0 ; AVX2-NEXT: vpbroadcastq {{.*#+}} xmm1 = [4.503599627370496E+15,4.503599627370496E+15]
; AVX2-NEXT: vsubpd {{.*}}(%rip), %xmm0, %xmm0 ; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vsubpd %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512F-LABEL: uitofp_volatile_load_4i32_to_2f64_2: ; AVX512F-LABEL: uitofp_volatile_load_4i32_to_2f64_2:
; AVX512F: # %bb.0: ; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovaps (%rdi), %xmm0 ; AVX512F-NEXT: vmovaps (%rdi), %xmm0
; AVX512F-NEXT: vcvtudq2pd %ymm0, %zmm0 ; AVX512F-NEXT: vcvtudq2pd %ymm0, %zmm0
; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
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; ;
; AVX1-LABEL: uitofp_load_4i32_to_4f64: ; AVX1-LABEL: uitofp_load_4i32_to_4f64:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vmovdqa (%rdi), %xmm0 ; AVX1-NEXT: vmovdqa (%rdi), %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm1 = xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm1 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero ; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: vmovapd {{.*#+}} ymm1 = [4.503599627370496E+15,4.503599627370496E+15,4.503599627370496E+15,4.503599627370496E+15] ; AVX1-NEXT: vbroadcastsd {{.*#+}} ymm1 = [4.503599627370496E+15,4.503599627370496E+15,4.503599627370496E+15,4.503599627370496E+15]
; AVX1-NEXT: vorpd %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vorpd %ymm1, %ymm0, %ymm0
; AVX1-NEXT: vsubpd %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vsubpd %ymm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: uitofp_load_4i32_to_4f64: ; AVX2-LABEL: uitofp_load_4i32_to_4f64:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero ; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [4.503599627370496E+15,4.503599627370496E+15,4.503599627370496E+15,4.503599627370496E+15] ; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [4.503599627370496E+15,4.503599627370496E+15,4.503599627370496E+15,4.503599627370496E+15]
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llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll

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; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX1-LABEL: constrained_vector_uitofp_v4f64_v4i32: ; AVX1-LABEL: constrained_vector_uitofp_v4f64_v4i32:
; AVX1: # %bb.0: # %entry ; AVX1: # %bb.0: # %entry
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm1 = xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm1 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero ; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: vmovapd {{.*#+}} ymm1 = [4.503599627370496E+15,4.503599627370496E+15,4.503599627370496E+15,4.503599627370496E+15] ; AVX1-NEXT: vbroadcastsd {{.*#+}} ymm1 = [4.503599627370496E+15,4.503599627370496E+15,4.503599627370496E+15,4.503599627370496E+15]
; AVX1-NEXT: vorpd %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vorpd %ymm1, %ymm0, %ymm0
; AVX1-NEXT: vsubpd %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vsubpd %ymm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX512-LABEL: constrained_vector_uitofp_v4f64_v4i32: ; AVX512-LABEL: constrained_vector_uitofp_v4f64_v4i32:
; AVX512: # %bb.0: # %entry ; AVX512: # %bb.0: # %entry
; AVX512-NEXT: vmovaps %xmm0, %xmm0 ; AVX512-NEXT: vmovaps %xmm0, %xmm0
; AVX512-NEXT: vcvtudq2pd %ymm0, %zmm0 ; AVX512-NEXT: vcvtudq2pd %ymm0, %zmm0
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