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Differential D72245

[PoC][RISCV][LTO] Pass target-abi via module flag metadata
AbandonedPublic

Authored by khchen on Jan 5 2020, 9:42 PM.

Details

Reviewers
None
Summary
  1. Support ABI checking with per function target-features

if users don't specific -mattr, the default target-feature come from IR attribute.

  1. Enable LTO for RISCV
  2. add TargetMachine::initTargetOptions to overwirte MCOptions.ABINameaccording to module info

Diff Detail

Event Timeline

khchen created this revision.Jan 5 2020, 9:42 PM
Herald added projects: Restricted Project, Restricted Project. · View Herald TranscriptJan 5 2020, 9:42 PM
Herald added subscribers: llvm-commits, cfe-commits, luismarques and 33 others. · View Herald Transcript
khchen updated this revision to Diff 236296.Jan 5 2020, 9:51 PM
khchen updated this revision to Diff 237084.Jan 9 2020, 8:01 AM
khchen edited the summary of this revision. (Show Details)
evandro added a subscriber: evandro.Jan 9 2020, 8:37 AM
kito-cheng added a comment.Jan 9 2020, 8:46 AM

Seems like this patch mixed with LTO related changes? Could you clean it up?

khchen updated this revision to Diff 237114.Jan 9 2020, 9:37 AM

remote LTO related code.
this PoC include D70837 patch for generate correct code.

khchen added a subscriber: efriedma.Jan 12 2020, 5:45 PM

Hi @efriedma
Could you please guide me and review this PoC?
or take a look at this [[ take a look at | maillist ]] thread?
Thank you!

tejohnson added a subscriber: tejohnson.Jan 13 2020, 7:42 AM
tejohnson added inline comments.
llvm/lib/LTO/LTOBackend.cpp
151

This is going to be problematic. The Conf is a reference to the Config object saved on the LTO class instance shared by all backend invocations (the regular LTO module if one exists and any ThinLTO modules). They will end up clobbering each other's values here - although from the assert in initTargetOptions I see they are required to all have the same value anyway. Still, it is not good as the assert may actually be missed with unlucky interference between the threads. The Config object here should really be marked const, let me see if I can change that.

You could make a copy of the Config here, but that essentially misses the assertion completely.

A better way to do this would be in LTO::addModule, which is invoked serially to add each Module to the LTO object.

However - this misses other places that invoke createTargetMachine - should other places be looking at this new module flag as well? One example I can think of is the old LTO API (*LTOCodeGenerator.cpp files), used by linkers such as ld64 and some other proprietary linkers and the llvm-lto testing tool. But I have no idea about other invocations of createTargetMachine.

Note that changes to LTO.cpp/LTOBackend.cpp (the new LTO API) needs some kind of llvm-lto2 based test.

lenary added inline comments.Jan 13 2020, 8:21 AM
llvm/lib/LTO/LTOBackend.cpp
151

Thank you for this feedback.

I've been looking at how to add an overridable TargetMachine hook which is not dissimilar to this static function, but is overridable by TargetMachine subclasses. It sounds like this approach will also not work (unless the TargetMachine is allowed to update its (Default)Options in LTO without issue).

I am hoping to get a patch out today for review (which does not include the RISC-V specific parts of this patch, and only includes a default empty implementation), but I imagine it will remain unsatisfactory for LTO for the same reasons this is.

tejohnson added inline comments.Jan 13 2020, 8:34 AM
llvm/lib/LTO/LTOBackend.cpp
151

Presumably you could still do the same thing I'm suggesting here - validate and aggregate the value across modules in LTO::addModule. Then your hook would just check the aggregated setting on the Config.

lenary mentioned this in D72624: [WIP] TargetMachine Hook for Module Metadata.Jan 13 2020, 8:49 AM
lenary added inline comments.Jan 13 2020, 8:51 AM
llvm/lib/LTO/LTOBackend.cpp
151

D72624 is the patch I have prepared, noting I haven't had time to implement the aggregation yet, which suggests that patch's approach is too general.

tejohnson added inline comments.Jan 13 2020, 12:28 PM
llvm/lib/LTO/LTOBackend.cpp
151

FYI I committed a change to make the Config object passed down to the backends a const reference in d0aad9f56e1588effa94b15804b098e6307da6b4.

lenary added inline comments.Jan 14 2020, 3:26 AM
llvm/lib/LTO/LTOBackend.cpp
151

Thank you! It is useful to have this restriction explicit :)

kito-cheng mentioned this in D132843: [RISCV] Ensure target features get passed to the LTO linker for RISC-V.Sep 5 2022, 8:20 AM
khchen abandoned this revision.May 23 2023, 9:32 AM

I'm not working on RISC-V now and please reference https://reviews.llvm.org/D132843#3770454 to see the follow-up work.

Herald added a project: Restricted Project. · View Herald TranscriptMay 23 2023, 9:32 AM
Herald added subscribers: jobnoorman, luke, • pcwang-thead and 6 others. · View Herald Transcript
rkruppe removed a subscriber: rkruppe.May 23 2023, 1:40 PM
evandro removed a subscriber: evandro.May 23 2023, 3:04 PM

Revision Contents

PathSize
clang/
lib/
CodeGen/
7 lines
test/
CodeGen/
14 lines
llvm/
include/
llvm/
Target/
2 lines
lib/
LTO/
2 lines
Target/
RISCV/
AsmParser/
12 lines
14 lines
Utils/
11 lines
13 lines
test/
CodeGen/
RISCV/
24 lines
11 lines
26 lines
tools/
llc/
1 line

Diff 237114

clang/lib/CodeGen/CodeGenModule.cpp

Show First 20 Lines • Show All 531 Lines • ▼ Show 20 Lines if ( Arch == llvm::Triple::arm
|| Arch == llvm::Triple::armeb || Arch == llvm::Triple::armeb
|| Arch == llvm::Triple::thumb || Arch == llvm::Triple::thumb
|| Arch == llvm::Triple::thumbeb) { || Arch == llvm::Triple::thumbeb) {
// The minimum width of an enum in bytes // The minimum width of an enum in bytes
uint64_t EnumWidth = Context.getLangOpts().ShortEnums ? 1 : 4; uint64_t EnumWidth = Context.getLangOpts().ShortEnums ? 1 : 4;
getModule().addModuleFlag(llvm::Module::Error, "min_enum_size", EnumWidth); getModule().addModuleFlag(llvm::Module::Error, "min_enum_size", EnumWidth);
} }
if (Arch == llvm::Triple::riscv32 || Arch == llvm::Triple::riscv64) {
StringRef ABIStr = Target.getABI();
llvm::LLVMContext &Ctx = TheModule.getContext();
getModule().addModuleFlag(llvm::Module::Error, "target-abi",
llvm::MDString::get(Ctx, ABIStr));
}
if (CodeGenOpts.SanitizeCfiCrossDso) { if (CodeGenOpts.SanitizeCfiCrossDso) {
// Indicate that we want cross-DSO control flow integrity checks. // Indicate that we want cross-DSO control flow integrity checks.
getModule().addModuleFlag(llvm::Module::Override, "Cross-DSO CFI", 1); getModule().addModuleFlag(llvm::Module::Override, "Cross-DSO CFI", 1);
} }
if (LangOpts.Sanitize.has(SanitizerKind::CFIICall)) { if (LangOpts.Sanitize.has(SanitizerKind::CFIICall)) {
getModule().addModuleFlag(llvm::Module::Override, getModule().addModuleFlag(llvm::Module::Override,
"CFI Canonical Jump Tables", "CFI Canonical Jump Tables",
▲ Show 20 Lines • Show All 5,413 Lines • Show Last 20 Lines

clang/test/CodeGen/riscv-metadata.c

  • This file was added.
// RUN: %clang_cc1 -triple riscv32 -target-abi ilp32 -emit-llvm -o - %s | FileCheck -check-prefix=ILP32 %s
// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-abi ilp32f -emit-llvm -o - %s | FileCheck -check-prefix=ILP32F %s
// RUN: %clang_cc1 -triple riscv32 -target-feature +d -target-abi ilp32d -emit-llvm -o - %s | FileCheck -check-prefix=ILP32D %s
// RUN: %clang_cc1 -triple riscv64 -target-abi lp64 -emit-llvm -o - %s | FileCheck -check-prefix=LP64 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-abi lp64f -emit-llvm -o - %s | FileCheck -check-prefix=LP64F %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +d -target-abi lp64d -emit-llvm -o - %s | FileCheck -check-prefix=LP64D %s
// ILP32: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32"}
// ILP32F: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32f"}
// ILP32D: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32d"}
// LP64: !{{[0-9]+}} = !{i32 1, !"target-abi", !"lp64"}
// LP64F: !{{[0-9]+}} = !{i32 1, !"target-abi", !"lp64f"}
// LP64D: !{{[0-9]+}} = !{i32 1, !"target-abi", !"lp64d"}

llvm/include/llvm/Target/TargetMachine.h

Show First 20 Lines • Show All 179 Lines • ▼ Show 20 Lines unsigned getAllocaPointerSize() const {
return DL.getPointerSize(DL.getAllocaAddrSpace()); return DL.getPointerSize(DL.getAllocaAddrSpace());
} }
/// Reset the target options based on the function's attributes. /// Reset the target options based on the function's attributes.
// FIXME: Remove TargetOptions that affect per-function code generation // FIXME: Remove TargetOptions that affect per-function code generation
// from TargetMachine. // from TargetMachine.
void resetTargetOptions(const Function &F) const; void resetTargetOptions(const Function &F) const;
static void initTargetOptions(const Module &M, TargetOptions &Options);
/// Return target specific asm information. /// Return target specific asm information.
const MCAsmInfo *getMCAsmInfo() const { return AsmInfo.get(); } const MCAsmInfo *getMCAsmInfo() const { return AsmInfo.get(); }
const MCRegisterInfo *getMCRegisterInfo() const { return MRI.get(); } const MCRegisterInfo *getMCRegisterInfo() const { return MRI.get(); }
const MCInstrInfo *getMCInstrInfo() const { return MII.get(); } const MCInstrInfo *getMCInstrInfo() const { return MII.get(); }
const MCSubtargetInfo *getMCSubtargetInfo() const { return STI.get(); } const MCSubtargetInfo *getMCSubtargetInfo() const { return STI.get(); }
/// If intrinsic information is available, return it. If not, return null. /// If intrinsic information is available, return it. If not, return null.
▲ Show 20 Lines • Show All 201 Lines • Show Last 20 Lines

llvm/lib/LTO/LTOBackend.cpp

Show First 20 Lines • Show All 142 Lines • ▼ Show 20 Lines RelocModel =
M.getPICLevel() == PICLevel::NotPIC ? Reloc::Static : Reloc::PIC_; M.getPICLevel() == PICLevel::NotPIC ? Reloc::Static : Reloc::PIC_;
Optional<CodeModel::Model> CodeModel; Optional<CodeModel::Model> CodeModel;
if (Conf.CodeModel) if (Conf.CodeModel)
CodeModel = *Conf.CodeModel; CodeModel = *Conf.CodeModel;
else else
CodeModel = M.getCodeModel(); CodeModel = M.getCodeModel();
TargetMachine::initTargetOptions(M, Conf.Options);
tejohnsonUnsubmitted
Not Done
ReplyInline Actions

This is going to be problematic. The Conf is a reference to the Config object saved on the LTO class instance shared by all backend invocations (the regular LTO module if one exists and any ThinLTO modules). They will end up clobbering each other's values here - although from the assert in initTargetOptions I see they are required to all have the same value anyway. Still, it is not good as the assert may actually be missed with unlucky interference between the threads. The Config object here should really be marked const, let me see if I can change that.

You could make a copy of the Config here, but that essentially misses the assertion completely.

A better way to do this would be in LTO::addModule, which is invoked serially to add each Module to the LTO object.

However - this misses other places that invoke createTargetMachine - should other places be looking at this new module flag as well? One example I can think of is the old LTO API (*LTOCodeGenerator.cpp files), used by linkers such as ld64 and some other proprietary linkers and the llvm-lto testing tool. But I have no idea about other invocations of createTargetMachine.

Note that changes to LTO.cpp/LTOBackend.cpp (the new LTO API) needs some kind of llvm-lto2 based test.

tejohnson: This is going to be problematic. The Conf is a reference to the Config object saved on the LTO…
lenaryUnsubmitted
Not Done
ReplyInline Actions

Thank you for this feedback.

I've been looking at how to add an overridable TargetMachine hook which is not dissimilar to this static function, but is overridable by TargetMachine subclasses. It sounds like this approach will also not work (unless the TargetMachine is allowed to update its (Default)Options in LTO without issue).

I am hoping to get a patch out today for review (which does not include the RISC-V specific parts of this patch, and only includes a default empty implementation), but I imagine it will remain unsatisfactory for LTO for the same reasons this is.

lenary: Thank you for this feedback. I've been looking at how to add an overridable TargetMachine…
tejohnsonUnsubmitted
Not Done
ReplyInline Actions

Presumably you could still do the same thing I'm suggesting here - validate and aggregate the value across modules in LTO::addModule. Then your hook would just check the aggregated setting on the Config.

tejohnson: Presumably you could still do the same thing I'm suggesting here - validate and aggregate the…
lenaryUnsubmitted
Not Done
ReplyInline Actions

D72624 is the patch I have prepared, noting I haven't had time to implement the aggregation yet, which suggests that patch's approach is too general.

lenary: D72624 is the patch I have prepared, noting I haven't had time to implement the aggregation yet…
tejohnsonUnsubmitted
Not Done
ReplyInline Actions

FYI I committed a change to make the Config object passed down to the backends a const reference in d0aad9f56e1588effa94b15804b098e6307da6b4.

tejohnson: FYI I committed a change to make the Config object passed down to the backends a const…
lenaryUnsubmitted
Not Done
ReplyInline Actions

Thank you! It is useful to have this restriction explicit :)

lenary: Thank you! It is useful to have this restriction explicit :)
return std::unique_ptr<TargetMachine>(TheTarget->createTargetMachine( return std::unique_ptr<TargetMachine>(TheTarget->createTargetMachine(
TheTriple, Conf.CPU, Features.getString(), Conf.Options, RelocModel, TheTriple, Conf.CPU, Features.getString(), Conf.Options, RelocModel,
CodeModel, Conf.CGOptLevel)); CodeModel, Conf.CGOptLevel));
} }
static void runNewPMPasses(Config &Conf, Module &Mod, TargetMachine *TM, static void runNewPMPasses(Config &Conf, Module &Mod, TargetMachine *TM,
unsigned OptLevel, bool IsThinLTO, unsigned OptLevel, bool IsThinLTO,
ModuleSummaryIndex *ExportSummary, ModuleSummaryIndex *ExportSummary,
▲ Show 20 Lines • Show All 411 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Show First 20 Lines • Show All 182 Lines • ▼ Show 20 Lines#undef GET_OPERAND_DIAGNOSTIC_TYPES
RISCVAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser, RISCVAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
const MCInstrInfo &MII, const MCTargetOptions &Options) const MCInstrInfo &MII, const MCTargetOptions &Options)
: MCTargetAsmParser(Options, STI, MII) { : MCTargetAsmParser(Options, STI, MII) {
Parser.addAliasForDirective(".half", ".2byte"); Parser.addAliasForDirective(".half", ".2byte");
Parser.addAliasForDirective(".hword", ".2byte"); Parser.addAliasForDirective(".hword", ".2byte");
Parser.addAliasForDirective(".word", ".4byte"); Parser.addAliasForDirective(".word", ".4byte");
Parser.addAliasForDirective(".dword", ".8byte"); Parser.addAliasForDirective(".dword", ".8byte");
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
if (Options.ABIName.back() == 'f' &&
!getSTI().getFeatureBits()[RISCV::FeatureStdExtF]) {
errs() << "Hard-float 'f' ABI can't be used for a target that "
"doesn't support the F instruction set extension (ignoring "
"target-abi)\n";
} else if (Options.ABIName.back() == 'd' &&
!getSTI().getFeatureBits()[RISCV::FeatureStdExtD]) {
errs() << "Hard-float 'd' ABI can't be used for a target that "
"doesn't support the D instruction set extension (ignoring "
"target-abi)\n";
}
} }
}; };
/// RISCVOperand - Instances of this class represent a parsed machine /// RISCVOperand - Instances of this class represent a parsed machine
/// instruction /// instruction
struct RISCVOperand : public MCParsedAsmOperand { struct RISCVOperand : public MCParsedAsmOperand {
enum class KindTy { enum class KindTy {
▲ Show 20 Lines • Show All 1,667 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 LinesRISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
: TargetLowering(TM), Subtarget(STI) { : TargetLowering(TM), Subtarget(STI) {
if (Subtarget.isRV32E()) if (Subtarget.isRV32E())
report_fatal_error("Codegen not yet implemented for RV32E"); report_fatal_error("Codegen not yet implemented for RV32E");
RISCVABI::ABI ABI = Subtarget.getTargetABI(); RISCVABI::ABI ABI = Subtarget.getTargetABI();
assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialised target ABI"); assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialised target ABI");
if ((ABI == RISCVABI::ABI_ILP32F || ABI == RISCVABI::ABI_LP64F) &&
!Subtarget.hasStdExtF()) {
errs() << "Hard-float 'f' ABI can't be used for a target that "
"doesn't support the F instruction set extension (ignoring "
"target-abi)\n";
ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32;
} else if ((ABI == RISCVABI::ABI_ILP32D || ABI == RISCVABI::ABI_LP64D) &&
!Subtarget.hasStdExtD()) {
errs() << "Hard-float 'd' ABI can't be used for a target that "
"doesn't support the D instruction set extension (ignoring "
"target-abi)\n";
ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32;
}
switch (ABI) { switch (ABI) {
default: default:
report_fatal_error("Don't know how to lower this ABI"); report_fatal_error("Don't know how to lower this ABI");
case RISCVABI::ABI_ILP32: case RISCVABI::ABI_ILP32:
case RISCVABI::ABI_ILP32F: case RISCVABI::ABI_ILP32F:
case RISCVABI::ABI_ILP32D: case RISCVABI::ABI_ILP32D:
case RISCVABI::ABI_LP64: case RISCVABI::ABI_LP64:
case RISCVABI::ABI_LP64F: case RISCVABI::ABI_LP64F:
▲ Show 20 Lines • Show All 2,852 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp

Show All 31 LinesABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
} else if (ABIName.startswith("ilp32") && IsRV64) { } else if (ABIName.startswith("ilp32") && IsRV64) {
errs() << "32-bit ABIs are not supported for 64-bit targets (ignoring " errs() << "32-bit ABIs are not supported for 64-bit targets (ignoring "
"target-abi)\n"; "target-abi)\n";
TargetABI = ABI_Unknown; TargetABI = ABI_Unknown;
} else if (ABIName.startswith("lp64") && !IsRV64) { } else if (ABIName.startswith("lp64") && !IsRV64) {
errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring " errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring "
"target-abi)\n"; "target-abi)\n";
TargetABI = ABI_Unknown; TargetABI = ABI_Unknown;
} else if (ABIName.endswith("f") && !FeatureBits[RISCV::FeatureStdExtF]) {
errs() << "Hard-float 'f' ABI can't be used for a target that "
"doesn't support the F instruction set extension (ignoring "
"target-abi)\n";
TargetABI = ABI_Unknown;
} else if (ABIName.endswith("d") && !FeatureBits[RISCV::FeatureStdExtD]) {
errs() << "Hard-float 'd' ABI can't be used for a target that "
"doesn't support the D instruction set extension (ignoring "
"target-abi)\n";
TargetABI = ABI_Unknown;
} else if (IsRV32E && TargetABI != ABI_ILP32E && TargetABI != ABI_Unknown) { } else if (IsRV32E && TargetABI != ABI_ILP32E && TargetABI != ABI_Unknown) {
// TODO: move this checking to RISCVTargetLowering and RISCVAsmParser
errs() errs()
<< "Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n"; << "Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n";
TargetABI = ABI_Unknown; TargetABI = ABI_Unknown;
} }
if (TargetABI != ABI_Unknown) if (TargetABI != ABI_Unknown)
return TargetABI; return TargetABI;
Show All 28 Lines

llvm/lib/Target/TargetMachine.cpp

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Lines do { \
else \ else \
Options.X = DefaultOptions.X; \ Options.X = DefaultOptions.X; \
} while (0) } while (0)
RESET_OPTION(UnsafeFPMath, "unsafe-fp-math"); RESET_OPTION(UnsafeFPMath, "unsafe-fp-math");
RESET_OPTION(NoInfsFPMath, "no-infs-fp-math"); RESET_OPTION(NoInfsFPMath, "no-infs-fp-math");
RESET_OPTION(NoNaNsFPMath, "no-nans-fp-math"); RESET_OPTION(NoNaNsFPMath, "no-nans-fp-math");
RESET_OPTION(NoSignedZerosFPMath, "no-signed-zeros-fp-math"); RESET_OPTION(NoSignedZerosFPMath, "no-signed-zeros-fp-math");
TargetMachine::initTargetOptions(*F.getParent(), Options);
}
void TargetMachine::initTargetOptions(const Module &M, TargetOptions &Options) {
if (const MDString *ModuleTargetABI =
dyn_cast_or_null<MDString>(M.getModuleFlag("target-abi"))) {
if (Options.MCOptions.ABIName != "" &&
Options.MCOptions.ABIName != ModuleTargetABI->getString()) {
errs() << "warning: -target-abi option != target-abi module "
"flag(ignoring target-abi option)\n";
}
Options.MCOptions.ABIName = ModuleTargetABI->getString();
}
} }
/// Returns the code generation relocation model. The choices are static, PIC, /// Returns the code generation relocation model. The choices are static, PIC,
/// and dynamic-no-pic. /// and dynamic-no-pic.
Reloc::Model TargetMachine::getRelocationModel() const { return RM; } Reloc::Model TargetMachine::getRelocationModel() const { return RM; }
/// Returns the code model. The choices are small, kernel, medium, large, and /// Returns the code model. The choices are small, kernel, medium, large, and
/// target default. /// target default.
▲ Show 20 Lines • Show All 199 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/module-target-abi.ll

  • This file was added.
; RUN: llc -mtriple=riscv32 < %s 2>&1 \
; RUN: | FileCheck -check-prefix=DEFAULT %s
; RUN: llc -mtriple=riscv32 -target-abi ilp32 < %s 2>&1 \
; RUN: | FileCheck -check-prefix=RV32IF-ILP32 %s
; RUN: llc -mtriple=riscv32 -target-abi ilp32f < %s 2>&1 \
; RUN: | FileCheck -check-prefix=RV32IF-ILP32F %s
; RUN: llc -mtriple=riscv32 -filetype=obj < %s | llvm-readelf -h - | FileCheck -check-prefixes=FLAGS %s
; RV32IF-ILP32F: -target-abi option != target-abi module flag(ignoring target-abi option)
; FLAGS: Flags: 0x0
define float @foo(i32 %a) nounwind #0 {
; DEFAULT: # %bb.0:
; DEFAULT: fmv.x.w a0, ft0
; RV32IF-ILP32: # %bb.0:
; RV32IF-ILP32: fmv.x.w a0, ft0
%conv = sitofp i32 %a to float
ret float %conv
}
attributes #0 = { "target-features"="+f"}
!llvm.module.flags = !{!0}
!0 = !{i32 1, !"target-abi", !"ilp32"}

llvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll

; RUN: llc -mtriple=riscv32 -target-abi ilp32 < %s 2>&1 \ ; RUN: llc -mtriple=riscv32 -target-abi ilp32 < %s 2>&1 \
; RUN: | FileCheck -check-prefix=RV32IF-ILP32 %s ; RUN: | FileCheck -check-prefix=RV32IF-ILP32 %s
; RUN: llc -mtriple=riscv32 -target-abi ilp32f < %s 2>&1 \ ; RUN: llc -mtriple=riscv32 -target-abi ilp32f < %s 2>&1 \
; RUN: | FileCheck -check-prefix=RV32IF-ILP32F %s ; RUN: | FileCheck -check-prefix=RV32IF-ILP32F %s
; RUN: llc -mtriple=riscv32 -mattr=-f -target-abi ilp32f <%s 2>&1 \
; RUN: | FileCheck -check-prefix=RV32I-ILP32F-FAILED %s
; RV32I-ILP32F-FAILED: Hard-float 'f' ABI can't be used for a target that doesn't support the F instruction set extension
; RV32IF-ILP32F: Hard-float 'f' ABI can't be used for a target that doesn't support the F instruction set extension (ignoring target-abi)
define float @foo(i32 %a) nounwind #0 { define float @foo(i32 %a) nounwind #0 {
; RV32IF-ILP32: # %bb.0: ; RV32IF-ILP32: fcvt.s.w ft0, a0
; RV32IF-ILP32-NEXT: fcvt.s.w ft0, a0 ; RV32IF-ILP32-NEXT: fmv.x.w a0, ft0
; RV32IF-ILP32F: fcvt.s.w fa0, a0
; RV32IF-ILP32F-NEXT: ret
%conv = sitofp i32 %a to float %conv = sitofp i32 %a to float
ret float %conv ret float %conv
} }
attributes #0 = { "target-features"="+f"} attributes #0 = { "target-features"="+f"}

llvm/test/CodeGen/RISCV/subtarget-features-target-abi.ll

  • This file was added.
; RUN: llc -mtriple=riscv32 < %s 2>&1 \
; RUN: | FileCheck -check-prefix=DEFAULT %s
; RUN: llc -mtriple=riscv32 -target-abi ilp32 < %s 2>&1 \
; RUN: | FileCheck -check-prefix=RV32IF-ILP32 %s
; RUN: llc -mtriple=riscv32 -target-abi ilp32f < %s 2>&1 \
; RUN: | FileCheck -check-prefix=RV32IF-ILP32F %s
; RUN: llc -mtriple=riscv32 -filetype=obj < %s | llvm-readelf -h - | FileCheck -check-prefixes=FLAGS %s
; RV32IF-ILP32: -target-abi option != target-abi module flag(ignoring target-abi option)
; FLAGS: Flags: 0x2, single-float ABI
define float @foo(i32 %a) nounwind #0 {
; DEFAULT: # %bb.0:
; DEFAULT-NEXT: fcvt.s.w fa0, a0
; DEFAULT-NEXT: ret
; RV32IF-ILP32F: # %bb.0:
; RV32IF-ILP32F-NEXT: fcvt.s.w fa0, a0
; RV32IF-ILP32F-NEXT: ret
%conv = sitofp i32 %a to float
ret float %conv
}
attributes #0 = { "target-features"="+f"}
!llvm.module.flags = !{!0}
!0 = !{i32 1, !"target-abi", !"ilp32f"}

llvm/tools/llc/llc.cpp

Show First 20 Lines • Show All 449 Lines • ▼ Show 20 Linesstatic int compileModule(char **argv, LLVMContext &Context) {
TargetOptions Options = InitTargetOptionsFromCodeGenFlags(); TargetOptions Options = InitTargetOptionsFromCodeGenFlags();
Options.DisableIntegratedAS = NoIntegratedAssembler; Options.DisableIntegratedAS = NoIntegratedAssembler;
Options.MCOptions.ShowMCEncoding = ShowMCEncoding; Options.MCOptions.ShowMCEncoding = ShowMCEncoding;
Options.MCOptions.MCUseDwarfDirectory = EnableDwarfDirectory; Options.MCOptions.MCUseDwarfDirectory = EnableDwarfDirectory;
Options.MCOptions.AsmVerbose = AsmVerbose; Options.MCOptions.AsmVerbose = AsmVerbose;
Options.MCOptions.PreserveAsmComments = PreserveComments; Options.MCOptions.PreserveAsmComments = PreserveComments;
Options.MCOptions.IASSearchPaths = IncludeDirs; Options.MCOptions.IASSearchPaths = IncludeDirs;
Options.MCOptions.SplitDwarfFile = SplitDwarfFile; Options.MCOptions.SplitDwarfFile = SplitDwarfFile;
TargetMachine::initTargetOptions(*M, Options);
std::unique_ptr<TargetMachine> Target(TheTarget->createTargetMachine( std::unique_ptr<TargetMachine> Target(TheTarget->createTargetMachine(
TheTriple.getTriple(), CPUStr, FeaturesStr, Options, getRelocModel(), TheTriple.getTriple(), CPUStr, FeaturesStr, Options, getRelocModel(),
getCodeModel(), OLvl)); getCodeModel(), OLvl));
assert(Target && "Could not allocate target machine!"); assert(Target && "Could not allocate target machine!");
// If we don't have a module then just exit now. We do this down // If we don't have a module then just exit now. We do this down
▲ Show 20 Lines • Show All 172 Lines • Show Last 20 Lines