[PowerPC] Delete PPCSubtarget::isDarwin and isDarwinABI

[MaskRay]

Summary

http://lists.llvm.org/pipermail/llvm-dev/2018-August/125614.html developers have agreed to remove Darwin support from POWER backends.

[merge_guards_bot]

Unit tests: pass. 61167 tests passed, 0 failed and 728 were skipped.

clang-tidy: fail. Please fix clang-tidy findings.

clang-format: fail. Please format your changes with clang-format by running git-clang-format HEAD^ or applying this patch.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

[nemanjai]

The code you are modifying should be unreachable and should be safe to remove. However, can you please provide a description with some rationale about why you are removing this now. Namely, is there a pressing concern to get this removed soon or is this just a regular cleanup?

The reason I am asking is that we have started the work to remove all Darwin code from the PPC back end but have paused it for now as there are situations where the ongoing AIX implementation benefits from seeing how things were handled in Darwin due to some ABI similarities. Of course, this is convenience rather than necessity, so if you have some reason that necessitates removal of this code now, that definitely trumps the reasons I outlined above.

In any case, I am adding @cebowleratibm to the review as he is much more familiar with AIX concerns.

[MaskRay]

In D72067#1801141, @nemanjai wrote:

The code you are modifying should be unreachable and should be safe to remove. However, can you please provide a description with some rationale about why you are removing this now. Namely, is there a pressing concern to get this removed soon or is this just a regular cleanup?

The reason I am asking is that we have started the work to remove all Darwin code from the PPC back end but have paused it for now as there are situations where the ongoing AIX implementation benefits from seeing how things were handled in Darwin due to some ABI similarities. Of course, this is convenience rather than necessity, so if you have some reason that necessitates removal of this code now, that definitely trumps the reasons I outlined above.

In any case, I am adding @cebowleratibm to the review as he is much more familiar with AIX concerns.

No pressing concern. This is only a regular cleanup. Added the discussion to the summary.

From http://lists.llvm.org/pipermail/llvm-dev/2018-August/125614.html

• it looks like we're all now in agreement to move forward.

The remaining Darwin PPC code is for its reference purposes. As you can see from this patch, the code now has no test. Let's wait for @cebowleratibm's opinions.

[sfertile]

I think we should be safe removing the Darwin code in this patch, but Chris will know better.

The clang-format and clang-tidy comments are pretty cool, but whats expected when they show up on code that wasn't changed? We have a lot of code in the PowerPC directory which will trigger these. I've never bothered with cleaning that code up because I though keeping the history was more important than fixing the formatting. If these are going to be flooding every review though maybe its better we start to fix them.

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

488

if (Subtarget->is32BitELFABI() && isPositionIndependent())

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

1806

If the comment is correct, the proper check would be if (Subtarget.is32BitELFABI() && (...)). I believe @cebowleratibm should be able to clarify what AIX's behavior should be.

2178–2179

Comment needs to be updated.

2349–2350

Comment needs to be updated.

llvm/lib/Target/PowerPC/PPCSubtarget.cpp

147

I believe the member variable HasLazyResolverStubs should be dead with the Darwin removal. Likewise for PPCSubtarget::hasLazyResolverStub.

llvm/lib/Target/PowerPC/PPCSubtarget.h

297

minor nit: drop the (Non-DarwinABI) from the comment.

[MaskRay]

Address sfertile's review comments

[merge_guards_bot]

Unit tests: pass. 61174 tests passed, 0 failed and 729 were skipped.

clang-tidy: fail. Please fix clang-tidy findings.

clang-format: fail. Please format your changes with clang-format by running git-clang-format HEAD^ or applying this patch.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

[jsji]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

299

Why we still need to call stripRegisterPrefix here? Why not just

O << "0, ";

488

is32BitELFABI() is NOT equivalent of !Subtarget->isPPC64().
If we are going to do this for AIX, I would prefer we do it in another patch, not in this one.
This should be a NFC patch.

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

1806

Again, I think we should do the change for AIX in another patch, don't mix a NFC patch with some functional changes for AIX.

2351

Remove this as well?

llvm/test/CodeGen/PowerPC/2008-10-31-PPCF128Libcalls.ll

16

Why we are removing whole testcase? Can we just use llvm.sinl.ppcf128 instead?

[MaskRay]

Address jsji's comments

[merge_guards_bot]

Unit tests: pass. 61174 tests passed, 0 failed and 729 were skipped.

clang-tidy: fail. Please fix clang-tidy findings.

clang-format: fail. Please format your changes with clang-format by running git-clang-format HEAD^ or applying this patch.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

[MaskRay]

llvm/lib/Target/PowerPC/PPCSubtarget.cpp

147

It looks like PPCSubtarget::hasLazyResolverStub is the only member variable that is dead now. I'll delete related code.

llvm/test/CodeGen/PowerPC/2008-10-31-PPCF128Libcalls.ll

16

D50988 did

-target triple = "powerpc-apple-darwin10.0"
+target triple = "powerpc-unknown-linux-gnu"

*$LDBL128 is used exclusively by Darwin. We have more appropriate tests for ELF ppc_fp128 in ppc_fp128*.ll ppc_f128* and various other files.

[MaskRay]

Delete more code related to hasLazyResolverStub

[merge_guards_bot]

Unit tests: pass. 61174 tests passed, 0 failed and 729 were skipped.

clang-tidy: fail. Please fix clang-tidy findings.

clang-format: fail. Please format your changes with clang-format by running git-clang-format HEAD^ or applying this patch.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

[sfertile]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

488

I would argue that this code is dead on AIX due to the early check we have here and so the change is still NFC. Even if that is being too loose about what NFC means, I don't see any value in keeping a patch NFC if it means we have to add code we know to be wrong.

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

1806

You are right on this one. Either this code is correct for AIX and only the comment needs to be updated to reflect that, or the behavior is ELF 32-bit only and we need to update it in a separate patch. Either way we missed this in the review for our initial AIX frame lowering patch. If it is the latter let me land a patch to fix the behavior with testing before we commit this one, that way we don't add purposefully wrong code in this patch.

[jsji]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

488

:), OK.
But since we will need another patch for AIX below, maybe it is better to include this change within that AIX patch, they both are related to AIX logically.

llvm/test/CodeGen/PowerPC/2008-10-31-PPCF128Libcalls.ll

16

Sounds good.. Thanks.

[MaskRay]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

488

Include which change?

Shall I use !Subtarget->isPPC64() or Subtarget->is32BitELFABI()?

[jsji]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

488

:), I am talking to Sean. He mentioned let me land a patch to fix the behavior with testing before we commit this one, that way we don't add purposefully wrong code in this patch.
I meant he can change !Subtarget->isPPC64() to Subtarget->is32BitELFABI() in his AIX patch too.

Then you can rebase this patch.

[sfertile]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

488

Thanks for the suggestion Jinsong. I committed this as a standalone patch. The other change is going to take longer then I expected.

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

1806

The code is wrong for AIX. AIX has a dedicated area for saving the cr register in the linkage area similar to the 64-bit ELF ABIs. I wrote a mir test for testing crsaves, but it will crash on PowerPC64 because we create a CSRInfo with a bad frame index. Once I fix AIX's behaviour I suspect it will have the same problem. Unfortunately I'm going on vacation tomorrow and won't be able to fix this until after I get back.

[MaskRay]

Rebase + ping

[merge_guards_bot]

Unit tests: pass. 61767 tests passed, 0 failed and 780 were skipped.

clang-tidy: fail. Please fix clang-tidy findings.

clang-format: fail. Please format your changes with clang-format by running git-clang-format HEAD^ or applying this patch.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

[sfertile]

Thanks for doing this cleanup. LGTM.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

14762–14763

Minor nit: since we are touching this switch anyway we should format it as the Lint check suggests so we don't keep getting the warning in other patches touching this file.

llvm/lib/Target/PowerPC/PPCSubtarget.h

298

Ditto on the formatting.

[MaskRay]

Rebase. clang-format

[merge_guards_bot]

Unit tests: fail. 62057 tests passed, 1 failed and 784 were skipped.

failed: Clang.Driver/cc-print-options.c

clang-tidy: unknown.

clang-format: pass.

Build artifacts: diff.json, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

void PPCAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
 
   switch (MO.getType()) {
   case MachineOperand::MO_Register: {
     // The MI is INLINEASM ONLY and UseVSXReg is always false.
     const char *RegName = PPCInstPrinter::getRegisterName(MO.getReg());
 
     // Linux assembler (Others?) does not take register mnemonics.
     // FIXME - What about special registers used in mfspr/mtspr?
-    if (!Subtarget->isDarwin())
-      RegName = PPCRegisterInfo::stripRegisterPrefix(RegName);
-    O << RegName;
+    O << PPCRegisterInfo::stripRegisterPrefix(RegName);
     return;
   }
   case MachineOperand::MO_Immediate:
     O << MO.getImm();
     return;
 
   case MachineOperand::MO_MachineBasicBlock:
     MO.getMBB()->getSymbol()->print(O, MAI);
bool PPCAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
                                           raw_ostream &O) {
   if (ExtraCode && ExtraCode[0]) {
     if (ExtraCode[1] != 0) return true; // Unknown modifier.
 
     switch (ExtraCode[0]) {
     default: return true;  // Unknown modifier.
     case 'y': // A memory reference for an X-form instruction
       {
-        const char *RegName = "r0";
-        if (!Subtarget->isDarwin())
-          RegName = PPCRegisterInfo::stripRegisterPrefix(RegName);
-        O << RegName << ", ";
+        O << PPCRegisterInfo::stripRegisterPrefix("r0") << ", ";
         printOperand(MI, OpNo, O);
         return false;
       }
     case 'U': // Print 'u' for update form.
     case 'X': // Print 'x' for indexed form.
     {
       // FIXME: Currently for PowerPC memory operands are always loaded
       // into a register, so we never get an update or indexed form.
       // This is bad even for offset forms, since even if we know we
       // have a value in -16(r1), we will generate a load into r<n>
       // and then load from 0(r<n>).  Until that issue is fixed,
       // tolerate 'U' and 'X' but don't output anything.
       assert(MI->getOperand(OpNo).isReg());
       return false;
     }
     }
   }
 
   assert(MI->getOperand(OpNo).isReg());
   O << "0(";
   printOperand(MI, OpNo, O);
   O << ")";
   return false;
 }
assert(MI->getOperand(0).isReg() &&
          ((Subtarget->isPPC64() && MI->getOperand(0).getReg() == PPC::X3) ||
           (!Subtarget->isPPC64() && MI->getOperand(0).getReg() == PPC::R3)) &&
          "GETtls[ld]ADDR[32] must define GPR3");
   assert(MI->getOperand(1).isReg() &&
          ((Subtarget->isPPC64() && MI->getOperand(1).getReg() == PPC::X3) ||
           (!Subtarget->isPPC64() && MI->getOperand(1).getReg() == PPC::R3)) &&
          "GETtls[ld]ADDR[32] must read GPR3");
 
-  if (!Subtarget->isPPC64() && !Subtarget->isDarwin() &&
-      isPositionIndependent())
+  if (Subtarget->is32BitELFABI() && isPositionIndependent())
     Kind = MCSymbolRefExpr::VK_PLT;
   const MCExpr *TlsRef =
     MCSymbolRefExpr::create(TlsGetAddr, Kind, OutContext);
 
   // Add 32768 offset to the symbol so we follow up the latest GOT/PLT ABI.
   if (Kind == MCSymbolRefExpr::VK_PLT && Subtarget->isSecurePlt() &&
       M->getPICLevel() == PICLevel::BigPIC)
     TlsRef = MCBinaryExpr::createAdd(

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

 static const MCPhysReg VRRegNo[] = {
  PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
  PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
  PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
  PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
 };
 
 static unsigned computeReturnSaveOffset(const PPCSubtarget &STI) {
-  if (STI.isDarwinABI() || STI.isAIXABI())
+  if (STI.isAIXABI())
     return STI.isPPC64() ? 16 : 8;
   // SVR4 ABI:
   return STI.isPPC64() ? 16 : 4;
 }
 
 static unsigned computeTOCSaveOffset(const PPCSubtarget &STI) {
   if (STI.isAIXABI())
     return STI.isPPC64() ? 40 : 20;
   return STI.isELFv2ABI() ? 24 : 40;
 }
 
 static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI) {
-  // For the Darwin ABI:
-  // We cannot use the TOC save slot (offset +20) in the PowerPC linkage area
-  // for saving the frame pointer (if needed.)  While the published ABI has
-  // not used this slot since at least MacOSX 10.2, there is older code
-  // around that does use it, and that needs to continue to work.
-  if (STI.isDarwinABI())
-    return STI.isPPC64() ? -8U : -4U;
-
   // SVR4 ABI: First slot in the general register save area.
   return STI.isPPC64() ? -8U : -4U;
 }
 
 static unsigned computeLinkageSize(const PPCSubtarget &STI) {
-  if ((STI.isDarwinABI() || STI.isAIXABI()) || STI.isPPC64())
+  if (STI.isAIXABI() || STI.isPPC64())
     return (STI.isELFv2ABI() ? 4 : 6) * (STI.isPPC64() ? 8 : 4);
 
   // 32-bit SVR4 ABI:
   return 8;
 }
 
 static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI) {
-  if (STI.isDarwinABI())
-    return STI.isPPC64() ? -16U : -8U;
-
   // SVR4 ABI: First slot in the general register save area.
   return STI.isPPC64()
              ? -16U
              : STI.getTargetMachine().isPositionIndependent() ? -12U : -8U;
 }
 
 static unsigned computeCRSaveOffset() {
   // The condition register save offset needs to be updated for AIX PPC32.
   return 8;
 }
 
 PPCFrameLowering::PPCFrameLowering(const PPCSubtarget &STI)
     : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
                           STI.getPlatformStackAlignment(), 0),
       Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)),
       TOCSaveOffset(computeTOCSaveOffset(Subtarget)),
       FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)),
       LinkageSize(computeLinkageSize(Subtarget)),
       BasePointerSaveOffset(computeBasePointerSaveOffset(Subtarget)),
       CRSaveOffset(computeCRSaveOffset()) {}
 
 // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
 const PPCFrameLowering::SpillSlot *PPCFrameLowering::getCalleeSavedSpillSlots(
     unsigned &NumEntries) const {
-  if (Subtarget.isDarwinABI()) {
-    NumEntries = 1;
-    if (Subtarget.isPPC64()) {
-      static const SpillSlot darwin64Offsets = {PPC::X31, -8};
-      return &darwin64Offsets;
-    } else {
-      static const SpillSlot darwinOffsets = {PPC::R31, -4};
-      return &darwinOffsets;
-    }
-  }
-
   // Early exit if not using the SVR4 ABI.
   if (!Subtarget.isSVR4ABI()) {
     NumEntries = 0;
     return nullptr;
   }
 
   // Note that the offsets here overlap, but this is fixed up in
   // processFunctionBeforeFrameFinalized.
void PPCFrameLowering::emitPrologue(MachineFunction &MF,
   MachineModuleInfo &MMI = MF.getMMI();
   const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
   DebugLoc dl;
   bool needsCFI = MF.needsFrameMoves();
 
   // Get processor type.
   bool isPPC64 = Subtarget.isPPC64();
   // Get the ABI.
   bool isSVR4ABI = Subtarget.isSVR4ABI();
   bool isAIXABI = Subtarget.isAIXABI();
   bool isELFv2ABI = Subtarget.isELFv2ABI();
-  assert((Subtarget.isDarwinABI() || isSVR4ABI || isAIXABI) &&
-         "Unsupported PPC ABI.");
+  assert((isSVR4ABI || isAIXABI) && "Unsupported PPC ABI.");
 
   // Scan the prolog, looking for an UPDATE_VRSAVE instruction.  If we find it,
   // process it.
   if (!isSVR4ABI)
     for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
       if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
         if (isAIXABI)
           report_fatal_error("UPDATE_VRSAVE is unexpected on AIX.");
void PPCFrameLowering::determineCalleeSaves(MachineFunction &MF,
   //  Save and clear the LR state.
   PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
   unsigned LR = RegInfo->getRARegister();
   FI->setMustSaveLR(MustSaveLR(MF, LR));
   SavedRegs.reset(LR);
 
   //  Save R31 if necessary
   int FPSI = FI->getFramePointerSaveIndex();
   const bool isPPC64 = Subtarget.isPPC64();
-  const bool IsDarwinABI  = Subtarget.isDarwinABI();
   MachineFrameInfo &MFI = MF.getFrameInfo();
 
   // If the frame pointer save index hasn't been defined yet.
   if (!FPSI && needsFP(MF)) {
     // Find out what the fix offset of the frame pointer save area.
     int FPOffset = getFramePointerSaveOffset();
     // Allocate the frame index for frame pointer save area.
     FPSI = MFI.CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
void PPCFrameLowering::determineCalleeSaves(MachineFunction &MF,
   int TCSPDelta = 0;
   if (MF.getTarget().Options.GuaranteedTailCallOpt &&
       (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
     MFI.CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
   }
 
   // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
   // function uses CR 2, 3, or 4.
-  if (!isPPC64 && !IsDarwinABI &&
-      (SavedRegs.test(PPC::CR2) ||
-       SavedRegs.test(PPC::CR3) ||
+  if (Subtarget.is32BitELFABI() &&
+      (SavedRegs.test(PPC::CR2) || SavedRegs.test(PPC::CR3) ||
        SavedRegs.test(PPC::CR4))) {
     int FrameIdx = MFI.CreateFixedObject((uint64_t)4, (int64_t)-4, true);
     FI->setCRSpillFrameIndex(FrameIdx);
   }
 }
 
 void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
                                                        RegScavenger *RS) const {
   // Early exit if not using the SVR4 ABI.
PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
   MachineFunction *MF = MBB.getParent();
   const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
   PPCFunctionInfo *FI = MF->getInfo<PPCFunctionInfo>();
   bool MustSaveTOC = FI->mustSaveTOC();
   DebugLoc DL;
   bool CRSpilled = false;
   MachineInstrBuilder CRMIB;
 
   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
     unsigned Reg = CSI[i].getReg();
-    // Only Darwin actually uses the VRSAVE register, but it can still appear
-    // here if, for example, @llvm.eh.unwind.init() is used.  If we're not on
-    // Darwin, ignore it.
-    if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
+    // VRSAVE can appear here if, for example, @llvm.eh.unwind.init() is used.
+    if (Reg == PPC::VRSAVE)
       continue;
 
     // CR2 through CR4 are the nonvolatile CR fields.
     bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
 
     // Add the callee-saved register as live-in; it's killed at the spill.
     // Do not do this for callee-saved registers that are live-in to the
     // function because they will already be marked live-in and this will be
PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
   // Initialize insertion-point logic; we will be restoring in reverse
   // order of spill.
   MachineBasicBlock::iterator I = MI, BeforeI = I;
   bool AtStart = I == MBB.begin();
 
   if (!AtStart)
     --BeforeI;
 
   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
     unsigned Reg = CSI[i].getReg();
 
-    // Only Darwin actually uses the VRSAVE register, but it can still appear
-    // here if, for example, @llvm.eh.unwind.init() is used.  If we're not on
+    // VRSAVE can appear here if, for example, @llvm.eh.unwind.init() is used.
     // Darwin, ignore it.
-    if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
+    if (Reg == PPC::VRSAVE)
       continue;
 
     if ((Reg == PPC::X2 || Reg == PPC::R2) && MustSaveTOC)
       continue;
 
     if (Reg == PPC::CR2) {
       CR2Spilled = true;
       // The spill slot is associated only with CR2, which is the

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

case ISD::BRIND: {
     unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8;
     Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, Target,
                                            Chain), 0);
     CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);
     return;
   }
   case PPCISD::TOC_ENTRY: {
     const bool isPPC64 = PPCSubTarget->isPPC64();
     const bool isELFABI = PPCSubTarget->isSVR4ABI();
     const bool isAIXABI = PPCSubTarget->isAIXABI();
 
-    assert(!PPCSubTarget->isDarwin() && "TOC is an ELF/XCOFF construct");
-
     // PowerPC only support small, medium and large code model.
     const CodeModel::Model CModel = TM.getCodeModel();
     assert(!(CModel == CodeModel::Tiny || CModel == CodeModel::Kernel) &&
            "PowerPC doesn't support tiny or kernel code models.");
 
     if (isAIXABI && CModel == CodeModel::Medium)
       report_fatal_error("Medium code model is not supported on AIX.");
 
while (Position != CurDAG->allnodes_begin()) {
 
     ReplaceUses(N, Op32.getNode());
   }
 
   if (MadeChange)
     CurDAG->RemoveDeadNodes();
 }
 
 void PPCDAGToDAGISel::PeepholePPC64() {
-  // These optimizations are currently supported only for 64-bit SVR4.
-  if (PPCSubTarget->isDarwin() || !PPCSubTarget->isPPC64())
-    return;
-
   SelectionDAG::allnodes_iterator Position = CurDAG->allnodes_end();
 
   while (Position != CurDAG->allnodes_begin()) {
     SDNode *N = &*--Position;
     // Skip dead nodes and any non-machine opcodes.
     if (N->use_empty() || !N->isMachineOpcode())
       continue;
 

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

if (TM.Options.UnsafeFPMath) {
     setTargetDAGCombine(ISD::FSQRT);
   }
 
   if (Subtarget.hasP9Altivec()) {
     setTargetDAGCombine(ISD::ABS);
     setTargetDAGCombine(ISD::VSELECT);
   }
 
-  // Darwin long double math library functions have $LDBL128 appended.
-  if (Subtarget.isDarwin()) {
-    setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
-    setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
-    setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
-    setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
-    setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
-    setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
-    setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
-    setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
-    setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
-    setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
-  }
-
   if (EnableQuadPrecision) {
     setLibcallName(RTLIB::LOG_F128, "logf128");
     setLibcallName(RTLIB::LOG2_F128, "log2f128");
     setLibcallName(RTLIB::LOG10_F128, "log10f128");
     setLibcallName(RTLIB::EXP_F128, "expf128");
     setLibcallName(RTLIB::EXP2_F128, "exp2f128");
     setLibcallName(RTLIB::SIN_F128, "sinf128");
     setLibcallName(RTLIB::COS_F128, "cosf128");
     setLibcallName(RTLIB::POW_F128, "powf128");
     setLibcallName(RTLIB::FMIN_F128, "fminf128");
     setLibcallName(RTLIB::FMAX_F128, "fmaxf128");
     setLibcallName(RTLIB::POWI_F128, "__powikf2");
     setLibcallName(RTLIB::REM_F128, "fmodf128");
   }
 
   // With 32 condition bits, we don't need to sink (and duplicate) compares
   // aggressively in CodeGenPrep.
   if (Subtarget.useCRBits()) {
     setHasMultipleConditionRegisters();
     setJumpIsExpensive();
   }
 
   setMinFunctionAlignment(Align(4));
-  if (Subtarget.isDarwin())
-    setPrefFunctionAlignment(Align(16));
 
   switch (Subtarget.getCPUDirective()) {
   default: break;
   case PPC::DIR_970:
   case PPC::DIR_A2:
   case PPC::DIR_E500:
   case PPC::DIR_E500mc:
   case PPC::DIR_E5500:
if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
     }
   }
 }
 
 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
 /// function arguments in the caller parameter area.
 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty,
                                                   const DataLayout &DL) const {
-  // Darwin passes everything on 4 byte boundary.
-  if (Subtarget.isDarwin())
-    return 4;
-
   // 16byte and wider vectors are passed on 16byte boundary.
   // The rest is 8 on PPC64 and 4 on PPC32 boundary.
   unsigned Align = Subtarget.isPPC64() ? 8 : 4;
   if (Subtarget.hasAltivec() || Subtarget.hasQPX())
     getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
   return Align;
 }
 
SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
   return CallResult.second;
 }
 
 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
   MachineFunction &MF = DAG.getMachineFunction();
   PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
   EVT PtrVT = getPointerTy(MF.getDataLayout());
 
   SDLoc dl(Op);
 
-  if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
+  if (Subtarget.isPPC64()) {
     // vastart just stores the address of the VarArgsFrameIndex slot into the
     // memory location argument.
     SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
     const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
     return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
                         MachinePointerInfo(SV));
   }
 
if (SPDiff) {
     int SlotSize = isPPC64 ? 8 : 4;
     int NewRetAddrLoc = SPDiff + FL->getReturnSaveOffset();
     int NewRetAddr = MF.getFrameInfo().CreateFixedObject(SlotSize,
                                                          NewRetAddrLoc, true);
     EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
     SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
     Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
                          MachinePointerInfo::getFixedStack(MF, NewRetAddr));
-
-    // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
-    // slot as the FP is never overwritten.
-    if (Subtarget.isDarwinABI()) {
-      int NewFPLoc = SPDiff + FL->getFramePointerSaveOffset();
-      int NewFPIdx = MF.getFrameInfo().CreateFixedObject(SlotSize, NewFPLoc,
-                                                         true);
-      SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
-      Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
-                           MachinePointerInfo::getFixedStack(
-                               DAG.getMachineFunction(), NewFPIdx));
-    }
   }
   return Chain;
 }
 
 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
 /// the position of the argument.
 static void
 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(
     SelectionDAG &DAG, int SPDiff, SDValue Chain, SDValue &LROpOut,
     SDValue &FPOpOut, const SDLoc &dl) const {
   if (SPDiff) {
     // Load the LR and FP stack slot for later adjusting.
     EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
     LROpOut = getReturnAddrFrameIndex(DAG);
     LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo());
     Chain = SDValue(LROpOut.getNode(), 1);
-
-    // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
-    // slot as the FP is never overwritten.
-    if (Subtarget.isDarwinABI()) {
-      FPOpOut = getFramePointerFrameIndex(DAG);
-      FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo());
-      Chain = SDValue(FPOpOut.getNode(), 1);
-    }
   }
   return Chain;
 }
 
 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
 /// by "Src" to address "Dst" of size "Size".  Alignment information is
 /// specified by the specific parameter attribute. The copy will be passed as
 /// a byval function parameter.
FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
                             FrameAddr, MachinePointerInfo());
   return FrameAddr;
 }
 
 // FIXME? Maybe this could be a TableGen attribute on some registers and
 // this table could be generated automatically from RegInfo.
 Register PPCTargetLowering::getRegisterByName(const char* RegName, EVT VT,
                                               const MachineFunction &MF) const {
   bool isPPC64 = Subtarget.isPPC64();
-  bool IsDarwinABI = Subtarget.isDarwinABI();
 
   if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
       (!isPPC64 && VT != MVT::i32))
     report_fatal_error("Invalid register global variable type");
 
   bool is64Bit = isPPC64 && VT == MVT::i64;
   Register Reg = StringSwitch<Register>(RegName)
                    .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
-                   .Case("r2", (IsDarwinABI || isPPC64) ? Register() : PPC::R2)
-                   .Case("r13", (!isPPC64 && IsDarwinABI) ? Register() :
-                                  (is64Bit ? PPC::X13 : PPC::R13))
+                   .Case("r2", isPPC64 ? Register() : PPC::R2)
+                   .Case("r13", (is64Bit ? PPC::X13 : PPC::R13))
                    .Default(Register());
 
   if (Reg)
     return Reg;
   report_fatal_error("Invalid register name global variable");
 }
 
 bool PPCTargetLowering::isAccessedAsGotIndirect(SDValue GA) const {

 // Create a fast isel object.
 FastISel *
 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
                                   const TargetLibraryInfo *LibInfo) const {
   return PPC::createFastISel(FuncInfo, LibInfo);
 }
 
 void PPCTargetLowering::initializeSplitCSR(MachineBasicBlock *Entry) const {
-  if (Subtarget.isDarwinABI()) return;
   if (!Subtarget.isPPC64()) return;
 
   // Update IsSplitCSR in PPCFunctionInfo
   PPCFunctionInfo *PFI = Entry->getParent()->getInfo<PPCFunctionInfo>();
   PFI->setIsSplitCSR(true);
 }
 
 void PPCTargetLowering::insertCopiesSplitCSR(

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
   if (MF->getFunction().getCallingConv() == CallingConv::AnyReg) {
     if (Subtarget.hasVSX())
       return CSR_64_AllRegs_VSX_SaveList;
     if (Subtarget.hasAltivec())
       return CSR_64_AllRegs_Altivec_SaveList;
     return CSR_64_AllRegs_SaveList;
   }
 
-  if (Subtarget.isDarwinABI())
-    return TM.isPPC64()
-               ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_SaveList
-                                         : CSR_Darwin64_SaveList)
-               : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_SaveList
-                                         : CSR_Darwin32_SaveList);
-
   if (TM.isPPC64() && MF->getInfo<PPCFunctionInfo>()->isSplitCSR())
     return CSR_SRV464_TLS_PE_SaveList;
 
   // On PPC64, we might need to save r2 (but only if it is not reserved).
   bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2);
 
   // Cold calling convention CSRs.
   if (MF->getFunction().getCallingConv() == CallingConv::Cold) {
else if (Subtarget.hasSPE())
     return CSR_SVR432_SPE_SaveList;
   return CSR_SVR432_SaveList;
 }
 
 const MCPhysReg *
 PPCRegisterInfo::getCalleeSavedRegsViaCopy(const MachineFunction *MF) const {
   assert(MF && "Invalid MachineFunction pointer.");
   const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
-  if (Subtarget.isDarwinABI())
-    return nullptr;
   if (!TM.isPPC64())
     return nullptr;
   if (MF->getFunction().getCallingConv() != CallingConv::CXX_FAST_TLS)
     return nullptr;
   if (!MF->getInfo<PPCFunctionInfo>()->isSplitCSR())
     return nullptr;
 
   // On PPC64, we might need to save r2 (but only if it is not reserved).
PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
   if (CC == CallingConv::AnyReg) {
     if (Subtarget.hasVSX())
       return CSR_64_AllRegs_VSX_RegMask;
     if (Subtarget.hasAltivec())
       return CSR_64_AllRegs_Altivec_RegMask;
     return CSR_64_AllRegs_RegMask;
   }
 
-  if (Subtarget.isDarwinABI())
-    return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_RegMask
-                                                  : CSR_Darwin64_RegMask)
-                        : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_RegMask
-                                                  : CSR_Darwin32_RegMask);
   if (Subtarget.isAIXABI()) {
     assert(!Subtarget.hasAltivec() && "Altivec is not implemented on AIX yet.");
     return TM.isPPC64() ? CSR_AIX64_RegMask : CSR_AIX32_RegMask;
   }
 
   if (CC == CallingConv::Cold) {
     return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR64_ColdCC_Altivec_RegMask
                                                   : CSR_SVR64_ColdCC_RegMask)
BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   markSuperRegs(Reserved, PPC::CTR);
   markSuperRegs(Reserved, PPC::CTR8);
 
   markSuperRegs(Reserved, PPC::R1);
   markSuperRegs(Reserved, PPC::LR);
   markSuperRegs(Reserved, PPC::LR8);
   markSuperRegs(Reserved, PPC::RM);
 
-  if (!Subtarget.isDarwinABI() || !Subtarget.hasAltivec())
-    markSuperRegs(Reserved, PPC::VRSAVE);
 
   // The SVR4 ABI reserves r2 and r13
   if (Subtarget.isSVR4ABI()) {
     // We only reserve r2 if we need to use the TOC pointer. If we have no
     // explicit uses of the TOC pointer (meaning we're a leaf function with
     // no constant-pool loads, etc.) and we have no potential uses inside an
     // inline asm block, then we can treat r2 has an ordinary callee-saved
     // register.

llvm/lib/Target/PowerPC/PPCSubtarget.h

public:
   bool isQPXStackUnaligned() const { return IsQPXStackUnaligned; }
   Align getPlatformStackAlignment() const {
     if ((hasQPX() || isBGQ()) && !isQPXStackUnaligned())
       return Align(32);
 
     return Align(16);
   }
 
-  // DarwinABI has a 224-byte red zone. PPC32 SVR4ABI(Non-DarwinABI) has no
-  // red zone and PPC64 SVR4ABI has a 288-byte red zone.
+  // PPC32 SVR4ABI has no red zone and PPC64 SVR4ABI has a 288-byte red zone.
   unsigned  getRedZoneSize() const {
-    return isDarwinABI() ? 224 : (isPPC64() ? 288 : 0);
+    return isPPC64() ? 288 : 0;
   }
 
   bool hasHTM() const { return HasHTM; }
   bool hasFloat128() const { return HasFloat128; }
   bool isISA3_0() const { return IsISA3_0; }
   bool useLongCalls() const { return UseLongCalls; }
   bool needsSwapsForVSXMemOps() const {
     return hasVSX() && isLittleEndian() && !hasP9Vector();
   }
 
   POPCNTDKind hasPOPCNTD() const { return HasPOPCNTD; }
 
   const Triple &getTargetTriple() const { return TargetTriple; }
 
-  /// isDarwin - True if this is any darwin platform.
-  bool isDarwin() const { return TargetTriple.isMacOSX(); }
   /// isBGQ - True if this is a BG/Q platform.
   bool isBGQ() const { return TargetTriple.getVendor() == Triple::BGQ; }
 
   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
 
-  bool isDarwinABI() const { return isTargetMachO() || isDarwin(); }
   bool isAIXABI() const { return TargetTriple.isOSAIX(); }
-  bool isSVR4ABI() const { return !isDarwinABI() && !isAIXABI(); }
+  bool isSVR4ABI() const { return !isAIXABI(); }
   bool isELFv2ABI() const;
 
   bool is64BitELFABI() const { return  isSVR4ABI() && isPPC64(); }
   bool is32BitELFABI() const { return  isSVR4ABI() && !isPPC64(); }
 
   /// Originally, this function return hasISEL(). Now we always enable it,
   /// but may expand the ISEL instruction later.
   bool enableEarlyIfConversion() const override { return true; }

llvm/lib/Target/PowerPC/PPCSubtarget.cpp

void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
   // Parse features string.
   ParseSubtargetFeatures(CPUName, FS);
 
   // If the user requested use of 64-bit regs, but the cpu selected doesn't
   // support it, ignore.
   if (IsPPC64 && has64BitSupport())
     Use64BitRegs = true;
 
-  // Set up darwin-specific properties.
-  if (isDarwin())
-    HasLazyResolverStubs = true;
-
   if ((TargetTriple.isOSFreeBSD() && TargetTriple.getOSMajorVersion() >= 13) ||
       TargetTriple.isOSNetBSD() || TargetTriple.isOSOpenBSD() ||
       TargetTriple.isMusl())
     SecurePlt = true;
 
   if (HasSPE && IsPPC64)
     report_fatal_error( "SPE is only supported for 32-bit targets.\n", false);
   if (HasSPE && (HasAltivec || HasQPX || HasVSX || HasFPU))

llvm/test/CodeGen/PowerPC/2008-10-31-PPCF128Libcalls.ll

-; RUN: llc -verify-machineinstrs < %s
-; PR2988
-target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
-target triple = "powerpc-unknown-linux-gnu"
-@a = common global ppc_fp128 0xM00000000000000000000000000000000, align 16    ; <ppc_fp128*> [#uses=2]
-@b = common global ppc_fp128 0xM00000000000000000000000000000000, align 16    ; <ppc_fp128*> [#uses=2]
-@c = common global ppc_fp128 0xM00000000000000000000000000000000, align 16    ; <ppc_fp128*> [#uses=3]
-@d = common global ppc_fp128 0xM00000000000000000000000000000000, align 16    ; <ppc_fp128*> [#uses=2]
-
-define void @foo() nounwind {
-entry:
-  %0 = load ppc_fp128, ppc_fp128* @a, align 16    ; <ppc_fp128> [#uses=1]
-  %1 = call ppc_fp128 @llvm.sqrt.ppcf128(ppc_fp128 %0)    ; <ppc_fp128> [#uses=1]
-  store ppc_fp128 %1, ppc_fp128* @a, align 16
-  %2 = load ppc_fp128, ppc_fp128* @b, align 16    ; <ppc_fp128> [#uses=1]
-  %3 = call ppc_fp128 @"\01_sinl$LDBL128"(ppc_fp128 %2) nounwind readonly    ; <ppc_fp128> [#uses=1]
-  store ppc_fp128 %3, ppc_fp128* @b, align 16
-  %4 = load ppc_fp128, ppc_fp128* @c, align 16    ; <ppc_fp128> [#uses=1]
-  %5 = call ppc_fp128 @"\01_cosl$LDBL128"(ppc_fp128 %4) nounwind readonly    ; <ppc_fp128> [#uses=1]
-  store ppc_fp128 %5, ppc_fp128* @c, align 16
-  %6 = load ppc_fp128, ppc_fp128* @d, align 16    ; <ppc_fp128> [#uses=1]
-  %7 = load ppc_fp128, ppc_fp128* @c, align 16    ; <ppc_fp128> [#uses=1]
-  %8 = call ppc_fp128 @llvm.pow.ppcf128(ppc_fp128 %6, ppc_fp128 %7)    ; <ppc_fp128> [#uses=1]
-  store ppc_fp128 %8, ppc_fp128* @d, align 16
-  br label %return
-
-return:   ; preds = %entry
-  ret void
-}
-
-declare ppc_fp128 @llvm.sqrt.ppcf128(ppc_fp128) nounwind readonly
-
-declare ppc_fp128 @"\01_sinl$LDBL128"(ppc_fp128) nounwind readonly
-
-declare ppc_fp128 @"\01_cosl$LDBL128"(ppc_fp128) nounwind readonly
-
-declare ppc_fp128 @llvm.pow.ppcf128(ppc_fp128, ppc_fp128) nounwind readonly
-
-declare ppc_fp128 @copysignl(ppc_fp128, ppc_fp128)
-
-define ppc_fp128 @cs(ppc_fp128 %from, ppc_fp128 %to) {
-  %tmp = call ppc_fp128 @copysignl(ppc_fp128 %from, ppc_fp128 %to)
-  ret ppc_fp128 %tmp
-}