[ELF][Hexagon]Add TPREL relocation support to Hexagon

[sidneym]

Summary

Adds support for tls TPREL relocations.

[MaskRay]

lld/test/ELF/hexagon-tls-tprel.s

33 ↗

(On Diff #232363)

// @a and // 0x1 below are redundant.

[sidneym]

remove redundant comments

[ruiu]

LGTM

[MaskRay]

lld/test/ELF/hexagon-tls-tprel.s

1 ↗

(On Diff #232836)

Maybe rename this test to hexagon-tls-le.s (See ppc32-tls-le.s)

Basically, I want the 4 TLS model tests to be named -le -ie` -ld and -gd.

[MaskRay]

lld/test/ELF/hexagon-tls-tprel.s

41 ↗

(On Diff #232836)

Don't simply copy clang output.

Directives like .type b,@object should be deleted. The symbol a b etc are of type STT_TYPE, not STT_OBJECT. The directives used here are just confusing.

41 ↗

(On Diff #232836)

Directives like .type b,@object should be deleted. The symbol a b etc are of type STT_TLS, not STT_OBJECT. The directives used here are just confusing.

[sidneym]

Change testcase name to hexagon-tls-le.s

[MaskRay]

lld/test/ELF/hexagon-tls-le.s

11

Testing relocations with llvm-readobj -r may be better. See https://reviews.llvm.org/rG47e3d3ec0c5607ae3bc6181537c0622080f3af27gg

Created D72093

lld/ELF/Arch/Hexagon.cpp

RelExpr Hexagon::getRelExpr(RelType type, const Symbol &s,
   case R_HEX_GOTREL_32_6_X:
   case R_HEX_GOTREL_HI16:
   case R_HEX_GOTREL_LO16:
     return R_GOTPLTREL;
   case R_HEX_GOT_11_X:
   case R_HEX_GOT_16_X:
   case R_HEX_GOT_32_6_X:
     return R_GOTPLT;
+  case R_HEX_TPREL_11_X:
+  case R_HEX_TPREL_16:
+  case R_HEX_TPREL_16_X:
+  case R_HEX_TPREL_32_6_X:
+  case R_HEX_TPREL_HI16:
+  case R_HEX_TPREL_LO16:
+    return R_TLS;
   default:
     error(getErrorLocation(loc) + "unknown relocation (" + Twine(type) +
           ") against symbol " + toString(s));
     return R_NONE;
   }
 }
 
 static uint32_t findMaskR6(uint32_t insn) {
case R_HEX_9_X:
     or32le(loc, applyMask(0x00003fe0, val & 0x3f));
     break;
   case R_HEX_10_X:
     or32le(loc, applyMask(0x00203fe0, val & 0x3f));
     break;
   case R_HEX_11_X:
   case R_HEX_GOT_11_X:
   case R_HEX_GOTREL_11_X:
+  case R_HEX_TPREL_11_X:
     or32le(loc, applyMask(findMaskR11(read32le(loc)), val & 0x3f));
     break;
   case R_HEX_12_X:
     or32le(loc, applyMask(0x000007e0, val));
     break;
   case R_HEX_16_X: // These relocs only have 6 effective bits.
   case R_HEX_GOT_16_X:
   case R_HEX_GOTREL_16_X:
+  case R_HEX_TPREL_16_X:
     or32le(loc, applyMask(findMaskR16(read32le(loc)), val & 0x3f));
     break;
+  case R_HEX_TPREL_16:
+    or32le(loc, applyMask(findMaskR16(read32le(loc)), val & 0xffff));
+    break;
   case R_HEX_32:
   case R_HEX_32_PCREL:
     or32le(loc, val);
     break;
   case R_HEX_32_6_X:
   case R_HEX_GOT_32_6_X:
   case R_HEX_GOTREL_32_6_X:
+  case R_HEX_TPREL_32_6_X:
     or32le(loc, applyMask(0x0fff3fff, val >> 6));
     break;
   case R_HEX_B9_PCREL:
     checkInt(loc, val, 11, type);
     or32le(loc, applyMask(0x003000fe, val >> 2));
     break;
   case R_HEX_B9_PCREL_X:
     or32le(loc, applyMask(0x003000fe, val & 0x3f));
void Hexagon::relocateOne(uint8_t *loc, RelType type, uint64_t val) const {
   case R_HEX_B22_PCREL_X:
     or32le(loc, applyMask(0x1ff3ffe, val & 0x3f));
     break;
   case R_HEX_B32_PCREL_X:
     or32le(loc, applyMask(0x0fff3fff, val >> 6));
     break;
   case R_HEX_GOTREL_HI16:
   case R_HEX_HI16:
+  case R_HEX_TPREL_HI16:
     or32le(loc, applyMask(0x00c03fff, val >> 16));
     break;
   case R_HEX_GOTREL_LO16:
   case R_HEX_LO16:
+  case R_HEX_TPREL_LO16:
     or32le(loc, applyMask(0x00c03fff, val));
     break;
   default:
     llvm_unreachable("unknown relocation");
   }
 }
 
 void Hexagon::writePltHeader(uint8_t *buf) const {

lld/ELF/InputSection.cpp

case EM_PPC64:
     // Adjusted Variant 1. TP is placed with a displacement of 0x7000, which is
     // to allow a signed 16-bit offset to reach 0x1000 of TCB/thread-library
     // data and 0xf000 of the program's TLS segment.
     return s.getVA(0) + (tls->p_vaddr & (tls->p_align - 1)) - 0x7000;
   case EM_RISCV:
     return s.getVA(0) + (tls->p_vaddr & (tls->p_align - 1));
 
     // Variant 2.
+  case EM_HEXAGON:
   case EM_386:
   case EM_X86_64:
     return s.getVA(0) - tls->p_memsz -
            ((-tls->p_vaddr - tls->p_memsz) & (tls->p_align - 1));
   default:
     llvm_unreachable("unhandled Config->EMachine");
   }
 }

lld/test/ELF/hexagon-tls-le.s

+# REQUIRES: hexagon
+# RUN: llvm-mc -filetype=obj -triple=hexagon-unknown-elf %s -o %t.o
+# RUN: ld.lld %t.o -o %t
+# RUN: llvm-objdump -d --print-imm-hex %t | FileCheck %s
+
+  .globl  _start
+  .type _start, @function
+_start:
+r0 = ugp
+
+# R_HEX_TPREL_32_6_X and R_HEX_TPREL_16_X
+# CHECK:      { immext(#0xffffffc0)
+# CHECK-NEXT:   r1 = add(r0,##-0x10) }
+                r1 = add(r0,##a@TPREL)
+
+# R_HEX_TPREL_32_6_X and R_HEX_TPREL_11_X
+# CHECK:      { immext(#0xffffffc0)
+# CHECK-NEXT:   r2 = memw(r0+##-0x10) }
+                r2 = memw(r0+##a@TPREL)
+
+# R_HEX_TPREL_HI16
+# CHECK: {      r3.h = #0xffff }
+                r3.h = #a@TPREL
+
+# R_HEX_TPREL_LO16
+# CHECK: {      r3.l = #0xfff0 }
+                r3.l = #a@TPREL
+
+# R_HEX_TPREL_16
+# CHECK: {      r4 = #-0x10 }
+                r4 = #a@TPREL
+
+        .section        .tdata,"awT",@progbits
+        .globl  a
+        .p2align        2
+a:
+        .word   1
+        .size   a, 4
+
+        .globl  b
+        .p2align        2
+b:
+        .word   2
+        .size   b, 4
+
+        .globl  c
+        .p2align        2
+c:
+        .word   3
+        .size   c, 4
+
+        .globl  d
+        .p2align        2
+d:
+        .word   4
+        .size   d, 4