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[IPRA][ARM] Spill extra registers at -Oz
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Authored by ostannard on Nov 7 2019, 2:59 AM.

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Summary

When optimising for code size at the expense of performance, it is often
worth saving and restoring some of r0-r3, if IPRA will be able to take
advantage of them. This doesn't cost any extra code size if we already
have a PUSH/POP pair, and increases the number of available registers
across any calls to the function.

We already have an optimisation which tries fold the subtract/add of the
SP into the PUSH/POP by using extra registers, which somewhat conflicts
with this. I've made the new optimisation less aggressive in cases where
the existing one is likely to trigger, which gives better results than
either of these optimisations by themselves.

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Event Timeline

ostannard created this revision.Nov 7 2019, 2:59 AM

Looks reasonable (haven't looked at the ARM part.)
The change in shrink wrapping doesn't look correct to me though. Is that particular change require?

llvm/lib/CodeGen/MachineRegisterInfo.cpp
629

Could you change unsigned to Register here and in enableCalleeSavedRegister while you are at it?
Fine as a follow-up commit or a preparatory commit :).

llvm/lib/CodeGen/ShrinkWrap.cpp
170

That change doesn't look right.

llvm/test/CodeGen/ARM/ipra-extra-spills-shrink-wrapping.mir
36

You should be able to remove the section with the LLVM IR.
Just make sure to remove the LLVM IR basic block names in the names of the MachineBasicBlock.
E.g., bb.0.entry: => bb.0: