[MachineVerifier] Relax verifier for predicated returns

[ostannard]

Summary

For ARM, the if-converter can generate predicated tail-calls. These are calls, so have a mask of clobbered registers, but execution may continue beyond them, so we want to check liveness of registers after them. However, it is not possible for the instruction to both clobber registers and continue execution, so we shouldn't consider the register mask when checking liveness in the verifier.

[efriedma]

In general, if we predicate a call, I think we need to somehow indicate the fact that the registers in the mask may not be clobbered by the call. This isn't really specific to tail calls, but I guess we don't currently predicate other calls on ARM?

Probably the right solution from a modeling perspective involves changing the predication code to correctly define the registers in question, as opposed to changing the verifier to understand what the backend currently generates. Maybe we need a special "predicated register mask" operand.

Related to bad modeling of predicated returns, I have a patch https://reviews.llvm.org/D40061 which I never got around to finishing. Only loosely related to this, though.

llvm/lib/CodeGen/MachineVerifier.cpp

   BBInfo &MInfo = MBBInfoMap[MI->getParent()];
   set_union(MInfo.regsKilled, regsKilled);
   set_subtract(regsLive, regsKilled); regsKilled.clear();
-  // Kill any masked registers.
-  while (!regMasks.empty()) {
-    const uint32_t *Mask = regMasks.pop_back_val();
-    for (RegSet::iterator I = regsLive.begin(), E = regsLive.end(); I != E; ++I)
-      if (Register::isPhysicalRegister(*I) &&
-          MachineOperand::clobbersPhysReg(Mask, *I))
-        regsDead.push_back(*I);
+  // Kill any masked registers, unless the instruction is a predicated return,
+  // in which case either it returns (so we don't care about liveness after
+  // it), or it doesn't actually clobber any registers.
+  if (!(TII->isPredicated(*MI) && MI->isReturn())) {
+    while (!regMasks.empty()) {
+      const uint32_t *Mask = regMasks.pop_back_val();
+      for (RegSet::iterator I = regsLive.begin(), E = regsLive.end(); I != E; ++I)
+        if (Register::isPhysicalRegister(*I) &&
+            MachineOperand::clobbersPhysReg(Mask, *I))
+          regsDead.push_back(*I);
+    }
   }
   set_subtract(regsLive, regsDead);   regsDead.clear();
   set_union(regsLive, regsDefined);   regsDefined.clear();

llvm/test/MachineVerifier/predicated-call.mir

+# RUN: llc -o - %s -mtriple=armv7a-none-eabi --run-pass none
+# REQUIRES: arm-registered-target
+
+# It looks like r0 is clobbered by the register mask of the first tTAILJMPd, so
+# the second tTAILJMPd uses a dead register ($r0).  However, the first
+# instruction is predicated, so there are two possible executions:
+# - If the predicate is true, then the tail call will be executed, and the
+#   second will never be reached, so the liveness of r0 there doesn't matter.
+# - If the predicate is false, the first call won't be executed, so $r0 will
+#   remain live until the second call.
+
+--- |
+  declare void @bar(i32)
+  declare void @baz(i32)
+  define void @foo() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            foo
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body:             |
+  bb.0.entry:
+    liveins: $lr
+  
+    $r0 = IMPLICIT_DEF
+    $cpsr = IMPLICIT_DEF
+
+    tTAILJMPd @bar, 1 /* CC::ne */, killed $cpsr, csr_aapcs, implicit $sp, implicit $r0
+    tTAILJMPd @baz, 14 /* CC::al */, $noreg, csr_aapcs, implicit $sp, implicit $r0
+
+...