[Mips] Add rematerialization support for ldi.fmt

[mbrkusanin]

Summary

Instruction ldi.fmt can be considered cheap enough to avoid spill and restore
of value that it produces since it's loaded from immediate.

[atanasyan]

As far as I understand the code, overriding isReallyTriviallyReMaterializable and reMaterialize is not mandatory to avoid spill for ldi.fmt. Let's split the patch. The first patch could adds isReMaterializable flag to the MSA_I10_LDI_DESC_BASE and test the change. The second one - overrides isReallyTriviallyReMaterializable and reMaterialize. By the way, what is a goal of overriding reMaterialize? Does it give any benefit?

llvm/test/CodeGen/Mips/msa/remat-ldi.ll

109

These lines can be removed from the test.

[mbrkusanin]

• Rebase
• Removed isReallyTriviallyReMaterializable and reMaterialize

[mbrkusanin]

In D69898#1740862, @atanasyan wrote:

As far as I understand the code, overriding isReallyTriviallyReMaterializable and reMaterialize is not mandatory to avoid spill for ldi.fmt. Let's split the patch. The first patch could adds isReMaterializable flag to the MSA_I10_LDI_DESC_BASE and test the change. The second one - overrides isReallyTriviallyReMaterializable and reMaterialize. By the way, what is a goal of overriding reMaterialize? Does it give any benefit?

I removed everything expect adding the isReMaterializable flag. You're right, no additional code is necessary. In my earlier version of the patch there was a part of the checking and rematerializing that was done manually so I needed the checks for other instructions. But now I see that all of that was unnecessary. I went in a roundabout way and arrived at the same thing that isReallyTriviallyReMaterializableGeneric was already doing. The only benefit of overriding isReallyTriviallyReMaterializable at this point would be in slightly less checks for some instructions (but not in case they can't be rematerialized). Sorry for wasting your time on redundant code.

[atanasyan]

LGTM

llvm/lib/Target/Mips/MipsInstrInfo.h

bool verifyInstruction(const MachineInstr &MI,
                          StringRef &ErrInfo) const override;
 
   std::pair<unsigned, unsigned>
   decomposeMachineOperandsTargetFlags(unsigned TF) const override;
 
   ArrayRef<std::pair<unsigned, const char *>>
   getSerializableDirectMachineOperandTargetFlags() const override;
 
+  bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
+                                         AAResults *AA) const override;
+
+  void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
+                     unsigned DestReg, unsigned SubIdx,
+                     const MachineInstr &Orig,
+                     const TargetRegisterInfo &TRI) const override;
+
 protected:
   bool isZeroImm(const MachineOperand &op) const;
 
   MachineMemOperand *GetMemOperand(MachineBasicBlock &MBB, int FI,
                                    MachineMemOperand::Flags Flags) const;
 
 private:
   virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0;

llvm/lib/Target/Mips/MipsInstrInfo.cpp

static const std::pair<unsigned, const char*> Flags[] = {
     {MO_GOT_HI16,     "mips-got-hi16"},
     {MO_GOT_LO16,     "mips-got-lo16"},
     {MO_CALL_HI16,    "mips-call-hi16"},
     {MO_CALL_LO16,    "mips-call-lo16"},
     {MO_JALR,         "mips-jalr"}
   };
   return makeArrayRef(Flags);
 }
+
+bool MipsInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
+                                                      AAResults *AA) const {
+  switch (MI.getOpcode()) {
+  default:
+    // This function should only be called for opcodes with the ReMaterializable
+    // flag set.
+    llvm_unreachable("Unknown rematerializable operation!");
+    break;
+
+  // class MSA_I10_LDI_DESC_BASE
+  case Mips::LDI_B:
+  case Mips::LDI_H:
+  case Mips::LDI_W:
+  case Mips::LDI_D:
+    return true;
+
+  // class LoadUpper
+  case Mips::LUi:
+  case Mips::LUi64:
+  case Mips::LUi_MM:
+    return true;
+
+  // class LoadImmMM16
+  case Mips::LI16_MM:
+  case Mips::LI16_MMR6:
+    return true;
+
+  // class LUI_MMR6_DESC
+  case Mips::LUI_MMR6:
+    return true;
+
+  // class ArithLogicI
+  case Mips::ADDIU_MMR6:
+  case Mips::ADDi:
+  case Mips::ADDi_MM:
+  case Mips::ADDiu:
+  case Mips::ADDiu_MM:
+  case Mips::ANDI_MMR6:
+  case Mips::ANDi:
+  case Mips::ANDi64:
+  case Mips::ANDi_MM:
+  case Mips::DADDi:
+  case Mips::DADDiu:
+  case Mips::ORI_MMR6:
+  case Mips::ORi:
+  case Mips::ORi64:
+  case Mips::ORi_MM:
+  case Mips::XORI_MMR6:
+  case Mips::XORi:
+  case Mips::XORi64:
+  case Mips::XORi_MM:
+    return MI.getOperand(1).getReg() == Mips::ZERO;
+
+  // class ArithLogicR
+  case Mips::ADD:
+  case Mips::ADDU_MMR6:
+  case Mips::ADD_MM:
+  case Mips::ADD_MMR6:
+  case Mips::ADDu:
+  case Mips::ADDu_MM:
+  case Mips::AND:
+  case Mips::AND64:
+  case Mips::AND_MM:
+  case Mips::AND_MMR6:
+  case Mips::BADDu:
+  case Mips::DADD:
+  case Mips::DADDu:
+  case Mips::DSUB:
+  case Mips::DSUBu:
+  case Mips::OR:
+  case Mips::OR64:
+  case Mips::OR_MM:
+  case Mips::OR_MMR6:
+  case Mips::SUB:
+  case Mips::SUBU_MMR6:
+  case Mips::SUB_MM:
+  case Mips::SUB_MMR6:
+  case Mips::SUBu:
+  case Mips::SUBu_MM:
+  case Mips::XOR:
+  case Mips::XOR64:
+  case Mips::XOR_MM:
+  case Mips::XOR_MMR6:
+    return (MI.getOperand(1).getReg() == Mips::ZERO) &&
+           (MI.getOperand(2).getReg() == Mips::ZERO);
+  case Mips::DMUL:
+  case Mips::MUHU_MMR6:
+  case Mips::MUH_MMR6:
+  case Mips::MUL:
+  case Mips::MULU_MMR6:
+  case Mips::MUL_MM:
+  case Mips::MUL_MMR6:
+  case Mips::V3MULU:
+  case Mips::VMM0:
+  case Mips::VMULU:
+    return false;
+
+  // class ArithLogic16Defs
+  case Mips::AddiuRxRxImm16:
+  case Mips::AddiuRxRxImmX16:
+  case Mips::AndRxRxRy16:
+  case Mips::OrRxRxRy16:
+    return MI.getOperand(1).getReg() == Mips::ZERO;
+  case Mips::AdduRxRyRz16:
+  case Mips::SubuRxRyRz16:
+  case Mips::XorRxRxRy16:
+    return false;
+
+  // class MoveMM16
+  case Mips::MOVE16_MM:
+  case Mips::MOVE16_MMR6:
+    return MI.getOperand(1).getReg() == Mips::ZERO;
+
+  // class MovePMM16
+  case Mips::MOVEP_MM:
+  case Mips::MOVEP_MMR6:
+    return MI.getOperand(2).getReg() == Mips::ZERO &&
+           MI.getOperand(3).getReg() == Mips::ZERO;
+
+  // class DIVMOD_MMR6_DESC_BASE
+  case Mips::DIVU_MMR6:
+  case Mips::DIV_MMR6:
+  case Mips::MODU_MMR6:
+  case Mips::MOD_MMR6:
+    return false;
+  }
+}
+
+void MipsInstrInfo::reMaterialize(MachineBasicBlock &MBB,
+                                  MachineBasicBlock::iterator I,
+                                  unsigned DestReg, unsigned SubIdx,
+                                  const MachineInstr &Orig,
+                                  const TargetRegisterInfo &TRI) const {
+  MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
+  MBB.insert(I, MI);
+  MachineInstr &NewMI = *std::prev(I);
+  NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
+}

llvm/lib/Target/Mips/MipsMSAInstrInfo.td

 class MSA_I10_LDI_DESC_BASE<string instr_asm, RegisterOperand ROWD,
                             InstrItinClass itin = NoItinerary> {
   dag OutOperandList = (outs ROWD:$wd);
   dag InOperandList = (ins vsplat_simm10:$s10);
   string AsmString = !strconcat(instr_asm, "\t$wd, $s10");
   // LDI is matched using custom matching code in MipsSEISelDAGToDAG.cpp
   list<dag> Pattern = [];
   bit hasSideEffects = 0;
+  bit isReMaterializable = 1;
   InstrItinClass Itinerary = itin;
 }
 
 class MSA_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
                        RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
                        InstrItinClass itin = NoItinerary> {
   dag OutOperandList = (outs ROWD:$wd);
   dag InOperandList = (ins ROWS:$ws);

llvm/test/CodeGen/Mips/msa/remat-ldi.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O3 -march=mipsel -mcpu=mips32r6 -mattr=+fp64,+msa %s -o - | FileCheck %s
+
+; Test that checks if spill for ldi can be avoided and instruction will be
+; rematerialized.
+
+declare dso_local void @foo()
+
+define dso_local void @test_ldi_b() {
+; CHECK-LABEL: test_ldi_b:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addiu $sp, $sp, -24
+; CHECK-NEXT:    .cfi_def_cfa_offset 24
+; CHECK-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
+; CHECK-NEXT:    .cfi_offset 31, -4
+; CHECK-NEXT:    ldi.b $w0, 1
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    jal foo
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    ldi.b $w0, 1
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    addiu $sp, $sp, 24
+entry:
+  tail call void asm sideeffect "", "f,~{memory},~{$1}"(<16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
+  tail call void @foo()
+  tail call void asm sideeffect "", "f,~{memory},~{$1}"(<16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
+  ret void
+}
+
+define dso_local void @test_ldi_h() {
+; CHECK-LABEL: test_ldi_h:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addiu $sp, $sp, -24
+; CHECK-NEXT:    .cfi_def_cfa_offset 24
+; CHECK-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
+; CHECK-NEXT:    .cfi_offset 31, -4
+; CHECK-NEXT:    ldi.h $w0, 2
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    jal foo
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    ldi.h $w0, 2
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    addiu $sp, $sp, 24
+entry:
+  tail call void asm sideeffect "", "f,~{memory},~{$1}"(<8 x i16> <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>)
+  tail call void @foo()
+  tail call void asm sideeffect "", "f,~{memory},~{$1}"(<8 x i16> <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>)
+  ret void
+}
+
+define dso_local void @test_ldi_w() {
+; CHECK-LABEL: test_ldi_w:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addiu $sp, $sp, -24
+; CHECK-NEXT:    .cfi_def_cfa_offset 24
+; CHECK-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
+; CHECK-NEXT:    .cfi_offset 31, -4
+; CHECK-NEXT:    ldi.w $w0, 3
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    jal foo
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    ldi.w $w0, 3
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    addiu $sp, $sp, 24
+entry:
+  tail call void asm sideeffect "", "f,~{memory},~{$1}"(<4 x i32> <i32 3, i32 3, i32 3, i32 3>)
+  tail call void @foo()
+  tail call void asm sideeffect "", "f,~{memory},~{$1}"(<4 x i32> <i32 3, i32 3, i32 3, i32 3>)
+  ret void
+}
+
+define dso_local void @test_ldi_d() {
+; CHECK-LABEL: test_ldi_d:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addiu $sp, $sp, -24
+; CHECK-NEXT:    .cfi_def_cfa_offset 24
+; CHECK-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
+; CHECK-NEXT:    .cfi_offset 31, -4
+; CHECK-NEXT:    ldi.d $w0, 4
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    jal foo
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    ldi.d $w0, 4
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    addiu $sp, $sp, 24
+entry:
+  tail call void asm sideeffect "", "f,~{memory},~{$1}"(<2 x i64> <i64 4, i64 4>)
+  tail call void @foo()
+  tail call void asm sideeffect "", "f,~{memory},~{$1}"(<2 x i64> <i64 4, i64 4>)
+  ret void
+}
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 1, !"wchar_size", i32 4}