[Power9] Implement the vector extend sign instruction pattern match

[steven.zhang]

Summary

Power9 has instructions to implement the semantics of SIGN_EXTEND_INREG for vector type. Mark it as legal and add the match pattern.

[amyk]

llvm/test/CodeGen/PowerPC/vector-extend-sign.ll

3

I think it would be better to separate the run lines so it is not over 80 characters.

[steven.zhang]

Update the test run line.

[steven.zhang]

llvm/test/CodeGen/PowerPC/vector-extend-sign.ll

3

Done.

[steven.zhang]

Gentle ping ... Thank you!

[nemanjai]

llvm/lib/Target/PowerPC/PPCInstrVSX.td

4305 ↗

(On Diff #227994)

I don't really see a reason to put this into PPCInstrVSX.td. Seems like PPCInstrAltivec.td would be a more appropriate place for it.

[steven.zhang]

llvm/lib/Target/PowerPC/PPCInstrVSX.td

4305 ↗

(On Diff #227994)

Hmm, make sense. It is interesting that, we put the match pattern from build_vector to VEXTSB2D here too ...

[steven.zhang]

Address Nemanjai's comments.

[steven.zhang]

Gentle ping ...

[lkail]

LGTM considering patterns added for SIGN_EXTENDED_INREG also follow its atomic semantics.

[steven.zhang]

Hmm, it is still in the "need review" state. 😢

[shchenz]

Thanks for this exploitation. LGTM too.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

936

Do we need these lines? The default action is Legal. If this is necessary, then maybe we need another NFC patch to add operation action for ISD::SIGN_EXTEND_INREG for type {i8, i16, i32} to make actions for ISD::SIGN_EXTEND_INREG be consistent? Up to you to change it or not.

[steven.zhang]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

936

Explicit specify it to legal didn't hurt anything, I think. And we have another patch to specify the default action for SIGN_EXTEND_INREG as Expand for vector type.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

if (Subtarget.hasP9Vector()) {
       }
       setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
 
     }
 
     if (Subtarget.hasP9Altivec()) {
       setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
       setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
+
+      setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8,  Legal);
+      setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal);
+      setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal);
+      setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8,  Legal);
+      setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal);
+      setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
+      setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
     }
   }
 
   if (Subtarget.hasQPX()) {
     setOperationAction(ISD::FADD, MVT::v4f64, Legal);
     setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
     setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
     setOperationAction(ISD::FREM, MVT::v4f64, Expand);

llvm/lib/Target/PowerPC/PPCInstrAltivec.td

 let isCodeGenOnly = 1 in {
   def VEXTSB2Ws : VX_VT5_EO5_VB5s<1538, 16, "vextsb2w", []>;
   def VEXTSH2Ws : VX_VT5_EO5_VB5s<1538, 17, "vextsh2w", []>;
   def VEXTSB2Ds : VX_VT5_EO5_VB5s<1538, 24, "vextsb2d", []>;
   def VEXTSH2Ds : VX_VT5_EO5_VB5s<1538, 25, "vextsh2d", []>;
   def VEXTSW2Ds : VX_VT5_EO5_VB5s<1538, 26, "vextsw2d", []>;
 }
 
+def : Pat<(v4i32 (sext_inreg v4i32:$VRB, v4i8)), (v4i32 (VEXTSB2W $VRB))>;
+def : Pat<(v4i32 (sext_inreg v4i32:$VRB, v4i16)), (v4i32 (VEXTSH2W $VRB))>;
+def : Pat<(v2i64 (sext_inreg v2i64:$VRB, v2i8)), (v2i64 (VEXTSB2D $VRB))>;
+def : Pat<(v2i64 (sext_inreg v2i64:$VRB, v2i16)), (v2i64 (VEXTSH2D $VRB))>;
+def : Pat<(v2i64 (sext_inreg v2i64:$VRB, v2i32)), (v2i64 (VEXTSW2D $VRB))>;
+
 // Vector Integer Negate
 def VNEGW : VX_VT5_EO5_VB5<1538, 6, "vnegw",
                            [(set v4i32:$vD,
                             (sub (v4i32 immAllZerosV), v4i32:$vB))]>;
 
 def VNEGD : VX_VT5_EO5_VB5<1538, 7, "vnegd",
                            [(set v2i64:$vD,
                             (sub (v2i64 (bitconvert (v4i32 immAllZerosV))),

llvm/test/CodeGen/PowerPC/vector-extend-sign.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:     -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-P9
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:     -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-P9
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:     -mcpu=pwr9 -mattr=-altivec < %s | FileCheck %s \
+; RUN:     --check-prefix=CHECK-P9-NOALTIVEC
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:     -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-P8
+
+define <4 x i32> @test_vextsh2w(<4 x i32> %m) {
+; CHECK-P9-LABEL: test_vextsh2w:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    vextsh2w 2, 2
+; CHECK-P9-NEXT:    blr
+;
+; CHECK-P9-NOALTIVEC-LABEL: test_vextsh2w:
+; CHECK-P9-NOALTIVEC:       # %bb.0: # %entry
+; CHECK-P9-NOALTIVEC-NEXT:    extsh 6, 6
+; CHECK-P9-NOALTIVEC-NEXT:    extsh 5, 5
+; CHECK-P9-NOALTIVEC-NEXT:    extsh 4, 4
+; CHECK-P9-NOALTIVEC-NEXT:    extsh 3, 3
+; CHECK-P9-NOALTIVEC-NEXT:    blr
+;
+; CHECK-P8-LABEL: test_vextsh2w:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    vspltisw 3, 8
+; CHECK-P8-NEXT:    vadduwm 3, 3, 3
+; CHECK-P8-NEXT:    vslw 2, 2, 3
+; CHECK-P8-NEXT:    vsraw 2, 2, 3
+; CHECK-P8-NEXT:    blr
+entry:
+  %shl = shl <4 x i32> %m, <i32 16, i32 16, i32 16, i32 16>
+  %shr = ashr exact <4 x i32> %shl, <i32 16, i32 16, i32 16, i32 16>
+  ret <4 x i32> %shr
+}
+
+define <4 x i32> @test_vextsb2w(<4 x i32> %m) {
+; CHECK-P9-LABEL: test_vextsb2w:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    vextsb2w 2, 2
+; CHECK-P9-NEXT:    blr
+;
+; CHECK-P9-NOALTIVEC-LABEL: test_vextsb2w:
+; CHECK-P9-NOALTIVEC:       # %bb.0: # %entry
+; CHECK-P9-NOALTIVEC-NEXT:    extsb 6, 6
+; CHECK-P9-NOALTIVEC-NEXT:    extsb 5, 5
+; CHECK-P9-NOALTIVEC-NEXT:    extsb 4, 4
+; CHECK-P9-NOALTIVEC-NEXT:    extsb 3, 3
+; CHECK-P9-NOALTIVEC-NEXT:    blr
+;
+; CHECK-P8-LABEL: test_vextsb2w:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    vspltisw 3, 12
+; CHECK-P8-NEXT:    vadduwm 3, 3, 3
+; CHECK-P8-NEXT:    vslw 2, 2, 3
+; CHECK-P8-NEXT:    vsraw 2, 2, 3
+; CHECK-P8-NEXT:    blr
+entry:
+  %shl = shl <4 x i32> %m, <i32 24, i32 24, i32 24, i32 24>
+  %shr = ashr exact <4 x i32> %shl, <i32 24, i32 24, i32 24, i32 24>
+  ret <4 x i32> %shr
+}
+
+define <2 x i64> @test_vextsb2d(<2 x i64> %m) {
+; CHECK-P9-LABEL: test_vextsb2d:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    vextsb2d 2, 2
+; CHECK-P9-NEXT:    blr
+;
+; CHECK-P9-NOALTIVEC-LABEL: test_vextsb2d:
+; CHECK-P9-NOALTIVEC:       # %bb.0: # %entry
+; CHECK-P9-NOALTIVEC-NEXT:    extsb 3, 3
+; CHECK-P9-NOALTIVEC-NEXT:    extsb 4, 4
+; CHECK-P9-NOALTIVEC-NEXT:    blr
+;
+; CHECK-P8-LABEL: test_vextsb2d:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
+; CHECK-P8-NEXT:    addi 3, 3, .LCPI2_0@toc@l
+; CHECK-P8-NEXT:    lxvd2x 0, 0, 3
+; CHECK-P8-NEXT:    xxswapd 35, 0
+; CHECK-P8-NEXT:    vsld 2, 2, 3
+; CHECK-P8-NEXT:    vsrad 2, 2, 3
+; CHECK-P8-NEXT:    blr
+entry:
+  %shl = shl <2 x i64> %m, <i64 56, i64 56>
+  %shr = ashr exact <2 x i64> %shl, <i64 56, i64 56>
+  ret <2 x i64> %shr
+}
+
+define <2 x i64> @test_vextsh2d(<2 x i64> %m) {
+; CHECK-P9-LABEL: test_vextsh2d:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    vextsh2d 2, 2
+; CHECK-P9-NEXT:    blr
+;
+; CHECK-P9-NOALTIVEC-LABEL: test_vextsh2d:
+; CHECK-P9-NOALTIVEC:       # %bb.0: # %entry
+; CHECK-P9-NOALTIVEC-NEXT:    extsh 3, 3
+; CHECK-P9-NOALTIVEC-NEXT:    extsh 4, 4
+; CHECK-P9-NOALTIVEC-NEXT:    blr
+;
+; CHECK-P8-LABEL: test_vextsh2d:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
+; CHECK-P8-NEXT:    addi 3, 3, .LCPI3_0@toc@l
+; CHECK-P8-NEXT:    lxvd2x 0, 0, 3
+; CHECK-P8-NEXT:    xxswapd 35, 0
+; CHECK-P8-NEXT:    vsld 2, 2, 3
+; CHECK-P8-NEXT:    vsrad 2, 2, 3
+; CHECK-P8-NEXT:    blr
+entry:
+  %shl = shl <2 x i64> %m, <i64 48, i64 48>
+  %shr = ashr exact <2 x i64> %shl, <i64 48, i64 48>
+  ret <2 x i64> %shr
+}
+
+define <2 x i64> @test_vextsw2d(<2 x i64> %m) {
+; CHECK-P9-LABEL: test_vextsw2d:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    vextsw2d 2, 2
+; CHECK-P9-NEXT:    blr
+;
+; CHECK-P9-NOALTIVEC-LABEL: test_vextsw2d:
+; CHECK-P9-NOALTIVEC:       # %bb.0: # %entry
+; CHECK-P9-NOALTIVEC-NEXT:    extsw 3, 3
+; CHECK-P9-NOALTIVEC-NEXT:    extsw 4, 4
+; CHECK-P9-NOALTIVEC-NEXT:    blr
+;
+; CHECK-P8-LABEL: test_vextsw2d:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    addis 3, 2, .LCPI4_0@toc@ha
+; CHECK-P8-NEXT:    addi 3, 3, .LCPI4_0@toc@l
+; CHECK-P8-NEXT:    lxvd2x 0, 0, 3
+; CHECK-P8-NEXT:    xxswapd 35, 0
+; CHECK-P8-NEXT:    vsld 2, 2, 3
+; CHECK-P8-NEXT:    vsrad 2, 2, 3
+; CHECK-P8-NEXT:    blr
+entry:
+  %shl = shl <2 x i64> %m, <i64 32, i64 32>
+  %shr = ashr exact <2 x i64> %shl, <i64 32, i64 32>
+  ret <2 x i64> %shr
+}
+
+define <2 x i64> @test_none(<2 x i64> %m) {
+; CHECK-P9-LABEL: test_none:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    addis 3, 2, .LCPI5_0@toc@ha
+; CHECK-P9-NEXT:    addi 3, 3, .LCPI5_0@toc@l
+; CHECK-P9-NEXT:    lxvx 35, 0, 3
+; CHECK-P9-NEXT:    vsld 2, 2, 3
+; CHECK-P9-NEXT:    vsrad 2, 2, 3
+; CHECK-P9-NEXT:    blr
+;
+; CHECK-P9-NOALTIVEC-LABEL: test_none:
+; CHECK-P9-NOALTIVEC:       # %bb.0: # %entry
+; CHECK-P9-NOALTIVEC-NEXT:    sldi 3, 3, 16
+; CHECK-P9-NOALTIVEC-NEXT:    sldi 4, 4, 16
+; CHECK-P9-NOALTIVEC-NEXT:    sradi 3, 3, 16
+; CHECK-P9-NOALTIVEC-NEXT:    sradi 4, 4, 16
+; CHECK-P9-NOALTIVEC-NEXT:    blr
+;
+; CHECK-P8-LABEL: test_none:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    addis 3, 2, .LCPI5_0@toc@ha
+; CHECK-P8-NEXT:    addi 3, 3, .LCPI5_0@toc@l
+; CHECK-P8-NEXT:    lxvd2x 0, 0, 3
+; CHECK-P8-NEXT:    xxswapd 35, 0
+; CHECK-P8-NEXT:    vsld 2, 2, 3
+; CHECK-P8-NEXT:    vsrad 2, 2, 3
+; CHECK-P8-NEXT:    blr
+entry:
+  %shl = shl <2 x i64> %m, <i64 16, i64 16>
+  %shr = ashr exact <2 x i64> %shl, <i64 16, i64 16>
+  ret <2 x i64> %shr
+}