[X86][SSE] LowerUINT_TO_FP_i64 - only use HADDPD for size/fast-hops

[RKSimon]

Summary

We were always generating a single source HADDPD, but really we should only do this if shouldUseHorizontalOp says its a good idea.

[spatel]

LGTM

[mstorsjo]

This broke building ffmpeg/libav for mingw, with errors like "Cannot select: t22: v2f64 = X86ISD::FHADD t21, t21". See https://bugs.llvm.org/show_bug.cgi?id=43729 for details.

[craig.topper]

In D69175#1715853, @mstorsjo wrote:

This broke building ffmpeg/libav for mingw, with errors like "Cannot select: t22: v2f64 = X86ISD::FHADD t21, t21". See https://bugs.llvm.org/show_bug.cgi?id=43729 for details.

I think we just need to add “Subtarget.hasSSE3() &&” before the call to shouldUseHorizontal.

llvm/lib/Target/X86/X86ISelLowering.cpp

if (useSSE) {
     Result = DAG.getLoad(
         Op.getValueType(), DL, Chain, StackSlot,
         MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI));
   }
 
   return Result;
 }
 
+/// Horizontal vector math instructions may be slower than normal math with
+/// shuffles. Limit horizontal op codegen based on size/speed trade-offs, uarch
+/// implementation, and likely shuffle complexity of the alternate sequence.
+static bool shouldUseHorizontalOp(bool IsSingleSource, SelectionDAG &DAG,
+                                  const X86Subtarget &Subtarget) {
+  bool IsOptimizingSize = DAG.getMachineFunction().getFunction().hasOptSize();
+  bool HasFastHOps = Subtarget.hasFastHorizontalOps();
+  return !IsSingleSource || IsOptimizingSize || HasFastHOps;
+}
+
 /// 64-bit unsigned integer to double expansion.
 static SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG,
                                    const X86Subtarget &Subtarget) {
   // This algorithm is not obvious. Here it is what we're trying to output:
   /*
      movq       %rax,  %xmm0
      punpckldq  (c0),  %xmm0  // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
      subpd      (c1),  %xmm0  // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
SDValue CLod1 =
       DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
                   MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
                   /* Alignment = */ 16);
   SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
   // TODO: Are there any fast-math-flags to propagate here?
   SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
   SDValue Result;
 
-  if (Subtarget.hasSSE3()) {
-    // FIXME: The 'haddpd' instruction may be slower than 'shuffle + addsd'.
+  if (shouldUseHorizontalOp(true, DAG, Subtarget)) {
     Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
   } else {
     SDValue Shuffle = DAG.getVectorShuffle(MVT::v2f64, dl, Sub, Sub, {1,-1});
     Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuffle, Sub);
   }
 
   return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
                      DAG.getIntPtrConstant(0, dl));

 // the default expansion of STRICT_FP_ROUND.
 static SDValue LowerSTRICT_FP_ROUND(SDValue Op, SelectionDAG &DAG) {
   // FIXME: Need to form a libcall with an input chain for f128.
   assert(Op.getOperand(0).getValueType() != MVT::f128 &&
          "Don't know how to handle f128 yet!");
   return Op;
 }
 
-/// Horizontal vector math instructions may be slower than normal math with
-/// shuffles. Limit horizontal op codegen based on size/speed trade-offs, uarch
-/// implementation, and likely shuffle complexity of the alternate sequence.
-static bool shouldUseHorizontalOp(bool IsSingleSource, SelectionDAG &DAG,
-                                  const X86Subtarget &Subtarget) {
-  bool IsOptimizingSize = DAG.getMachineFunction().getFunction().hasOptSize();
-  bool HasFastHOps = Subtarget.hasFastHorizontalOps();
-  return !IsSingleSource || IsOptimizingSize || HasFastHOps;
-}
-
 /// Depending on uarch and/or optimizing for size, we might prefer to use a
 /// vector operation in place of the typical scalar operation.
 static SDValue lowerAddSubToHorizontalOp(SDValue Op, SelectionDAG &DAG,
                                          const X86Subtarget &Subtarget) {
   // If both operands have other uses, this is probably not profitable.
   SDValue LHS = Op.getOperand(0);
   SDValue RHS = Op.getOperand(1);
   if (!LHS.hasOneUse() && !RHS.hasOneUse())

llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll

 
 define <2 x double> @test_mm_cvtu64_sd(<2 x double> %__A, i64 %__B) {
 ; X86-LABEL: test_mm_cvtu64_sd:
 ; X86:       # %bb.0: # %entry
 ; X86-NEXT:    vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; X86-NEXT:    vpinsrd $1, {{[0-9]+}}(%esp), %xmm1, %xmm1
 ; X86-NEXT:    vpunpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
 ; X86-NEXT:    vsubpd {{\.LCPI.*}}, %xmm1, %xmm1
-; X86-NEXT:    vhaddpd %xmm1, %xmm1, %xmm1
+; X86-NEXT:    vpermilpd {{.*#+}} xmm2 = xmm1[1,0]
+; X86-NEXT:    vaddsd %xmm1, %xmm2, %xmm1
 ; X86-NEXT:    vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: test_mm_cvtu64_sd:
 ; X64:       # %bb.0: # %entry
 ; X64-NEXT:    vcvtusi2sd %rdi, %xmm0, %xmm0
 ; X64-NEXT:    retq
 entry:

llvm/test/CodeGen/X86/haddsub-3.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE2
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3 | FileCheck %s --check-prefixes=SSE,SSSE3
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2            | FileCheck %s --check-prefixes=SSE,SSE2
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3           | FileCheck %s --check-prefixes=SSE,SSSE3,SSSE3-SLOW
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3,fast-hops | FileCheck %s --check-prefixes=SSE,SSSE3,SSSE3-FAST
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx             | FileCheck %s --check-prefixes=AVX,AVX1,AVX1-SLOW
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx,fast-hops   | FileCheck %s --check-prefixes=AVX,AVX1,AVX1-FAST
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2            | FileCheck %s --check-prefixes=AVX,AVX2
 
 define float @pr26491(<4 x float> %a0) {
 ; SSE2-LABEL: pr26491:
 ; SSE2:       # %bb.0:
 ; SSE2-NEXT:    movaps %xmm0, %xmm1
 ; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[3,3]
 ; SSE2-NEXT:    addps %xmm0, %xmm1
 ; SSE2-NEXT:    movaps %xmm1, %xmm0

 ; SSE2-NEXT:    unpcklpd {{.*#+}} xmm3 = xmm3[0,0]
 ; SSE2-NEXT:    divpd %xmm3, %xmm1
 ; SSE2-NEXT:    divpd %xmm3, %xmm0
 ; SSE2-NEXT:    xorpd %xmm2, %xmm2
 ; SSE2-NEXT:    addpd %xmm2, %xmm0
 ; SSE2-NEXT:    addpd %xmm2, %xmm1
 ; SSE2-NEXT:    retq
 ;
-; SSSE3-LABEL: PR41414:
-; SSSE3:       # %bb.0:
-; SSSE3-NEXT:    movq %rdi, %xmm2
-; SSSE3-NEXT:    punpckldq {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[1],mem[1]
-; SSSE3-NEXT:    subpd {{.*}}(%rip), %xmm2
-; SSSE3-NEXT:    haddpd %xmm2, %xmm2
-; SSSE3-NEXT:    divpd %xmm2, %xmm1
-; SSSE3-NEXT:    divpd %xmm2, %xmm0
-; SSSE3-NEXT:    xorpd %xmm2, %xmm2
-; SSSE3-NEXT:    addpd %xmm2, %xmm0
-; SSSE3-NEXT:    addpd %xmm2, %xmm1
-; SSSE3-NEXT:    retq
+; SSSE3-SLOW-LABEL: PR41414:
+; SSSE3-SLOW:       # %bb.0:
+; SSSE3-SLOW-NEXT:    movq %rdi, %xmm2
+; SSSE3-SLOW-NEXT:    punpckldq {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[1],mem[1]
+; SSSE3-SLOW-NEXT:    subpd {{.*}}(%rip), %xmm2
+; SSSE3-SLOW-NEXT:    movapd %xmm2, %xmm3
+; SSSE3-SLOW-NEXT:    unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm2[1]
+; SSSE3-SLOW-NEXT:    addpd %xmm2, %xmm3
+; SSSE3-SLOW-NEXT:    movddup {{.*#+}} xmm2 = xmm3[0,0]
+; SSSE3-SLOW-NEXT:    divpd %xmm2, %xmm1
+; SSSE3-SLOW-NEXT:    divpd %xmm2, %xmm0
+; SSSE3-SLOW-NEXT:    xorpd %xmm2, %xmm2
+; SSSE3-SLOW-NEXT:    addpd %xmm2, %xmm0
+; SSSE3-SLOW-NEXT:    addpd %xmm2, %xmm1
+; SSSE3-SLOW-NEXT:    retq
+;
+; SSSE3-FAST-LABEL: PR41414:
+; SSSE3-FAST:       # %bb.0:
+; SSSE3-FAST-NEXT:    movq %rdi, %xmm2
+; SSSE3-FAST-NEXT:    punpckldq {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[1],mem[1]
+; SSSE3-FAST-NEXT:    subpd {{.*}}(%rip), %xmm2
+; SSSE3-FAST-NEXT:    haddpd %xmm2, %xmm2
+; SSSE3-FAST-NEXT:    divpd %xmm2, %xmm1
+; SSSE3-FAST-NEXT:    divpd %xmm2, %xmm0
+; SSSE3-FAST-NEXT:    xorpd %xmm2, %xmm2
+; SSSE3-FAST-NEXT:    addpd %xmm2, %xmm0
+; SSSE3-FAST-NEXT:    addpd %xmm2, %xmm1
+; SSSE3-FAST-NEXT:    retq
+;
+; AVX1-SLOW-LABEL: PR41414:
+; AVX1-SLOW:       # %bb.0:
+; AVX1-SLOW-NEXT:    vmovq %rdi, %xmm1
+; AVX1-SLOW-NEXT:    vpunpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
+; AVX1-SLOW-NEXT:    vsubpd {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-SLOW-NEXT:    vpermilpd {{.*#+}} xmm2 = xmm1[1,0]
+; AVX1-SLOW-NEXT:    vaddpd %xmm1, %xmm2, %xmm1
+; AVX1-SLOW-NEXT:    vmovddup {{.*#+}} xmm1 = xmm1[0,0]
+; AVX1-SLOW-NEXT:    vinsertf128 $1, %xmm1, %ymm1, %ymm1
+; AVX1-SLOW-NEXT:    vdivpd %ymm1, %ymm0, %ymm0
+; AVX1-SLOW-NEXT:    vxorpd %xmm1, %xmm1, %xmm1
+; AVX1-SLOW-NEXT:    vaddpd %ymm1, %ymm0, %ymm0
+; AVX1-SLOW-NEXT:    retq
 ;
-; AVX1-LABEL: PR41414:
-; AVX1:       # %bb.0:
-; AVX1-NEXT:    vmovq %rdi, %xmm1
-; AVX1-NEXT:    vpunpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
-; AVX1-NEXT:    vsubpd {{.*}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT:    vhaddpd %xmm1, %xmm1, %xmm1
-; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm1, %ymm1
-; AVX1-NEXT:    vdivpd %ymm1, %ymm0, %ymm0
-; AVX1-NEXT:    vxorpd %xmm1, %xmm1, %xmm1
-; AVX1-NEXT:    vaddpd %ymm1, %ymm0, %ymm0
-; AVX1-NEXT:    retq
+; AVX1-FAST-LABEL: PR41414:
+; AVX1-FAST:       # %bb.0:
+; AVX1-FAST-NEXT:    vmovq %rdi, %xmm1
+; AVX1-FAST-NEXT:    vpunpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
+; AVX1-FAST-NEXT:    vsubpd {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-FAST-NEXT:    vhaddpd %xmm1, %xmm1, %xmm1
+; AVX1-FAST-NEXT:    vinsertf128 $1, %xmm1, %ymm1, %ymm1
+; AVX1-FAST-NEXT:    vdivpd %ymm1, %ymm0, %ymm0
+; AVX1-FAST-NEXT:    vxorpd %xmm1, %xmm1, %xmm1
+; AVX1-FAST-NEXT:    vaddpd %ymm1, %ymm0, %ymm0
+; AVX1-FAST-NEXT:    retq
 ;
 ; AVX2-LABEL: PR41414:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vmovq %rdi, %xmm1
 ; AVX2-NEXT:    vpunpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
 ; AVX2-NEXT:    vsubpd {{.*}}(%rip), %xmm1, %xmm1
-; AVX2-NEXT:    vhaddpd %xmm1, %xmm1, %xmm1
+; AVX2-NEXT:    vpermilpd {{.*#+}} xmm2 = xmm1[1,0]
+; AVX2-NEXT:    vaddsd %xmm1, %xmm2, %xmm1
 ; AVX2-NEXT:    vbroadcastsd %xmm1, %ymm1
 ; AVX2-NEXT:    vdivpd %ymm1, %ymm0, %ymm0
 ; AVX2-NEXT:    vxorpd %xmm1, %xmm1, %xmm1
 ; AVX2-NEXT:    vaddpd %ymm1, %ymm0, %ymm0
 ; AVX2-NEXT:    retq
   %conv = uitofp i64 %x to double
   %t0 = insertelement <4 x double> undef, double %conv, i32 0
   %t1 = shufflevector <4 x double> %t0, <4 x double> undef, <4 x i32> zeroinitializer
   %t2 = fdiv <4 x double> %y, %t1
   %t3 = fadd <4 x double> zeroinitializer, %t2
   ret <4 x double> %t3
 }

llvm/test/CodeGen/X86/haddsub-broadcast.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-- -mattr=avx2  | FileCheck %s
 
 ; The broadcast node takes a vector operand as input and changes its length.
 
 define <4 x double> @PR43402(i64 %x) {
 ; CHECK-LABEL: PR43402:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    vunpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
 ; CHECK-NEXT:    vsubpd {{\.LCPI.*}}, %xmm0, %xmm0
-; CHECK-NEXT:    vhaddpd %xmm0, %xmm0, %xmm0
+; CHECK-NEXT:    vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
+; CHECK-NEXT:    vaddsd %xmm0, %xmm1, %xmm0
 ; CHECK-NEXT:    vbroadcastsd %xmm0, %ymm0
 ; CHECK-NEXT:    retl
   %conv = uitofp i64 %x to double
   %t2 = insertelement <4 x double> undef, double %conv, i32 0
   %t3 = shufflevector <4 x double> %t2, <4 x double> undef, <4 x i32> zeroinitializer
   ret <4 x double> %t3
 }
 

llvm/test/CodeGen/X86/scalar-int-to-fp.ll

 ; AVX512F_32:       # %bb.0:
 ; AVX512F_32-NEXT:    pushl %ebp
 ; AVX512F_32-NEXT:    movl %esp, %ebp
 ; AVX512F_32-NEXT:    andl $-8, %esp
 ; AVX512F_32-NEXT:    subl $8, %esp
 ; AVX512F_32-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX512F_32-NEXT:    vunpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
 ; AVX512F_32-NEXT:    vsubpd {{\.LCPI.*}}, %xmm0, %xmm0
-; AVX512F_32-NEXT:    vhaddpd %xmm0, %xmm0, %xmm0
-; AVX512F_32-NEXT:    vmovlpd %xmm0, (%esp)
+; AVX512F_32-NEXT:    vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
+; AVX512F_32-NEXT:    vaddsd %xmm0, %xmm1, %xmm0
+; AVX512F_32-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX512F_32-NEXT:    fldl (%esp)
 ; AVX512F_32-NEXT:    movl %ebp, %esp
 ; AVX512F_32-NEXT:    popl %ebp
 ; AVX512F_32-NEXT:    retl
 ;
 ; SSE2_32-LABEL: u64_to_d:
 ; SSE2_32:       # %bb.0:
 ; SSE2_32-NEXT:    pushl %ebp