Page MenuHomePhabricator

[ARM] Sink add/mul(shufflevector(insertelement(...), ...), ...) for MVE instruction selection
ClosedPublic

Authored by samtebbs on Aug 15 2019, 8:14 AM.

Details

Summary

This patch sinks add/mul(shufflevector(insertelement(...), ...), ...) into the basic block in which they are used so that they can then be selected together. This is useful for various MVE instructions, such as vmla and others that take R registers.

Loop tests have been added to the vmla test file to make sure vmlas are generated in loops.

Diff Detail

Repository
rL LLVM

Event Timeline

samtebbs created this revision.Aug 15 2019, 8:14 AM

Looks useful. What happens if there are multiple uses of the splat? Do things get handled correctly then?

llvm/lib/Target/ARM/ARMISelLowering.cpp
14263 ↗(On Diff #215402)

Do we need to check that this is an instruction, or will the match handle that for us?

14268 ↗(On Diff #215402)

ShuffleOp1 isn't needed?

samtebbs updated this revision to Diff 215596.Aug 16 2019, 7:24 AM
samtebbs marked 2 inline comments as done.
samtebbs marked 2 inline comments as done.
samtebbs added inline comments.
llvm/lib/Target/ARM/ARMISelLowering.cpp
14263 ↗(On Diff #215402)

We don't in fact, will remove.

14268 ↗(On Diff #215402)

It isn't :)

samtebbs updated this revision to Diff 216837.Aug 23 2019, 7:04 AM
samtebbs marked 2 inline comments as done.
dmgreen added inline comments.Aug 27 2019, 12:13 PM
llvm/lib/Target/ARM/ARMISelLowering.cpp
14317 ↗(On Diff #216837)

Is it possible to come up with a way to not have to repeat which instructions can be sunk to? Possibly considering things like vsub, which can only be sunk if the operand is the second instruction (although that is not your problem here, it will likely be someones problem soon enough).

llvm/test/Transforms/CodeGenPrepare/ARM/sink-add-mul-shufflevector.ll
129 ↗(On Diff #216837)

Can you change this to the first operand of the sub. There is technically an MVE VSUB instruction that takes a grp as the second operand, and I presume eventually we will be looking at making that perform the same trick we have here for add and mul.

samtebbs updated this revision to Diff 217668.Aug 28 2019, 9:15 AM
samtebbs marked 2 inline comments as done.
dmgreen added inline comments.Aug 28 2019, 10:47 AM
llvm/lib/Target/ARM/ARMISelLowering.cpp
14325 ↗(On Diff #217668)

Can you add a comment saying that we want all uses to be sunk (else we'll just end up with the same value in both gpr and vector regs!)

Also if this loop is moved to after the match check below, we won't need to do the O(n) loop if the O(1) match fails. Also negating the condition and returning early is apparently a good thing in llvm.

14327 ↗(On Diff #217668)

I think this should be checking the operand of the use, which may not be the same for the original instruction.

samtebbs marked 2 inline comments as done.Aug 29 2019, 2:30 AM
samtebbs added inline comments.
llvm/lib/Target/ARM/ARMISelLowering.cpp
14325 ↗(On Diff #217668)

Agreed.

14327 ↗(On Diff #217668)

The Op value here isn't actually used by the lambda and is only passed as a reference so that it can be set.

samtebbs updated this revision to Diff 217818.Aug 29 2019, 3:29 AM
samtebbs marked an inline comment as done.
samtebbs updated this revision to Diff 217821.Aug 29 2019, 3:33 AM
samtebbs marked an inline comment as done.
samparker added inline comments.Sep 2 2019, 7:35 AM
llvm/lib/Target/ARM/ARMISelLowering.cpp
14317 ↗(On Diff #217821)

Hoist this condition and exit early if we don't have MVE.

14329 ↗(On Diff #217821)

just cast is fine.

14332 ↗(On Diff #217821)

cast is fine.

samtebbs updated this revision to Diff 218411.Sep 3 2019, 2:06 AM
samtebbs marked 3 inline comments as done.
samparker accepted this revision.Sep 3 2019, 2:41 AM

LGTM. But please address comments before committing.

llvm/lib/Target/ARM/ARMISelLowering.cpp
14331 ↗(On Diff #218411)

But still use llvm style cast... = cast<Instruction>

llvm/test/Transforms/CodeGenPrepare/ARM/sink-add-mul-shufflevector.ll
1 ↗(On Diff #218411)

Since we have codegen support for vmla, could you also add an llc line here to test that vmlas are generated in loops.

This revision is now accepted and ready to land.Sep 3 2019, 2:41 AM

Yeah. This looks good.

We should wait to commit until we have the instructions that make use of it though. I think Oliver is working on a few patterns for VADD, VMUL and VSUB, which would cover the cases here.

Also can you add a couple of tests for sub (on there own), that the first operand is not sunk but the second operand is.

llvm/lib/Target/ARM/ARMISelLowering.cpp
14326 ↗(On Diff #218411)

Make sure you run clang-format.

samtebbs updated this revision to Diff 218671.Sep 4 2019, 5:59 AM
samtebbs marked 5 inline comments as done.
samtebbs edited the summary of this revision. (Show Details)
samtebbs added inline comments.Sep 4 2019, 7:17 AM
llvm/test/Transforms/CodeGenPrepare/ARM/sink-add-mul-shufflevector.ll
1 ↗(On Diff #218411)

I've added loop tests to the vmla test file

dmgreen accepted this revision.Sep 4 2019, 11:59 AM

Sure. LGTM

Very nice. Oliver went and put together a few patches for mul, add and sub, in https://reviews.llvm.org/D67268 and related. So we now (or soon will) produce the other instruction this can effect. This is good to go I think.

Very nice. Oliver went and put together a few patches for mul, add and sub, in https://reviews.llvm.org/D67268 and related. So we now (or soon will) produce the other instruction this can effect. This is good to go I think.

Thanks!

This revision was automatically updated to reflect the committed changes.