This is an archive of the discontinued LLVM Phabricator instance.

[ARM] Correct register for narrowing and widening MVE loads and stores.
ClosedPublic

Authored by dmgreen on Aug 15 2019, 3:15 AM.

Details

Summary

The widening and narrowing MVE instructions like VLDRH.32 are only permitted to use low "thumb1" registers. This means that if they are used for a stack slots, where the register used is only decided during frame setup, we need to be able to correctly pick a thumb1 register over a normal GPR.

This attempts to add the required logic into eliminateFrameIndex and rewriteT2FrameIndex, only picking the FrameReg if it is a valid register for the operands register class, and picking a valid scratch register for the register class.

Diff Detail

Event Timeline

dmgreen created this revision.Aug 15 2019, 3:15 AM
chill added a subscriber: chill.Aug 15 2019, 5:23 AM
ostannard added inline comments.Aug 16 2019, 2:15 AM
llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
656

Is it possible to get here with a virtual register of the wrong class? I think we'd need a call to constrainRegClass here in that case.

dmgreen marked an inline comment as done.Aug 16 2019, 4:12 AM

Thanks for taking a look

llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
656

Hmm, I have not seen us hit this, but it's certainly better to be safe than sorry! I'll add a check.

dmgreen updated this revision to Diff 215560.Aug 16 2019, 4:13 AM
dmgreen marked an inline comment as done.
ostannard accepted this revision.Aug 16 2019, 5:08 AM

LGTM, thanks

This revision is now accepted and ready to land.Aug 16 2019, 5:08 AM

Thanks!

This has survived a Thumb2 bootstrap without issue at least.

This revision was automatically updated to reflect the committed changes.