[PowerPC] Fix ICE when truncating to vector with odd-size elements.

[qiucf]

Summary

In type legalizing on PowerPC platform, when we are going to truncate normal vectors into vectors with elements whose size is not power of 2, the compiler will hit an assert complaining size-mismatch. Since such situation is rare, I add a check to prevent the trunc being optimized if the size of element is not power of 2.

[hfinkel]

LGTM

[MaskRay]

llvm/test/CodeGen/PowerPC/pr25080.ll

1 ↗

(On Diff #211662)

Is update_llc_test_checks too much for an assertion fix?

[MaskRay]

pr25080.ll

Did you write a wrong PR number?

[qiucf]

In D65261#1621307, @MaskRay wrote:

pr25080.ll

Did you write a wrong PR number?

PR25080 is originally a X86 bug and this test is the piece of code to reproduce it, which is fixed by D13660.

[qiucf]

llvm/test/CodeGen/PowerPC/pr25080.ll

1 ↗

(On Diff #211662)

Checking if it exits successfully with no diagnostics is enough for an assertion fix. Here I just disabled doing the optimization since the occasion is rare.

In case someone would like to do it for such odd vectors in the future, I recommend to keep it as-is. After that, this case can notify and be changed.

llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
   case ISD::FP_TO_UINT:
     // LowerFP_TO_INT() can only handle f32 and f64.
     if (N->getOperand(0).getValueType() == MVT::ppcf128)
       return;
     Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
     return;
   case ISD::TRUNCATE: {
     EVT TrgVT = N->getValueType(0);
+    EVT OpVT = N->getOperand(0).getValueType();
     if (TrgVT.isVector() &&
         isOperationCustom(N->getOpcode(), TrgVT) &&
-        N->getOperand(0).getValueType().getSizeInBits() <= 128)
+        OpVT.getSizeInBits() <= 128 &&
+        isPowerOf2_32(OpVT.getVectorElementType().getSizeInBits()))
       Results.push_back(LowerTRUNCATEVector(SDValue(N, 0), DAG));
     return;
   }
   case ISD::BITCAST:
     // Don't handle bitcast here.
     return;
   }
 }

llvm/trunk/test/CodeGen/PowerPC/pr25080.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- -mcpu=pwr8 < %s | FileCheck %s --check-prefix=LE
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -mcpu=pwr8 < %s | FileCheck %s --check-prefix=BE
+
+define <8 x i16> @pr25080(<8 x i32> %a) {
+; LE-LABEL: pr25080:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
+; LE-NEXT:    xxlxor 37, 37, 37
+; LE-NEXT:    addi 3, 3, .LCPI0_0@toc@l
+; LE-NEXT:    lvx 4, 0, 3
+; LE-NEXT:    xxland 34, 34, 36
+; LE-NEXT:    xxland 35, 35, 36
+; LE-NEXT:    vcmpequw 2, 2, 5
+; LE-NEXT:    vcmpequw 3, 3, 5
+; LE-NEXT:    xxswapd 0, 34
+; LE-NEXT:    mfvsrwz 3, 34
+; LE-NEXT:    xxsldwi 1, 34, 34, 1
+; LE-NEXT:    mfvsrwz 4, 35
+; LE-NEXT:    xxsldwi 4, 34, 34, 3
+; LE-NEXT:    mtvsrd 2, 3
+; LE-NEXT:    mfvsrwz 3, 0
+; LE-NEXT:    xxswapd 0, 35
+; LE-NEXT:    mtvsrd 3, 4
+; LE-NEXT:    xxsldwi 5, 35, 35, 1
+; LE-NEXT:    mfvsrwz 4, 1
+; LE-NEXT:    xxsldwi 7, 35, 35, 3
+; LE-NEXT:    mtvsrd 1, 3
+; LE-NEXT:    xxswapd 33, 3
+; LE-NEXT:    mfvsrwz 3, 4
+; LE-NEXT:    mtvsrd 4, 4
+; LE-NEXT:    xxswapd 34, 1
+; LE-NEXT:    mfvsrwz 4, 0
+; LE-NEXT:    mtvsrd 0, 3
+; LE-NEXT:    xxswapd 35, 4
+; LE-NEXT:    mfvsrwz 3, 5
+; LE-NEXT:    mtvsrd 6, 4
+; LE-NEXT:    xxswapd 36, 0
+; LE-NEXT:    mtvsrd 1, 3
+; LE-NEXT:    mfvsrwz 3, 7
+; LE-NEXT:    xxswapd 37, 6
+; LE-NEXT:    vmrglh 2, 3, 2
+; LE-NEXT:    xxswapd 35, 2
+; LE-NEXT:    mtvsrd 2, 3
+; LE-NEXT:    xxswapd 32, 1
+; LE-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
+; LE-NEXT:    addi 3, 3, .LCPI0_1@toc@l
+; LE-NEXT:    xxswapd 38, 2
+; LE-NEXT:    vmrglh 3, 4, 3
+; LE-NEXT:    vmrglh 4, 0, 5
+; LE-NEXT:    vmrglh 5, 6, 1
+; LE-NEXT:    vmrglw 2, 3, 2
+; LE-NEXT:    vmrglw 3, 5, 4
+; LE-NEXT:    vspltish 4, 15
+; LE-NEXT:    xxmrgld 34, 35, 34
+; LE-NEXT:    lvx 3, 0, 3
+; LE-NEXT:    xxlor 34, 34, 35
+; LE-NEXT:    vslh 2, 2, 4
+; LE-NEXT:    vsrah 2, 2, 4
+; LE-NEXT:    blr
+;
+; BE-LABEL: pr25080:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
+; BE-NEXT:    xxlxor 36, 36, 36
+; BE-NEXT:    addi 3, 3, .LCPI0_0@toc@l
+; BE-NEXT:    lxvw4x 0, 0, 3
+; BE-NEXT:    xxland 35, 35, 0
+; BE-NEXT:    xxland 34, 34, 0
+; BE-NEXT:    vcmpequw 3, 3, 4
+; BE-NEXT:    vcmpequw 2, 2, 4
+; BE-NEXT:    xxswapd 0, 35
+; BE-NEXT:    mfvsrwz 3, 35
+; BE-NEXT:    xxsldwi 1, 35, 35, 1
+; BE-NEXT:    sldi 3, 3, 48
+; BE-NEXT:    mfvsrwz 4, 0
+; BE-NEXT:    xxsldwi 0, 35, 35, 3
+; BE-NEXT:    mtvsrd 36, 3
+; BE-NEXT:    mfvsrwz 3, 1
+; BE-NEXT:    sldi 4, 4, 48
+; BE-NEXT:    xxswapd 1, 34
+; BE-NEXT:    mtvsrd 35, 4
+; BE-NEXT:    mfvsrwz 4, 34
+; BE-NEXT:    sldi 3, 3, 48
+; BE-NEXT:    mtvsrd 37, 3
+; BE-NEXT:    mfvsrwz 3, 0
+; BE-NEXT:    sldi 4, 4, 48
+; BE-NEXT:    xxsldwi 0, 34, 34, 1
+; BE-NEXT:    vmrghh 3, 5, 3
+; BE-NEXT:    mtvsrd 37, 4
+; BE-NEXT:    sldi 3, 3, 48
+; BE-NEXT:    mfvsrwz 4, 1
+; BE-NEXT:    xxsldwi 1, 34, 34, 3
+; BE-NEXT:    mtvsrd 34, 3
+; BE-NEXT:    mfvsrwz 3, 0
+; BE-NEXT:    sldi 4, 4, 48
+; BE-NEXT:    mtvsrd 32, 4
+; BE-NEXT:    mfvsrwz 4, 1
+; BE-NEXT:    sldi 3, 3, 48
+; BE-NEXT:    mtvsrd 33, 3
+; BE-NEXT:    sldi 3, 4, 48
+; BE-NEXT:    vmrghh 2, 2, 4
+; BE-NEXT:    mtvsrd 36, 3
+; BE-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
+; BE-NEXT:    vmrghh 0, 1, 0
+; BE-NEXT:    addi 3, 3, .LCPI0_1@toc@l
+; BE-NEXT:    vmrghh 4, 4, 5
+; BE-NEXT:    lxvw4x 0, 0, 3
+; BE-NEXT:    vmrghw 2, 2, 3
+; BE-NEXT:    vmrghw 3, 4, 0
+; BE-NEXT:    xxmrghd 34, 35, 34
+; BE-NEXT:    vspltish 3, 15
+; BE-NEXT:    xxlor 34, 34, 0
+; BE-NEXT:    vslh 2, 2, 3
+; BE-NEXT:    vsrah 2, 2, 3
+; BE-NEXT:    blr
+entry:
+  %0 = trunc <8 x i32> %a to <8 x i23>
+  %1 = icmp eq <8 x i23> %0, zeroinitializer
+  %2 = or <8 x i1> %1, <i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>
+  %3 = sext <8 x i1> %2 to <8 x i16>
+  ret <8 x i16> %3
+}