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RolandF (Roland Froese)
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User Since
May 16 2016, 11:34 AM (165 w, 3 d)

Recent Activity

Today

RolandF created D64960: [PowerPC] Expand v1i128 smin.
Thu, Jul 18, 4:26 PM · Restricted Project

Thu, Jun 27

RolandF committed rG9f7f5858fe46: Recommit [PowerPC] Update P9 vector costs for insert/extract element (authored by RolandF).
Recommit [PowerPC] Update P9 vector costs for insert/extract element
Thu, Jun 27, 9:21 AM

Mon, Jun 24

RolandF committed rGea08248b2bc9: [CodeGen] Add missing vector type legalization for ctlz_zero_undef (authored by RolandF).
[CodeGen] Add missing vector type legalization for ctlz_zero_undef
Mon, Jun 24, 12:29 PM

Jun 18 2019

RolandF updated the diff for D63463: [CodeGen] Add missing vector type legalization for ctlz_zero_undef.

Generated test checks with script.

Jun 18 2019, 3:55 PM · Restricted Project
RolandF updated the diff for D63463: [CodeGen] Add missing vector type legalization for ctlz_zero_undef.

Add X86 test.

Jun 18 2019, 10:47 AM · Restricted Project

Jun 17 2019

RolandF created D63463: [CodeGen] Add missing vector type legalization for ctlz_zero_undef.
Jun 17 2019, 4:06 PM · Restricted Project

May 13 2019

RolandF added a comment to D59514: [PGO] Profile guided code size optimization..

The following file and command should reproduce the failure we are seeing.

May 13 2019, 3:16 PM · Restricted Project

May 6 2019

RolandF added a comment to D59514: [PGO] Profile guided code size optimization..

This revision causes a traceback when compiling SPEC2017 523.xalanbmk_r with -O3 -m64 -mcpu=power9 -flto and PGO, on the -fprofile-use compile step for XMLDateTime.cpp. Can you please take a look? Let me know if don't have access to SPEC0217 source and need a reproducer. The traceback was as follows:

May 6 2019, 9:34 AM · Restricted Project

Apr 29 2019

RolandF committed rG728e13970088: [PowerPC] Try harder to avoid load/move-to VSR for partial vector loads (authored by RolandF).
[PowerPC] Try harder to avoid load/move-to VSR for partial vector loads
Apr 29 2019, 2:12 PM

Apr 26 2019

RolandF committed rG4b17772b9ee7: [PowerPC] Update P9 vector costs for insert/extract element (authored by RolandF).
[PowerPC] Update P9 vector costs for insert/extract element
Apr 26 2019, 9:15 AM

Apr 18 2019

RolandF committed rGa5dd08cac299: [PowerPC] Add some PPC vec cost tests to prep for D60160 NFC (authored by RolandF).
[PowerPC] Add some PPC vec cost tests to prep for D60160 NFC
Apr 18 2019, 11:11 AM

Apr 2 2019

RolandF added reviewers for D60160: [PowerPC] Update P9 vector costs for insert/extract element: jsji, nemanjai.
Apr 2 2019, 3:48 PM · Restricted Project
RolandF created D60160: [PowerPC] Update P9 vector costs for insert/extract element.
Apr 2 2019, 3:45 PM · Restricted Project

Apr 1 2019

RolandF created D60102: [PowerPC] Try harder to avoid load/move-to VSR for partial vector loads.
Apr 1 2019, 3:41 PM · Restricted Project

Feb 11 2019

RolandF committed rG732fe22454da: [PowerPC] Avoid scalarization of vector truncate (authored by RolandF).
[PowerPC] Avoid scalarization of vector truncate
Feb 11 2019, 9:29 AM

Feb 8 2019

RolandF updated the diff for D56507: [PowerPC] Avoid scalarization of vector truncate.

Update diff to show test changes and respond to comments.

Feb 8 2019, 3:30 PM · Restricted Project

Feb 7 2019

Herald added a project to D56507: [PowerPC] Avoid scalarization of vector truncate: Restricted Project.
Feb 7 2019, 3:42 PM · Restricted Project

Feb 6 2019

RolandF added inline comments to D56507: [PowerPC] Avoid scalarization of vector truncate.
Feb 6 2019, 2:47 PM · Restricted Project
RolandF committed rG42f58498c563: [PowerPC] Add vector truncate test to prep for D56507 NFC (authored by RolandF).
[PowerPC] Add vector truncate test to prep for D56507 NFC
Feb 6 2019, 1:36 PM

Jan 25 2019

RolandF added a comment to D55461: [PowerPC] Update Vector Costs for P9.

@nemanjai Yes, please, I do need it committed for me. Last time I promise!

Jan 25 2019, 2:45 PM
RolandF updated the diff for D55461: [PowerPC] Update Vector Costs for P9.

Deleted commented out code and added suggested comments.

Jan 25 2019, 11:51 AM

Jan 17 2019

RolandF added inline comments to D55461: [PowerPC] Update Vector Costs for P9.
Jan 17 2019, 10:24 AM
RolandF updated the diff for D55461: [PowerPC] Update Vector Costs for P9.

Added a new TTI method vectorCostAdjustment to consolidate and make uniform for all instruction types the checks and cost modification.

Jan 17 2019, 10:02 AM

Jan 11 2019

RolandF added a comment to D55461: [PowerPC] Update Vector Costs for P9.

For memory ops it should be the same as arithmetic. The LSUs are a separate resource from the slices, but a vector load or store still consumes multiple LSUs (2x if aligned, 3x if not). I don't follow why there should be a problem with shuffle - I assume a shuffle will require one or more vector ALU ops.

Jan 11 2019, 2:44 PM

Jan 9 2019

RolandF added a comment to D55461: [PowerPC] Update Vector Costs for P9.

I don't think adding a new TTI function is necessary, as I think the way I am modeling the costs here is what is expected. The following comment (from TargetTransformInfo.h: getArithmeticInstrCost()) may shed some light:

Jan 9 2019, 3:50 PM
RolandF updated the diff for D56507: [PowerPC] Avoid scalarization of vector truncate.

Fix comment.

Jan 9 2019, 3:28 PM · Restricted Project
RolandF created D56507: [PowerPC] Avoid scalarization of vector truncate.
Jan 9 2019, 11:17 AM · Restricted Project

Dec 18 2018

RolandF added a comment to D55461: [PowerPC] Update Vector Costs for P9.

I am confused by this patch.

In LoopVectorize.cpp, getInstructionCost returns the execution time cost of an instruction for a given vector.

So I think the cost model here should be related to latency.

Why we need to take into consideration of execution units for execution time cost ?
Considering execution units looks more like throughput cost model?

Dec 18 2018, 9:43 AM

Dec 7 2018

RolandF created D55461: [PowerPC] Update Vector Costs for P9.
Dec 7 2018, 4:02 PM

Nov 21 2018

RolandF added inline comments to D54663: [PowerPC] Complete the custom legalization of vector int to fp conversion.
Nov 21 2018, 3:19 PM

Nov 20 2018

RolandF added a comment to D54663: [PowerPC] Complete the custom legalization of vector int to fp conversion.

Nice! Glad to see this stuff get completed.

Nov 20 2018, 10:49 AM

Oct 23 2018

RolandF updated the diff for D53346: [PowerPC] Keep vector int to fp conversions in vector domain.

Address review comments - change variable names, support/test big-endian.

Oct 23 2018, 9:29 AM

Oct 16 2018

RolandF created D53346: [PowerPC] Keep vector int to fp conversions in vector domain.
Oct 16 2018, 4:09 PM

Aug 15 2018

RolandF added inline comments to D49879: [PowerPC] Generate Power9 extswsli extend sign and shift immediate instruction.
Aug 15 2018, 12:00 PM
RolandF updated the diff for D49879: [PowerPC] Generate Power9 extswsli extend sign and shift immediate instruction.

Changed == NULL to == nullptr.

Aug 15 2018, 11:57 AM

Aug 14 2018

RolandF updated the diff for D49879: [PowerPC] Generate Power9 extswsli extend sign and shift immediate instruction.

Update to access constant shift amount by dynamic cast and to reverse if from block form to early exit.

Aug 14 2018, 3:37 PM

Aug 8 2018

RolandF updated the diff for D49879: [PowerPC] Generate Power9 extswsli extend sign and shift immediate instruction.

Updated to incorporate review comments.

Aug 8 2018, 3:32 PM

Aug 2 2018

RolandF updated subscribers of D49879: [PowerPC] Generate Power9 extswsli extend sign and shift immediate instruction.
Aug 2 2018, 9:47 AM

Jul 26 2018

RolandF created D49879: [PowerPC] Generate Power9 extswsli extend sign and shift immediate instruction.
Jul 26 2018, 3:22 PM

Aug 24 2016

RolandF updated the diff for D23467: Generate -1/0/1 memcmp/strcmp result for z13.

Unlike the php test failure, which is dependent on the library memcmp behaviour and fails for both clang and gcc, the postgres test failure only happens with clang. The uuid regression test fails for clang, and the failure goes away if src/backend/utils/adt/uuid.c is compiled with gcc. The issue is the result for the uuid_internal_cmp function, which is just a 16 byte memcmp. The address of the function is stored in a table of builtins and only called by address, and the complexity of the application and test environment make it difficult to trace back to where this function is called, which may be many places. It might be desirable to just be compatible with gcc. This diff updates the approach to use the gcc-type IPM/SLL/SRA sequence. The sequence is first translated into a SELECT_CMP operation. This makes it easier to perform the memcmp compare to zero optimization (SRA kills the CC). It also should make it easier to add support for LOCHI, since the compare to zero code can be shared, and to get the promotion to 64-bit case with shared code.

Aug 24 2016, 12:16 PM

Aug 19 2016

RolandF added a comment to D23467: Generate -1/0/1 memcmp/strcmp result for z13.

I took a look at the php problem. It was failing test /ext/standard/tests/strings/substr_compare.phpt, due to a -2 from a substr_compare operation where -1 was expected. The implementation in Zend/zend_operators.c is a call to the library memcmp function, so it is not a compiler issue.

Aug 19 2016, 1:55 PM

Aug 17 2016

RolandF added a comment to D23467: Generate -1/0/1 memcmp/strcmp result for z13.

The ipm/sll/sra sequence gives -2/0/1 rather than -1/0/1.

Aug 17 2016, 3:59 PM

Aug 16 2016

RolandF updated D23467: Generate -1/0/1 memcmp/strcmp result for z13.
Aug 16 2016, 3:11 PM

Aug 15 2016

RolandF updated subscribers of D23467: Generate -1/0/1 memcmp/strcmp result for z13.
Aug 15 2016, 11:15 AM
RolandF added a reviewer for D23467: Generate -1/0/1 memcmp/strcmp result for z13: uweigand.
Aug 15 2016, 7:49 AM

Aug 12 2016

RolandF retitled D23467: Generate -1/0/1 memcmp/strcmp result for z13 from to Generate -1/0/1 memcmp/strcmp result for z13.
Aug 12 2016, 2:51 PM

Jul 11 2016

RolandF updated the diff for D22117: [SystemZ] Recognize Load On Condition Immediate (LOCHI/LOGHI) opportunities.

Added assembler tests.

Jul 11 2016, 9:51 AM

Jul 7 2016

RolandF retitled D22117: [SystemZ] Recognize Load On Condition Immediate (LOCHI/LOGHI) opportunities from to [SystemZ] Recognize Load On Condition Immediate (LOCHI/LOGHI) opportunities.
Jul 7 2016, 3:42 PM

Jun 21 2016

RolandF added inline comments to D21452: [SystemZ] Recognize RISBG opportunities involving a truncate.
Jun 21 2016, 1:31 PM
RolandF updated the diff for D21452: [SystemZ] Recognize RISBG opportunities involving a truncate.

Added tests.
Added check for RNSBG.
Added TRUNCATE profitability check to tryRxSBG.
Added comment to TRUNCATE profitability check.
Updated comment on struct RxSBGOperands.

Jun 21 2016, 1:28 PM

Jun 17 2016

RolandF retitled D21452: [SystemZ] Recognize RISBG opportunities involving a truncate from Recognize narrowing RISBG opportunities to [SystemZ] Recognize RISBG opportunities involving a truncate.
Jun 17 2016, 8:13 AM

Jun 16 2016

RolandF retitled D21452: [SystemZ] Recognize RISBG opportunities involving a truncate from to Recognize narrowing RISBG opportunities.
Jun 16 2016, 3:48 PM