[Xtensa 8/10] Add support of the Xtensa shift/load/store/move and processor control instructions.

[andreisfr]

Summary

Add new subset of Core Instructions (not full yet). Add appropriate operands description,
modify asm parser, printer and code emitter. Modify tests to support new instructions.

[arsenm]

llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp

137–139

There are already various forms of isInt/isUInt in MathExtras.h

[andreisfr]

Register names are capitalized.

[andreisfr]

llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp

137–139

Did you mean do not create/use special functions isImm and inRange? Initially I used the same approach as in SystemZ and AArch64 architecture, because we need to check whether expression immediate and also get value of it.

[andreisfr]

Patch is updated according to latest upstream version.

[andreisfr]

Patch is updated according to LLVM upstream version and latest Xtensa backend version.

[andreisfr]

Correct instruction descriptions, format descriptions and instruction operands according to common style for *.td files. The llvm_unreachable is substituted to report_fatal_error.