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[Xtensa 8/10] Add support of the Xtensa shift/load/store/move and processor control instructions.
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Authored by andreisfr on Jul 16 2019, 3:28 PM.

Details

Reviewers
jyknight
ivanbaev
Summary

Add new subset of Core Instructions (not full yet). Add appropriate operands description,
modify asm parser, printer and code emitter. Modify tests to support new instructions.

Diff Detail

Event Timeline

andreisfr created this revision.Jul 16 2019, 3:28 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 16 2019, 3:28 PM
arsenm added a subscriber: arsenm.Jul 16 2019, 3:35 PM
arsenm added inline comments.
llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
133–135

There are already various forms of isInt/isUInt in MathExtras.h

andreisfr updated this revision to Diff 212693.Jul 31 2019, 4:02 PM

Register names are capitalized.

andreisfr marked an inline comment as done.Jul 31 2019, 4:49 PM
andreisfr added inline comments.
llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
133–135

Did you mean do not create/use special functions isImm and inRange? Initially I used the same approach as in SystemZ and AArch64 architecture, because we need to check whether expression immediate and also get value of it.

andreisfr updated this revision to Diff 242218.Feb 3 2020, 3:19 PM

Patch is updated according to latest upstream version.