[AIX] Implement LR prolog/epilog save/restore

[cebowleratibm]

Summary

This patch fixes the offsets of fields in the stack frame linkage save area for AIX.

[jsji]

FYI. You can Edit Related Revision to set the parent revision to show dependency.

[sfertile]

I'll have to dig into the AIX ABI docs before I can review this more thoroughly but it looks good. I suggest we split out renaming of the hardcoded '8' to --> getCRSaveOffset() as a separate NFC patch and that we can land immediately.

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

795

minor nit: Can we just say Unsupported PPC ABI?

802

FWIW according to the original commit that guards this for ELF it shouldn't be needed for AIX either:

commit 38d945872097549606ea62b64ded743afdab0648
Author: Bill Schmidt <[e-mail]>
Date:   Wed Oct 10 20:54:15 2012 +0000

    The PowerPC VRSAVE register has been somewhat of an odd beast since
    the Altivec extensions were introduced.  Its use is optional, and
    allows the compiler to communicate to the operating system which
    vector registers should be saved and restored during a context switch.
    In practice, this information is ignored by the various operating
    systems using the SVR4 ABI; the kernel saves and restores the entire
    register state.  Setting the VRSAVE register is no longer performed by
    the AIX XL compilers, the IBM i compilers, or by GCC on Power Linux
    systems.  It seems best to avoid this logic within LLVM as well.
    
    This patch avoids generating code to update and restore VRSAVE for the
    PowerPC SVR4 ABIs (32- and 64-bit).  The code remains in place for the
    Darwin ABI.
    
    llvm-svn: 165656

[cebowleratibm]

Rebased changes after D63738 and

commit 9bd22fec0d7bee6fa32479ba090b9c89656c0a3c
Date: Fri Jul 26 14:02:17 2019 +0000

[PowerPC] Add getCRSaveOffset to improve readability. [NFC]

Other NFC change to update assertion text.

[hubert.reinterpretcast]

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

58

The patch does not add testing for this.

802

It is also documented by the Assembler Language Reference for AIX version 7.2 that VRSAVE is not to be used or modified by AIX ABI-compliant programs.

923

Minor nit: Let's treat report_fatal_error messages as consisting of full sentences. This one should end in a period.

llvm/test/CodeGen/PowerPC/aix-lr.ll

13

Can we check for the stack pointer adjustment in the prologue? As it is, I am under the impression that the saved link register would be overwritten by the call.

22

Same comment.

[hubert.reinterpretcast]

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

62

This patch does not add testing for this.

83

This patch does not add testing for this.

87

This looks like a copy/paste error (copied from line 71).

90

This logic does not seem to be common for 32-bit SVR4 and 32-bit AIX. See PPCFrameLowering::determineCalleeSaves:

// Reserve stack space for the PIC Base register (R30).
// Only used in SVR4 32-bit.

[sfertile]

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

62

Chris and I had briefly discussed this offline and I asked that we add asserts (or errors) if we need a frame-pointer or base-pointer on AIX. We can then add the testing and remove the assert/errors in a subsequent patch

[cebowleratibm]

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

58

Because the TOC save/restore is typically handled in the glue code / nop that follows the call, I don't have a reliable way to exercise this functionality. I believe this offset comes into play for indirect calls, however, we haven't implemented that for AIX yet.

I'll add a report_fatal_error on the code path but leave the new logic in place.

87

I'll defer this to the FP/BP follow on work.

90

to be addressed in FP/BP follow on work.

795

Updated the assertion text.

802

Noted and we should simplify this in a separate patch when we remove Darwin support.

llvm/test/CodeGen/PowerPC/aix-lr.ll

13

"stwu 1, -64(1)" is the SP adjustment in the prolog. Why do you think the saved link register would be overwritten by the call? This code saves the LR at offset 8 from SP, then saves the SP at offset 0 from SP and decrements SP by 64.

[cebowleratibm]

Update the TOC, FP and BP offset accessors to assert for AIX. The assertions will be removed with future work that accompanied by appropriate test coverage.

[hubert.reinterpretcast]

LGTM.

llvm/test/CodeGen/PowerPC/aix-lr.ll

13

I missed that this was using the update form of the instruction. Sorry for the noise.

[hubert.reinterpretcast]

My attempt to commit this only committed the test. I'll try again once the bots clear.

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

 static const MCPhysReg VRRegNo[] = {
  PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
  PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
  PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
  PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
 };
 
 static unsigned computeReturnSaveOffset(const PPCSubtarget &STI) {
-  if (STI.isDarwinABI())
+  if (STI.isDarwinABI() || STI.isAIXABI())
     return STI.isPPC64() ? 16 : 8;
   // SVR4 ABI:
   return STI.isPPC64() ? 16 : 4;
 }
 
 static unsigned computeTOCSaveOffset(const PPCSubtarget &STI) {
+  if (STI.isAIXABI())
+     return STI.isPPC64() ? 40 : 20;
   return STI.isELFv2ABI() ? 24 : 40;
 }
 
 static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI) {
   // For the Darwin ABI:
   // We cannot use the TOC save slot (offset +20) in the PowerPC linkage area
   // for saving the frame pointer (if needed.)  While the published ABI has
   // not used this slot since at least MacOSX 10.2, there is older code
   // around that does use it, and that needs to continue to work.
   if (STI.isDarwinABI())
     return STI.isPPC64() ? -8U : -4U;
 
-  // SVR4 ABI: First slot in the general register save area.
+  // SVR4/AIX ABI: First slot in the general register save area.
   return STI.isPPC64() ? -8U : -4U;
 }
 
 static unsigned computeLinkageSize(const PPCSubtarget &STI) {
   if ((STI.isDarwinABI() || STI.isAIXABI()) || STI.isPPC64())
     return (STI.isELFv2ABI() ? 4 : 6) * (STI.isPPC64() ? 8 : 4);
 
   // 32-bit SVR4 ABI:
   return 8;
 }
 
 static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI) {
   if (STI.isDarwinABI())
     return STI.isPPC64() ? -16U : -8U;
 
-  // SVR4 ABI: First slot in the general register save area.
+  // SVR4/AIX ABI: First slot in the general register save area.
   return STI.isPPC64()
              ? -16U
              : STI.getTargetMachine().isPositionIndependent() ? -12U : -8U;
 }
 
 static unsigned computeCRSaveOffset() {
   // The condition register save offset needs to be updated for AIX PPC32.
   return 8;
 }
 
 PPCFrameLowering::PPCFrameLowering(const PPCSubtarget &STI)
void PPCFrameLowering::emitPrologue(MachineFunction &MF,
   DebugLoc dl;
   bool needsCFI = MMI.hasDebugInfo() ||
     MF.getFunction().needsUnwindTableEntry();
 
   // Get processor type.
   bool isPPC64 = Subtarget.isPPC64();
   // Get the ABI.
   bool isSVR4ABI = Subtarget.isSVR4ABI();
+  bool isAIXABI = Subtarget.isAIXABI();
   bool isELFv2ABI = Subtarget.isELFv2ABI();
-  assert((Subtarget.isDarwinABI() || isSVR4ABI) &&
-         "Currently only Darwin and SVR4 ABIs are supported for PowerPC.");
+  assert((Subtarget.isDarwinABI() || isSVR4ABI || isAIXABI) &&
+         "Unsupported PPC ABI.");
 
   // Scan the prolog, looking for an UPDATE_VRSAVE instruction.  If we find it,
   // process it.
   if (!isSVR4ABI)
     for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
-      if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
+      if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {        
+        if (isAIXABI)
+          report_fatal_error("VRSAVE is unimplemented on AIX");        
         HandleVRSaveUpdate(*MBBI, TII);
         break;
       }
     }
 
   // Move MBBI back to the beginning of the prologue block.
   MBBI = MBB.begin();
 
void PPCFrameLowering::emitPrologue(MachineFunction &MF,
 
   // Frames of 32KB & larger require special handling because they cannot be
   // indexed into with a simple STDU/STWU/STD/STW immediate offset operand.
   bool isLargeFrame = !isInt<16>(NegFrameSize);
 
   assert((isPPC64 || !MustSaveCR) &&
          "Prologue CR saving supported only in 64-bit mode");
 
+  if (MustSaveCR && isAIXABI)
+    report_fatal_error("Prologue CR saving is unimplemented on AIX");
+
   // Check if we can move the stack update instruction (stdu) down the prologue
   // past the callee saves. Hopefully this will avoid the situation where the
   // saves are waiting for the update on the store with update to complete.
   MachineBasicBlock::iterator StackUpdateLoc = MBBI;
   bool MovingStackUpdateDown = false;
 
   // Check if we can move the stack update.
   if (stackUpdateCanBeMoved(MF)) {

llvm/test/CodeGen/PowerPC/aix-lr.ll

+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff < %s | \
+; RUN: FileCheck --check-prefix=32BIT %s
+
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff < %s | \
+; RUN: FileCheck --check-prefix=64BIT %s
+
+define void @bar() {
+entry:
+
+; 32BIT: mflr 0
+; 32BIT: stw 0, 8(1)
+; 32BIT: stwu 1, -64(1)
+; 32BIT: bl .foo
+; 32BIT: nop
+; 32BIT: addi 1, 1, 64
+; 32BIT: lwz 0, 8(1)
+; 32BIT: mtlr 0
+
+; 64BIT: mflr 0
+; 64BIT: std 0, 16(1)
+; 64BIT: stdu 1, -112(1)
+; 64BIT: bl .foo
+; 64BIT: nop
+; 64BIT: addi 1, 1, 112
+; 64BIT: ld 0, 16(1)
+; 64BIT: mtlr 0
+
+  call void bitcast (void (...)* @foo to void ()*)()
+  ret void
+}
+
+declare void @foo(...)

llvm/test/CodeGen/PowerPC/test_call_aix.ll

-; XFAIL: asserts
-
 ; RUN: llc -mtriple powerpc-ibm-aix-xcoff -stop-after=machine-cp < %s | \
 ; RUN: FileCheck --check-prefix=32BIT %s
 
 ; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -stop-after=machine-cp < %s | \
 ; RUN: FileCheck --check-prefix=64BIT %s
 
 ; RUN: llc -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
 ; RUN: llc -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s