[ARM] Enable VPUSH/VPOP aliases when either MVE or VFP is present

[miyuki]

Summary

Use the same predicates as VSTMDB/VLDMIA since VPUSH/VPOP alias to
these.

Patch by Momchil Velikov.

[dmgreen]

llvm/lib/Target/ARM/ARMInstrVFP.td

312 ↗

(On Diff #208662)

Are these needed too, for the optional suffix?

[miyuki]

Changed predicate for variants with suffixes

[miyuki]

Uploaded the correct patch

[dmgreen]

Other than a couple of test nits, LGTM.

llvm/test/MC/ARM/mve-fp-registers.s

52 ↗

(On Diff #208751)

I think this should be vpop.64

64 ↗

(On Diff #208751)

same here.

88 ↗

(On Diff #208751)

and this one vpush.32

(although none of these we seems to be very stringent on, the spec says "If present, it must be equal to the size in bits, 32 or 64, of the registers being transferred." )

llvm/lib/Target/ARM/ARMInstrMVE.td

 multiclass MVE_unpred_vector_store<Instruction RegImmInst, PatFrag StoreKind,
                                    int shift> {
   def : MVE_unpred_vector_store_typed<v16i8, RegImmInst, StoreKind, shift>;
   def : MVE_unpred_vector_store_typed<v8i16, RegImmInst, StoreKind, shift>;
   def : MVE_unpred_vector_store_typed<v8f16, RegImmInst, StoreKind, shift>;
   def : MVE_unpred_vector_store_typed<v4i32, RegImmInst, StoreKind, shift>;
   def : MVE_unpred_vector_store_typed<v4f32, RegImmInst, StoreKind, shift>;
   def : MVE_unpred_vector_store_typed<v2i64, RegImmInst, StoreKind, shift>;
+  def : MVE_unpred_vector_store_typed<v2f64, RegImmInst, StoreKind, shift>;
 }
 
 class MVE_unpred_vector_load_typed<ValueType Ty, Instruction RegImmInst,
                                    PatFrag LoadKind, int shift>
       : Pat<(Ty (LoadKind t2addrmode_imm7<shift>:$addr)),
           (Ty (RegImmInst t2addrmode_imm7<shift>:$addr))>;
 multiclass MVE_unpred_vector_load<Instruction RegImmInst, PatFrag LoadKind,
                                   int shift> {
   def : MVE_unpred_vector_load_typed<v16i8, RegImmInst, LoadKind, shift>;
   def : MVE_unpred_vector_load_typed<v8i16, RegImmInst, LoadKind, shift>;
   def : MVE_unpred_vector_load_typed<v8f16, RegImmInst, LoadKind, shift>;
   def : MVE_unpred_vector_load_typed<v4i32, RegImmInst, LoadKind, shift>;
   def : MVE_unpred_vector_load_typed<v4f32, RegImmInst, LoadKind, shift>;
   def : MVE_unpred_vector_load_typed<v2i64, RegImmInst, LoadKind, shift>;
+  def : MVE_unpred_vector_load_typed<v2f64, RegImmInst, LoadKind, shift>;
 }
 
 let Predicates = [HasMVEInt, IsLE] in {
   defm : MVE_unpred_vector_store<MVE_VSTRBU8, byte_alignedstore, 0>;
   defm : MVE_unpred_vector_store<MVE_VSTRHU16, hword_alignedstore, 1>;
   defm : MVE_unpred_vector_store<MVE_VSTRWU32, alignedstore32, 2>;
 
   defm : MVE_unpred_vector_load<MVE_VLDRBU8, byte_alignedload, 0>;

llvm/test/CodeGen/Thumb2/mve-basic.ll

 ; CHECK-NEXT:    vstrw.32 q0, [r0]
 ; CHECK-NEXT:    bx lr
   %lhs = load <4 x i32>, <4 x i32>* %lhsp, align 16
   %rhs = load <4 x i32>, <4 x i32>* %rhsp, align 16
   %result = tail call <4 x i32> asm "vadd.i32 $0,$1,$2", "=t,t,t"(<4 x i32> %lhs, <4 x i32> %rhs)
   store <4 x i32> %result, <4 x i32>* %resultp, align 16
   ret void
 }
+
+define void @vector_f64_copy(<2 x double>* %from, <2 x double>* %to) {
+; CHECK-LABEL: vector_f64_copy:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vldrw.u32 q0, [r0]
+; CHECK-NEXT:    vstrw.32 q0, [r1]
+; CHECK-NEXT:    bx lr
+  %v = load <2 x double>, <2 x double>* %from, align 16
+  store <2 x double> %v, <2 x double>* %to, align 16
+  ret void
+}
+
+define arm_aapcs_vfpcc <16 x i8> @stack_slot_handling(<16 x i8> %a) #0 {
+; CHECK-LABEL: stack_slot_handling:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    push {r4, r6, r7, lr}
+; CHECK-NEXT:    add r7, sp, #8
+; CHECK-NEXT:    sub sp, #16
+; CHECK-NEXT:    mov r4, sp
+; CHECK-NEXT:    bfc r4, #0, #4
+; CHECK-NEXT:    mov sp, r4
+; CHECK-NEXT:    mov r0, sp
+; CHECK-NEXT:    vstrw.32 q0, [r0]
+; CHECK-NEXT:    vldrw.u32 q0, [r0]
+; CHECK-NEXT:    sub.w r4, r7, #8
+; CHECK-NEXT:    mov sp, r4
+; CHECK-NEXT:    pop {r4, r6, r7, pc}
+entry:
+  %a.addr = alloca <16 x i8>, align 8
+  store <16 x i8> %a, <16 x i8>* %a.addr, align 8
+  %0 = load <16 x i8>, <16 x i8>* %a.addr, align 8
+  ret <16 x i8> %0
+}
+
+attributes #0 = { noinline optnone }