[ARM] Enable VPUSH/VPOP aliases when either MVE or VFP is present

[miyuki]

Summary

Use the same predicates as VSTMDB/VLDMIA since VPUSH/VPOP alias to
these.

Patch by Momchil Velikov.

[dmgreen]

llvm/lib/Target/ARM/ARMInstrVFP.td

312 ↗

(On Diff #208662)

Are these needed too, for the optional suffix?

[miyuki]

Changed predicate for variants with suffixes

[miyuki]

Uploaded the correct patch

[dmgreen]

Other than a couple of test nits, LGTM.

llvm/test/MC/ARM/mve-fp-registers.s

52 ↗

(On Diff #208751)

I think this should be vpop.64

64 ↗

(On Diff #208751)

same here.

88 ↗

(On Diff #208751)

and this one vpush.32

(although none of these we seems to be very stringent on, the spec says "If present, it must be equal to the size in bits, 32 or 64, of the registers being transferred." )

llvm/trunk/lib/Target/ARM/ARMInstrFormats.td

 // for single-precision FP.
 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
   list<Predicate> Predicates = [HasNEON,UseNEONForFP];
 }
 
 // VFP/NEON Instruction aliases for type suffices.
 // Note: When EmitPriority == 1, the alias will be used for printing
 class VFPDataTypeInstAlias<string opc, string dt, string asm, dag Result, bit EmitPriority = 0> :
-  InstAlias<!strconcat(opc, dt, "\t", asm), Result, EmitPriority>, Requires<[HasVFP2]>;
+  InstAlias<!strconcat(opc, dt, "\t", asm), Result, EmitPriority>, Requires<[HasFPRegs]>;
 
 // Note: When EmitPriority == 1, the alias will be used for printing
 multiclass VFPDTAnyInstAlias<string opc, string asm, dag Result, bit EmitPriority = 0> {
   def : VFPDataTypeInstAlias<opc, ".8", asm, Result, EmitPriority>;
   def : VFPDataTypeInstAlias<opc, ".16", asm, Result, EmitPriority>;
   def : VFPDataTypeInstAlias<opc, ".32", asm, Result, EmitPriority>;
   def : VFPDataTypeInstAlias<opc, ".64", asm, Result, EmitPriority>;
 }

llvm/trunk/lib/Target/ARM/ARMInstrVFP.td

def VLSTM : AXSI4<(outs), (ins GPRnopc:$Rn, pred:$p), IndexModeNone,
     let Inst{21}    = 1;
     let Inst{20}    = 0;
     let Inst{15-12} = 0;
     let Inst{7-0}   = 0;
     let mayStore    = 1;
 }
 
 def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r), 0>,
-                Requires<[HasVFP2]>;
+                Requires<[HasFPRegs]>;
 def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r), 0>,
-                Requires<[HasVFP2]>;
+                Requires<[HasFPRegs]>;
 def : InstAlias<"vpop${p} $r",  (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r), 0>,
-                Requires<[HasVFP2]>;
+                Requires<[HasFPRegs]>;
 def : InstAlias<"vpop${p} $r",  (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r), 0>,
-                Requires<[HasVFP2]>;
+                Requires<[HasFPRegs]>;
 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
                          (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>;
 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
                          (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>;
 defm : VFPDTAnyInstAlias<"vpop${p}", "$r",
                          (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>;
 defm : VFPDTAnyInstAlias<"vpop${p}", "$r",
                          (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>;

llvm/trunk/test/MC/ARM/mve-fp-registers.s

 
 // Maximal v8.1M target: MVE with FP, and scalar FP with double-precision.
 // RUN: llvm-mc -triple=thumbv8.1m.main -show-encoding -mattr=+mve.fp < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FP16 --check-prefix=FP32 --check-prefix=FP64
 
 vldmia  r0, {d0}
 # FP32: vldmia  r0, {d0}               @ encoding: [0x90,0xec,0x02,0x0b]
 # NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
 
+vpop    {d0-d15}
+# FP32: vpop {{.*}}                     @ encoding: [0xbd,0xec,0x20,0x0b]
+# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
+
+vpop.64    {d0-d15}
+# FP32: vpop {{.*}}                     @ encoding: [0xbd,0xec,0x20,0x0b]
+# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
+
 vstmia  r0, {d0}
 # FP32: vstmia  r0, {d0}                @ encoding: [0x80,0xec,0x02,0x0b]
 # NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
 
+vpush    {d0-d15}
+# FP32: vpush {{.*}}                    @ encoding: [0x2d,0xed,0x20,0x0b]
+# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
+
+vpush.64    {d0-d15}
+# FP32: vpush {{.*}}                    @ encoding: [0x2d,0xed,0x20,0x0b]
+# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
+
 vldmia  r0, {s0}
 # FP32: vldmia  r0, {s0}                @ encoding: [0x90,0xec,0x01,0x0a]
 # NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
 
+vpop {s0-s31}
+# FP32: vpop {{.*}}                     @ encoding: [0xbd,0xec,0x20,0x0a]
+# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
+
+vpop.32 {s0-s31}
+# FP32: vpop {{.*}}                     @ encoding: [0xbd,0xec,0x20,0x0a]
+# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
+
 vstmia  r0, {s0}
 # FP32: vstmia  r0, {s0}                @ encoding: [0x80,0xec,0x01,0x0a]
 # NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
 
+vpush {s0-s31}
+# FP32: vpush {{.*}}                    @ encoding: [0x2d,0xed,0x20,0x0a]
+# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
+
+vpush.32 {s0-s31}
+# FP32: vpush {{.*}}                    @ encoding: [0x2d,0xed,0x20,0x0a]
+# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
+
 fldmdbx r0!, {d0}
 # FP32: fldmdbx r0!, {d0}               @ encoding: [0x30,0xed,0x03,0x0b]
 # NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
 
 fstmiax r0, {d0}
 # FP32: fstmiax r0, {d0}                @ encoding: [0x80,0xec,0x03,0x0b]
 # NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers