RISC-V psABI doesn't specify TLS relaxation. Though the code sequences
are not relaxed, dynamic relocations DTPMOD/DTPREL can be omitted if the
TLS model can be relaxed to Local-Exec.
Details
Diff Detail
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- rL LLVM
Event Timeline
ELF/Arch/RISCV.cpp | ||
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77 ↗ | (On Diff #204441) | I think it would be better to fold this into the if. |
ELF/Relocations.cpp | ||
224 ↗ | (On Diff #204441) | The RISC-V behaviour is identical to ARM if I remember correctly, so we should be reusing that code rather than reimplementing it again here. |
test/ELF/riscv-tls-ld.s | ||
1 ↗ | (On Diff #204441) | This file is the same as GD just with different check prefixes, no? RISC-V’s local dynamic is the same as global dynamic as far as relocations are concerned. |
ELF/Relocations.cpp | ||
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224 ↗ | (On Diff #204441) | R_ARM_TLS_GD32 <-> R_RISCV_TLS_GD_HI20 If this is what you mean :) However, there is a big difference: RISC-V doesn't support relaxation. So I have to make sure no R_RELAX_TLS_* code is called. Having the two variables is the least intrusive approach I can think of. (I complained the lack of linker relaxation turns out to make lld's generic TLS handling uglier. Here it is :)) |
test/ELF/riscv-tls-ld.s | ||
1 ↗ | (On Diff #204441) | No exactly the same. riscv-tls-gd.s checks preemptable symbols. This file checks .LANCHOR0. I do struggle to make the tests simpler while covering useful/possible scenarios. |
For the curious. I used the tests to compare the behaviors of lld and ld.bfd and found 2 problems that ld.bfd have :) https://sourceware.org/bugzilla/show_bug.cgi?id=24673 https://sourceware.org/bugzilla/show_bug.cgi?id=24676
I think it is fine to never have GD->IE, GD->LE, LD->LE, if we can get deprecate GD/LD (R_RISCV_TLS_GD_HI20) and migrate to TLSDESC (https://github.com/riscv/riscv-elf-psabi-doc/issues/94). However, IE->LE is still useful. It would be nice if psABI specified that.
ELF/Relocations.cpp | ||
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224 ↗ | (On Diff #204441) | Sorry, I think you probably meant we can reuse handleARMTlsRelocation() for RISC-V. I have compared it with handleTlsRelocation() and find it may be worth merging the two functions. Created D63333 for that idea. With that patch, the Relocations.cpp change in this patch will be trivial. - bool Relax = Config->EMachine != EM_ARM; + bool Relax = Config->EMachine != EM_ARM && Config->EMachine != EM_RISCV; |
One minor pedantic stylistic comment but otherwise this seems fine to me.
ELF/Arch/RISCV.cpp | ||
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342 ↗ | (On Diff #205808) | This order is inconsistent with the LO12_[IS] variants. Personally I'd leave HI20/LO12_* as the final case statement before the block, and put the TLS/TPREL statements between PCREL and the plain HI20/LO12_*. This also has the benefit of reducing churn in the diff by not modifying existing lines unnecessarily. |