[RISCV] Support RISC-V in getBitcodeMachineKind

[kito-cheng]

Summary

This patch add Triple::riscv64 and Triple::riscv32 to getBitcodeMachineKind for get right e_machine.

[ruiu]

Is this a part of a series of patches? If so, please merge this into another patch as this is perhaps too small. Doing that should allow you to write a test.

[Disasm]

@ruiu This patch is useful on its own: it allows linking bitcode files with lld. As an example, we use ThinLTO in Rust to perform simple assembly inlining. Without lld support it is impossible to use ThinLTO with RISC-V target.

[MaskRay]

For riscv64, you can write a test (placed under test/ELF/lto/) like this:

; REQUIRES: riscv

; RUN: llvm-as %s -o %t.o
; RUN: ld.lld %t.o -o %t
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
target triple = "riscv64-unknown-elf"

define void @f() {
  ret void
}

[kito-cheng]

@MaskRay Thanks, I'll add test case soon :)

[kito-cheng]

Add 2 test cases.

[MaskRay]

LGTM. I think lld's RISCV support is pretty complete now. R_RISCV_RELAX is not implemented, but that is used by linker relaxation which isn't really needed. Many programs should build after D63220, D63259 and this revision.

@ruiu What do you think?

[ruiu]

LGTM

lld/trunk/ELF/InputFiles.cpp

case Triple::mips64el:
     return EM_MIPS;
   case Triple::msp430:
     return EM_MSP430;
   case Triple::ppc:
     return EM_PPC;
   case Triple::ppc64:
   case Triple::ppc64le:
     return EM_PPC64;
+  case Triple::riscv32:
+  case Triple::riscv64:
+    return EM_RISCV;
   case Triple::x86:
     return T.isOSIAMCU() ? EM_IAMCU : EM_386;
   case Triple::x86_64:
     return EM_X86_64;
   default:
     error(Path + ": could not infer e_machine from bitcode target triple " +
           T.str());
     return EM_NONE;

lld/trunk/test/ELF/lto/riscv32.ll

+; REQUIRES: riscv
+
+; RUN: llvm-as %s -o %t.o
+; RUN: ld.lld %t.o -o %t
+target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
+target triple = "riscv32-unknown-elf"
+
+define void @f() {
+  ret void
+}

lld/trunk/test/ELF/lto/riscv64.ll

+; REQUIRES: riscv
+
+; RUN: llvm-as %s -o %t.o
+; RUN: ld.lld %t.o -o %t
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
+target triple = "riscv64-unknown-elf"
+
+define void @f() {
+  ret void
+}