[AArch64] check for INLINEASM_BR along w/ INLINEASM

[nickdesaulniers]

Summary

It looks like since INLINEASM_BR was created off of INLINEASM, a few
checks for INLINEASM needed to be updated to check for either case.

pr/41999

[peter.smith]

LGTM. Unlike with the ARM constant pools, I've no idea how to write a test case to trigger an error here.

[efriedma]

There are two ways you could write a testcase: you could construct a test with an out of range "tbz" (if BranchRelaxation fails to trigger when it should), or you could write a testcase with a jump table entry that doesn't fit (if AArch64CompressJumpTables compresses a jump table too much).

llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp

 
 /// GetInstSize - Return the number of bytes of code the specified
 /// instruction may be.  This returns the maximum number of bytes.
 unsigned AArch64InstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
   const MachineBasicBlock &MBB = *MI.getParent();
   const MachineFunction *MF = MBB.getParent();
   const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
 
-  if (MI.getOpcode() == AArch64::INLINEASM)
+  {
+    auto Op = MI.getOpcode();
+    if (Op == AArch64::INLINEASM || Op == AArch64::INLINEASM_BR)
       return getInlineAsmLength(MI.getOperand(0).getSymbolName(), *MAI);
+  }
 
   // FIXME: We currently only handle pseudoinstructions that don't get expanded
   //        before the assembly printer.
   unsigned NumBytes = 0;
   const MCInstrDesc &Desc = MI.getDesc();
   switch (Desc.getOpcode()) {
   default:
     // Anything not explicitly designated otherwise is a normal 4-byte insn.