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[SelectionDAG] define binops as a superset of commutative binops
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Authored by spatel on May 21 2019, 5:58 AM.

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Reviewers

RKSimon
craig.topper
lebedev.ri

Commits

rL361701: [SelectionDAG] define binops as a superset of commutative binops
rG3f0905e46f39: [SelectionDAG] define binops as a superset of commutative binops

Summary

The test diffs show improved vector narrowing for integer min/max opcodes because those were all absent from the list. I'm not sure if we can expose functional diffs for all of the moved/added opcodes though.

It seems like we are missing an AVX512 opportunity to use 256-bit ops in place of 512-ops on some tests/targets, but I think that can be a follow-up.

Diff Detail

Repository: rG LLVM Github Monorepo

Event Timeline

spatel created this revision.May 21 2019, 5:58 AM

Herald added a project: Restricted Project. · View Herald TranscriptMay 21 2019, 5:58 AM

Herald added a subscriber: mcrosier. · View Herald Transcript

Looks good to me.

This revision is now accepted and ready to land.May 21 2019, 6:10 AM

lebedev.ri added inline comments.May 21 2019, 6:23 AM

llvm/include/llvm/CodeGen/TargetLowering.h
2177	Actually, while this patch in itself looks good, this function looks a bit scary. FP ops are commutative, but not associative..

spatel marked an inline comment as done.May 21 2019, 6:38 AM

spatel added inline comments.

llvm/include/llvm/CodeGen/TargetLowering.h
2177	Yes, that is scary. From what I can tell, we only call this via DAGCombiner::reassociateOps() starting from add/mul/and/or/xor. Add an assert on the value type to prevent misuse?

lebedev.ri marked an inline comment as done.May 21 2019, 6:43 AM

lebedev.ri added inline comments.

llvm/include/llvm/CodeGen/TargetLowering.h
2177	Asserts are great.

spatel mentioned this in rL361268: [DAGCombiner] prevent unsafe reassociation of FP ops.May 21 2019, 7:45 AM

spatel mentioned this in rG78c3f58122f4: [DAGCombiner] prevent unsafe reassociation of FP ops.

spatel marked an inline comment as done.May 21 2019, 7:54 AM

spatel added inline comments.

llvm/include/llvm/CodeGen/TargetLowering.h
2177	Digging in a bit more - if we have loose FP math, we might want to try the mild FP reassociations within DAGCombiner::reassociateOpsCommutative(). And we're already checking the node flags there, so I added a real check for FMF (even though it should currently never trigger): rL361268 I'll let that bake a bit to see if there are any non-trunk complaints, then come back to this patch.

spatel mentioned this in rL361547: [DAGCombiner] make folds of binops safe for opcodes that produce >1 value.May 23 2019, 1:14 PM

spatel mentioned this in rG7d6c0bce503f: [DAGCombiner] make folds of binops safe for opcodes that produce >1 value.

Closed by commit rG3f0905e46f39: [SelectionDAG] define binops as a superset of commutative binops (authored by spatel). · Explain WhyMay 25 2019, 8:28 AM

This revision was automatically updated to reflect the committed changes.

sidorovd mentioned this in rG84228547e121: [DAGCombiner] prevent unsafe reassociation of FP ops.May 30 2019, 10:51 AM

Revision Contents

Path

Size

llvm/

include/

llvm/

CodeGen/

TargetLowering.h

59 lines

test/

CodeGen/

X86/

horizontal-reduce-smax.ll

44 lines

horizontal-reduce-smin.ll

44 lines

horizontal-reduce-umax.ll

44 lines

horizontal-reduce-umin.ll

44 lines

vector-reduce-smax-widen.ll

111 lines

vector-reduce-smax.ll

111 lines

vector-reduce-smin-widen.ll

111 lines

vector-reduce-smin.ll

111 lines

vector-reduce-umax-widen.ll

111 lines

vector-reduce-umax.ll

111 lines

vector-reduce-umin-widen.ll

111 lines

vector-reduce-umin.ll

111 lines

Diff 201402

llvm/include/llvm/CodeGen/TargetLowering.h

Show First 20 Lines • Show All 2,167 Lines • ▼ Show 20 Lines	public:
/// Return true if it's significantly cheaper to shift a vector by a uniform		/// Return true if it's significantly cheaper to shift a vector by a uniform
/// scalar than by an amount which will vary across each lane. On x86, for		/// scalar than by an amount which will vary across each lane. On x86, for
/// example, there is a "psllw" instruction for the former case, but no simple		/// example, there is a "psllw" instruction for the former case, but no simple
/// instruction for a general "a << b" operation on vectors.		/// instruction for a general "a << b" operation on vectors.
virtual bool isVectorShiftByScalarCheap(Type *Ty) const {		virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
return false;		return false;
}		}

/// Return true if the node is a math/logic binary operator.
virtual bool isBinOp(unsigned Opcode) const {
switch (Opcode) {
case ISD::ADD:
case ISD::SUB:
case ISD::MUL:
case ISD::AND:
case ISD::OR:
case ISD::XOR:
case ISD::SHL:
case ISD::SRL:
case ISD::SRA:
case ISD::SDIV:
case ISD::UDIV:
case ISD::SREM:
case ISD::UREM:
case ISD::FADD:
case ISD::FSUB:
case ISD::FMUL:
case ISD::FDIV:
case ISD::FREM:
case ISD::FMINNUM:
case ISD::FMAXNUM:
case ISD::FMINNUM_IEEE:
case ISD::FMAXNUM_IEEE:
case ISD::FMAXIMUM:
case ISD::FMINIMUM:
return true;
default:
return false;
}
}

/// Returns true if the opcode is a commutative binary operation.		/// Returns true if the opcode is a commutative binary operation.
virtual bool isCommutativeBinOp(unsigned Opcode) const {		virtual bool isCommutativeBinOp(unsigned Opcode) const {
		lebedev.riUnsubmitted Not Done Reply Inline Actions Actually, while this patch in itself looks good, this function looks a bit scary. FP ops are commutative, but not associative.. lebedev.ri: Actually, while this patch in itself looks good, this function looks a bit scary. FP ops are…
		spatelAuthorUnsubmitted Done Reply Inline Actions Yes, that is scary. From what I can tell, we only call this via DAGCombiner::reassociateOps() starting from add/mul/and/or/xor. Add an assert on the value type to prevent misuse? spatel: Yes, that is scary. From what I can tell, we only call this via DAGCombiner::reassociateOps()…
		lebedev.riUnsubmitted Done Reply Inline Actions Asserts are great. lebedev.ri: Asserts are great.
		spatelAuthorUnsubmitted Done Reply Inline Actions Digging in a bit more - if we have loose FP math, we might want to try the mild FP reassociations within DAGCombiner::reassociateOpsCommutative(). And we're already checking the node flags there, so I added a real check for FMF (even though it should currently never trigger): rL361268 I'll let that bake a bit to see if there are any non-trunk complaints, then come back to this patch. spatel: Digging in a bit more - if we have loose FP math, we might want to try the mild FP…
// FIXME: This should get its info from the td file.		// FIXME: This should get its info from the td file.
switch (Opcode) {		switch (Opcode) {
case ISD::ADD:		case ISD::ADD:
case ISD::SMIN:		case ISD::SMIN:
case ISD::SMAX:		case ISD::SMAX:
case ISD::UMIN:		case ISD::UMIN:
case ISD::UMAX:		case ISD::UMAX:
case ISD::MUL:		case ISD::MUL:
Show All 9 Lines	virtual bool isCommutativeBinOp(unsigned Opcode) const {
case ISD::SADDO:		case ISD::SADDO:
case ISD::UADDO:		case ISD::UADDO:
case ISD::ADDC:		case ISD::ADDC:
case ISD::ADDE:		case ISD::ADDE:
case ISD::SADDSAT:		case ISD::SADDSAT:
case ISD::UADDSAT:		case ISD::UADDSAT:
case ISD::FMINNUM:		case ISD::FMINNUM:
case ISD::FMAXNUM:		case ISD::FMAXNUM:
		case ISD::FMINNUM_IEEE:
		case ISD::FMAXNUM_IEEE:
case ISD::FMINIMUM:		case ISD::FMINIMUM:
case ISD::FMAXIMUM:		case ISD::FMAXIMUM:
return true;		return true;
default: return false;		default: return false;
}		}
}		}

		/// Return true if the node is a math/logic binary operator.
		virtual bool isBinOp(unsigned Opcode) const {
		// A commutative binop must be a binop.
		if (isCommutativeBinOp(Opcode))
		return true;
		// These are non-commutative binops.
		switch (Opcode) {
		case ISD::SUB:
		case ISD::SHL:
		case ISD::SRL:
		case ISD::SRA:
		case ISD::SDIV:
		case ISD::UDIV:
		case ISD::SREM:
		case ISD::UREM:
		case ISD::FSUB:
		case ISD::FDIV:
		case ISD::FREM:
		return true;
		default:
		return false;
		}
		}

/// Return true if it's free to truncate a value of type FromTy to type		/// Return true if it's free to truncate a value of type FromTy to type
/// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16		/// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
/// by referencing its sub-register AX.		/// by referencing its sub-register AX.
/// Targets must return false when FromTy <= ToTy.		/// Targets must return false when FromTy <= ToTy.
virtual bool isTruncateFree(Type FromTy, Type ToTy) const {		virtual bool isTruncateFree(Type FromTy, Type ToTy) const {
return false;		return false;
}		}

▲ Show 20 Lines • Show All 1,813 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/horizontal-reduce-smax.ll

	Show First 20 Lines • Show All 551 Lines • ▼ Show 20 Lines
	; X64-AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0			; X64-AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
	; X64-AVX2-NEXT: vmovq %xmm0, %rax			; X64-AVX2-NEXT: vmovq %xmm0, %rax
	; X64-AVX2-NEXT: vzeroupper			; X64-AVX2-NEXT: vzeroupper
	; X64-AVX2-NEXT: retq			; X64-AVX2-NEXT: retq
	;			;
	; X64-AVX512-LABEL: test_reduce_v4i64:			; X64-AVX512-LABEL: test_reduce_v4i64:
	; X64-AVX512: ## %bb.0:			; X64-AVX512: ## %bb.0:
	; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; X64-AVX512-NEXT: vpmaxsq %ymm1, %ymm0, %ymm0			; X64-AVX512-NEXT: vpmaxsq %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; X64-AVX512-NEXT: vpmaxsq %ymm1, %ymm0, %ymm0			; X64-AVX512-NEXT: vpmaxsq %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vmovq %xmm0, %rax			; X64-AVX512-NEXT: vmovq %xmm0, %rax
	; X64-AVX512-NEXT: vzeroupper			; X64-AVX512-NEXT: vzeroupper
	; X64-AVX512-NEXT: retq			; X64-AVX512-NEXT: retq
	%1 = shufflevector <4 x i64> %a0, <4 x i64> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>			%1 = shufflevector <4 x i64> %a0, <4 x i64> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
	%2 = icmp sgt <4 x i64> %a0, %1			%2 = icmp sgt <4 x i64> %a0, %1
	%3 = select <4 x i1> %2, <4 x i64> %a0, <4 x i64> %1			%3 = select <4 x i1> %2, <4 x i64> %a0, <4 x i64> %1
	%4 = shufflevector <4 x i64> %3, <4 x i64> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>			%4 = shufflevector <4 x i64> %3, <4 x i64> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
	%5 = icmp sgt <4 x i64> %3, %4			%5 = icmp sgt <4 x i64> %3, %4
	▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
	; X86-AVX1-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0			; X86-AVX1-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; X86-AVX1-NEXT: vmovd %xmm0, %eax			; X86-AVX1-NEXT: vmovd %xmm0, %eax
	; X86-AVX1-NEXT: vzeroupper			; X86-AVX1-NEXT: vzeroupper
	; X86-AVX1-NEXT: retl			; X86-AVX1-NEXT: retl
	;			;
	; X86-AVX2-LABEL: test_reduce_v8i32:			; X86-AVX2-LABEL: test_reduce_v8i32:
	; X86-AVX2: ## %bb.0:			; X86-AVX2: ## %bb.0:
	; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; X86-AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; X86-AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; X86-AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; X86-AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; X86-AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; X86-AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; X86-AVX2-NEXT: vmovd %xmm0, %eax			; X86-AVX2-NEXT: vmovd %xmm0, %eax
	; X86-AVX2-NEXT: vzeroupper			; X86-AVX2-NEXT: vzeroupper
	; X86-AVX2-NEXT: retl			; X86-AVX2-NEXT: retl
	;			;
	; X64-SSE2-LABEL: test_reduce_v8i32:			; X64-SSE2-LABEL: test_reduce_v8i32:
	; X64-SSE2: ## %bb.0:			; X64-SSE2: ## %bb.0:
	; X64-SSE2-NEXT: movdqa %xmm0, %xmm2			; X64-SSE2-NEXT: movdqa %xmm0, %xmm2
	; X64-SSE2-NEXT: pcmpgtd %xmm1, %xmm2			; X64-SSE2-NEXT: pcmpgtd %xmm1, %xmm2
	Show All 35 Lines
	; X64-AVX1-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0			; X64-AVX1-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; X64-AVX1-NEXT: vmovd %xmm0, %eax			; X64-AVX1-NEXT: vmovd %xmm0, %eax
	; X64-AVX1-NEXT: vzeroupper			; X64-AVX1-NEXT: vzeroupper
	; X64-AVX1-NEXT: retq			; X64-AVX1-NEXT: retq
	;			;
	; X64-AVX2-LABEL: test_reduce_v8i32:			; X64-AVX2-LABEL: test_reduce_v8i32:
	; X64-AVX2: ## %bb.0:			; X64-AVX2: ## %bb.0:
	; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; X64-AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; X64-AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; X64-AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; X64-AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; X64-AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; X64-AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; X64-AVX2-NEXT: vmovd %xmm0, %eax			; X64-AVX2-NEXT: vmovd %xmm0, %eax
	; X64-AVX2-NEXT: vzeroupper			; X64-AVX2-NEXT: vzeroupper
	; X64-AVX2-NEXT: retq			; X64-AVX2-NEXT: retq
	;			;
	; X64-AVX512-LABEL: test_reduce_v8i32:			; X64-AVX512-LABEL: test_reduce_v8i32:
	; X64-AVX512: ## %bb.0:			; X64-AVX512: ## %bb.0:
	; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; X64-AVX512-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; X64-AVX512-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; X64-AVX512-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; X64-AVX512-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; X64-AVX512-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; X64-AVX512-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vmovd %xmm0, %eax			; X64-AVX512-NEXT: vmovd %xmm0, %eax
	; X64-AVX512-NEXT: vzeroupper			; X64-AVX512-NEXT: vzeroupper
	; X64-AVX512-NEXT: retq			; X64-AVX512-NEXT: retq
	%1 = shufflevector <8 x i32> %a0, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>			%1 = shufflevector <8 x i32> %a0, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
	%2 = icmp sgt <8 x i32> %a0, %1			%2 = icmp sgt <8 x i32> %a0, %1
	%3 = select <8 x i1> %2, <8 x i32> %a0, <8 x i32> %1			%3 = select <8 x i1> %2, <8 x i32> %a0, <8 x i32> %1
	%4 = shufflevector <8 x i32> %3, <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>			%4 = shufflevector <8 x i32> %3, <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
	%5 = icmp sgt <8 x i32> %3, %4			%5 = icmp sgt <8 x i32> %3, %4
	▲ Show 20 Lines • Show All 566 Lines • ▼ Show 20 Lines
	; X64-AVX2-NEXT: vzeroupper			; X64-AVX2-NEXT: vzeroupper
	; X64-AVX2-NEXT: retq			; X64-AVX2-NEXT: retq
	;			;
	; X64-AVX512-LABEL: test_reduce_v8i64:			; X64-AVX512-LABEL: test_reduce_v8i64:
	; X64-AVX512: ## %bb.0:			; X64-AVX512: ## %bb.0:
	; X64-AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; X64-AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; X64-AVX512-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0			; X64-AVX512-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
	; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; X64-AVX512-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0			; X64-AVX512-NEXT: vpmaxsq %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; X64-AVX512-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0			; X64-AVX512-NEXT: vpmaxsq %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vmovq %xmm0, %rax			; X64-AVX512-NEXT: vmovq %xmm0, %rax
	; X64-AVX512-NEXT: vzeroupper			; X64-AVX512-NEXT: vzeroupper
	; X64-AVX512-NEXT: retq			; X64-AVX512-NEXT: retq
	%1 = shufflevector <8 x i64> %a0, <8 x i64> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>			%1 = shufflevector <8 x i64> %a0, <8 x i64> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
	%2 = icmp sgt <8 x i64> %a0, %1			%2 = icmp sgt <8 x i64> %a0, %1
	%3 = select <8 x i1> %2, <8 x i64> %a0, <8 x i64> %1			%3 = select <8 x i1> %2, <8 x i64> %a0, <8 x i64> %1
	%4 = shufflevector <8 x i64> %3, <8 x i64> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>			%4 = shufflevector <8 x i64> %3, <8 x i64> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
	%5 = icmp sgt <8 x i64> %3, %4			%5 = icmp sgt <8 x i64> %3, %4
	▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
	; X86-AVX1-NEXT: vmovd %xmm0, %eax			; X86-AVX1-NEXT: vmovd %xmm0, %eax
	; X86-AVX1-NEXT: vzeroupper			; X86-AVX1-NEXT: vzeroupper
	; X86-AVX1-NEXT: retl			; X86-AVX1-NEXT: retl
	;			;
	; X86-AVX2-LABEL: test_reduce_v16i32:			; X86-AVX2-LABEL: test_reduce_v16i32:
	; X86-AVX2: ## %bb.0:			; X86-AVX2: ## %bb.0:
	; X86-AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; X86-AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
	; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; X86-AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; X86-AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; X86-AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; X86-AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; X86-AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; X86-AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; X86-AVX2-NEXT: vmovd %xmm0, %eax			; X86-AVX2-NEXT: vmovd %xmm0, %eax
	; X86-AVX2-NEXT: vzeroupper			; X86-AVX2-NEXT: vzeroupper
	; X86-AVX2-NEXT: retl			; X86-AVX2-NEXT: retl
	;			;
	; X64-SSE2-LABEL: test_reduce_v16i32:			; X64-SSE2-LABEL: test_reduce_v16i32:
	; X64-SSE2: ## %bb.0:			; X64-SSE2: ## %bb.0:
	; X64-SSE2-NEXT: movdqa %xmm1, %xmm4			; X64-SSE2-NEXT: movdqa %xmm1, %xmm4
	; X64-SSE2-NEXT: pcmpgtd %xmm3, %xmm4			; X64-SSE2-NEXT: pcmpgtd %xmm3, %xmm4
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	; X64-AVX1-NEXT: vmovd %xmm0, %eax			; X64-AVX1-NEXT: vmovd %xmm0, %eax
	; X64-AVX1-NEXT: vzeroupper			; X64-AVX1-NEXT: vzeroupper
	; X64-AVX1-NEXT: retq			; X64-AVX1-NEXT: retq
	;			;
	; X64-AVX2-LABEL: test_reduce_v16i32:			; X64-AVX2-LABEL: test_reduce_v16i32:
	; X64-AVX2: ## %bb.0:			; X64-AVX2: ## %bb.0:
	; X64-AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; X64-AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
	; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; X64-AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; X64-AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; X64-AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; X64-AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; X64-AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; X64-AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; X64-AVX2-NEXT: vmovd %xmm0, %eax			; X64-AVX2-NEXT: vmovd %xmm0, %eax
	; X64-AVX2-NEXT: vzeroupper			; X64-AVX2-NEXT: vzeroupper
	; X64-AVX2-NEXT: retq			; X64-AVX2-NEXT: retq
	;			;
	; X64-AVX512-LABEL: test_reduce_v16i32:			; X64-AVX512-LABEL: test_reduce_v16i32:
	; X64-AVX512: ## %bb.0:			; X64-AVX512: ## %bb.0:
	; X64-AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; X64-AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; X64-AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0			; X64-AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0
	; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; X64-AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0			; X64-AVX512-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; X64-AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0			; X64-AVX512-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; X64-AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0			; X64-AVX512-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vmovd %xmm0, %eax			; X64-AVX512-NEXT: vmovd %xmm0, %eax
	; X64-AVX512-NEXT: vzeroupper			; X64-AVX512-NEXT: vzeroupper
	; X64-AVX512-NEXT: retq			; X64-AVX512-NEXT: retq
	%1 = shufflevector <16 x i32> %a0, <16 x i32> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>			%1 = shufflevector <16 x i32> %a0, <16 x i32> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
	%2 = icmp sgt <16 x i32> %a0, %1			%2 = icmp sgt <16 x i32> %a0, %1
	%3 = select <16 x i1> %2, <16 x i32> %a0, <16 x i32> %1			%3 = select <16 x i1> %2, <16 x i32> %a0, <16 x i32> %1
	%4 = shufflevector <16 x i32> %3, <16 x i32> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>			%4 = shufflevector <16 x i32> %3, <16 x i32> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
	%5 = icmp sgt <16 x i32> %3, %4			%5 = icmp sgt <16 x i32> %3, %4
	▲ Show 20 Lines • Show All 381 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/horizontal-reduce-smin.ll

	Show First 20 Lines • Show All 555 Lines • ▼ Show 20 Lines
	; X64-AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0			; X64-AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
	; X64-AVX2-NEXT: vmovq %xmm0, %rax			; X64-AVX2-NEXT: vmovq %xmm0, %rax
	; X64-AVX2-NEXT: vzeroupper			; X64-AVX2-NEXT: vzeroupper
	; X64-AVX2-NEXT: retq			; X64-AVX2-NEXT: retq
	;			;
	; X64-AVX512-LABEL: test_reduce_v4i64:			; X64-AVX512-LABEL: test_reduce_v4i64:
	; X64-AVX512: ## %bb.0:			; X64-AVX512: ## %bb.0:
	; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; X64-AVX512-NEXT: vpminsq %ymm1, %ymm0, %ymm0			; X64-AVX512-NEXT: vpminsq %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; X64-AVX512-NEXT: vpminsq %ymm1, %ymm0, %ymm0			; X64-AVX512-NEXT: vpminsq %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vmovq %xmm0, %rax			; X64-AVX512-NEXT: vmovq %xmm0, %rax
	; X64-AVX512-NEXT: vzeroupper			; X64-AVX512-NEXT: vzeroupper
	; X64-AVX512-NEXT: retq			; X64-AVX512-NEXT: retq
	%1 = shufflevector <4 x i64> %a0, <4 x i64> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>			%1 = shufflevector <4 x i64> %a0, <4 x i64> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
	%2 = icmp slt <4 x i64> %a0, %1			%2 = icmp slt <4 x i64> %a0, %1
	%3 = select <4 x i1> %2, <4 x i64> %a0, <4 x i64> %1			%3 = select <4 x i1> %2, <4 x i64> %a0, <4 x i64> %1
	%4 = shufflevector <4 x i64> %3, <4 x i64> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>			%4 = shufflevector <4 x i64> %3, <4 x i64> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
	%5 = icmp slt <4 x i64> %3, %4			%5 = icmp slt <4 x i64> %3, %4
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	; X86-AVX1-NEXT: vpminsd %xmm1, %xmm0, %xmm0			; X86-AVX1-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; X86-AVX1-NEXT: vmovd %xmm0, %eax			; X86-AVX1-NEXT: vmovd %xmm0, %eax
	; X86-AVX1-NEXT: vzeroupper			; X86-AVX1-NEXT: vzeroupper
	; X86-AVX1-NEXT: retl			; X86-AVX1-NEXT: retl
	;			;
	; X86-AVX2-LABEL: test_reduce_v8i32:			; X86-AVX2-LABEL: test_reduce_v8i32:
	; X86-AVX2: ## %bb.0:			; X86-AVX2: ## %bb.0:
	; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; X86-AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; X86-AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; X86-AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; X86-AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; X86-AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; X86-AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; X86-AVX2-NEXT: vmovd %xmm0, %eax			; X86-AVX2-NEXT: vmovd %xmm0, %eax
	; X86-AVX2-NEXT: vzeroupper			; X86-AVX2-NEXT: vzeroupper
	; X86-AVX2-NEXT: retl			; X86-AVX2-NEXT: retl
	;			;
	; X64-SSE2-LABEL: test_reduce_v8i32:			; X64-SSE2-LABEL: test_reduce_v8i32:
	; X64-SSE2: ## %bb.0:			; X64-SSE2: ## %bb.0:
	; X64-SSE2-NEXT: movdqa %xmm1, %xmm2			; X64-SSE2-NEXT: movdqa %xmm1, %xmm2
	; X64-SSE2-NEXT: pcmpgtd %xmm0, %xmm2			; X64-SSE2-NEXT: pcmpgtd %xmm0, %xmm2
	Show All 35 Lines
	; X64-AVX1-NEXT: vpminsd %xmm1, %xmm0, %xmm0			; X64-AVX1-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; X64-AVX1-NEXT: vmovd %xmm0, %eax			; X64-AVX1-NEXT: vmovd %xmm0, %eax
	; X64-AVX1-NEXT: vzeroupper			; X64-AVX1-NEXT: vzeroupper
	; X64-AVX1-NEXT: retq			; X64-AVX1-NEXT: retq
	;			;
	; X64-AVX2-LABEL: test_reduce_v8i32:			; X64-AVX2-LABEL: test_reduce_v8i32:
	; X64-AVX2: ## %bb.0:			; X64-AVX2: ## %bb.0:
	; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; X64-AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; X64-AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; X64-AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; X64-AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; X64-AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; X64-AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; X64-AVX2-NEXT: vmovd %xmm0, %eax			; X64-AVX2-NEXT: vmovd %xmm0, %eax
	; X64-AVX2-NEXT: vzeroupper			; X64-AVX2-NEXT: vzeroupper
	; X64-AVX2-NEXT: retq			; X64-AVX2-NEXT: retq
	;			;
	; X64-AVX512-LABEL: test_reduce_v8i32:			; X64-AVX512-LABEL: test_reduce_v8i32:
	; X64-AVX512: ## %bb.0:			; X64-AVX512: ## %bb.0:
	; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; X64-AVX512-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; X64-AVX512-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; X64-AVX512-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; X64-AVX512-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; X64-AVX512-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; X64-AVX512-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vmovd %xmm0, %eax			; X64-AVX512-NEXT: vmovd %xmm0, %eax
	; X64-AVX512-NEXT: vzeroupper			; X64-AVX512-NEXT: vzeroupper
	; X64-AVX512-NEXT: retq			; X64-AVX512-NEXT: retq
	%1 = shufflevector <8 x i32> %a0, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>			%1 = shufflevector <8 x i32> %a0, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
	%2 = icmp slt <8 x i32> %a0, %1			%2 = icmp slt <8 x i32> %a0, %1
	%3 = select <8 x i1> %2, <8 x i32> %a0, <8 x i32> %1			%3 = select <8 x i1> %2, <8 x i32> %a0, <8 x i32> %1
	%4 = shufflevector <8 x i32> %3, <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>			%4 = shufflevector <8 x i32> %3, <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
	%5 = icmp slt <8 x i32> %3, %4			%5 = icmp slt <8 x i32> %3, %4
	▲ Show 20 Lines • Show All 566 Lines • ▼ Show 20 Lines
	; X64-AVX2-NEXT: vzeroupper			; X64-AVX2-NEXT: vzeroupper
	; X64-AVX2-NEXT: retq			; X64-AVX2-NEXT: retq
	;			;
	; X64-AVX512-LABEL: test_reduce_v8i64:			; X64-AVX512-LABEL: test_reduce_v8i64:
	; X64-AVX512: ## %bb.0:			; X64-AVX512: ## %bb.0:
	; X64-AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; X64-AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; X64-AVX512-NEXT: vpminsq %zmm1, %zmm0, %zmm0			; X64-AVX512-NEXT: vpminsq %zmm1, %zmm0, %zmm0
	; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; X64-AVX512-NEXT: vpminsq %zmm1, %zmm0, %zmm0			; X64-AVX512-NEXT: vpminsq %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; X64-AVX512-NEXT: vpminsq %zmm1, %zmm0, %zmm0			; X64-AVX512-NEXT: vpminsq %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vmovq %xmm0, %rax			; X64-AVX512-NEXT: vmovq %xmm0, %rax
	; X64-AVX512-NEXT: vzeroupper			; X64-AVX512-NEXT: vzeroupper
	; X64-AVX512-NEXT: retq			; X64-AVX512-NEXT: retq
	%1 = shufflevector <8 x i64> %a0, <8 x i64> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>			%1 = shufflevector <8 x i64> %a0, <8 x i64> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
	%2 = icmp slt <8 x i64> %a0, %1			%2 = icmp slt <8 x i64> %a0, %1
	%3 = select <8 x i1> %2, <8 x i64> %a0, <8 x i64> %1			%3 = select <8 x i1> %2, <8 x i64> %a0, <8 x i64> %1
	%4 = shufflevector <8 x i64> %3, <8 x i64> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>			%4 = shufflevector <8 x i64> %3, <8 x i64> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
	%5 = icmp slt <8 x i64> %3, %4			%5 = icmp slt <8 x i64> %3, %4
	▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
	; X86-AVX1-NEXT: vmovd %xmm0, %eax			; X86-AVX1-NEXT: vmovd %xmm0, %eax
	; X86-AVX1-NEXT: vzeroupper			; X86-AVX1-NEXT: vzeroupper
	; X86-AVX1-NEXT: retl			; X86-AVX1-NEXT: retl
	;			;
	; X86-AVX2-LABEL: test_reduce_v16i32:			; X86-AVX2-LABEL: test_reduce_v16i32:
	; X86-AVX2: ## %bb.0:			; X86-AVX2: ## %bb.0:
	; X86-AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; X86-AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0
	; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; X86-AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; X86-AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; X86-AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; X86-AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; X86-AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; X86-AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; X86-AVX2-NEXT: vmovd %xmm0, %eax			; X86-AVX2-NEXT: vmovd %xmm0, %eax
	; X86-AVX2-NEXT: vzeroupper			; X86-AVX2-NEXT: vzeroupper
	; X86-AVX2-NEXT: retl			; X86-AVX2-NEXT: retl
	;			;
	; X64-SSE2-LABEL: test_reduce_v16i32:			; X64-SSE2-LABEL: test_reduce_v16i32:
	; X64-SSE2: ## %bb.0:			; X64-SSE2: ## %bb.0:
	; X64-SSE2-NEXT: movdqa %xmm2, %xmm4			; X64-SSE2-NEXT: movdqa %xmm2, %xmm4
	; X64-SSE2-NEXT: pcmpgtd %xmm0, %xmm4			; X64-SSE2-NEXT: pcmpgtd %xmm0, %xmm4
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	; X64-AVX1-NEXT: vmovd %xmm0, %eax			; X64-AVX1-NEXT: vmovd %xmm0, %eax
	; X64-AVX1-NEXT: vzeroupper			; X64-AVX1-NEXT: vzeroupper
	; X64-AVX1-NEXT: retq			; X64-AVX1-NEXT: retq
	;			;
	; X64-AVX2-LABEL: test_reduce_v16i32:			; X64-AVX2-LABEL: test_reduce_v16i32:
	; X64-AVX2: ## %bb.0:			; X64-AVX2: ## %bb.0:
	; X64-AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; X64-AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0
	; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; X64-AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; X64-AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; X64-AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; X64-AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; X64-AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; X64-AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; X64-AVX2-NEXT: vmovd %xmm0, %eax			; X64-AVX2-NEXT: vmovd %xmm0, %eax
	; X64-AVX2-NEXT: vzeroupper			; X64-AVX2-NEXT: vzeroupper
	; X64-AVX2-NEXT: retq			; X64-AVX2-NEXT: retq
	;			;
	; X64-AVX512-LABEL: test_reduce_v16i32:			; X64-AVX512-LABEL: test_reduce_v16i32:
	; X64-AVX512: ## %bb.0:			; X64-AVX512: ## %bb.0:
	; X64-AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; X64-AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; X64-AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0			; X64-AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0
	; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; X64-AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0			; X64-AVX512-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; X64-AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0			; X64-AVX512-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; X64-AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0			; X64-AVX512-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vmovd %xmm0, %eax			; X64-AVX512-NEXT: vmovd %xmm0, %eax
	; X64-AVX512-NEXT: vzeroupper			; X64-AVX512-NEXT: vzeroupper
	; X64-AVX512-NEXT: retq			; X64-AVX512-NEXT: retq
	%1 = shufflevector <16 x i32> %a0, <16 x i32> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>			%1 = shufflevector <16 x i32> %a0, <16 x i32> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
	%2 = icmp slt <16 x i32> %a0, %1			%2 = icmp slt <16 x i32> %a0, %1
	%3 = select <16 x i1> %2, <16 x i32> %a0, <16 x i32> %1			%3 = select <16 x i1> %2, <16 x i32> %a0, <16 x i32> %1
	%4 = shufflevector <16 x i32> %3, <16 x i32> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>			%4 = shufflevector <16 x i32> %3, <16 x i32> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
	%5 = icmp slt <16 x i32> %3, %4			%5 = icmp slt <16 x i32> %3, %4
	▲ Show 20 Lines • Show All 381 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/horizontal-reduce-umax.ll

	Show First 20 Lines • Show All 660 Lines • ▼ Show 20 Lines
	; X64-AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0			; X64-AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
	; X64-AVX2-NEXT: vmovq %xmm0, %rax			; X64-AVX2-NEXT: vmovq %xmm0, %rax
	; X64-AVX2-NEXT: vzeroupper			; X64-AVX2-NEXT: vzeroupper
	; X64-AVX2-NEXT: retq			; X64-AVX2-NEXT: retq
	;			;
	; X64-AVX512-LABEL: test_reduce_v4i64:			; X64-AVX512-LABEL: test_reduce_v4i64:
	; X64-AVX512: ## %bb.0:			; X64-AVX512: ## %bb.0:
	; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; X64-AVX512-NEXT: vpmaxuq %ymm1, %ymm0, %ymm0			; X64-AVX512-NEXT: vpmaxuq %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; X64-AVX512-NEXT: vpmaxuq %ymm1, %ymm0, %ymm0			; X64-AVX512-NEXT: vpmaxuq %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vmovq %xmm0, %rax			; X64-AVX512-NEXT: vmovq %xmm0, %rax
	; X64-AVX512-NEXT: vzeroupper			; X64-AVX512-NEXT: vzeroupper
	; X64-AVX512-NEXT: retq			; X64-AVX512-NEXT: retq
	%1 = shufflevector <4 x i64> %a0, <4 x i64> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>			%1 = shufflevector <4 x i64> %a0, <4 x i64> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
	%2 = icmp ugt <4 x i64> %a0, %1			%2 = icmp ugt <4 x i64> %a0, %1
	%3 = select <4 x i1> %2, <4 x i64> %a0, <4 x i64> %1			%3 = select <4 x i1> %2, <4 x i64> %a0, <4 x i64> %1
	%4 = shufflevector <4 x i64> %3, <4 x i64> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>			%4 = shufflevector <4 x i64> %3, <4 x i64> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
	%5 = icmp ugt <4 x i64> %3, %4			%5 = icmp ugt <4 x i64> %3, %4
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	; X86-AVX1-NEXT: vpmaxud %xmm1, %xmm0, %xmm0			; X86-AVX1-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; X86-AVX1-NEXT: vmovd %xmm0, %eax			; X86-AVX1-NEXT: vmovd %xmm0, %eax
	; X86-AVX1-NEXT: vzeroupper			; X86-AVX1-NEXT: vzeroupper
	; X86-AVX1-NEXT: retl			; X86-AVX1-NEXT: retl
	;			;
	; X86-AVX2-LABEL: test_reduce_v8i32:			; X86-AVX2-LABEL: test_reduce_v8i32:
	; X86-AVX2: ## %bb.0:			; X86-AVX2: ## %bb.0:
	; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; X86-AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; X86-AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; X86-AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; X86-AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; X86-AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; X86-AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; X86-AVX2-NEXT: vmovd %xmm0, %eax			; X86-AVX2-NEXT: vmovd %xmm0, %eax
	; X86-AVX2-NEXT: vzeroupper			; X86-AVX2-NEXT: vzeroupper
	; X86-AVX2-NEXT: retl			; X86-AVX2-NEXT: retl
	;			;
	; X64-SSE2-LABEL: test_reduce_v8i32:			; X64-SSE2-LABEL: test_reduce_v8i32:
	; X64-SSE2: ## %bb.0:			; X64-SSE2: ## %bb.0:
	; X64-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]			; X64-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
	; X64-SSE2-NEXT: movdqa %xmm1, %xmm3			; X64-SSE2-NEXT: movdqa %xmm1, %xmm3
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	; X64-AVX1-NEXT: vpmaxud %xmm1, %xmm0, %xmm0			; X64-AVX1-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; X64-AVX1-NEXT: vmovd %xmm0, %eax			; X64-AVX1-NEXT: vmovd %xmm0, %eax
	; X64-AVX1-NEXT: vzeroupper			; X64-AVX1-NEXT: vzeroupper
	; X64-AVX1-NEXT: retq			; X64-AVX1-NEXT: retq
	;			;
	; X64-AVX2-LABEL: test_reduce_v8i32:			; X64-AVX2-LABEL: test_reduce_v8i32:
	; X64-AVX2: ## %bb.0:			; X64-AVX2: ## %bb.0:
	; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; X64-AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; X64-AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; X64-AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; X64-AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; X64-AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; X64-AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; X64-AVX2-NEXT: vmovd %xmm0, %eax			; X64-AVX2-NEXT: vmovd %xmm0, %eax
	; X64-AVX2-NEXT: vzeroupper			; X64-AVX2-NEXT: vzeroupper
	; X64-AVX2-NEXT: retq			; X64-AVX2-NEXT: retq
	;			;
	; X64-AVX512-LABEL: test_reduce_v8i32:			; X64-AVX512-LABEL: test_reduce_v8i32:
	; X64-AVX512: ## %bb.0:			; X64-AVX512: ## %bb.0:
	; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; X64-AVX512-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; X64-AVX512-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; X64-AVX512-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; X64-AVX512-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; X64-AVX512-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; X64-AVX512-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vmovd %xmm0, %eax			; X64-AVX512-NEXT: vmovd %xmm0, %eax
	; X64-AVX512-NEXT: vzeroupper			; X64-AVX512-NEXT: vzeroupper
	; X64-AVX512-NEXT: retq			; X64-AVX512-NEXT: retq
	%1 = shufflevector <8 x i32> %a0, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>			%1 = shufflevector <8 x i32> %a0, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
	%2 = icmp ugt <8 x i32> %a0, %1			%2 = icmp ugt <8 x i32> %a0, %1
	%3 = select <8 x i1> %2, <8 x i32> %a0, <8 x i32> %1			%3 = select <8 x i1> %2, <8 x i32> %a0, <8 x i32> %1
	%4 = shufflevector <8 x i32> %3, <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>			%4 = shufflevector <8 x i32> %3, <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
	%5 = icmp ugt <8 x i32> %3, %4			%5 = icmp ugt <8 x i32> %3, %4
	▲ Show 20 Lines • Show All 617 Lines • ▼ Show 20 Lines
	; X64-AVX2-NEXT: vzeroupper			; X64-AVX2-NEXT: vzeroupper
	; X64-AVX2-NEXT: retq			; X64-AVX2-NEXT: retq
	;			;
	; X64-AVX512-LABEL: test_reduce_v8i64:			; X64-AVX512-LABEL: test_reduce_v8i64:
	; X64-AVX512: ## %bb.0:			; X64-AVX512: ## %bb.0:
	; X64-AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; X64-AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; X64-AVX512-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0			; X64-AVX512-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
	; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; X64-AVX512-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0			; X64-AVX512-NEXT: vpmaxuq %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; X64-AVX512-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0			; X64-AVX512-NEXT: vpmaxuq %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vmovq %xmm0, %rax			; X64-AVX512-NEXT: vmovq %xmm0, %rax
	; X64-AVX512-NEXT: vzeroupper			; X64-AVX512-NEXT: vzeroupper
	; X64-AVX512-NEXT: retq			; X64-AVX512-NEXT: retq
	%1 = shufflevector <8 x i64> %a0, <8 x i64> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>			%1 = shufflevector <8 x i64> %a0, <8 x i64> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
	%2 = icmp ugt <8 x i64> %a0, %1			%2 = icmp ugt <8 x i64> %a0, %1
	%3 = select <8 x i1> %2, <8 x i64> %a0, <8 x i64> %1			%3 = select <8 x i1> %2, <8 x i64> %a0, <8 x i64> %1
	%4 = shufflevector <8 x i64> %3, <8 x i64> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>			%4 = shufflevector <8 x i64> %3, <8 x i64> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
	%5 = icmp ugt <8 x i64> %3, %4			%5 = icmp ugt <8 x i64> %3, %4
	▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
	; X86-AVX1-NEXT: vmovd %xmm0, %eax			; X86-AVX1-NEXT: vmovd %xmm0, %eax
	; X86-AVX1-NEXT: vzeroupper			; X86-AVX1-NEXT: vzeroupper
	; X86-AVX1-NEXT: retl			; X86-AVX1-NEXT: retl
	;			;
	; X86-AVX2-LABEL: test_reduce_v16i32:			; X86-AVX2-LABEL: test_reduce_v16i32:
	; X86-AVX2: ## %bb.0:			; X86-AVX2: ## %bb.0:
	; X86-AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; X86-AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0
	; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; X86-AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; X86-AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; X86-AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; X86-AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; X86-AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; X86-AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; X86-AVX2-NEXT: vmovd %xmm0, %eax			; X86-AVX2-NEXT: vmovd %xmm0, %eax
	; X86-AVX2-NEXT: vzeroupper			; X86-AVX2-NEXT: vzeroupper
	; X86-AVX2-NEXT: retl			; X86-AVX2-NEXT: retl
	;			;
	; X64-SSE2-LABEL: test_reduce_v16i32:			; X64-SSE2-LABEL: test_reduce_v16i32:
	; X64-SSE2: ## %bb.0:			; X64-SSE2: ## %bb.0:
	; X64-SSE2-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,2147483648,2147483648,2147483648]			; X64-SSE2-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,2147483648,2147483648,2147483648]
	; X64-SSE2-NEXT: movdqa %xmm2, %xmm6			; X64-SSE2-NEXT: movdqa %xmm2, %xmm6
	▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
	; X64-AVX1-NEXT: vmovd %xmm0, %eax			; X64-AVX1-NEXT: vmovd %xmm0, %eax
	; X64-AVX1-NEXT: vzeroupper			; X64-AVX1-NEXT: vzeroupper
	; X64-AVX1-NEXT: retq			; X64-AVX1-NEXT: retq
	;			;
	; X64-AVX2-LABEL: test_reduce_v16i32:			; X64-AVX2-LABEL: test_reduce_v16i32:
	; X64-AVX2: ## %bb.0:			; X64-AVX2: ## %bb.0:
	; X64-AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; X64-AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0
	; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; X64-AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; X64-AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; X64-AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; X64-AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; X64-AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; X64-AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; X64-AVX2-NEXT: vmovd %xmm0, %eax			; X64-AVX2-NEXT: vmovd %xmm0, %eax
	; X64-AVX2-NEXT: vzeroupper			; X64-AVX2-NEXT: vzeroupper
	; X64-AVX2-NEXT: retq			; X64-AVX2-NEXT: retq
	;			;
	; X64-AVX512-LABEL: test_reduce_v16i32:			; X64-AVX512-LABEL: test_reduce_v16i32:
	; X64-AVX512: ## %bb.0:			; X64-AVX512: ## %bb.0:
	; X64-AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; X64-AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; X64-AVX512-NEXT: vpmaxud %zmm1, %zmm0, %zmm0			; X64-AVX512-NEXT: vpmaxud %zmm1, %zmm0, %zmm0
	; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; X64-AVX512-NEXT: vpmaxud %zmm1, %zmm0, %zmm0			; X64-AVX512-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; X64-AVX512-NEXT: vpmaxud %zmm1, %zmm0, %zmm0			; X64-AVX512-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; X64-AVX512-NEXT: vpmaxud %zmm1, %zmm0, %zmm0			; X64-AVX512-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vmovd %xmm0, %eax			; X64-AVX512-NEXT: vmovd %xmm0, %eax
	; X64-AVX512-NEXT: vzeroupper			; X64-AVX512-NEXT: vzeroupper
	; X64-AVX512-NEXT: retq			; X64-AVX512-NEXT: retq
	%1 = shufflevector <16 x i32> %a0, <16 x i32> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>			%1 = shufflevector <16 x i32> %a0, <16 x i32> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
	%2 = icmp ugt <16 x i32> %a0, %1			%2 = icmp ugt <16 x i32> %a0, %1
	%3 = select <16 x i1> %2, <16 x i32> %a0, <16 x i32> %1			%3 = select <16 x i1> %2, <16 x i32> %a0, <16 x i32> %1
	%4 = shufflevector <16 x i32> %3, <16 x i32> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>			%4 = shufflevector <16 x i32> %3, <16 x i32> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
	%5 = icmp ugt <16 x i32> %3, %4			%5 = icmp ugt <16 x i32> %3, %4
	▲ Show 20 Lines • Show All 365 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/horizontal-reduce-umin.ll

	Show First 20 Lines • Show All 600 Lines • ▼ Show 20 Lines
	; X64-AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0			; X64-AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
	; X64-AVX2-NEXT: vmovq %xmm0, %rax			; X64-AVX2-NEXT: vmovq %xmm0, %rax
	; X64-AVX2-NEXT: vzeroupper			; X64-AVX2-NEXT: vzeroupper
	; X64-AVX2-NEXT: retq			; X64-AVX2-NEXT: retq
	;			;
	; X64-AVX512-LABEL: test_reduce_v4i64:			; X64-AVX512-LABEL: test_reduce_v4i64:
	; X64-AVX512: ## %bb.0:			; X64-AVX512: ## %bb.0:
	; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; X64-AVX512-NEXT: vpminuq %ymm1, %ymm0, %ymm0			; X64-AVX512-NEXT: vpminuq %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; X64-AVX512-NEXT: vpminuq %ymm1, %ymm0, %ymm0			; X64-AVX512-NEXT: vpminuq %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vmovq %xmm0, %rax			; X64-AVX512-NEXT: vmovq %xmm0, %rax
	; X64-AVX512-NEXT: vzeroupper			; X64-AVX512-NEXT: vzeroupper
	; X64-AVX512-NEXT: retq			; X64-AVX512-NEXT: retq
	%1 = shufflevector <4 x i64> %a0, <4 x i64> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>			%1 = shufflevector <4 x i64> %a0, <4 x i64> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
	%2 = icmp ult <4 x i64> %a0, %1			%2 = icmp ult <4 x i64> %a0, %1
	%3 = select <4 x i1> %2, <4 x i64> %a0, <4 x i64> %1			%3 = select <4 x i1> %2, <4 x i64> %a0, <4 x i64> %1
	%4 = shufflevector <4 x i64> %3, <4 x i64> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>			%4 = shufflevector <4 x i64> %3, <4 x i64> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
	%5 = icmp ult <4 x i64> %3, %4			%5 = icmp ult <4 x i64> %3, %4
	▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
	; X86-AVX1-NEXT: vpminud %xmm1, %xmm0, %xmm0			; X86-AVX1-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; X86-AVX1-NEXT: vmovd %xmm0, %eax			; X86-AVX1-NEXT: vmovd %xmm0, %eax
	; X86-AVX1-NEXT: vzeroupper			; X86-AVX1-NEXT: vzeroupper
	; X86-AVX1-NEXT: retl			; X86-AVX1-NEXT: retl
	;			;
	; X86-AVX2-LABEL: test_reduce_v8i32:			; X86-AVX2-LABEL: test_reduce_v8i32:
	; X86-AVX2: ## %bb.0:			; X86-AVX2: ## %bb.0:
	; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; X86-AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; X86-AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; X86-AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; X86-AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; X86-AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; X86-AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; X86-AVX2-NEXT: vmovd %xmm0, %eax			; X86-AVX2-NEXT: vmovd %xmm0, %eax
	; X86-AVX2-NEXT: vzeroupper			; X86-AVX2-NEXT: vzeroupper
	; X86-AVX2-NEXT: retl			; X86-AVX2-NEXT: retl
	;			;
	; X64-SSE2-LABEL: test_reduce_v8i32:			; X64-SSE2-LABEL: test_reduce_v8i32:
	; X64-SSE2: ## %bb.0:			; X64-SSE2: ## %bb.0:
	; X64-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]			; X64-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
	; X64-SSE2-NEXT: movdqa %xmm0, %xmm3			; X64-SSE2-NEXT: movdqa %xmm0, %xmm3
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	; X64-AVX1-NEXT: vpminud %xmm1, %xmm0, %xmm0			; X64-AVX1-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; X64-AVX1-NEXT: vmovd %xmm0, %eax			; X64-AVX1-NEXT: vmovd %xmm0, %eax
	; X64-AVX1-NEXT: vzeroupper			; X64-AVX1-NEXT: vzeroupper
	; X64-AVX1-NEXT: retq			; X64-AVX1-NEXT: retq
	;			;
	; X64-AVX2-LABEL: test_reduce_v8i32:			; X64-AVX2-LABEL: test_reduce_v8i32:
	; X64-AVX2: ## %bb.0:			; X64-AVX2: ## %bb.0:
	; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; X64-AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; X64-AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; X64-AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; X64-AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; X64-AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; X64-AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; X64-AVX2-NEXT: vmovd %xmm0, %eax			; X64-AVX2-NEXT: vmovd %xmm0, %eax
	; X64-AVX2-NEXT: vzeroupper			; X64-AVX2-NEXT: vzeroupper
	; X64-AVX2-NEXT: retq			; X64-AVX2-NEXT: retq
	;			;
	; X64-AVX512-LABEL: test_reduce_v8i32:			; X64-AVX512-LABEL: test_reduce_v8i32:
	; X64-AVX512: ## %bb.0:			; X64-AVX512: ## %bb.0:
	; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; X64-AVX512-NEXT: vpminud %ymm1, %ymm0, %ymm0			; X64-AVX512-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; X64-AVX512-NEXT: vpminud %ymm1, %ymm0, %ymm0			; X64-AVX512-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; X64-AVX512-NEXT: vpminud %ymm1, %ymm0, %ymm0			; X64-AVX512-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vmovd %xmm0, %eax			; X64-AVX512-NEXT: vmovd %xmm0, %eax
	; X64-AVX512-NEXT: vzeroupper			; X64-AVX512-NEXT: vzeroupper
	; X64-AVX512-NEXT: retq			; X64-AVX512-NEXT: retq
	%1 = shufflevector <8 x i32> %a0, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>			%1 = shufflevector <8 x i32> %a0, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
	%2 = icmp ult <8 x i32> %a0, %1			%2 = icmp ult <8 x i32> %a0, %1
	%3 = select <8 x i1> %2, <8 x i32> %a0, <8 x i32> %1			%3 = select <8 x i1> %2, <8 x i32> %a0, <8 x i32> %1
	%4 = shufflevector <8 x i32> %3, <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>			%4 = shufflevector <8 x i32> %3, <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
	%5 = icmp ult <8 x i32> %3, %4			%5 = icmp ult <8 x i32> %3, %4
	▲ Show 20 Lines • Show All 581 Lines • ▼ Show 20 Lines
	; X64-AVX2-NEXT: vzeroupper			; X64-AVX2-NEXT: vzeroupper
	; X64-AVX2-NEXT: retq			; X64-AVX2-NEXT: retq
	;			;
	; X64-AVX512-LABEL: test_reduce_v8i64:			; X64-AVX512-LABEL: test_reduce_v8i64:
	; X64-AVX512: ## %bb.0:			; X64-AVX512: ## %bb.0:
	; X64-AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; X64-AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; X64-AVX512-NEXT: vpminuq %zmm1, %zmm0, %zmm0			; X64-AVX512-NEXT: vpminuq %zmm1, %zmm0, %zmm0
	; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; X64-AVX512-NEXT: vpminuq %zmm1, %zmm0, %zmm0			; X64-AVX512-NEXT: vpminuq %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; X64-AVX512-NEXT: vpminuq %zmm1, %zmm0, %zmm0			; X64-AVX512-NEXT: vpminuq %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vmovq %xmm0, %rax			; X64-AVX512-NEXT: vmovq %xmm0, %rax
	; X64-AVX512-NEXT: vzeroupper			; X64-AVX512-NEXT: vzeroupper
	; X64-AVX512-NEXT: retq			; X64-AVX512-NEXT: retq
	%1 = shufflevector <8 x i64> %a0, <8 x i64> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>			%1 = shufflevector <8 x i64> %a0, <8 x i64> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
	%2 = icmp ult <8 x i64> %a0, %1			%2 = icmp ult <8 x i64> %a0, %1
	%3 = select <8 x i1> %2, <8 x i64> %a0, <8 x i64> %1			%3 = select <8 x i1> %2, <8 x i64> %a0, <8 x i64> %1
	%4 = shufflevector <8 x i64> %3, <8 x i64> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>			%4 = shufflevector <8 x i64> %3, <8 x i64> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
	%5 = icmp ult <8 x i64> %3, %4			%5 = icmp ult <8 x i64> %3, %4
	▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
	; X86-AVX1-NEXT: vmovd %xmm0, %eax			; X86-AVX1-NEXT: vmovd %xmm0, %eax
	; X86-AVX1-NEXT: vzeroupper			; X86-AVX1-NEXT: vzeroupper
	; X86-AVX1-NEXT: retl			; X86-AVX1-NEXT: retl
	;			;
	; X86-AVX2-LABEL: test_reduce_v16i32:			; X86-AVX2-LABEL: test_reduce_v16i32:
	; X86-AVX2: ## %bb.0:			; X86-AVX2: ## %bb.0:
	; X86-AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; X86-AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0
	; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; X86-AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; X86-AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; X86-AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; X86-AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; X86-AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; X86-AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; X86-AVX2-NEXT: vmovd %xmm0, %eax			; X86-AVX2-NEXT: vmovd %xmm0, %eax
	; X86-AVX2-NEXT: vzeroupper			; X86-AVX2-NEXT: vzeroupper
	; X86-AVX2-NEXT: retl			; X86-AVX2-NEXT: retl
	;			;
	; X64-SSE2-LABEL: test_reduce_v16i32:			; X64-SSE2-LABEL: test_reduce_v16i32:
	; X64-SSE2: ## %bb.0:			; X64-SSE2: ## %bb.0:
	; X64-SSE2-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,2147483648,2147483648,2147483648]			; X64-SSE2-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,2147483648,2147483648,2147483648]
	; X64-SSE2-NEXT: movdqa %xmm1, %xmm5			; X64-SSE2-NEXT: movdqa %xmm1, %xmm5
	▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
	; X64-AVX1-NEXT: vmovd %xmm0, %eax			; X64-AVX1-NEXT: vmovd %xmm0, %eax
	; X64-AVX1-NEXT: vzeroupper			; X64-AVX1-NEXT: vzeroupper
	; X64-AVX1-NEXT: retq			; X64-AVX1-NEXT: retq
	;			;
	; X64-AVX2-LABEL: test_reduce_v16i32:			; X64-AVX2-LABEL: test_reduce_v16i32:
	; X64-AVX2: ## %bb.0:			; X64-AVX2: ## %bb.0:
	; X64-AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; X64-AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0
	; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; X64-AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; X64-AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; X64-AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; X64-AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; X64-AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; X64-AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; X64-AVX2-NEXT: vmovd %xmm0, %eax			; X64-AVX2-NEXT: vmovd %xmm0, %eax
	; X64-AVX2-NEXT: vzeroupper			; X64-AVX2-NEXT: vzeroupper
	; X64-AVX2-NEXT: retq			; X64-AVX2-NEXT: retq
	;			;
	; X64-AVX512-LABEL: test_reduce_v16i32:			; X64-AVX512-LABEL: test_reduce_v16i32:
	; X64-AVX512: ## %bb.0:			; X64-AVX512: ## %bb.0:
	; X64-AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; X64-AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; X64-AVX512-NEXT: vpminud %zmm1, %zmm0, %zmm0			; X64-AVX512-NEXT: vpminud %zmm1, %zmm0, %zmm0
	; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; X64-AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; X64-AVX512-NEXT: vpminud %zmm1, %zmm0, %zmm0			; X64-AVX512-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; X64-AVX512-NEXT: vpminud %zmm1, %zmm0, %zmm0			; X64-AVX512-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; X64-AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; X64-AVX512-NEXT: vpminud %zmm1, %zmm0, %zmm0			; X64-AVX512-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; X64-AVX512-NEXT: vmovd %xmm0, %eax			; X64-AVX512-NEXT: vmovd %xmm0, %eax
	; X64-AVX512-NEXT: vzeroupper			; X64-AVX512-NEXT: vzeroupper
	; X64-AVX512-NEXT: retq			; X64-AVX512-NEXT: retq
	%1 = shufflevector <16 x i32> %a0, <16 x i32> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>			%1 = shufflevector <16 x i32> %a0, <16 x i32> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
	%2 = icmp ult <16 x i32> %a0, %1			%2 = icmp ult <16 x i32> %a0, %1
	%3 = select <16 x i1> %2, <16 x i32> %a0, <16 x i32> %1			%3 = select <16 x i1> %2, <16 x i32> %a0, <16 x i32> %1
	%4 = shufflevector <16 x i32> %3, <16 x i32> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>			%4 = shufflevector <16 x i32> %3, <16 x i32> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
	%5 = icmp ult <16 x i32> %3, %4			%5 = icmp ult <16 x i32> %3, %4
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llvm/test/CodeGen/X86/vector-reduce-smax-widen.ll

	Show First 20 Lines • Show All 180 Lines • ▼ Show 20 Lines
	; AVX512BW-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
	; AVX512BW-NEXT: vmovq %xmm0, %rax			; AVX512BW-NEXT: vmovq %xmm0, %rax
	; AVX512BW-NEXT: vzeroupper			; AVX512BW-NEXT: vzeroupper
	; AVX512BW-NEXT: retq			; AVX512BW-NEXT: retq
	;			;
	; AVX512VL-LABEL: test_v4i64:			; AVX512VL-LABEL: test_v4i64:
	; AVX512VL: # %bb.0:			; AVX512VL: # %bb.0:
	; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512VL-NEXT: vpmaxsq %ymm1, %ymm0, %ymm0			; AVX512VL-NEXT: vpmaxsq %xmm1, %xmm0, %xmm0
	; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512VL-NEXT: vpmaxsq %ymm1, %ymm0, %ymm0			; AVX512VL-NEXT: vpmaxsq %xmm1, %xmm0, %xmm0
	; AVX512VL-NEXT: vmovq %xmm0, %rax			; AVX512VL-NEXT: vmovq %xmm0, %rax
	; AVX512VL-NEXT: vzeroupper			; AVX512VL-NEXT: vzeroupper
	; AVX512VL-NEXT: retq			; AVX512VL-NEXT: retq
	%1 = call i64 @llvm.experimental.vector.reduce.smax.i64.v4i64(<4 x i64> %a0)			%1 = call i64 @llvm.experimental.vector.reduce.smax.i64.v4i64(<4 x i64> %a0)
	ret i64 %1			ret i64 %1
	}			}

	define i64 @test_v8i64(<8 x i64> %a0) {			define i64 @test_v8i64(<8 x i64> %a0) {
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	; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0			; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
	; AVX2-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX2-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm2			; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm2
	; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0			; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
	; AVX2-NEXT: vmovq %xmm0, %rax			; AVX2-NEXT: vmovq %xmm0, %rax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v8i64:			; AVX512BW-LABEL: test_v8i64:
	; AVX512: # %bb.0:			; AVX512BW: # %bb.0:
	; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; AVX512BW-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; AVX512-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512BW-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512BW-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vmovq %xmm0, %rax			; AVX512BW-NEXT: vmovq %xmm0, %rax
	; AVX512-NEXT: vzeroupper			; AVX512BW-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512BW-NEXT: retq
				;
				; AVX512VL-LABEL: test_v8i64:
				; AVX512VL: # %bb.0:
				; AVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm1
				; AVX512VL-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
				; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1
				; AVX512VL-NEXT: vpmaxsq %xmm1, %xmm0, %xmm0
				; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
				; AVX512VL-NEXT: vpmaxsq %xmm1, %xmm0, %xmm0
				; AVX512VL-NEXT: vmovq %xmm0, %rax
				; AVX512VL-NEXT: vzeroupper
				; AVX512VL-NEXT: retq
	%1 = call i64 @llvm.experimental.vector.reduce.smax.i64.v8i64(<8 x i64> %a0)			%1 = call i64 @llvm.experimental.vector.reduce.smax.i64.v8i64(<8 x i64> %a0)
	ret i64 %1			ret i64 %1
	}			}

	define i64 @test_v16i64(<16 x i64> %a0) {			define i64 @test_v16i64(<16 x i64> %a0) {
	; SSE2-LABEL: test_v16i64:			; SSE2-LABEL: test_v16i64:
	; SSE2: # %bb.0:			; SSE2: # %bb.0:
	; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [2147483648,2147483648]			; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [2147483648,2147483648]
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	; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0			; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
	; AVX2-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX2-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm2			; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm2
	; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0			; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
	; AVX2-NEXT: vmovq %xmm0, %rax			; AVX2-NEXT: vmovq %xmm0, %rax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v16i64:			; AVX512BW-LABEL: test_v16i64:
	; AVX512: # %bb.0:			; AVX512BW: # %bb.0:
	; AVX512-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; AVX512BW-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; AVX512-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512BW-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512BW-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vmovq %xmm0, %rax			; AVX512BW-NEXT: vmovq %xmm0, %rax
	; AVX512-NEXT: vzeroupper			; AVX512BW-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512BW-NEXT: retq
				;
				; AVX512VL-LABEL: test_v16i64:
				; AVX512VL: # %bb.0:
				; AVX512VL-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
				; AVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm1
				; AVX512VL-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
				; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1
				; AVX512VL-NEXT: vpmaxsq %xmm1, %xmm0, %xmm0
				; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
				; AVX512VL-NEXT: vpmaxsq %xmm1, %xmm0, %xmm0
				; AVX512VL-NEXT: vmovq %xmm0, %rax
				; AVX512VL-NEXT: vzeroupper
				; AVX512VL-NEXT: retq
	%1 = call i64 @llvm.experimental.vector.reduce.smax.i64.v16i64(<16 x i64> %a0)			%1 = call i64 @llvm.experimental.vector.reduce.smax.i64.v16i64(<16 x i64> %a0)
	ret i64 %1			ret i64 %1
	}			}

	;			;
	; vXi32			; vXi32
	;			;

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	; AVX1-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0			; AVX1-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX1-NEXT: vmovd %xmm0, %eax			; AVX1-NEXT: vmovd %xmm0, %eax
	; AVX1-NEXT: vzeroupper			; AVX1-NEXT: vzeroupper
	; AVX1-NEXT: retq			; AVX1-NEXT: retq
	;			;
	; AVX2-LABEL: test_v8i32:			; AVX2-LABEL: test_v8i32:
	; AVX2: # %bb.0:			; AVX2: # %bb.0:
	; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vmovd %xmm0, %eax			; AVX2-NEXT: vmovd %xmm0, %eax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v8i32:			; AVX512-LABEL: test_v8i32:
	; AVX512: # %bb.0:			; AVX512: # %bb.0:
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; AVX512-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; AVX512-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX512-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; AVX512-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vmovd %xmm0, %eax			; AVX512-NEXT: vmovd %xmm0, %eax
	; AVX512-NEXT: vzeroupper			; AVX512-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512-NEXT: retq
	%1 = call i32 @llvm.experimental.vector.reduce.smax.i32.v8i32(<8 x i32> %a0)			%1 = call i32 @llvm.experimental.vector.reduce.smax.i32.v8i32(<8 x i32> %a0)
	ret i32 %1			ret i32 %1
	}			}

	define i32 @test_v16i32(<16 x i32> %a0) {			define i32 @test_v16i32(<16 x i32> %a0) {
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	; AVX1-NEXT: vmovd %xmm0, %eax			; AVX1-NEXT: vmovd %xmm0, %eax
	; AVX1-NEXT: vzeroupper			; AVX1-NEXT: vzeroupper
	; AVX1-NEXT: retq			; AVX1-NEXT: retq
	;			;
	; AVX2-LABEL: test_v16i32:			; AVX2-LABEL: test_v16i32:
	; AVX2: # %bb.0:			; AVX2: # %bb.0:
	; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
	; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vmovd %xmm0, %eax			; AVX2-NEXT: vmovd %xmm0, %eax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v16i32:			; AVX512-LABEL: test_v16i32:
	; AVX512: # %bb.0:			; AVX512: # %bb.0:
	; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vmovd %xmm0, %eax			; AVX512-NEXT: vmovd %xmm0, %eax
	; AVX512-NEXT: vzeroupper			; AVX512-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512-NEXT: retq
	%1 = call i32 @llvm.experimental.vector.reduce.smax.i32.v16i32(<16 x i32> %a0)			%1 = call i32 @llvm.experimental.vector.reduce.smax.i32.v16i32(<16 x i32> %a0)
	ret i32 %1			ret i32 %1
	}			}

	define i32 @test_v32i32(<32 x i32> %a0) {			define i32 @test_v32i32(<32 x i32> %a0) {
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	; AVX1-NEXT: retq			; AVX1-NEXT: retq
	;			;
	; AVX2-LABEL: test_v32i32:			; AVX2-LABEL: test_v32i32:
	; AVX2: # %bb.0:			; AVX2: # %bb.0:
	; AVX2-NEXT: vpmaxsd %ymm3, %ymm1, %ymm1			; AVX2-NEXT: vpmaxsd %ymm3, %ymm1, %ymm1
	; AVX2-NEXT: vpmaxsd %ymm2, %ymm0, %ymm0			; AVX2-NEXT: vpmaxsd %ymm2, %ymm0, %ymm0
	; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
	; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vmovd %xmm0, %eax			; AVX2-NEXT: vmovd %xmm0, %eax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v32i32:			; AVX512-LABEL: test_v32i32:
	; AVX512: # %bb.0:			; AVX512: # %bb.0:
	; AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vmovd %xmm0, %eax			; AVX512-NEXT: vmovd %xmm0, %eax
	; AVX512-NEXT: vzeroupper			; AVX512-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512-NEXT: retq
	%1 = call i32 @llvm.experimental.vector.reduce.smax.i32.v32i32(<32 x i32> %a0)			%1 = call i32 @llvm.experimental.vector.reduce.smax.i32.v32i32(<32 x i32> %a0)
	ret i32 %1			ret i32 %1
	}			}

	;			;
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llvm/test/CodeGen/X86/vector-reduce-smax.ll

	Show First 20 Lines • Show All 180 Lines • ▼ Show 20 Lines
	; AVX512BW-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
	; AVX512BW-NEXT: vmovq %xmm0, %rax			; AVX512BW-NEXT: vmovq %xmm0, %rax
	; AVX512BW-NEXT: vzeroupper			; AVX512BW-NEXT: vzeroupper
	; AVX512BW-NEXT: retq			; AVX512BW-NEXT: retq
	;			;
	; AVX512VL-LABEL: test_v4i64:			; AVX512VL-LABEL: test_v4i64:
	; AVX512VL: # %bb.0:			; AVX512VL: # %bb.0:
	; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512VL-NEXT: vpmaxsq %ymm1, %ymm0, %ymm0			; AVX512VL-NEXT: vpmaxsq %xmm1, %xmm0, %xmm0
	; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512VL-NEXT: vpmaxsq %ymm1, %ymm0, %ymm0			; AVX512VL-NEXT: vpmaxsq %xmm1, %xmm0, %xmm0
	; AVX512VL-NEXT: vmovq %xmm0, %rax			; AVX512VL-NEXT: vmovq %xmm0, %rax
	; AVX512VL-NEXT: vzeroupper			; AVX512VL-NEXT: vzeroupper
	; AVX512VL-NEXT: retq			; AVX512VL-NEXT: retq
	%1 = call i64 @llvm.experimental.vector.reduce.smax.i64.v4i64(<4 x i64> %a0)			%1 = call i64 @llvm.experimental.vector.reduce.smax.i64.v4i64(<4 x i64> %a0)
	ret i64 %1			ret i64 %1
	}			}

	define i64 @test_v8i64(<8 x i64> %a0) {			define i64 @test_v8i64(<8 x i64> %a0) {
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	; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0			; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
	; AVX2-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX2-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm2			; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm2
	; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0			; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
	; AVX2-NEXT: vmovq %xmm0, %rax			; AVX2-NEXT: vmovq %xmm0, %rax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v8i64:			; AVX512BW-LABEL: test_v8i64:
	; AVX512: # %bb.0:			; AVX512BW: # %bb.0:
	; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; AVX512BW-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; AVX512-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512BW-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512BW-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vmovq %xmm0, %rax			; AVX512BW-NEXT: vmovq %xmm0, %rax
	; AVX512-NEXT: vzeroupper			; AVX512BW-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512BW-NEXT: retq
				;
				; AVX512VL-LABEL: test_v8i64:
				; AVX512VL: # %bb.0:
				; AVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm1
				; AVX512VL-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
				; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1
				; AVX512VL-NEXT: vpmaxsq %xmm1, %xmm0, %xmm0
				; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
				; AVX512VL-NEXT: vpmaxsq %xmm1, %xmm0, %xmm0
				; AVX512VL-NEXT: vmovq %xmm0, %rax
				; AVX512VL-NEXT: vzeroupper
				; AVX512VL-NEXT: retq
	%1 = call i64 @llvm.experimental.vector.reduce.smax.i64.v8i64(<8 x i64> %a0)			%1 = call i64 @llvm.experimental.vector.reduce.smax.i64.v8i64(<8 x i64> %a0)
	ret i64 %1			ret i64 %1
	}			}

	define i64 @test_v16i64(<16 x i64> %a0) {			define i64 @test_v16i64(<16 x i64> %a0) {
	; SSE2-LABEL: test_v16i64:			; SSE2-LABEL: test_v16i64:
	; SSE2: # %bb.0:			; SSE2: # %bb.0:
	; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [2147483648,2147483648]			; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [2147483648,2147483648]
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	; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0			; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
	; AVX2-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX2-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm2			; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm2
	; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0			; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
	; AVX2-NEXT: vmovq %xmm0, %rax			; AVX2-NEXT: vmovq %xmm0, %rax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v16i64:			; AVX512BW-LABEL: test_v16i64:
	; AVX512: # %bb.0:			; AVX512BW: # %bb.0:
	; AVX512-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; AVX512BW-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; AVX512-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512BW-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512BW-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vmovq %xmm0, %rax			; AVX512BW-NEXT: vmovq %xmm0, %rax
	; AVX512-NEXT: vzeroupper			; AVX512BW-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512BW-NEXT: retq
				;
				; AVX512VL-LABEL: test_v16i64:
				; AVX512VL: # %bb.0:
				; AVX512VL-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
				; AVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm1
				; AVX512VL-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
				; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1
				; AVX512VL-NEXT: vpmaxsq %xmm1, %xmm0, %xmm0
				; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
				; AVX512VL-NEXT: vpmaxsq %xmm1, %xmm0, %xmm0
				; AVX512VL-NEXT: vmovq %xmm0, %rax
				; AVX512VL-NEXT: vzeroupper
				; AVX512VL-NEXT: retq
	%1 = call i64 @llvm.experimental.vector.reduce.smax.i64.v16i64(<16 x i64> %a0)			%1 = call i64 @llvm.experimental.vector.reduce.smax.i64.v16i64(<16 x i64> %a0)
	ret i64 %1			ret i64 %1
	}			}

	;			;
	; vXi32			; vXi32
	;			;

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	; AVX1-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0			; AVX1-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX1-NEXT: vmovd %xmm0, %eax			; AVX1-NEXT: vmovd %xmm0, %eax
	; AVX1-NEXT: vzeroupper			; AVX1-NEXT: vzeroupper
	; AVX1-NEXT: retq			; AVX1-NEXT: retq
	;			;
	; AVX2-LABEL: test_v8i32:			; AVX2-LABEL: test_v8i32:
	; AVX2: # %bb.0:			; AVX2: # %bb.0:
	; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vmovd %xmm0, %eax			; AVX2-NEXT: vmovd %xmm0, %eax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v8i32:			; AVX512-LABEL: test_v8i32:
	; AVX512: # %bb.0:			; AVX512: # %bb.0:
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; AVX512-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; AVX512-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX512-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; AVX512-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vmovd %xmm0, %eax			; AVX512-NEXT: vmovd %xmm0, %eax
	; AVX512-NEXT: vzeroupper			; AVX512-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512-NEXT: retq
	%1 = call i32 @llvm.experimental.vector.reduce.smax.i32.v8i32(<8 x i32> %a0)			%1 = call i32 @llvm.experimental.vector.reduce.smax.i32.v8i32(<8 x i32> %a0)
	ret i32 %1			ret i32 %1
	}			}

	define i32 @test_v16i32(<16 x i32> %a0) {			define i32 @test_v16i32(<16 x i32> %a0) {
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	; AVX1-NEXT: vmovd %xmm0, %eax			; AVX1-NEXT: vmovd %xmm0, %eax
	; AVX1-NEXT: vzeroupper			; AVX1-NEXT: vzeroupper
	; AVX1-NEXT: retq			; AVX1-NEXT: retq
	;			;
	; AVX2-LABEL: test_v16i32:			; AVX2-LABEL: test_v16i32:
	; AVX2: # %bb.0:			; AVX2: # %bb.0:
	; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
	; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vmovd %xmm0, %eax			; AVX2-NEXT: vmovd %xmm0, %eax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v16i32:			; AVX512-LABEL: test_v16i32:
	; AVX512: # %bb.0:			; AVX512: # %bb.0:
	; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vmovd %xmm0, %eax			; AVX512-NEXT: vmovd %xmm0, %eax
	; AVX512-NEXT: vzeroupper			; AVX512-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512-NEXT: retq
	%1 = call i32 @llvm.experimental.vector.reduce.smax.i32.v16i32(<16 x i32> %a0)			%1 = call i32 @llvm.experimental.vector.reduce.smax.i32.v16i32(<16 x i32> %a0)
	ret i32 %1			ret i32 %1
	}			}

	define i32 @test_v32i32(<32 x i32> %a0) {			define i32 @test_v32i32(<32 x i32> %a0) {
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	; AVX1-NEXT: retq			; AVX1-NEXT: retq
	;			;
	; AVX2-LABEL: test_v32i32:			; AVX2-LABEL: test_v32i32:
	; AVX2: # %bb.0:			; AVX2: # %bb.0:
	; AVX2-NEXT: vpmaxsd %ymm3, %ymm1, %ymm1			; AVX2-NEXT: vpmaxsd %ymm3, %ymm1, %ymm1
	; AVX2-NEXT: vpmaxsd %ymm2, %ymm0, %ymm0			; AVX2-NEXT: vpmaxsd %ymm2, %ymm0, %ymm0
	; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
	; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vmovd %xmm0, %eax			; AVX2-NEXT: vmovd %xmm0, %eax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v32i32:			; AVX512-LABEL: test_v32i32:
	; AVX512: # %bb.0:			; AVX512: # %bb.0:
	; AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vmovd %xmm0, %eax			; AVX512-NEXT: vmovd %xmm0, %eax
	; AVX512-NEXT: vzeroupper			; AVX512-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512-NEXT: retq
	%1 = call i32 @llvm.experimental.vector.reduce.smax.i32.v32i32(<32 x i32> %a0)			%1 = call i32 @llvm.experimental.vector.reduce.smax.i32.v32i32(<32 x i32> %a0)
	ret i32 %1			ret i32 %1
	}			}

	;			;
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llvm/test/CodeGen/X86/vector-reduce-smin-widen.ll

	Show First 20 Lines • Show All 179 Lines • ▼ Show 20 Lines
	; AVX512BW-NEXT: vpminsq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpminsq %zmm1, %zmm0, %zmm0
	; AVX512BW-NEXT: vmovq %xmm0, %rax			; AVX512BW-NEXT: vmovq %xmm0, %rax
	; AVX512BW-NEXT: vzeroupper			; AVX512BW-NEXT: vzeroupper
	; AVX512BW-NEXT: retq			; AVX512BW-NEXT: retq
	;			;
	; AVX512VL-LABEL: test_v4i64:			; AVX512VL-LABEL: test_v4i64:
	; AVX512VL: # %bb.0:			; AVX512VL: # %bb.0:
	; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512VL-NEXT: vpminsq %ymm1, %ymm0, %ymm0			; AVX512VL-NEXT: vpminsq %xmm1, %xmm0, %xmm0
	; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512VL-NEXT: vpminsq %ymm1, %ymm0, %ymm0			; AVX512VL-NEXT: vpminsq %xmm1, %xmm0, %xmm0
	; AVX512VL-NEXT: vmovq %xmm0, %rax			; AVX512VL-NEXT: vmovq %xmm0, %rax
	; AVX512VL-NEXT: vzeroupper			; AVX512VL-NEXT: vzeroupper
	; AVX512VL-NEXT: retq			; AVX512VL-NEXT: retq
	%1 = call i64 @llvm.experimental.vector.reduce.smin.i64.v4i64(<4 x i64> %a0)			%1 = call i64 @llvm.experimental.vector.reduce.smin.i64.v4i64(<4 x i64> %a0)
	ret i64 %1			ret i64 %1
	}			}

	define i64 @test_v8i64(<8 x i64> %a0) {			define i64 @test_v8i64(<8 x i64> %a0) {
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	; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0			; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
	; AVX2-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX2-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm2			; AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm2
	; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0			; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
	; AVX2-NEXT: vmovq %xmm0, %rax			; AVX2-NEXT: vmovq %xmm0, %rax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v8i64:			; AVX512BW-LABEL: test_v8i64:
	; AVX512: # %bb.0:			; AVX512BW: # %bb.0:
	; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; AVX512BW-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; AVX512-NEXT: vpminsq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpminsq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512BW-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpminsq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpminsq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512BW-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpminsq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpminsq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vmovq %xmm0, %rax			; AVX512BW-NEXT: vmovq %xmm0, %rax
	; AVX512-NEXT: vzeroupper			; AVX512BW-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512BW-NEXT: retq
				;
				; AVX512VL-LABEL: test_v8i64:
				; AVX512VL: # %bb.0:
				; AVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm1
				; AVX512VL-NEXT: vpminsq %zmm1, %zmm0, %zmm0
				; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1
				; AVX512VL-NEXT: vpminsq %xmm1, %xmm0, %xmm0
				; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
				; AVX512VL-NEXT: vpminsq %xmm1, %xmm0, %xmm0
				; AVX512VL-NEXT: vmovq %xmm0, %rax
				; AVX512VL-NEXT: vzeroupper
				; AVX512VL-NEXT: retq
	%1 = call i64 @llvm.experimental.vector.reduce.smin.i64.v8i64(<8 x i64> %a0)			%1 = call i64 @llvm.experimental.vector.reduce.smin.i64.v8i64(<8 x i64> %a0)
	ret i64 %1			ret i64 %1
	}			}

	define i64 @test_v16i64(<16 x i64> %a0) {			define i64 @test_v16i64(<16 x i64> %a0) {
	; SSE2-LABEL: test_v16i64:			; SSE2-LABEL: test_v16i64:
	; SSE2: # %bb.0:			; SSE2: # %bb.0:
	; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [2147483648,2147483648]			; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [2147483648,2147483648]
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	; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0			; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
	; AVX2-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX2-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm2			; AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm2
	; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0			; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
	; AVX2-NEXT: vmovq %xmm0, %rax			; AVX2-NEXT: vmovq %xmm0, %rax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v16i64:			; AVX512BW-LABEL: test_v16i64:
	; AVX512: # %bb.0:			; AVX512BW: # %bb.0:
	; AVX512-NEXT: vpminsq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpminsq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; AVX512BW-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; AVX512-NEXT: vpminsq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpminsq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512BW-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpminsq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpminsq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512BW-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpminsq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpminsq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vmovq %xmm0, %rax			; AVX512BW-NEXT: vmovq %xmm0, %rax
	; AVX512-NEXT: vzeroupper			; AVX512BW-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512BW-NEXT: retq
				;
				; AVX512VL-LABEL: test_v16i64:
				; AVX512VL: # %bb.0:
				; AVX512VL-NEXT: vpminsq %zmm1, %zmm0, %zmm0
				; AVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm1
				; AVX512VL-NEXT: vpminsq %zmm1, %zmm0, %zmm0
				; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1
				; AVX512VL-NEXT: vpminsq %xmm1, %xmm0, %xmm0
				; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
				; AVX512VL-NEXT: vpminsq %xmm1, %xmm0, %xmm0
				; AVX512VL-NEXT: vmovq %xmm0, %rax
				; AVX512VL-NEXT: vzeroupper
				; AVX512VL-NEXT: retq
	%1 = call i64 @llvm.experimental.vector.reduce.smin.i64.v16i64(<16 x i64> %a0)			%1 = call i64 @llvm.experimental.vector.reduce.smin.i64.v16i64(<16 x i64> %a0)
	ret i64 %1			ret i64 %1
	}			}

	;			;
	; vXi32			; vXi32
	;			;

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	; AVX1-NEXT: vpminsd %xmm1, %xmm0, %xmm0			; AVX1-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX1-NEXT: vmovd %xmm0, %eax			; AVX1-NEXT: vmovd %xmm0, %eax
	; AVX1-NEXT: vzeroupper			; AVX1-NEXT: vzeroupper
	; AVX1-NEXT: retq			; AVX1-NEXT: retq
	;			;
	; AVX2-LABEL: test_v8i32:			; AVX2-LABEL: test_v8i32:
	; AVX2: # %bb.0:			; AVX2: # %bb.0:
	; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vmovd %xmm0, %eax			; AVX2-NEXT: vmovd %xmm0, %eax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v8i32:			; AVX512-LABEL: test_v8i32:
	; AVX512: # %bb.0:			; AVX512: # %bb.0:
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; AVX512-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; AVX512-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX512-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; AVX512-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vmovd %xmm0, %eax			; AVX512-NEXT: vmovd %xmm0, %eax
	; AVX512-NEXT: vzeroupper			; AVX512-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512-NEXT: retq
	%1 = call i32 @llvm.experimental.vector.reduce.smin.i32.v8i32(<8 x i32> %a0)			%1 = call i32 @llvm.experimental.vector.reduce.smin.i32.v8i32(<8 x i32> %a0)
	ret i32 %1			ret i32 %1
	}			}

	define i32 @test_v16i32(<16 x i32> %a0) {			define i32 @test_v16i32(<16 x i32> %a0) {
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	; AVX1-NEXT: vmovd %xmm0, %eax			; AVX1-NEXT: vmovd %xmm0, %eax
	; AVX1-NEXT: vzeroupper			; AVX1-NEXT: vzeroupper
	; AVX1-NEXT: retq			; AVX1-NEXT: retq
	;			;
	; AVX2-LABEL: test_v16i32:			; AVX2-LABEL: test_v16i32:
	; AVX2: # %bb.0:			; AVX2: # %bb.0:
	; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0
	; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vmovd %xmm0, %eax			; AVX2-NEXT: vmovd %xmm0, %eax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v16i32:			; AVX512-LABEL: test_v16i32:
	; AVX512: # %bb.0:			; AVX512: # %bb.0:
	; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vmovd %xmm0, %eax			; AVX512-NEXT: vmovd %xmm0, %eax
	; AVX512-NEXT: vzeroupper			; AVX512-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512-NEXT: retq
	%1 = call i32 @llvm.experimental.vector.reduce.smin.i32.v16i32(<16 x i32> %a0)			%1 = call i32 @llvm.experimental.vector.reduce.smin.i32.v16i32(<16 x i32> %a0)
	ret i32 %1			ret i32 %1
	}			}

	define i32 @test_v32i32(<32 x i32> %a0) {			define i32 @test_v32i32(<32 x i32> %a0) {
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	; AVX1-NEXT: retq			; AVX1-NEXT: retq
	;			;
	; AVX2-LABEL: test_v32i32:			; AVX2-LABEL: test_v32i32:
	; AVX2: # %bb.0:			; AVX2: # %bb.0:
	; AVX2-NEXT: vpminsd %ymm3, %ymm1, %ymm1			; AVX2-NEXT: vpminsd %ymm3, %ymm1, %ymm1
	; AVX2-NEXT: vpminsd %ymm2, %ymm0, %ymm0			; AVX2-NEXT: vpminsd %ymm2, %ymm0, %ymm0
	; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0
	; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vmovd %xmm0, %eax			; AVX2-NEXT: vmovd %xmm0, %eax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v32i32:			; AVX512-LABEL: test_v32i32:
	; AVX512: # %bb.0:			; AVX512: # %bb.0:
	; AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vmovd %xmm0, %eax			; AVX512-NEXT: vmovd %xmm0, %eax
	; AVX512-NEXT: vzeroupper			; AVX512-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512-NEXT: retq
	%1 = call i32 @llvm.experimental.vector.reduce.smin.i32.v32i32(<32 x i32> %a0)			%1 = call i32 @llvm.experimental.vector.reduce.smin.i32.v32i32(<32 x i32> %a0)
	ret i32 %1			ret i32 %1
	}			}

	;			;
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llvm/test/CodeGen/X86/vector-reduce-smin.ll

	Show First 20 Lines • Show All 179 Lines • ▼ Show 20 Lines
	; AVX512BW-NEXT: vpminsq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpminsq %zmm1, %zmm0, %zmm0
	; AVX512BW-NEXT: vmovq %xmm0, %rax			; AVX512BW-NEXT: vmovq %xmm0, %rax
	; AVX512BW-NEXT: vzeroupper			; AVX512BW-NEXT: vzeroupper
	; AVX512BW-NEXT: retq			; AVX512BW-NEXT: retq
	;			;
	; AVX512VL-LABEL: test_v4i64:			; AVX512VL-LABEL: test_v4i64:
	; AVX512VL: # %bb.0:			; AVX512VL: # %bb.0:
	; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512VL-NEXT: vpminsq %ymm1, %ymm0, %ymm0			; AVX512VL-NEXT: vpminsq %xmm1, %xmm0, %xmm0
	; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512VL-NEXT: vpminsq %ymm1, %ymm0, %ymm0			; AVX512VL-NEXT: vpminsq %xmm1, %xmm0, %xmm0
	; AVX512VL-NEXT: vmovq %xmm0, %rax			; AVX512VL-NEXT: vmovq %xmm0, %rax
	; AVX512VL-NEXT: vzeroupper			; AVX512VL-NEXT: vzeroupper
	; AVX512VL-NEXT: retq			; AVX512VL-NEXT: retq
	%1 = call i64 @llvm.experimental.vector.reduce.smin.i64.v4i64(<4 x i64> %a0)			%1 = call i64 @llvm.experimental.vector.reduce.smin.i64.v4i64(<4 x i64> %a0)
	ret i64 %1			ret i64 %1
	}			}

	define i64 @test_v8i64(<8 x i64> %a0) {			define i64 @test_v8i64(<8 x i64> %a0) {
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	; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0			; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
	; AVX2-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX2-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm2			; AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm2
	; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0			; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
	; AVX2-NEXT: vmovq %xmm0, %rax			; AVX2-NEXT: vmovq %xmm0, %rax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v8i64:			; AVX512BW-LABEL: test_v8i64:
	; AVX512: # %bb.0:			; AVX512BW: # %bb.0:
	; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; AVX512BW-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; AVX512-NEXT: vpminsq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpminsq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512BW-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpminsq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpminsq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512BW-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpminsq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpminsq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vmovq %xmm0, %rax			; AVX512BW-NEXT: vmovq %xmm0, %rax
	; AVX512-NEXT: vzeroupper			; AVX512BW-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512BW-NEXT: retq
				;
				; AVX512VL-LABEL: test_v8i64:
				; AVX512VL: # %bb.0:
				; AVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm1
				; AVX512VL-NEXT: vpminsq %zmm1, %zmm0, %zmm0
				; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1
				; AVX512VL-NEXT: vpminsq %xmm1, %xmm0, %xmm0
				; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
				; AVX512VL-NEXT: vpminsq %xmm1, %xmm0, %xmm0
				; AVX512VL-NEXT: vmovq %xmm0, %rax
				; AVX512VL-NEXT: vzeroupper
				; AVX512VL-NEXT: retq
	%1 = call i64 @llvm.experimental.vector.reduce.smin.i64.v8i64(<8 x i64> %a0)			%1 = call i64 @llvm.experimental.vector.reduce.smin.i64.v8i64(<8 x i64> %a0)
	ret i64 %1			ret i64 %1
	}			}

	define i64 @test_v16i64(<16 x i64> %a0) {			define i64 @test_v16i64(<16 x i64> %a0) {
	; SSE2-LABEL: test_v16i64:			; SSE2-LABEL: test_v16i64:
	; SSE2: # %bb.0:			; SSE2: # %bb.0:
	; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [2147483648,2147483648]			; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [2147483648,2147483648]
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	; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0			; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
	; AVX2-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX2-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm2			; AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm2
	; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0			; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
	; AVX2-NEXT: vmovq %xmm0, %rax			; AVX2-NEXT: vmovq %xmm0, %rax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v16i64:			; AVX512BW-LABEL: test_v16i64:
	; AVX512: # %bb.0:			; AVX512BW: # %bb.0:
	; AVX512-NEXT: vpminsq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpminsq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; AVX512BW-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; AVX512-NEXT: vpminsq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpminsq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512BW-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpminsq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpminsq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512BW-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpminsq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpminsq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vmovq %xmm0, %rax			; AVX512BW-NEXT: vmovq %xmm0, %rax
	; AVX512-NEXT: vzeroupper			; AVX512BW-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512BW-NEXT: retq
				;
				; AVX512VL-LABEL: test_v16i64:
				; AVX512VL: # %bb.0:
				; AVX512VL-NEXT: vpminsq %zmm1, %zmm0, %zmm0
				; AVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm1
				; AVX512VL-NEXT: vpminsq %zmm1, %zmm0, %zmm0
				; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1
				; AVX512VL-NEXT: vpminsq %xmm1, %xmm0, %xmm0
				; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
				; AVX512VL-NEXT: vpminsq %xmm1, %xmm0, %xmm0
				; AVX512VL-NEXT: vmovq %xmm0, %rax
				; AVX512VL-NEXT: vzeroupper
				; AVX512VL-NEXT: retq
	%1 = call i64 @llvm.experimental.vector.reduce.smin.i64.v16i64(<16 x i64> %a0)			%1 = call i64 @llvm.experimental.vector.reduce.smin.i64.v16i64(<16 x i64> %a0)
	ret i64 %1			ret i64 %1
	}			}

	;			;
	; vXi32			; vXi32
	;			;

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	; AVX1-NEXT: vpminsd %xmm1, %xmm0, %xmm0			; AVX1-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX1-NEXT: vmovd %xmm0, %eax			; AVX1-NEXT: vmovd %xmm0, %eax
	; AVX1-NEXT: vzeroupper			; AVX1-NEXT: vzeroupper
	; AVX1-NEXT: retq			; AVX1-NEXT: retq
	;			;
	; AVX2-LABEL: test_v8i32:			; AVX2-LABEL: test_v8i32:
	; AVX2: # %bb.0:			; AVX2: # %bb.0:
	; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vmovd %xmm0, %eax			; AVX2-NEXT: vmovd %xmm0, %eax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v8i32:			; AVX512-LABEL: test_v8i32:
	; AVX512: # %bb.0:			; AVX512: # %bb.0:
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; AVX512-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; AVX512-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX512-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; AVX512-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vmovd %xmm0, %eax			; AVX512-NEXT: vmovd %xmm0, %eax
	; AVX512-NEXT: vzeroupper			; AVX512-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512-NEXT: retq
	%1 = call i32 @llvm.experimental.vector.reduce.smin.i32.v8i32(<8 x i32> %a0)			%1 = call i32 @llvm.experimental.vector.reduce.smin.i32.v8i32(<8 x i32> %a0)
	ret i32 %1			ret i32 %1
	}			}

	define i32 @test_v16i32(<16 x i32> %a0) {			define i32 @test_v16i32(<16 x i32> %a0) {
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	; AVX1-NEXT: vmovd %xmm0, %eax			; AVX1-NEXT: vmovd %xmm0, %eax
	; AVX1-NEXT: vzeroupper			; AVX1-NEXT: vzeroupper
	; AVX1-NEXT: retq			; AVX1-NEXT: retq
	;			;
	; AVX2-LABEL: test_v16i32:			; AVX2-LABEL: test_v16i32:
	; AVX2: # %bb.0:			; AVX2: # %bb.0:
	; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0
	; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vmovd %xmm0, %eax			; AVX2-NEXT: vmovd %xmm0, %eax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v16i32:			; AVX512-LABEL: test_v16i32:
	; AVX512: # %bb.0:			; AVX512: # %bb.0:
	; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vmovd %xmm0, %eax			; AVX512-NEXT: vmovd %xmm0, %eax
	; AVX512-NEXT: vzeroupper			; AVX512-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512-NEXT: retq
	%1 = call i32 @llvm.experimental.vector.reduce.smin.i32.v16i32(<16 x i32> %a0)			%1 = call i32 @llvm.experimental.vector.reduce.smin.i32.v16i32(<16 x i32> %a0)
	ret i32 %1			ret i32 %1
	}			}

	define i32 @test_v32i32(<32 x i32> %a0) {			define i32 @test_v32i32(<32 x i32> %a0) {
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	; AVX1-NEXT: retq			; AVX1-NEXT: retq
	;			;
	; AVX2-LABEL: test_v32i32:			; AVX2-LABEL: test_v32i32:
	; AVX2: # %bb.0:			; AVX2: # %bb.0:
	; AVX2-NEXT: vpminsd %ymm3, %ymm1, %ymm1			; AVX2-NEXT: vpminsd %ymm3, %ymm1, %ymm1
	; AVX2-NEXT: vpminsd %ymm2, %ymm0, %ymm0			; AVX2-NEXT: vpminsd %ymm2, %ymm0, %ymm0
	; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0
	; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vmovd %xmm0, %eax			; AVX2-NEXT: vmovd %xmm0, %eax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v32i32:			; AVX512-LABEL: test_v32i32:
	; AVX512: # %bb.0:			; AVX512: # %bb.0:
	; AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminsd %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vmovd %xmm0, %eax			; AVX512-NEXT: vmovd %xmm0, %eax
	; AVX512-NEXT: vzeroupper			; AVX512-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512-NEXT: retq
	%1 = call i32 @llvm.experimental.vector.reduce.smin.i32.v32i32(<32 x i32> %a0)			%1 = call i32 @llvm.experimental.vector.reduce.smin.i32.v32i32(<32 x i32> %a0)
	ret i32 %1			ret i32 %1
	}			}

	;			;
	▲ Show 20 Lines • Show All 1,238 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vector-reduce-umax-widen.ll

	Show First 20 Lines • Show All 193 Lines • ▼ Show 20 Lines
	; AVX512BW-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
	; AVX512BW-NEXT: vmovq %xmm0, %rax			; AVX512BW-NEXT: vmovq %xmm0, %rax
	; AVX512BW-NEXT: vzeroupper			; AVX512BW-NEXT: vzeroupper
	; AVX512BW-NEXT: retq			; AVX512BW-NEXT: retq
	;			;
	; AVX512VL-LABEL: test_v4i64:			; AVX512VL-LABEL: test_v4i64:
	; AVX512VL: # %bb.0:			; AVX512VL: # %bb.0:
	; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512VL-NEXT: vpmaxuq %ymm1, %ymm0, %ymm0			; AVX512VL-NEXT: vpmaxuq %xmm1, %xmm0, %xmm0
	; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512VL-NEXT: vpmaxuq %ymm1, %ymm0, %ymm0			; AVX512VL-NEXT: vpmaxuq %xmm1, %xmm0, %xmm0
	; AVX512VL-NEXT: vmovq %xmm0, %rax			; AVX512VL-NEXT: vmovq %xmm0, %rax
	; AVX512VL-NEXT: vzeroupper			; AVX512VL-NEXT: vzeroupper
	; AVX512VL-NEXT: retq			; AVX512VL-NEXT: retq
	%1 = call i64 @llvm.experimental.vector.reduce.umax.i64.v4i64(<4 x i64> %a0)			%1 = call i64 @llvm.experimental.vector.reduce.umax.i64.v4i64(<4 x i64> %a0)
	ret i64 %1			ret i64 %1
	}			}

	define i64 @test_v8i64(<8 x i64> %a0) {			define i64 @test_v8i64(<8 x i64> %a0) {
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	; AVX2-NEXT: vxorpd %ymm2, %ymm0, %ymm3			; AVX2-NEXT: vxorpd %ymm2, %ymm0, %ymm3
	; AVX2-NEXT: vxorpd %ymm2, %ymm1, %ymm2			; AVX2-NEXT: vxorpd %ymm2, %ymm1, %ymm2
	; AVX2-NEXT: vpcmpgtq %ymm2, %ymm3, %ymm2			; AVX2-NEXT: vpcmpgtq %ymm2, %ymm3, %ymm2
	; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0			; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
	; AVX2-NEXT: vmovq %xmm0, %rax			; AVX2-NEXT: vmovq %xmm0, %rax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v8i64:			; AVX512BW-LABEL: test_v8i64:
	; AVX512: # %bb.0:			; AVX512BW: # %bb.0:
	; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; AVX512BW-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; AVX512-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512BW-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512BW-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vmovq %xmm0, %rax			; AVX512BW-NEXT: vmovq %xmm0, %rax
	; AVX512-NEXT: vzeroupper			; AVX512BW-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512BW-NEXT: retq
				;
				; AVX512VL-LABEL: test_v8i64:
				; AVX512VL: # %bb.0:
				; AVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm1
				; AVX512VL-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
				; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1
				; AVX512VL-NEXT: vpmaxuq %xmm1, %xmm0, %xmm0
				; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
				; AVX512VL-NEXT: vpmaxuq %xmm1, %xmm0, %xmm0
				; AVX512VL-NEXT: vmovq %xmm0, %rax
				; AVX512VL-NEXT: vzeroupper
				; AVX512VL-NEXT: retq
	%1 = call i64 @llvm.experimental.vector.reduce.umax.i64.v8i64(<8 x i64> %a0)			%1 = call i64 @llvm.experimental.vector.reduce.umax.i64.v8i64(<8 x i64> %a0)
	ret i64 %1			ret i64 %1
	}			}

	define i64 @test_v16i64(<16 x i64> %a0) {			define i64 @test_v16i64(<16 x i64> %a0) {
	; SSE2-LABEL: test_v16i64:			; SSE2-LABEL: test_v16i64:
	; SSE2: # %bb.0:			; SSE2: # %bb.0:
	; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [9223372039002259456,9223372039002259456]			; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [9223372039002259456,9223372039002259456]
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	; AVX2-NEXT: vxorpd %ymm4, %ymm0, %ymm2			; AVX2-NEXT: vxorpd %ymm4, %ymm0, %ymm2
	; AVX2-NEXT: vxorpd %ymm4, %ymm1, %ymm3			; AVX2-NEXT: vxorpd %ymm4, %ymm1, %ymm3
	; AVX2-NEXT: vpcmpgtq %ymm3, %ymm2, %ymm2			; AVX2-NEXT: vpcmpgtq %ymm3, %ymm2, %ymm2
	; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0			; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
	; AVX2-NEXT: vmovq %xmm0, %rax			; AVX2-NEXT: vmovq %xmm0, %rax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v16i64:			; AVX512BW-LABEL: test_v16i64:
	; AVX512: # %bb.0:			; AVX512BW: # %bb.0:
	; AVX512-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; AVX512BW-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; AVX512-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512BW-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512BW-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vmovq %xmm0, %rax			; AVX512BW-NEXT: vmovq %xmm0, %rax
	; AVX512-NEXT: vzeroupper			; AVX512BW-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512BW-NEXT: retq
				;
				; AVX512VL-LABEL: test_v16i64:
				; AVX512VL: # %bb.0:
				; AVX512VL-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
				; AVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm1
				; AVX512VL-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
				; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1
				; AVX512VL-NEXT: vpmaxuq %xmm1, %xmm0, %xmm0
				; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
				; AVX512VL-NEXT: vpmaxuq %xmm1, %xmm0, %xmm0
				; AVX512VL-NEXT: vmovq %xmm0, %rax
				; AVX512VL-NEXT: vzeroupper
				; AVX512VL-NEXT: retq
	%1 = call i64 @llvm.experimental.vector.reduce.umax.i64.v16i64(<16 x i64> %a0)			%1 = call i64 @llvm.experimental.vector.reduce.umax.i64.v16i64(<16 x i64> %a0)
	ret i64 %1			ret i64 %1
	}			}

	;			;
	; vXi32			; vXi32
	;			;

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	; AVX1-NEXT: vpmaxud %xmm1, %xmm0, %xmm0			; AVX1-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX1-NEXT: vmovd %xmm0, %eax			; AVX1-NEXT: vmovd %xmm0, %eax
	; AVX1-NEXT: vzeroupper			; AVX1-NEXT: vzeroupper
	; AVX1-NEXT: retq			; AVX1-NEXT: retq
	;			;
	; AVX2-LABEL: test_v8i32:			; AVX2-LABEL: test_v8i32:
	; AVX2: # %bb.0:			; AVX2: # %bb.0:
	; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vmovd %xmm0, %eax			; AVX2-NEXT: vmovd %xmm0, %eax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v8i32:			; AVX512-LABEL: test_v8i32:
	; AVX512: # %bb.0:			; AVX512: # %bb.0:
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; AVX512-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; AVX512-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX512-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; AVX512-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vmovd %xmm0, %eax			; AVX512-NEXT: vmovd %xmm0, %eax
	; AVX512-NEXT: vzeroupper			; AVX512-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512-NEXT: retq
	%1 = call i32 @llvm.experimental.vector.reduce.umax.i32.v8i32(<8 x i32> %a0)			%1 = call i32 @llvm.experimental.vector.reduce.umax.i32.v8i32(<8 x i32> %a0)
	ret i32 %1			ret i32 %1
	}			}

	define i32 @test_v16i32(<16 x i32> %a0) {			define i32 @test_v16i32(<16 x i32> %a0) {
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	; AVX1-NEXT: vmovd %xmm0, %eax			; AVX1-NEXT: vmovd %xmm0, %eax
	; AVX1-NEXT: vzeroupper			; AVX1-NEXT: vzeroupper
	; AVX1-NEXT: retq			; AVX1-NEXT: retq
	;			;
	; AVX2-LABEL: test_v16i32:			; AVX2-LABEL: test_v16i32:
	; AVX2: # %bb.0:			; AVX2: # %bb.0:
	; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0
	; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vmovd %xmm0, %eax			; AVX2-NEXT: vmovd %xmm0, %eax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v16i32:			; AVX512-LABEL: test_v16i32:
	; AVX512: # %bb.0:			; AVX512: # %bb.0:
	; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; AVX512-NEXT: vpmaxud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxud %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpmaxud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpmaxud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX512-NEXT: vpmaxud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vmovd %xmm0, %eax			; AVX512-NEXT: vmovd %xmm0, %eax
	; AVX512-NEXT: vzeroupper			; AVX512-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512-NEXT: retq
	%1 = call i32 @llvm.experimental.vector.reduce.umax.i32.v16i32(<16 x i32> %a0)			%1 = call i32 @llvm.experimental.vector.reduce.umax.i32.v16i32(<16 x i32> %a0)
	ret i32 %1			ret i32 %1
	}			}

	define i32 @test_v32i32(<32 x i32> %a0) {			define i32 @test_v32i32(<32 x i32> %a0) {
	▲ Show 20 Lines • Show All 114 Lines • ▼ Show 20 Lines
	; AVX1-NEXT: retq			; AVX1-NEXT: retq
	;			;
	; AVX2-LABEL: test_v32i32:			; AVX2-LABEL: test_v32i32:
	; AVX2: # %bb.0:			; AVX2: # %bb.0:
	; AVX2-NEXT: vpmaxud %ymm3, %ymm1, %ymm1			; AVX2-NEXT: vpmaxud %ymm3, %ymm1, %ymm1
	; AVX2-NEXT: vpmaxud %ymm2, %ymm0, %ymm0			; AVX2-NEXT: vpmaxud %ymm2, %ymm0, %ymm0
	; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0
	; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vmovd %xmm0, %eax			; AVX2-NEXT: vmovd %xmm0, %eax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v32i32:			; AVX512-LABEL: test_v32i32:
	; AVX512: # %bb.0:			; AVX512: # %bb.0:
	; AVX512-NEXT: vpmaxud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxud %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; AVX512-NEXT: vpmaxud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxud %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpmaxud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpmaxud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX512-NEXT: vpmaxud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vmovd %xmm0, %eax			; AVX512-NEXT: vmovd %xmm0, %eax
	; AVX512-NEXT: vzeroupper			; AVX512-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512-NEXT: retq
	%1 = call i32 @llvm.experimental.vector.reduce.umax.i32.v32i32(<32 x i32> %a0)			%1 = call i32 @llvm.experimental.vector.reduce.umax.i32.v32i32(<32 x i32> %a0)
	ret i32 %1			ret i32 %1
	}			}

	;			;
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llvm/test/CodeGen/X86/vector-reduce-umax.ll

	Show First 20 Lines • Show All 193 Lines • ▼ Show 20 Lines
	; AVX512BW-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
	; AVX512BW-NEXT: vmovq %xmm0, %rax			; AVX512BW-NEXT: vmovq %xmm0, %rax
	; AVX512BW-NEXT: vzeroupper			; AVX512BW-NEXT: vzeroupper
	; AVX512BW-NEXT: retq			; AVX512BW-NEXT: retq
	;			;
	; AVX512VL-LABEL: test_v4i64:			; AVX512VL-LABEL: test_v4i64:
	; AVX512VL: # %bb.0:			; AVX512VL: # %bb.0:
	; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512VL-NEXT: vpmaxuq %ymm1, %ymm0, %ymm0			; AVX512VL-NEXT: vpmaxuq %xmm1, %xmm0, %xmm0
	; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512VL-NEXT: vpmaxuq %ymm1, %ymm0, %ymm0			; AVX512VL-NEXT: vpmaxuq %xmm1, %xmm0, %xmm0
	; AVX512VL-NEXT: vmovq %xmm0, %rax			; AVX512VL-NEXT: vmovq %xmm0, %rax
	; AVX512VL-NEXT: vzeroupper			; AVX512VL-NEXT: vzeroupper
	; AVX512VL-NEXT: retq			; AVX512VL-NEXT: retq
	%1 = call i64 @llvm.experimental.vector.reduce.umax.i64.v4i64(<4 x i64> %a0)			%1 = call i64 @llvm.experimental.vector.reduce.umax.i64.v4i64(<4 x i64> %a0)
	ret i64 %1			ret i64 %1
	}			}

	define i64 @test_v8i64(<8 x i64> %a0) {			define i64 @test_v8i64(<8 x i64> %a0) {
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	; AVX2-NEXT: vxorpd %ymm2, %ymm0, %ymm3			; AVX2-NEXT: vxorpd %ymm2, %ymm0, %ymm3
	; AVX2-NEXT: vxorpd %ymm2, %ymm1, %ymm2			; AVX2-NEXT: vxorpd %ymm2, %ymm1, %ymm2
	; AVX2-NEXT: vpcmpgtq %ymm2, %ymm3, %ymm2			; AVX2-NEXT: vpcmpgtq %ymm2, %ymm3, %ymm2
	; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0			; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
	; AVX2-NEXT: vmovq %xmm0, %rax			; AVX2-NEXT: vmovq %xmm0, %rax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v8i64:			; AVX512BW-LABEL: test_v8i64:
	; AVX512: # %bb.0:			; AVX512BW: # %bb.0:
	; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; AVX512BW-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; AVX512-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512BW-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512BW-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vmovq %xmm0, %rax			; AVX512BW-NEXT: vmovq %xmm0, %rax
	; AVX512-NEXT: vzeroupper			; AVX512BW-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512BW-NEXT: retq
				;
				; AVX512VL-LABEL: test_v8i64:
				; AVX512VL: # %bb.0:
				; AVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm1
				; AVX512VL-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
				; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1
				; AVX512VL-NEXT: vpmaxuq %xmm1, %xmm0, %xmm0
				; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
				; AVX512VL-NEXT: vpmaxuq %xmm1, %xmm0, %xmm0
				; AVX512VL-NEXT: vmovq %xmm0, %rax
				; AVX512VL-NEXT: vzeroupper
				; AVX512VL-NEXT: retq
	%1 = call i64 @llvm.experimental.vector.reduce.umax.i64.v8i64(<8 x i64> %a0)			%1 = call i64 @llvm.experimental.vector.reduce.umax.i64.v8i64(<8 x i64> %a0)
	ret i64 %1			ret i64 %1
	}			}

	define i64 @test_v16i64(<16 x i64> %a0) {			define i64 @test_v16i64(<16 x i64> %a0) {
	; SSE2-LABEL: test_v16i64:			; SSE2-LABEL: test_v16i64:
	; SSE2: # %bb.0:			; SSE2: # %bb.0:
	; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [9223372039002259456,9223372039002259456]			; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [9223372039002259456,9223372039002259456]
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	; AVX2-NEXT: vxorpd %ymm4, %ymm0, %ymm2			; AVX2-NEXT: vxorpd %ymm4, %ymm0, %ymm2
	; AVX2-NEXT: vxorpd %ymm4, %ymm1, %ymm3			; AVX2-NEXT: vxorpd %ymm4, %ymm1, %ymm3
	; AVX2-NEXT: vpcmpgtq %ymm3, %ymm2, %ymm2			; AVX2-NEXT: vpcmpgtq %ymm3, %ymm2, %ymm2
	; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0			; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
	; AVX2-NEXT: vmovq %xmm0, %rax			; AVX2-NEXT: vmovq %xmm0, %rax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v16i64:			; AVX512BW-LABEL: test_v16i64:
	; AVX512: # %bb.0:			; AVX512BW: # %bb.0:
	; AVX512-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; AVX512BW-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; AVX512-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512BW-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512BW-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vmovq %xmm0, %rax			; AVX512BW-NEXT: vmovq %xmm0, %rax
	; AVX512-NEXT: vzeroupper			; AVX512BW-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512BW-NEXT: retq
				;
				; AVX512VL-LABEL: test_v16i64:
				; AVX512VL: # %bb.0:
				; AVX512VL-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
				; AVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm1
				; AVX512VL-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
				; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1
				; AVX512VL-NEXT: vpmaxuq %xmm1, %xmm0, %xmm0
				; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
				; AVX512VL-NEXT: vpmaxuq %xmm1, %xmm0, %xmm0
				; AVX512VL-NEXT: vmovq %xmm0, %rax
				; AVX512VL-NEXT: vzeroupper
				; AVX512VL-NEXT: retq
	%1 = call i64 @llvm.experimental.vector.reduce.umax.i64.v16i64(<16 x i64> %a0)			%1 = call i64 @llvm.experimental.vector.reduce.umax.i64.v16i64(<16 x i64> %a0)
	ret i64 %1			ret i64 %1
	}			}

	;			;
	; vXi32			; vXi32
	;			;

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	; AVX1-NEXT: vpmaxud %xmm1, %xmm0, %xmm0			; AVX1-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX1-NEXT: vmovd %xmm0, %eax			; AVX1-NEXT: vmovd %xmm0, %eax
	; AVX1-NEXT: vzeroupper			; AVX1-NEXT: vzeroupper
	; AVX1-NEXT: retq			; AVX1-NEXT: retq
	;			;
	; AVX2-LABEL: test_v8i32:			; AVX2-LABEL: test_v8i32:
	; AVX2: # %bb.0:			; AVX2: # %bb.0:
	; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vmovd %xmm0, %eax			; AVX2-NEXT: vmovd %xmm0, %eax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v8i32:			; AVX512-LABEL: test_v8i32:
	; AVX512: # %bb.0:			; AVX512: # %bb.0:
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; AVX512-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; AVX512-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX512-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; AVX512-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vmovd %xmm0, %eax			; AVX512-NEXT: vmovd %xmm0, %eax
	; AVX512-NEXT: vzeroupper			; AVX512-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512-NEXT: retq
	%1 = call i32 @llvm.experimental.vector.reduce.umax.i32.v8i32(<8 x i32> %a0)			%1 = call i32 @llvm.experimental.vector.reduce.umax.i32.v8i32(<8 x i32> %a0)
	ret i32 %1			ret i32 %1
	}			}

	define i32 @test_v16i32(<16 x i32> %a0) {			define i32 @test_v16i32(<16 x i32> %a0) {
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	; AVX1-NEXT: vmovd %xmm0, %eax			; AVX1-NEXT: vmovd %xmm0, %eax
	; AVX1-NEXT: vzeroupper			; AVX1-NEXT: vzeroupper
	; AVX1-NEXT: retq			; AVX1-NEXT: retq
	;			;
	; AVX2-LABEL: test_v16i32:			; AVX2-LABEL: test_v16i32:
	; AVX2: # %bb.0:			; AVX2: # %bb.0:
	; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0
	; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vmovd %xmm0, %eax			; AVX2-NEXT: vmovd %xmm0, %eax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v16i32:			; AVX512-LABEL: test_v16i32:
	; AVX512: # %bb.0:			; AVX512: # %bb.0:
	; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; AVX512-NEXT: vpmaxud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxud %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpmaxud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpmaxud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX512-NEXT: vpmaxud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vmovd %xmm0, %eax			; AVX512-NEXT: vmovd %xmm0, %eax
	; AVX512-NEXT: vzeroupper			; AVX512-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512-NEXT: retq
	%1 = call i32 @llvm.experimental.vector.reduce.umax.i32.v16i32(<16 x i32> %a0)			%1 = call i32 @llvm.experimental.vector.reduce.umax.i32.v16i32(<16 x i32> %a0)
	ret i32 %1			ret i32 %1
	}			}

	define i32 @test_v32i32(<32 x i32> %a0) {			define i32 @test_v32i32(<32 x i32> %a0) {
	▲ Show 20 Lines • Show All 114 Lines • ▼ Show 20 Lines
	; AVX1-NEXT: retq			; AVX1-NEXT: retq
	;			;
	; AVX2-LABEL: test_v32i32:			; AVX2-LABEL: test_v32i32:
	; AVX2: # %bb.0:			; AVX2: # %bb.0:
	; AVX2-NEXT: vpmaxud %ymm3, %ymm1, %ymm1			; AVX2-NEXT: vpmaxud %ymm3, %ymm1, %ymm1
	; AVX2-NEXT: vpmaxud %ymm2, %ymm0, %ymm0			; AVX2-NEXT: vpmaxud %ymm2, %ymm0, %ymm0
	; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0
	; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vmovd %xmm0, %eax			; AVX2-NEXT: vmovd %xmm0, %eax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v32i32:			; AVX512-LABEL: test_v32i32:
	; AVX512: # %bb.0:			; AVX512: # %bb.0:
	; AVX512-NEXT: vpmaxud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxud %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; AVX512-NEXT: vpmaxud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxud %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpmaxud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpmaxud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX512-NEXT: vpmaxud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vmovd %xmm0, %eax			; AVX512-NEXT: vmovd %xmm0, %eax
	; AVX512-NEXT: vzeroupper			; AVX512-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512-NEXT: retq
	%1 = call i32 @llvm.experimental.vector.reduce.umax.i32.v32i32(<32 x i32> %a0)			%1 = call i32 @llvm.experimental.vector.reduce.umax.i32.v32i32(<32 x i32> %a0)
	ret i32 %1			ret i32 %1
	}			}

	;			;
	▲ Show 20 Lines • Show All 1,238 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vector-reduce-umin-widen.ll

	Show First 20 Lines • Show All 192 Lines • ▼ Show 20 Lines
	; AVX512BW-NEXT: vpminuq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpminuq %zmm1, %zmm0, %zmm0
	; AVX512BW-NEXT: vmovq %xmm0, %rax			; AVX512BW-NEXT: vmovq %xmm0, %rax
	; AVX512BW-NEXT: vzeroupper			; AVX512BW-NEXT: vzeroupper
	; AVX512BW-NEXT: retq			; AVX512BW-NEXT: retq
	;			;
	; AVX512VL-LABEL: test_v4i64:			; AVX512VL-LABEL: test_v4i64:
	; AVX512VL: # %bb.0:			; AVX512VL: # %bb.0:
	; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512VL-NEXT: vpminuq %ymm1, %ymm0, %ymm0			; AVX512VL-NEXT: vpminuq %xmm1, %xmm0, %xmm0
	; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512VL-NEXT: vpminuq %ymm1, %ymm0, %ymm0			; AVX512VL-NEXT: vpminuq %xmm1, %xmm0, %xmm0
	; AVX512VL-NEXT: vmovq %xmm0, %rax			; AVX512VL-NEXT: vmovq %xmm0, %rax
	; AVX512VL-NEXT: vzeroupper			; AVX512VL-NEXT: vzeroupper
	; AVX512VL-NEXT: retq			; AVX512VL-NEXT: retq
	%1 = call i64 @llvm.experimental.vector.reduce.umin.i64.v4i64(<4 x i64> %a0)			%1 = call i64 @llvm.experimental.vector.reduce.umin.i64.v4i64(<4 x i64> %a0)
	ret i64 %1			ret i64 %1
	}			}

	define i64 @test_v8i64(<8 x i64> %a0) {			define i64 @test_v8i64(<8 x i64> %a0) {
	▲ Show 20 Lines • Show All 163 Lines • ▼ Show 20 Lines
	; AVX2-NEXT: vxorpd %ymm2, %ymm0, %ymm3			; AVX2-NEXT: vxorpd %ymm2, %ymm0, %ymm3
	; AVX2-NEXT: vxorpd %ymm2, %ymm1, %ymm2			; AVX2-NEXT: vxorpd %ymm2, %ymm1, %ymm2
	; AVX2-NEXT: vpcmpgtq %ymm3, %ymm2, %ymm2			; AVX2-NEXT: vpcmpgtq %ymm3, %ymm2, %ymm2
	; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0			; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
	; AVX2-NEXT: vmovq %xmm0, %rax			; AVX2-NEXT: vmovq %xmm0, %rax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v8i64:			; AVX512BW-LABEL: test_v8i64:
	; AVX512: # %bb.0:			; AVX512BW: # %bb.0:
	; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; AVX512BW-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; AVX512-NEXT: vpminuq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpminuq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512BW-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpminuq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpminuq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512BW-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpminuq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpminuq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vmovq %xmm0, %rax			; AVX512BW-NEXT: vmovq %xmm0, %rax
	; AVX512-NEXT: vzeroupper			; AVX512BW-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512BW-NEXT: retq
				;
				; AVX512VL-LABEL: test_v8i64:
				; AVX512VL: # %bb.0:
				; AVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm1
				; AVX512VL-NEXT: vpminuq %zmm1, %zmm0, %zmm0
				; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1
				; AVX512VL-NEXT: vpminuq %xmm1, %xmm0, %xmm0
				; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
				; AVX512VL-NEXT: vpminuq %xmm1, %xmm0, %xmm0
				; AVX512VL-NEXT: vmovq %xmm0, %rax
				; AVX512VL-NEXT: vzeroupper
				; AVX512VL-NEXT: retq
	%1 = call i64 @llvm.experimental.vector.reduce.umin.i64.v8i64(<8 x i64> %a0)			%1 = call i64 @llvm.experimental.vector.reduce.umin.i64.v8i64(<8 x i64> %a0)
	ret i64 %1			ret i64 %1
	}			}

	define i64 @test_v16i64(<16 x i64> %a0) {			define i64 @test_v16i64(<16 x i64> %a0) {
	; SSE2-LABEL: test_v16i64:			; SSE2-LABEL: test_v16i64:
	; SSE2: # %bb.0:			; SSE2: # %bb.0:
	; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [9223372039002259456,9223372039002259456]			; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [9223372039002259456,9223372039002259456]
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	; AVX2-NEXT: vxorpd %ymm4, %ymm0, %ymm2			; AVX2-NEXT: vxorpd %ymm4, %ymm0, %ymm2
	; AVX2-NEXT: vxorpd %ymm4, %ymm1, %ymm3			; AVX2-NEXT: vxorpd %ymm4, %ymm1, %ymm3
	; AVX2-NEXT: vpcmpgtq %ymm2, %ymm3, %ymm2			; AVX2-NEXT: vpcmpgtq %ymm2, %ymm3, %ymm2
	; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0			; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
	; AVX2-NEXT: vmovq %xmm0, %rax			; AVX2-NEXT: vmovq %xmm0, %rax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v16i64:			; AVX512BW-LABEL: test_v16i64:
	; AVX512: # %bb.0:			; AVX512BW: # %bb.0:
	; AVX512-NEXT: vpminuq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpminuq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; AVX512BW-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; AVX512-NEXT: vpminuq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpminuq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512BW-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpminuq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpminuq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512BW-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpminuq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpminuq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vmovq %xmm0, %rax			; AVX512BW-NEXT: vmovq %xmm0, %rax
	; AVX512-NEXT: vzeroupper			; AVX512BW-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512BW-NEXT: retq
				;
				; AVX512VL-LABEL: test_v16i64:
				; AVX512VL: # %bb.0:
				; AVX512VL-NEXT: vpminuq %zmm1, %zmm0, %zmm0
				; AVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm1
				; AVX512VL-NEXT: vpminuq %zmm1, %zmm0, %zmm0
				; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1
				; AVX512VL-NEXT: vpminuq %xmm1, %xmm0, %xmm0
				; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
				; AVX512VL-NEXT: vpminuq %xmm1, %xmm0, %xmm0
				; AVX512VL-NEXT: vmovq %xmm0, %rax
				; AVX512VL-NEXT: vzeroupper
				; AVX512VL-NEXT: retq
	%1 = call i64 @llvm.experimental.vector.reduce.umin.i64.v16i64(<16 x i64> %a0)			%1 = call i64 @llvm.experimental.vector.reduce.umin.i64.v16i64(<16 x i64> %a0)
	ret i64 %1			ret i64 %1
	}			}

	;			;
	; vXi32			; vXi32
	;			;

	▲ Show 20 Lines • Show All 142 Lines • ▼ Show 20 Lines
	; AVX1-NEXT: vpminud %xmm1, %xmm0, %xmm0			; AVX1-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX1-NEXT: vmovd %xmm0, %eax			; AVX1-NEXT: vmovd %xmm0, %eax
	; AVX1-NEXT: vzeroupper			; AVX1-NEXT: vzeroupper
	; AVX1-NEXT: retq			; AVX1-NEXT: retq
	;			;
	; AVX2-LABEL: test_v8i32:			; AVX2-LABEL: test_v8i32:
	; AVX2: # %bb.0:			; AVX2: # %bb.0:
	; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vmovd %xmm0, %eax			; AVX2-NEXT: vmovd %xmm0, %eax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v8i32:			; AVX512-LABEL: test_v8i32:
	; AVX512: # %bb.0:			; AVX512: # %bb.0:
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpminud %ymm1, %ymm0, %ymm0			; AVX512-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpminud %ymm1, %ymm0, %ymm0			; AVX512-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX512-NEXT: vpminud %ymm1, %ymm0, %ymm0			; AVX512-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vmovd %xmm0, %eax			; AVX512-NEXT: vmovd %xmm0, %eax
	; AVX512-NEXT: vzeroupper			; AVX512-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512-NEXT: retq
	%1 = call i32 @llvm.experimental.vector.reduce.umin.i32.v8i32(<8 x i32> %a0)			%1 = call i32 @llvm.experimental.vector.reduce.umin.i32.v8i32(<8 x i32> %a0)
	ret i32 %1			ret i32 %1
	}			}

	define i32 @test_v16i32(<16 x i32> %a0) {			define i32 @test_v16i32(<16 x i32> %a0) {
	▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines
	; AVX1-NEXT: vmovd %xmm0, %eax			; AVX1-NEXT: vmovd %xmm0, %eax
	; AVX1-NEXT: vzeroupper			; AVX1-NEXT: vzeroupper
	; AVX1-NEXT: retq			; AVX1-NEXT: retq
	;			;
	; AVX2-LABEL: test_v16i32:			; AVX2-LABEL: test_v16i32:
	; AVX2: # %bb.0:			; AVX2: # %bb.0:
	; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0
	; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vmovd %xmm0, %eax			; AVX2-NEXT: vmovd %xmm0, %eax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v16i32:			; AVX512-LABEL: test_v16i32:
	; AVX512: # %bb.0:			; AVX512: # %bb.0:
	; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; AVX512-NEXT: vpminud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminud %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpminud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpminud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX512-NEXT: vpminud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vmovd %xmm0, %eax			; AVX512-NEXT: vmovd %xmm0, %eax
	; AVX512-NEXT: vzeroupper			; AVX512-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512-NEXT: retq
	%1 = call i32 @llvm.experimental.vector.reduce.umin.i32.v16i32(<16 x i32> %a0)			%1 = call i32 @llvm.experimental.vector.reduce.umin.i32.v16i32(<16 x i32> %a0)
	ret i32 %1			ret i32 %1
	}			}

	define i32 @test_v32i32(<32 x i32> %a0) {			define i32 @test_v32i32(<32 x i32> %a0) {
	▲ Show 20 Lines • Show All 114 Lines • ▼ Show 20 Lines
	; AVX1-NEXT: retq			; AVX1-NEXT: retq
	;			;
	; AVX2-LABEL: test_v32i32:			; AVX2-LABEL: test_v32i32:
	; AVX2: # %bb.0:			; AVX2: # %bb.0:
	; AVX2-NEXT: vpminud %ymm3, %ymm1, %ymm1			; AVX2-NEXT: vpminud %ymm3, %ymm1, %ymm1
	; AVX2-NEXT: vpminud %ymm2, %ymm0, %ymm0			; AVX2-NEXT: vpminud %ymm2, %ymm0, %ymm0
	; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0
	; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vmovd %xmm0, %eax			; AVX2-NEXT: vmovd %xmm0, %eax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v32i32:			; AVX512-LABEL: test_v32i32:
	; AVX512: # %bb.0:			; AVX512: # %bb.0:
	; AVX512-NEXT: vpminud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminud %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; AVX512-NEXT: vpminud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminud %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpminud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpminud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX512-NEXT: vpminud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vmovd %xmm0, %eax			; AVX512-NEXT: vmovd %xmm0, %eax
	; AVX512-NEXT: vzeroupper			; AVX512-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512-NEXT: retq
	%1 = call i32 @llvm.experimental.vector.reduce.umin.i32.v32i32(<32 x i32> %a0)			%1 = call i32 @llvm.experimental.vector.reduce.umin.i32.v32i32(<32 x i32> %a0)
	ret i32 %1			ret i32 %1
	}			}

	;			;
	▲ Show 20 Lines • Show All 853 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vector-reduce-umin.ll

	Show First 20 Lines • Show All 192 Lines • ▼ Show 20 Lines
	; AVX512BW-NEXT: vpminuq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpminuq %zmm1, %zmm0, %zmm0
	; AVX512BW-NEXT: vmovq %xmm0, %rax			; AVX512BW-NEXT: vmovq %xmm0, %rax
	; AVX512BW-NEXT: vzeroupper			; AVX512BW-NEXT: vzeroupper
	; AVX512BW-NEXT: retq			; AVX512BW-NEXT: retq
	;			;
	; AVX512VL-LABEL: test_v4i64:			; AVX512VL-LABEL: test_v4i64:
	; AVX512VL: # %bb.0:			; AVX512VL: # %bb.0:
	; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512VL-NEXT: vpminuq %ymm1, %ymm0, %ymm0			; AVX512VL-NEXT: vpminuq %xmm1, %xmm0, %xmm0
	; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512VL-NEXT: vpminuq %ymm1, %ymm0, %ymm0			; AVX512VL-NEXT: vpminuq %xmm1, %xmm0, %xmm0
	; AVX512VL-NEXT: vmovq %xmm0, %rax			; AVX512VL-NEXT: vmovq %xmm0, %rax
	; AVX512VL-NEXT: vzeroupper			; AVX512VL-NEXT: vzeroupper
	; AVX512VL-NEXT: retq			; AVX512VL-NEXT: retq
	%1 = call i64 @llvm.experimental.vector.reduce.umin.i64.v4i64(<4 x i64> %a0)			%1 = call i64 @llvm.experimental.vector.reduce.umin.i64.v4i64(<4 x i64> %a0)
	ret i64 %1			ret i64 %1
	}			}

	define i64 @test_v8i64(<8 x i64> %a0) {			define i64 @test_v8i64(<8 x i64> %a0) {
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	; AVX2-NEXT: vxorpd %ymm2, %ymm0, %ymm3			; AVX2-NEXT: vxorpd %ymm2, %ymm0, %ymm3
	; AVX2-NEXT: vxorpd %ymm2, %ymm1, %ymm2			; AVX2-NEXT: vxorpd %ymm2, %ymm1, %ymm2
	; AVX2-NEXT: vpcmpgtq %ymm3, %ymm2, %ymm2			; AVX2-NEXT: vpcmpgtq %ymm3, %ymm2, %ymm2
	; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0			; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
	; AVX2-NEXT: vmovq %xmm0, %rax			; AVX2-NEXT: vmovq %xmm0, %rax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v8i64:			; AVX512BW-LABEL: test_v8i64:
	; AVX512: # %bb.0:			; AVX512BW: # %bb.0:
	; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; AVX512BW-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; AVX512-NEXT: vpminuq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpminuq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512BW-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpminuq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpminuq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512BW-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpminuq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpminuq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vmovq %xmm0, %rax			; AVX512BW-NEXT: vmovq %xmm0, %rax
	; AVX512-NEXT: vzeroupper			; AVX512BW-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512BW-NEXT: retq
				;
				; AVX512VL-LABEL: test_v8i64:
				; AVX512VL: # %bb.0:
				; AVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm1
				; AVX512VL-NEXT: vpminuq %zmm1, %zmm0, %zmm0
				; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1
				; AVX512VL-NEXT: vpminuq %xmm1, %xmm0, %xmm0
				; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
				; AVX512VL-NEXT: vpminuq %xmm1, %xmm0, %xmm0
				; AVX512VL-NEXT: vmovq %xmm0, %rax
				; AVX512VL-NEXT: vzeroupper
				; AVX512VL-NEXT: retq
	%1 = call i64 @llvm.experimental.vector.reduce.umin.i64.v8i64(<8 x i64> %a0)			%1 = call i64 @llvm.experimental.vector.reduce.umin.i64.v8i64(<8 x i64> %a0)
	ret i64 %1			ret i64 %1
	}			}

	define i64 @test_v16i64(<16 x i64> %a0) {			define i64 @test_v16i64(<16 x i64> %a0) {
	; SSE2-LABEL: test_v16i64:			; SSE2-LABEL: test_v16i64:
	; SSE2: # %bb.0:			; SSE2: # %bb.0:
	; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [9223372039002259456,9223372039002259456]			; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [9223372039002259456,9223372039002259456]
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	; AVX2-NEXT: vxorpd %ymm4, %ymm0, %ymm2			; AVX2-NEXT: vxorpd %ymm4, %ymm0, %ymm2
	; AVX2-NEXT: vxorpd %ymm4, %ymm1, %ymm3			; AVX2-NEXT: vxorpd %ymm4, %ymm1, %ymm3
	; AVX2-NEXT: vpcmpgtq %ymm2, %ymm3, %ymm2			; AVX2-NEXT: vpcmpgtq %ymm2, %ymm3, %ymm2
	; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0			; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
	; AVX2-NEXT: vmovq %xmm0, %rax			; AVX2-NEXT: vmovq %xmm0, %rax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v16i64:			; AVX512BW-LABEL: test_v16i64:
	; AVX512: # %bb.0:			; AVX512BW: # %bb.0:
	; AVX512-NEXT: vpminuq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpminuq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; AVX512BW-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; AVX512-NEXT: vpminuq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpminuq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512BW-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpminuq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpminuq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512BW-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpminuq %zmm1, %zmm0, %zmm0			; AVX512BW-NEXT: vpminuq %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vmovq %xmm0, %rax			; AVX512BW-NEXT: vmovq %xmm0, %rax
	; AVX512-NEXT: vzeroupper			; AVX512BW-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512BW-NEXT: retq
				;
				; AVX512VL-LABEL: test_v16i64:
				; AVX512VL: # %bb.0:
				; AVX512VL-NEXT: vpminuq %zmm1, %zmm0, %zmm0
				; AVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm1
				; AVX512VL-NEXT: vpminuq %zmm1, %zmm0, %zmm0
				; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1
				; AVX512VL-NEXT: vpminuq %xmm1, %xmm0, %xmm0
				; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
				; AVX512VL-NEXT: vpminuq %xmm1, %xmm0, %xmm0
				; AVX512VL-NEXT: vmovq %xmm0, %rax
				; AVX512VL-NEXT: vzeroupper
				; AVX512VL-NEXT: retq
	%1 = call i64 @llvm.experimental.vector.reduce.umin.i64.v16i64(<16 x i64> %a0)			%1 = call i64 @llvm.experimental.vector.reduce.umin.i64.v16i64(<16 x i64> %a0)
	ret i64 %1			ret i64 %1
	}			}

	;			;
	; vXi32			; vXi32
	;			;

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	; AVX1-NEXT: vpminud %xmm1, %xmm0, %xmm0			; AVX1-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX1-NEXT: vmovd %xmm0, %eax			; AVX1-NEXT: vmovd %xmm0, %eax
	; AVX1-NEXT: vzeroupper			; AVX1-NEXT: vzeroupper
	; AVX1-NEXT: retq			; AVX1-NEXT: retq
	;			;
	; AVX2-LABEL: test_v8i32:			; AVX2-LABEL: test_v8i32:
	; AVX2: # %bb.0:			; AVX2: # %bb.0:
	; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vmovd %xmm0, %eax			; AVX2-NEXT: vmovd %xmm0, %eax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v8i32:			; AVX512-LABEL: test_v8i32:
	; AVX512: # %bb.0:			; AVX512: # %bb.0:
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpminud %ymm1, %ymm0, %ymm0			; AVX512-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpminud %ymm1, %ymm0, %ymm0			; AVX512-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX512-NEXT: vpminud %ymm1, %ymm0, %ymm0			; AVX512-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vmovd %xmm0, %eax			; AVX512-NEXT: vmovd %xmm0, %eax
	; AVX512-NEXT: vzeroupper			; AVX512-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512-NEXT: retq
	%1 = call i32 @llvm.experimental.vector.reduce.umin.i32.v8i32(<8 x i32> %a0)			%1 = call i32 @llvm.experimental.vector.reduce.umin.i32.v8i32(<8 x i32> %a0)
	ret i32 %1			ret i32 %1
	}			}

	define i32 @test_v16i32(<16 x i32> %a0) {			define i32 @test_v16i32(<16 x i32> %a0) {
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	; AVX1-NEXT: vmovd %xmm0, %eax			; AVX1-NEXT: vmovd %xmm0, %eax
	; AVX1-NEXT: vzeroupper			; AVX1-NEXT: vzeroupper
	; AVX1-NEXT: retq			; AVX1-NEXT: retq
	;			;
	; AVX2-LABEL: test_v16i32:			; AVX2-LABEL: test_v16i32:
	; AVX2: # %bb.0:			; AVX2: # %bb.0:
	; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0
	; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vmovd %xmm0, %eax			; AVX2-NEXT: vmovd %xmm0, %eax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v16i32:			; AVX512-LABEL: test_v16i32:
	; AVX512: # %bb.0:			; AVX512: # %bb.0:
	; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; AVX512-NEXT: vpminud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminud %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpminud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpminud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX512-NEXT: vpminud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vmovd %xmm0, %eax			; AVX512-NEXT: vmovd %xmm0, %eax
	; AVX512-NEXT: vzeroupper			; AVX512-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512-NEXT: retq
	%1 = call i32 @llvm.experimental.vector.reduce.umin.i32.v16i32(<16 x i32> %a0)			%1 = call i32 @llvm.experimental.vector.reduce.umin.i32.v16i32(<16 x i32> %a0)
	ret i32 %1			ret i32 %1
	}			}

	define i32 @test_v32i32(<32 x i32> %a0) {			define i32 @test_v32i32(<32 x i32> %a0) {
	▲ Show 20 Lines • Show All 114 Lines • ▼ Show 20 Lines
	; AVX1-NEXT: retq			; AVX1-NEXT: retq
	;			;
	; AVX2-LABEL: test_v32i32:			; AVX2-LABEL: test_v32i32:
	; AVX2: # %bb.0:			; AVX2: # %bb.0:
	; AVX2-NEXT: vpminud %ymm3, %ymm1, %ymm1			; AVX2-NEXT: vpminud %ymm3, %ymm1, %ymm1
	; AVX2-NEXT: vpminud %ymm2, %ymm0, %ymm0			; AVX2-NEXT: vpminud %ymm2, %ymm0, %ymm0
	; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0
	; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0			; AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX2-NEXT: vmovd %xmm0, %eax			; AVX2-NEXT: vmovd %xmm0, %eax
	; AVX2-NEXT: vzeroupper			; AVX2-NEXT: vzeroupper
	; AVX2-NEXT: retq			; AVX2-NEXT: retq
	;			;
	; AVX512-LABEL: test_v32i32:			; AVX512-LABEL: test_v32i32:
	; AVX512: # %bb.0:			; AVX512: # %bb.0:
	; AVX512-NEXT: vpminud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminud %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1			; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
	; AVX512-NEXT: vpminud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminud %zmm1, %zmm0, %zmm0
	; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1			; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
	; AVX512-NEXT: vpminud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
	; AVX512-NEXT: vpminud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]			; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
	; AVX512-NEXT: vpminud %zmm1, %zmm0, %zmm0			; AVX512-NEXT: vpminud %xmm1, %xmm0, %xmm0
	; AVX512-NEXT: vmovd %xmm0, %eax			; AVX512-NEXT: vmovd %xmm0, %eax
	; AVX512-NEXT: vzeroupper			; AVX512-NEXT: vzeroupper
	; AVX512-NEXT: retq			; AVX512-NEXT: retq
	%1 = call i32 @llvm.experimental.vector.reduce.umin.i32.v32i32(<32 x i32> %a0)			%1 = call i32 @llvm.experimental.vector.reduce.umin.i32.v32i32(<32 x i32> %a0)
	ret i32 %1			ret i32 %1
	}			}

	;			;
	▲ Show 20 Lines • Show All 1,044 Lines • Show Last 20 Lines

This is an archive of the discontinued LLVM Phabricator instance.

[SelectionDAG] define binops as a superset of commutative binopsClosedPublic

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Diff 201402

llvm/include/llvm/CodeGen/TargetLowering.h

llvm/test/CodeGen/X86/horizontal-reduce-smax.ll

llvm/test/CodeGen/X86/horizontal-reduce-smin.ll

llvm/test/CodeGen/X86/horizontal-reduce-umax.ll

llvm/test/CodeGen/X86/horizontal-reduce-umin.ll

llvm/test/CodeGen/X86/vector-reduce-smax-widen.ll

llvm/test/CodeGen/X86/vector-reduce-smax.ll

llvm/test/CodeGen/X86/vector-reduce-smin-widen.ll

llvm/test/CodeGen/X86/vector-reduce-smin.ll

llvm/test/CodeGen/X86/vector-reduce-umax-widen.ll

llvm/test/CodeGen/X86/vector-reduce-umax.ll

llvm/test/CodeGen/X86/vector-reduce-umin-widen.ll

llvm/test/CodeGen/X86/vector-reduce-umin.ll

[SelectionDAG] define binops as a superset of commutative binops
ClosedPublic