[RISCV] Support stack offset exceed 32-bit for RV64

[shiva0217]

Summary

Support prologue/epilogue generation for RV64 when the stack offset exceeds 32-bit

[shiva0217]

Rebase to the trunk

[shiva0217]

Using T1 as temp register for prologue/epilogue generation if there is no shrink wrapping optimization occur.

[lenary]

Thanks for the patch! I have two comments, which I think will help improve this patch.

lib/Target/RISCV/RISCVFrameLowering.cpp

90

I think you can probably get rid of movImm32, and only use movImm64 (the logic in generateInstSeq covers 32-bit operands), which I think will address the TODO in movImm32.

Then my only worry would be how we error when we need a larger-than-32-bit offset on RISC-V 32, which would probably cause errors somewhere way before this code anyway.

test/CodeGen/RISCV/rv64-large-stack.ll

43

I think this test case can be significantly simplified. You should just need a single alloca, and then maybe a call that uses a pointer into the alloca?

[shiva0217]

lib/Target/RISCV/RISCVFrameLowering.cpp

90

Yes, there's some test case improvement by replacing movImm32 with the generateInstSeq one, thanks!

I would add an error message for RV32 with a larger-than-32-bit offset. We could update the message when we support a larger-than-32-bit offset in RV32.

test/CodeGen/RISCV/rv64-large-stack.ll

43

Yes, it becomes significantly cleaner, thanks!

[shiva0217]

Update patch to address the comments.

Hi @lenary, thanks for the review.

[lenary]

Nice, this is looking a lot better.

I chatted to @asb about this this morning, and he's not sure of the value of using t1 (if it's free) instead of any general-purpose-register. This is going to compromise how many of these instructions we can compress when the C extension is enabled. If you use a virtual register, then the register allocator can use a0-5 if it wishes, which can be compressed, unlike t1. Do you have a justification for explicitly choosing t1?

[shiva0217]

In D61884#1666175, @lenary wrote:

Nice, this is looking a lot better.

I chatted to @asb about this this morning, and he's not sure of the value of using t1 (if it's free) instead of any general-purpose-register. This is going to compromise how many of these instructions we can compress when the C extension is enabled. If you use a virtual register, then the register allocator can use a0-5 if it wishes, which can be compressed, unlike t1. Do you have a justification for explicitly choosing t1?

To my understanding, the caller saved registers which are not parameter registers(a0-7) could be used as temp register for prologue and epilogue without any spill because the lifetime of these registers won't cross function call, and it would start after prologue and end before the epilogue. For the virtual register, if there are not enough scratch registers, the allocator will try to spill one. So choosing t1 could avoid spill and GCC choose t1, too. If the offset need to be rematlize, the constant after spilit might not fit in the C extension instructions in most cases.

[lenary]

In D61884#1667185, @shiva0217 wrote:

In D61884#1666175, @lenary wrote:

Nice, this is looking a lot better.

I chatted to @asb about this this morning, and he's not sure of the value of using t1 (if it's free) instead of any general-purpose-register. This is going to compromise how many of these instructions we can compress when the C extension is enabled. If you use a virtual register, then the register allocator can use a0-5 if it wishes, which can be compressed, unlike t1. Do you have a justification for explicitly choosing t1?

To my understanding, the caller saved registers which are not parameter registers(a0-7) could be used as temp register for prologue and epilogue without any spill because the lifetime of these registers won't cross function call, and it would start after prologue and end before the epilogue. For the virtual register, if there are not enough scratch registers, the allocator will try to spill one. So choosing t1 could avoid spill and GCC choose t1, too. If the offset need to be rematlize, the constant after spilit might not fit in the C extension instructions in most cases.

I see your point that t0 is guaranteed not to be live over a function call boundary.

If parameter registers a0-7 are not being used to pass arguments, then their lifetime will also not cross the function call and they are effectively no different from the temp registers, as far as their usage in the ABI is concerned.

In the case where there are unallocated (general purpose) registers, presumably choosing a virtual GPR will choose an unallocated one, and not spill. LLVM should know that if a0-7 is used for argument passing, then it cannot be used for a spill.

I think if we have to spill, we should let the compiler choose the register that is cheapest to spill. And if we don't have to spill, choosing in allocation order is more important as we have put the compressible registers earlier in the GPR allocation order.

Thus, if we have the ability to let LLVM choose for us, then we should.

[shiva0217]

Choosing virtual register as temp register.

I thought to choose a virtual register may cause spill, but I was wrong. After dumping the liveness info in Scavenger, LLVM could know caller saved register which is not using for parameter passing could be used. If the shrink wrap didn't occur, the caller saved registers which not used for parameter passing should always free to use for prologue and epilogue. And Scavenger will follow the AllocationOrder for the backend. So choosing a virtual register will be more reasonable. Thanks for @asb and @lenary comments, I got your point now :)

[lenary]

Great! This looks good to me! I'm glad we're getting rid of all those mov a0, a0 (which are really useless addi a0, a0, 0).

I'm not worried about changes from addi to addiw.

I'm happy that this means improvements to RISCVMatInt will affect these offsets as well as anywhere else we use that code.

lib/Target/RISCV/RISCVFrameLowering.cpp

void RISCVFrameLowering::adjustReg(MachineBasicBlock &MBB,
   if (DestReg == SrcReg && Val == 0)
     return;
 
   if (isInt<12>(Val)) {
     BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DestReg)
         .addReg(SrcReg)
         .addImm(Val)
         .setMIFlag(Flag);
-  } else if (isInt<32>(Val)) {
+  } else {
     unsigned Opc = RISCV::ADD;
     bool isSub = Val < 0;
     if (isSub) {
       Val = -Val;
       Opc = RISCV::SUB;
     }
 
     Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
-    TII->movImm32(MBB, MBBI, DL, ScratchReg, Val, Flag);
+    TII->movImm(MBB, MBBI, DL, ScratchReg, Val, Flag);
     BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
         .addReg(SrcReg)
         .addReg(ScratchReg, RegState::Kill)
         .setMIFlag(Flag);
-  } else {
-    report_fatal_error("adjustReg cannot yet handle adjustments >32 bits");
   }
 }
 
 // Returns the register used to hold the frame pointer.
 static Register getFPReg(const RISCVSubtarget &STI) { return RISCV::X8; }
 
 // Returns the register used to hold the stack pointer.
 static Register getSPReg(const RISCVSubtarget &STI) { return RISCV::X2; }

lib/Target/RISCV/RISCVInstrInfo.h

void storeRegToStackSlot(MachineBasicBlock &MBB,
                            const TargetRegisterClass *RC,
                            const TargetRegisterInfo *TRI) const override;
 
   void loadRegFromStackSlot(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MBBI, unsigned DstReg,
                             int FrameIndex, const TargetRegisterClass *RC,
                             const TargetRegisterInfo *TRI) const override;
 
-  // Materializes the given int32 Val into DstReg.
-  void movImm32(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
-                const DebugLoc &DL, Register DstReg, uint64_t Val,
-                MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const;
+  // Materializes the given integer Val into DstReg.
+  void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
 
   unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
 
   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
                      MachineBasicBlock *&FBB,
                      SmallVectorImpl<MachineOperand> &Cond,
                      bool AllowModify) const override;
 

lib/Target/RISCV/RISCVInstrInfo.cpp

 //===-- RISCVInstrInfo.cpp - RISCV Instruction Information ------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the RISCV implementation of the TargetInstrInfo class.
 //
 //===----------------------------------------------------------------------===//
 
 #include "RISCVInstrInfo.h"
 #include "RISCV.h"
 #include "RISCVSubtarget.h"
 #include "RISCVTargetMachine.h"
+#include "Utils/RISCVMatInt.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/RegisterScavenging.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"
void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
   else if (RISCV::FPR64RegClass.hasSubClassEq(RC))
     Opcode = RISCV::FLD;
   else
     llvm_unreachable("Can't load this register from stack slot");
 
   BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(0);
 }
 
-void RISCVInstrInfo::movImm32(MachineBasicBlock &MBB,
-                              MachineBasicBlock::iterator MBBI,
-                              const DebugLoc &DL, Register DstReg, uint64_t Val,
-                              MachineInstr::MIFlag Flag) const {
-  assert(isInt<32>(Val) && "Can only materialize 32-bit constants");
-
-  // TODO: If the value can be materialized using only one instruction, only
-  // insert a single instruction.
-
-  uint64_t Hi20 = ((Val + 0x800) >> 12) & 0xfffff;
-  uint64_t Lo12 = SignExtend64<12>(Val);
-  BuildMI(MBB, MBBI, DL, get(RISCV::LUI), DstReg)
-      .addImm(Hi20)
+void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,
+  MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
+  bool IsRV64 = MF->getSubtarget<RISCVSubtarget>().is64Bit();
+  Register SrcReg = RISCV::X0;
+  Register Result = MRI.createVirtualRegister(&RISCV::GPRRegClass);
+  unsigned Num = 0;
+
+  if (!IsRV64 && !isInt<32>(Val))
+    report_fatal_error("Should only materialize 32-bit constants for RV32");
+
+  RISCVMatInt::InstSeq Seq;
+  RISCVMatInt::generateInstSeq(Val, IsRV64, Seq);
+  assert(Seq.size() > 0);
+
+  for (RISCVMatInt::Inst &Inst : Seq) {
+    // Write the final result to DstReg if it's the last instruction in the Seq.
+    // Otherwise, write the result to the temp register.
+    if (++Num == Seq.size())
+      Result = DstReg;
+
+    if (Inst.Opc == RISCV::LUI) {
+      BuildMI(MBB, MBBI, DL, get(RISCV::LUI), Result)
+          .addImm(Inst.Imm)
           .setMIFlag(Flag);
-  BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
-      .addReg(DstReg, RegState::Kill)
-      .addImm(Lo12)
+    } else {
+      BuildMI(MBB, MBBI, DL, get(Inst.Opc), Result)
+          .addReg(SrcReg, RegState::Kill)
+          .addImm(Inst.Imm)
           .setMIFlag(Flag);
     }
+    // Only the first instruction has X0 as its source.
+    SrcReg = Result;
+  }
+}
 
 // The contents of values added to Cond are not examined outside of
 // RISCVInstrInfo, giving us flexibility in what to push to it. For RISCV, we
 // push BranchOpcode, Reg1, Reg2.
 static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target,
                             SmallVectorImpl<MachineOperand> &Cond) {
   // Block ends with fall-through condbranch.
   assert(LastInst.getDesc().isConditionalBranch() &&

lib/Target/RISCV/RISCVRegisterInfo.cpp

void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   MachineBasicBlock &MBB = *MI.getParent();
   bool FrameRegIsKill = false;
 
   if (!isInt<12>(Offset)) {
     assert(isInt<32>(Offset) && "Int32 expected");
     // The offset won't fit in an immediate, so use a scratch register instead
     // Modify Offset and FrameReg appropriately
     Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
-    TII->movImm32(MBB, II, DL, ScratchReg, Offset);
+    TII->movImm(MBB, II, DL, ScratchReg, Offset);
     BuildMI(MBB, II, DL, TII->get(RISCV::ADD), ScratchReg)
         .addReg(FrameReg)
         .addReg(ScratchReg, RegState::Kill);
     Offset = 0;
     FrameReg = ScratchReg;
     FrameRegIsKill = true;
   }
 

test/CodeGen/RISCV/rv64-large-stack.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s
+;
+; The test case check that RV64 could handle the stack adjustment offset exceed
+; 32-bit.
+
+define void @foo() nounwind {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lui a0, 95
+; CHECK-NEXT:    addiw a0, a0, 1505
+; CHECK-NEXT:    slli a0, a0, 13
+; CHECK-NEXT:    addi a0, a0, 32
+; CHECK-NEXT:    sub sp, sp, a0
+; CHECK-NEXT:    lui a0, 781250
+; CHECK-NEXT:    addiw a0, a0, 24
+; CHECK-NEXT:    add a0, sp, a0
+; CHECK-NEXT:    sd ra, 0(a0)
+; CHECK-NEXT:    addi a0, sp, 16
+; CHECK-NEXT:    call baz
+; CHECK-NEXT:    lui a0, 781250
+; CHECK-NEXT:    addiw a0, a0, 24
+; CHECK-NEXT:    add a0, sp, a0
+; CHECK-NEXT:    ld ra, 0(a0)
+; CHECK-NEXT:    lui a0, 95
+; CHECK-NEXT:    addiw a0, a0, 1505
+; CHECK-NEXT:    slli a0, a0, 13
+; CHECK-NEXT:    addi a0, a0, 32
+; CHECK-NEXT:    add sp, sp, a0
+; CHECK-NEXT:    ret
+entry:
+  %w = alloca [100000000 x { fp128, fp128 }], align 16
+  %arraydecay = getelementptr inbounds [100000000 x { fp128, fp128 }], [100000000 x { fp128, fp128 }]* %w, i64 0, i64 0
+  call void @baz({ fp128, fp128 }* nonnull %arraydecay)
+  ret void
+}
+
+declare void @baz({ fp128, fp128 }*)

test/CodeGen/RISCV/stack-realignment.ll

 ; RV32I-NEXT:    lui a0, 1
 ; RV32I-NEXT:    addi a0, a0, -1024
 ; RV32I-NEXT:    add sp, sp, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: caller1024:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, -1024
+; RV64I-NEXT:    addiw a0, a0, -1024
 ; RV64I-NEXT:    sub sp, sp, a0
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, -1032
+; RV64I-NEXT:    addiw a0, a0, -1032
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    sd ra, 0(a0)
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, -1040
+; RV64I-NEXT:    addiw a0, a0, -1040
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    sd s0, 0(a0)
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, -1024
+; RV64I-NEXT:    addiw a0, a0, -1024
 ; RV64I-NEXT:    add s0, sp, a0
 ; RV64I-NEXT:    andi sp, sp, -1024
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, -2048
+; RV64I-NEXT:    addiw a0, a0, -2048
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    mv a0, a0
 ; RV64I-NEXT:    call callee
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, -1024
+; RV64I-NEXT:    addiw a0, a0, -1024
 ; RV64I-NEXT:    sub sp, s0, a0
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, -1040
+; RV64I-NEXT:    addiw a0, a0, -1040
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    ld s0, 0(a0)
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, -1032
+; RV64I-NEXT:    addiw a0, a0, -1032
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    ld ra, 0(a0)
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, -1024
+; RV64I-NEXT:    addiw a0, a0, -1024
 ; RV64I-NEXT:    add sp, sp, a0
 ; RV64I-NEXT:    ret
   %1 = alloca i8, align 1024
   call void @callee(i8* %1)
   ret void
 }
 
 define void @caller_no_realign1024() nounwind "no-realign-stack" {

 ; RV32I-NEXT:    addi a0, a0, 2040
 ; RV32I-NEXT:    add a0, sp, a0
 ; RV32I-NEXT:    sw s0, 0(a0)
 ; RV32I-NEXT:    lui a0, 2
 ; RV32I-NEXT:    addi a0, a0, -2048
 ; RV32I-NEXT:    add s0, sp, a0
 ; RV32I-NEXT:    andi sp, sp, -2048
 ; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    add a0, sp, a0
 ; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    call callee
 ; RV32I-NEXT:    lui a0, 2
 ; RV32I-NEXT:    addi a0, a0, -2048
 ; RV32I-NEXT:    sub sp, s0, a0
 ; RV32I-NEXT:    lui a0, 1
 ; RV32I-NEXT:    addi a0, a0, 2040
 ; RV32I-NEXT:    add a0, sp, a0
 ; RV32I-NEXT:    lw s0, 0(a0)
 ; RV32I-NEXT:    lui a0, 1
 ; RV32I-NEXT:    addi a0, a0, 2044
 ; RV32I-NEXT:    add a0, sp, a0
 ; RV32I-NEXT:    lw ra, 0(a0)
 ; RV32I-NEXT:    lui a0, 2
 ; RV32I-NEXT:    addi a0, a0, -2048
 ; RV32I-NEXT:    add sp, sp, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: caller2048:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 2
-; RV64I-NEXT:    addi a0, a0, -2048
+; RV64I-NEXT:    addiw a0, a0, -2048
 ; RV64I-NEXT:    sub sp, sp, a0
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, 2040
+; RV64I-NEXT:    addiw a0, a0, 2040
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    sd ra, 0(a0)
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, 2032
+; RV64I-NEXT:    addiw a0, a0, 2032
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    sd s0, 0(a0)
 ; RV64I-NEXT:    lui a0, 2
-; RV64I-NEXT:    addi a0, a0, -2048
+; RV64I-NEXT:    addiw a0, a0, -2048
 ; RV64I-NEXT:    add s0, sp, a0
 ; RV64I-NEXT:    andi sp, sp, -2048
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    mv a0, a0
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    mv a0, a0
 ; RV64I-NEXT:    call callee
 ; RV64I-NEXT:    lui a0, 2
-; RV64I-NEXT:    addi a0, a0, -2048
+; RV64I-NEXT:    addiw a0, a0, -2048
 ; RV64I-NEXT:    sub sp, s0, a0
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, 2032
+; RV64I-NEXT:    addiw a0, a0, 2032
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    ld s0, 0(a0)
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, 2040
+; RV64I-NEXT:    addiw a0, a0, 2040
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    ld ra, 0(a0)
 ; RV64I-NEXT:    lui a0, 2
-; RV64I-NEXT:    addi a0, a0, -2048
+; RV64I-NEXT:    addiw a0, a0, -2048
 ; RV64I-NEXT:    add sp, sp, a0
 ; RV64I-NEXT:    ret
   %1 = alloca i8, align 2048
   call void @callee(i8* %1)
   ret void
 }
 
 define void @caller_no_realign2048() nounwind "no-realign-stack" {
; RV64I-NEXT:    ret
   call void @callee(i8* %1)
   ret void
 }
 
 define void @caller4096() nounwind {
 ; RV32I-LABEL: caller4096:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a0, 3
-; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    sub sp, sp, a0
 ; RV32I-NEXT:    lui a0, 3
 ; RV32I-NEXT:    addi a0, a0, -4
 ; RV32I-NEXT:    add a0, sp, a0
 ; RV32I-NEXT:    sw ra, 0(a0)
 ; RV32I-NEXT:    lui a0, 3
 ; RV32I-NEXT:    addi a0, a0, -8
 ; RV32I-NEXT:    add a0, sp, a0
 ; RV32I-NEXT:    sw s0, 0(a0)
 ; RV32I-NEXT:    lui a0, 3
-; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    add s0, sp, a0
 ; RV32I-NEXT:    srli a0, sp, 12
 ; RV32I-NEXT:    slli sp, a0, 12
 ; RV32I-NEXT:    lui a0, 2
-; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    add a0, sp, a0
 ; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    call callee
 ; RV32I-NEXT:    lui a0, 3
-; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    sub sp, s0, a0
 ; RV32I-NEXT:    lui a0, 3
 ; RV32I-NEXT:    addi a0, a0, -8
 ; RV32I-NEXT:    add a0, sp, a0
 ; RV32I-NEXT:    lw s0, 0(a0)
 ; RV32I-NEXT:    lui a0, 3
 ; RV32I-NEXT:    addi a0, a0, -4
 ; RV32I-NEXT:    add a0, sp, a0
 ; RV32I-NEXT:    lw ra, 0(a0)
 ; RV32I-NEXT:    lui a0, 3
-; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    add sp, sp, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: caller4096:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 3
-; RV64I-NEXT:    mv a0, a0
 ; RV64I-NEXT:    sub sp, sp, a0
 ; RV64I-NEXT:    lui a0, 3
-; RV64I-NEXT:    addi a0, a0, -8
+; RV64I-NEXT:    addiw a0, a0, -8
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    sd ra, 0(a0)
 ; RV64I-NEXT:    lui a0, 3
-; RV64I-NEXT:    addi a0, a0, -16
+; RV64I-NEXT:    addiw a0, a0, -16
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    sd s0, 0(a0)
 ; RV64I-NEXT:    lui a0, 3
-; RV64I-NEXT:    mv a0, a0
 ; RV64I-NEXT:    add s0, sp, a0
 ; RV64I-NEXT:    srli a0, sp, 12
 ; RV64I-NEXT:    slli sp, a0, 12
 ; RV64I-NEXT:    lui a0, 2
-; RV64I-NEXT:    mv a0, a0
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    mv a0, a0
 ; RV64I-NEXT:    call callee
 ; RV64I-NEXT:    lui a0, 3
-; RV64I-NEXT:    mv a0, a0
 ; RV64I-NEXT:    sub sp, s0, a0
 ; RV64I-NEXT:    lui a0, 3
-; RV64I-NEXT:    addi a0, a0, -16
+; RV64I-NEXT:    addiw a0, a0, -16
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    ld s0, 0(a0)
 ; RV64I-NEXT:    lui a0, 3
-; RV64I-NEXT:    addi a0, a0, -8
+; RV64I-NEXT:    addiw a0, a0, -8
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    ld ra, 0(a0)
 ; RV64I-NEXT:    lui a0, 3
-; RV64I-NEXT:    mv a0, a0
 ; RV64I-NEXT:    add sp, sp, a0
 ; RV64I-NEXT:    ret
   %1 = alloca i8, align 4096
   call void @callee(i8* %1)
   ret void
 }
 
 define void @caller_no_realign4096() nounwind "no-realign-stack" {