[AArc64] Handle ISD::LROUND and ISD::LLROUND

[zatrazz]

Summary

This patch optimizes ISD::LROUND and ISD::LROUND to fcvtas
instruction. It currently only handles the scalar version.

This patch depends on https://reviews.llvm.org/D61390.

[craig.topper]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

769

Is this really legal? I don't see any patterns or tests for lround.i32.

[efriedma]

Missing testcase for lroundl.

[zatrazz]

Updated patch based on the previous comment. The main change adapt the testcases for D61390
update and handle lroundl/llroundl correctly.

[zatrazz]

Updated patch based on D61390 changes. The main change is it allows
index both lround/llround by returned type.

[zatrazz]

Ping again now that D61390 has been approved.

[SjoerdMeijer]

llvm/lib/Target/AArch64/AArch64InstrInfo.td

3076

I think this is supported too for f16s with Armv8.2.

[zatrazz]

llvm/lib/Target/AArch64/AArch64InstrInfo.td

3076

Indeed it does, but FPToIntegerPats does not define a pattern for f16 currently. I think one possible addition would to extends fp to/from int pattern to f16 as well, however, I also think it is out the scope of this specific patch.

[zatrazz]

So should I handle f16 in a different patch or should I also adapt it on this one?

[SjoerdMeijer]

Looks reasonable to me.

llvm/lib/Target/AArch64/AArch64InstrInfo.td

3076

Okay, I see, there's indeed a pattern missing for f16s in FPToIntegerPats, so that's indeed extra work that belongs to a follow up patch. Would be highly appreciated if you can follow this up with a patch, so that we don't run into this later.

[zatrazz]

llvm/lib/Target/AArch64/AArch64InstrInfo.td

3076

Ok, I will add it on my backlog. I plan to send a lrint patch similar to lround, and then I will take a look at f16 support on FPToIntegerPats.

llvm/include/llvm/Target/TargetSelectionDAG.td

 def flog2      : SDNode<"ISD::FLOG2"      , SDTFPUnaryOp>;
 def frint      : SDNode<"ISD::FRINT"      , SDTFPUnaryOp>;
 def ftrunc     : SDNode<"ISD::FTRUNC"     , SDTFPUnaryOp>;
 def fceil      : SDNode<"ISD::FCEIL"      , SDTFPUnaryOp>;
 def ffloor     : SDNode<"ISD::FFLOOR"     , SDTFPUnaryOp>;
 def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
 def fround     : SDNode<"ISD::FROUND"     , SDTFPUnaryOp>;
 
+def lround     : SDNode<"ISD::LROUND"     , SDTFPToIntOp>;
+def llround    : SDNode<"ISD::LLROUND"    , SDTFPToIntOp>;
+
 def fpround    : SDNode<"ISD::FP_ROUND"   , SDTFPRoundOp>;
 def fpextend   : SDNode<"ISD::FP_EXTEND"  , SDTFPExtendOp>;
 def fcopysign  : SDNode<"ISD::FCOPYSIGN"  , SDTFPSignOp>;
 
 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;

llvm/lib/Target/AArch64/AArch64ISelLowering.h

private:
   SDValue LowerF128Call(SDValue Op, SelectionDAG &DAG,
                         RTLIB::Libcall Call) const;
   SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
+  SDValue LowerLROUND(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerATOMIC_LOAD_AND(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerWindowsDYNAMIC_STACKALLOC(SDValue Op, SDValue Chain,

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

if (Subtarget->hasFullFP16()) {
         setOperationAction(ISD::FCEIL, Ty, Legal);
         setOperationAction(ISD::FRINT, Ty, Legal);
         setOperationAction(ISD::FTRUNC, Ty, Legal);
         setOperationAction(ISD::FROUND, Ty, Legal);
       }
     }
 
     setTruncStoreAction(MVT::v4i16, MVT::v4i8, Custom);
+
+    setOperationAction(ISD::LROUND,  MVT::i64, Custom);
+    setOperationAction(ISD::LLROUND, MVT::i64, Custom);
   }
 
   PredictableSelectIsExpensive = Subtarget->predictableSelectIsExpensive();
 }
 
 void AArch64TargetLowering::addTypeForNEON(MVT VT, MVT PromotedBitwiseVT) {
   assert(VT.isVector() && "VT should be a vector type");
 
SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
   if (Op.getOpcode() == ISD::SINT_TO_FP)
     LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
   else
     LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
 
   return LowerF128Call(Op, DAG, LC);
 }
 
+SDValue AArch64TargetLowering::LowerLROUND(SDValue Op,
+                                           SelectionDAG &DAG) const {
+  if (Op.getOperand(0).getValueType() != MVT::f128) {
+    // It's legal except when f128 is involved.
+    return Op;
+  }
+
+  // Default action is to lower to a libcall.
+  return SDValue();
+}
+
 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
                                             SelectionDAG &DAG) const {
   // For iOS, we want to call an alternative entry point: __sincos_stret,
   // which returns the values in two S / D registers.
   SDLoc dl(Op);
   SDValue Arg = Op.getOperand(0);
   EVT ArgVT = Arg.getValueType();
   Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
   case ISD::PREFETCH:
     return LowerPREFETCH(Op, DAG);
   case ISD::SINT_TO_FP:
   case ISD::UINT_TO_FP:
     return LowerINT_TO_FP(Op, DAG);
   case ISD::FP_TO_SINT:
   case ISD::FP_TO_UINT:
     return LowerFP_TO_INT(Op, DAG);
+  case ISD::LROUND:
+  case ISD::LLROUND:
+    return LowerLROUND(Op, DAG);
   case ISD::FSINCOS:
     return LowerFSINCOS(Op, DAG);
   case ISD::FLT_ROUNDS_:
     return LowerFLT_ROUNDS_(Op, DAG);
   case ISD::MUL:
     return LowerMUL(Op, DAG);
   case ISD::INTRINSIC_WO_CHAIN:
     return LowerINTRINSIC_WO_CHAIN(Op, DAG);

llvm/lib/Target/AArch64/AArch64InstrInfo.td

 defm : FPToIntegerPats<fp_to_uint, fceil,  "FCVTPU">;
 defm : FPToIntegerPats<fp_to_sint, ffloor, "FCVTMS">;
 defm : FPToIntegerPats<fp_to_uint, ffloor, "FCVTMU">;
 defm : FPToIntegerPats<fp_to_sint, ftrunc, "FCVTZS">;
 defm : FPToIntegerPats<fp_to_uint, ftrunc, "FCVTZU">;
 defm : FPToIntegerPats<fp_to_sint, fround, "FCVTAS">;
 defm : FPToIntegerPats<fp_to_uint, fround, "FCVTAU">;
 
+def : Pat<(i64 (lround f32:$Rn)),
+          (!cast<Instruction>(FCVTASUXSr) f32:$Rn)>;
+def : Pat<(i64 (lround f64:$Rn)),
+          (!cast<Instruction>(FCVTASUXDr) f64:$Rn)>;
+def : Pat<(i64 (llround f32:$Rn)),
+          (!cast<Instruction>(FCVTASUXSr) f32:$Rn)>;
+def : Pat<(i64 (llround f64:$Rn)),
+          (!cast<Instruction>(FCVTASUXDr) f64:$Rn)>;
+
 //===----------------------------------------------------------------------===//
 // Scaled integer to floating point conversion instructions.
 //===----------------------------------------------------------------------===//
 
 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
 defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>;
 
 //===----------------------------------------------------------------------===//

llvm/test/CodeGen/AArch64/llround-conv.ll

 ; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s
 
 ; CHECK-LABEL: testmsws:
-; CHECK:       bl      llroundf
+; CHECK:       fcvtas  x0, s0
+; CHECK:       ret
 define i32 @testmsws(float %x) {
 entry:
   %0 = tail call i64 @llvm.llround.f32(float %x)
   %conv = trunc i64 %0 to i32
   ret i32 %conv
 }
 
 ; CHECK-LABEL: testmsxs:
-; CHECK:       b       llroundf
+; CHECK:       fcvtas  x0, s0
+; CHECK-NEXT:  ret
 define i64 @testmsxs(float %x) {
 entry:
   %0 = tail call i64 @llvm.llround.f32(float %x)
   ret i64 %0
 }
 
 ; CHECK-LABEL: testmswd:
-; CHECK:       bl      llround
+; CHECK:       fcvtas  x0, d0
+; CHECK:       ret
 define i32 @testmswd(double %x) {
 entry:
   %0 = tail call i64 @llvm.llround.f64(double %x)
   %conv = trunc i64 %0 to i32
   ret i32 %conv
 }
 
 ; CHECK-LABEL: testmsxd:
-; CHECK:       b       llround
+; CHECK:       fcvtas  x0, d0
+; CHECK-NEXT:  ret
 define i64 @testmsxd(double %x) {
 entry:
   %0 = tail call i64 @llvm.llround.f64(double %x)
   ret i64 %0
 }
 
 ; CHECK-LABEL: testmswl:
 ; CHECK:       bl      llroundl

llvm/test/CodeGen/AArch64/lround-conv.ll

 ; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s
 
 ; CHECK-LABEL: testmsws:
-; CHECK:       bl      lroundf
+; CHECK:       fcvtas  x0, s0
+; CHECK:       ret
 define i32 @testmsws(float %x) {
 entry:
   %0 = tail call i64 @llvm.lround.i64.f32(float %x)
   %conv = trunc i64 %0 to i32
   ret i32 %conv
 }
 
 ; CHECK-LABEL: testmsxs:
-; CHECK:       b       lroundf
+; CHECK:       fcvtas  x0, s0
+; CHECK-NEXT:  ret
 define i64 @testmsxs(float %x) {
 entry:
   %0 = tail call i64 @llvm.lround.i64.f32(float %x)
   ret i64 %0
 }
 
 ; CHECK-LABEL: testmswd:
-; CHECK:       bl      lround
+; CHECK:       fcvtas  x0, d0
+; CHECK:       ret
 define i32 @testmswd(double %x) {
 entry:
   %0 = tail call i64 @llvm.lround.i64.f64(double %x)
   %conv = trunc i64 %0 to i32
   ret i32 %conv
 }
 
 ; CHECK-LABEL: testmsxd:
-; CHECK:       b       lround
+; CHECK:       fcvtas  x0, d0
+; CHECK-NEXT:  ret
 define i64 @testmsxd(double %x) {
 entry:
   %0 = tail call i64 @llvm.lround.i64.f64(double %x)
   ret i64 %0
 }
 
 ; CHECK-LABEL: testmswl:
 ; CHECK:       bl      lroundl