[SelectionDAG] Add scalarization of ABS node.

[ikulagin]

Summary

Add scalarization of ABS node.
It is fix for pr41149.

[lebedev.ri]

Needs vector tests, to show that the issue is fixed.

[ikulagin]

In D59577#1435885, @lebedev.ri wrote:

Needs vector tests, to show that the issue is fixed.

Ok! What's the best way for test, unittest only for scalarization of vector ABS node or system test for code generation for every architecture?

[lebedev.ri]

In D59577#1436013, @ikulagin wrote:

In D59577#1435885, @lebedev.ri wrote:

Needs vector tests, to show that the issue is fixed.

Ok! What's the best way for test, unittest only for scalarization of vector ABS node or system test for code generation for every architecture?

$ find -iname *iabs*
./AArch64/iabs.ll
./ARM/iabs.ll
./PowerPC/iabs.ll
./Thumb/iabs.ll
./X86/viabs.ll
./X86/iabs.ll

Only the X86 has vector test coverage here.
At least copy ./X86/viabs.ll to those other arches.

[RKSimon]

The test case should be based around the PR41149 wasm code

[RKSimon]

PR41149 reduced to:

target triple = "wasm32-unknown--wasm"

define void @mod() {
entry:
  %tmp = load <4 x i8>, <4 x i8>* undef
  %tmp2 = icmp slt <4 x i8> %tmp, zeroinitializer
  %tmp3 = sub <4 x i8> zeroinitializer, %tmp
  %tmp4 = select <4 x i1> %tmp2, <4 x i8> %tmp3, <4 x i8> %tmp
  store <4 x i8> %tmp4, <4 x i8>* undef
  ret void
}

[ikulagin]

Add test case for PR41149

[aheejin]

llvm/test/CodeGen/WebAssembly/PR41149.ll

5 ↗

(On Diff #191635)

We usually use "wasm32-unknown-unknown"

[ikulagin]

llvm/test/CodeGen/WebAssembly/PR41149.ll

5 ↗

(On Diff #191635)

Ok.

[aheejin]

llvm/test/CodeGen/WebAssembly/PR41149.ll

5 ↗

(On Diff #191635)

Thanks, but no double dash between two unknowns

[RKSimon]

LGTM - I'll tidyup the test case as @aheejin requested and add some basic checks

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

#endif
   case ISD::SETCC:             R = ScalarizeVecRes_SETCC(N); break;
   case ISD::UNDEF:             R = ScalarizeVecRes_UNDEF(N); break;
   case ISD::VECTOR_SHUFFLE:    R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
   case ISD::ANY_EXTEND_VECTOR_INREG:
   case ISD::SIGN_EXTEND_VECTOR_INREG:
   case ISD::ZERO_EXTEND_VECTOR_INREG:
     R = ScalarizeVecRes_VecInregOp(N);
     break;
+  case ISD::ABS:
   case ISD::ANY_EXTEND:
   case ISD::BITREVERSE:
   case ISD::BSWAP:
   case ISD::CTLZ:
   case ISD::CTLZ_ZERO_UNDEF:
   case ISD::CTPOP:
   case ISD::CTTZ:
   case ISD::CTTZ_ZERO_UNDEF: