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[AMDGPU] Asm/disasm v_cndmask_b32_e64 with abs/neg source modifiers
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Authored by tpr on Mar 10 2019, 1:11 PM.

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Summary

This commit allows v_cndmask_b32_e64 with abs, neg source
modifiers on src0, src1 to be assembled and disassembled.

This does appear to be allowed, even though they are floating point
modifiers and the operand type is b32.

To do this, I added src0_modifiers and src1_modifiers to the
MachineInstr, which involved fixing up several places in codegen and mir
tests.

Change-Id: I69bf4a8c73ebc65744f6110bb8fc4e937d79fbea

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rL LLVM

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tpr created this revision.Mar 10 2019, 1:11 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 10 2019, 1:11 PM

Are you sure these actually do anything? I thought I tried this a long time ago, and found these are ignored by the instruction (along with a bunch of others like mov)

tpr added a comment.Mar 11 2019, 2:22 AM

I'll double check.

If these do work, we do have a lot of code assuming they don't to try moving the modifiers around so they can fold in the inputs/users

tpr added a comment.Mar 11 2019, 10:38 AM

The answer I have got from the HW team is that you can use abs and neg modifiers on f32 data in v_cndmask_b32, v_mov_b32 and v_movrel*_b32.

vpykhtin accepted this revision.Mar 14 2019, 6:08 AM

LGTM, Thanks!

This revision is now accepted and ready to land.Mar 14 2019, 6:08 AM
This revision was automatically updated to reflect the committed changes.