vpykhtin (Valery Pykhtin)
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User Since
Jan 28 2016, 8:30 AM (64 w, 4 d)

Recent Activity

Today

vpykhtin accepted D32101: Skip bitcasts while looking for GEP in LoadStoreVectorizer.
Tue, Apr 25, 5:37 AM
vpykhtin added a comment to D32101: Skip bitcasts while looking for GEP in LoadStoreVectorizer.

LGTM.

Tue, Apr 25, 5:37 AM

Fri, Apr 21

vpykhtin accepted D32279: [AMDGPU] Merge M0 initializations.

Looks very good now! Thanks!

Fri, Apr 21, 4:10 AM

Thu, Apr 20

vpykhtin added inline comments to D32279: [AMDGPU] Merge M0 initializations.
Thu, Apr 20, 11:01 AM
vpykhtin added inline comments to D32279: [AMDGPU] Merge M0 initializations.
Thu, Apr 20, 10:38 AM
vpykhtin added a comment to D32279: [AMDGPU] Merge M0 initializations.

Thank you for doing this! I really need it.

Thu, Apr 20, 6:57 AM

Thu, Apr 13

vpykhtin accepted D31993: [AMDGPU] Combine DS operations with offsets bigger than byte.
Thu, Apr 13, 10:48 AM
vpykhtin added inline comments to D31993: [AMDGPU] Combine DS operations with offsets bigger than byte.
Thu, Apr 13, 10:44 AM
vpykhtin added a comment to D31993: [AMDGPU] Combine DS operations with offsets bigger than byte.

Looks good.

Thu, Apr 13, 10:25 AM

Wed, Apr 12

vpykhtin accepted D31587: MachineScheduler/ScheduleDAG: Add support for getSUTopoIndex.

LGTM.

Wed, Apr 12, 3:58 AM
vpykhtin added a comment to D31124: AMDGPU/SI: Add lane tracking to SI Scheduler.

For the second assert it may be the case for iterator invalidation, though I haven't checked.

Wed, Apr 12, 3:55 AM · Restricted Project
vpykhtin accepted D31820: [AMDGPU][MC] Fix for bug 32565 + LIT tests.

LGTM.

Wed, Apr 12, 3:49 AM
vpykhtin accepted D31810: [AMDGPU][MC] Fix for bug 32552 + LIT tests.

LGTM.

Wed, Apr 12, 3:48 AM
vpykhtin accepted D31809: [AMDGPU][MC] Fix for Bug 32551 + LIT tests.

LGTM.

Wed, Apr 12, 3:48 AM
vpykhtin accepted D31808: [AMDGPU][MC] Fix for Bug 28227 + LIT tests.

LGTM.

Wed, Apr 12, 3:47 AM
vpykhtin accepted D31595: [AMDGPU][MC] Fix for Bug 28159 + LIT tests.

LGTM.

Wed, Apr 12, 3:30 AM

Mon, Apr 10

vpykhtin accepted D31854: AMDGPU: Fix crash when disassembling VOP3 mac.

LGTM.

Mon, Apr 10, 11:07 AM
vpykhtin added a reviewer for D31854: AMDGPU: Fix crash when disassembling VOP3 mac: dp.
Mon, Apr 10, 11:06 AM

Fri, Apr 7

vpykhtin accepted D31693: [AMDGPU] Unroll more to eliminate phis and conditions.

LGTM.

Fri, Apr 7, 4:16 AM

Thu, Apr 6

vpykhtin added a comment to D31124: AMDGPU/SI: Add lane tracking to SI Scheduler.

Thanks Axel!

Thu, Apr 6, 2:49 PM · Restricted Project
vpykhtin added a comment to D31124: AMDGPU/SI: Add lane tracking to SI Scheduler.

The following tests assert with this (and predecessors) patches:

Thu, Apr 6, 9:41 AM · Restricted Project

Wed, Apr 5

vpykhtin accepted D31707: [AMDGPU][MC] Fix for Bug 28211 + LIT tests.

LGTM.

Wed, Apr 5, 7:02 AM

Tue, Apr 4

vpykhtin added a comment to D31124: AMDGPU/SI: Add lane tracking to SI Scheduler.

First part of comments related only to C++ issues

Tue, Apr 4, 8:02 AM · Restricted Project

Fri, Mar 31

vpykhtin added a comment to D31124: AMDGPU/SI: Add lane tracking to SI Scheduler.

If SU(i) uses register produced by SI(j):

Fri, Mar 31, 10:32 AM · Restricted Project
vpykhtin added a comment to D31124: AMDGPU/SI: Add lane tracking to SI Scheduler.

I may miss something, but it looks that you can build data edges when building a superdag consisting of blocks. Incoming data edges would be liveins, outcoming - liveouts.

Fri, Mar 31, 10:05 AM · Restricted Project
vpykhtin added a comment to D31124: AMDGPU/SI: Add lane tracking to SI Scheduler.

In general, I think moving instructions just to use standard RP tracker to discover liveins/liveouts isn't a good idea. It isn't only slow but doesn't look reliable too. Why not discover these sets using DAG directly?

Fri, Mar 31, 9:48 AM · Restricted Project
vpykhtin added a comment to D31124: AMDGPU/SI: Add lane tracking to SI Scheduler.

Stack trace:

Fri, Mar 31, 9:39 AM · Restricted Project
vpykhtin added a comment to D31124: AMDGPU/SI: Add lane tracking to SI Scheduler.

I didn't debugged it and I don't know why you decided so.

Fri, Mar 31, 9:05 AM · Restricted Project
vpykhtin added a comment to D31124: AMDGPU/SI: Add lane tracking to SI Scheduler.

I ran lit tests with sished with ShouldTrackLaneMasks=true enabled by default with this patch, the following tests asserted:

Fri, Mar 31, 5:54 AM · Restricted Project
vpykhtin added inline comments to D30147: AMDGPU/SI: Add new SISched policy to reduce register usage.
Fri, Mar 31, 3:24 AM · Restricted Project
vpykhtin added inline comments to D31124: AMDGPU/SI: Add lane tracking to SI Scheduler.
Fri, Mar 31, 3:22 AM · Restricted Project

Wed, Mar 29

vpykhtin accepted D31469: [AMDGPU][MC] Fix for Bug 28158 + LIT tests.

LGTM.

Wed, Mar 29, 9:23 AM
vpykhtin accepted D31463: [AMDGPU][MC] Fix for Bug 28167 + LIT tests.

LGTM.

Wed, Mar 29, 9:02 AM
vpykhtin accepted D31455: [AMDGPU] SDWA Peephole: improve search for immediates in SDWA patterns.

LGTM.

Wed, Mar 29, 5:37 AM
vpykhtin added a comment to D31455: [AMDGPU] SDWA Peephole: improve search for immediates in SDWA patterns.

Mostly good.

Wed, Mar 29, 4:35 AM

Tue, Mar 28

vpykhtin added a comment to D31124: AMDGPU/SI: Add lane tracking to SI Scheduler.

Axel, thanks for the update.

Tue, Mar 28, 8:33 PM · Restricted Project
vpykhtin accepted D31434: [AMDGPU] Fix recorded region boundaries in max-occupancy scheduler.

This looks elegant, mine was longer :), thanks!

Tue, Mar 28, 12:57 PM
vpykhtin added inline comments to D31124: AMDGPU/SI: Add lane tracking to SI Scheduler.
Tue, Mar 28, 11:32 AM · Restricted Project
vpykhtin added a comment to D31124: AMDGPU/SI: Add lane tracking to SI Scheduler.

Ok, I understood SIScheduleBlockCreator::scheduleInsideBlocks() moves instructions to actually get LiveIn and LiveOut set for a block, but this is rather heavy. Have you thought about getting those using DAG directly, not regpressure tracker? By the common sence the dependencies between blocks correspond to that liveness info. There is a problem however: LiveIn and LiveOut dependencies aren't modelled for boundary SUs. I have local patch that build such dependencies - scheduling region LiveIns edges comes from EntrySU, LiveOut - to ExitSU. Another problem - dependency edges doesn't have lanemask, need to think how to deal with this.

Tue, Mar 28, 11:01 AM · Restricted Project
vpykhtin added a comment to D31124: AMDGPU/SI: Add lane tracking to SI Scheduler.

Why SIScheduleBlockCreator::scheduleInsideBlocks() actually move instructions? Why it isn't done on the final scheduling?

Tue, Mar 28, 6:51 AM · Restricted Project
vpykhtin committed rL298902: [AMDGPU] Update SI scheduler colorHighLatenciesGroups.
[AMDGPU] Update SI scheduler colorHighLatenciesGroups
Tue, Mar 28, 12:32 AM
vpykhtin closed D30152: AMDGPU/SI: Update SI scheduler colorHighLatenciesGroups by committing rL298902: [AMDGPU] Update SI scheduler colorHighLatenciesGroups.
Tue, Mar 28, 12:32 AM · Restricted Project

Mon, Mar 27

vpykhtin committed rL298896: MachineScheduler/ScheduleDAG: Add support for GetSubGraph.
MachineScheduler/ScheduleDAG: Add support for GetSubGraph
Mon, Mar 27, 10:25 PM
vpykhtin closed D30626: MachineScheduler/ScheduleDAG: Add support for GetSubGraph by committing rL298896: MachineScheduler/ScheduleDAG: Add support for GetSubGraph.
Mon, Mar 27, 10:25 PM
vpykhtin committed rL298872: [AMDGPU] SISched: Detect dependency types between blocks.
[AMDGPU] SISched: Detect dependency types between blocks
Mon, Mar 27, 11:35 AM
vpykhtin closed D30153: AMDGPU/SI: Detect dependency types between blocks by committing rL298872: [AMDGPU] SISched: Detect dependency types between blocks.
Mon, Mar 27, 11:35 AM · Restricted Project
vpykhtin committed rL298861: [AMDGPU] SISched: Update colorEndsAccordingToDependencies.
[AMDGPU] SISched: Update colorEndsAccordingToDependencies
Mon, Mar 27, 10:39 AM
vpykhtin closed D30150: AMDGPU/SI: Update colorEndsAccordingToDependencies by committing rL298861: [AMDGPU] SISched: Update colorEndsAccordingToDependencies.
Mon, Mar 27, 10:39 AM · Restricted Project
vpykhtin committed rL298857: [AMDGPU] Fix SI scheduler LiveOut Refcount issue.
[AMDGPU] Fix SI scheduler LiveOut Refcount issue
Mon, Mar 27, 10:19 AM
vpykhtin closed D30145: AMDGPU/SI: Fix SI scheduler LiveOut Refcount issue by committing rL298857: [AMDGPU] Fix SI scheduler LiveOut Refcount issue.
Mon, Mar 27, 10:18 AM · Restricted Project
vpykhtin added a dependency for D30152: AMDGPU/SI: Update SI scheduler colorHighLatenciesGroups: D30626: MachineScheduler/ScheduleDAG: Add support for GetSubGraph.
Mon, Mar 27, 7:51 AM · Restricted Project
vpykhtin added a dependent revision for D30626: MachineScheduler/ScheduleDAG: Add support for GetSubGraph: D30152: AMDGPU/SI: Update SI scheduler colorHighLatenciesGroups.
Mon, Mar 27, 7:51 AM
vpykhtin added a comment to D30147: AMDGPU/SI: Add new SISched policy to reduce register usage.

Sorry but I give up reviewing this. Your code looks like after "inline all" pass. Can you refactor common parts into functions with meaningfull names?

Mon, Mar 27, 7:30 AM · Restricted Project
vpykhtin added a comment to D30148: AMDGPU/SI: Fix listing of Low and High latency instructions.

It's still missing a few. VINTRP and EXP. I think it would be better to check instruction latency data. In absence of that, I think it would be simpler to just use isHighLatencyInstruction, and !isHighLatencyInstruction

The true usage of these helper functions is to deduce instructions which need a VMCNT wait or a LGKMCNT wait (former ones being incorrectly called 'high latency' and the latter ones 'lon latency').

What about renaming to isVMCNTInstruction and isLGKMCNTInstruction ?

Mon, Mar 27, 7:26 AM · Restricted Project

Mar 24 2017

vpykhtin committed rL298718: [AMDGPU] Remove double map lookups in SI scheduler.
[AMDGPU] Remove double map lookups in SI scheduler
Mar 24 2017, 11:01 AM
vpykhtin closed D30382: AMDGPU/SI: Remove double lookups in SI scheduler by committing rL298718: [AMDGPU] Remove double map lookups in SI scheduler.
Mar 24 2017, 11:01 AM · Restricted Project
vpykhtin accepted D31323: [AMDGPU] Add AMDGPUAliasAnalysis to opt pipeline.

LGTM.

Mar 24 2017, 10:53 AM
vpykhtin committed rL298710: [AMDGPU] Fix SGPR usage count in SI scheduler.
[AMDGPU] Fix SGPR usage count in SI scheduler
Mar 24 2017, 9:58 AM
vpykhtin closed D30149: AMDGPU/SI: Fix SGPR usage count in SI scheduler by committing rL298710: [AMDGPU] Fix SGPR usage count in SI scheduler.
Mar 24 2017, 9:58 AM · Restricted Project
vpykhtin committed rL298708: [AMDGPU] Add a new line after a debug message.
[AMDGPU] Add a new line after a debug message
Mar 24 2017, 9:50 AM
vpykhtin closed D30146: AMDGPU/SI: Add a new line after a debug message by committing rL298708: [AMDGPU] Add a new line after a debug message.
Mar 24 2017, 9:50 AM · Restricted Project
vpykhtin accepted D30150: AMDGPU/SI: Update colorEndsAccordingToDependencies.

LGTM.

Mar 24 2017, 8:39 AM · Restricted Project
vpykhtin accepted D30152: AMDGPU/SI: Update SI scheduler colorHighLatenciesGroups.

LGTM, Thanks!

Mar 24 2017, 8:37 AM · Restricted Project
vpykhtin accepted D31327: [AMDGPU][MC] Fix for Bug 28207 + LIT tests.

LGTM.

Mar 24 2017, 7:05 AM

Mar 23 2017

vpykhtin added inline comments to D30152: AMDGPU/SI: Update SI scheduler colorHighLatenciesGroups.
Mar 23 2017, 8:06 AM · Restricted Project
vpykhtin accepted D30153: AMDGPU/SI: Detect dependency types between blocks.

LGTM.

Mar 23 2017, 7:46 AM · Restricted Project
vpykhtin added inline comments to D30150: AMDGPU/SI: Update colorEndsAccordingToDependencies.
Mar 23 2017, 7:43 AM · Restricted Project
vpykhtin accepted D30145: AMDGPU/SI: Fix SI scheduler LiveOut Refcount issue.

LGTM, Thanks!

Mar 23 2017, 7:40 AM · Restricted Project

Mar 22 2017

vpykhtin added inline comments to D30152: AMDGPU/SI: Update SI scheduler colorHighLatenciesGroups.
Mar 22 2017, 10:54 AM · Restricted Project
vpykhtin added inline comments to D30153: AMDGPU/SI: Detect dependency types between blocks.
Mar 22 2017, 10:36 AM · Restricted Project
vpykhtin added inline comments to D30150: AMDGPU/SI: Update colorEndsAccordingToDependencies.
Mar 22 2017, 10:14 AM · Restricted Project
vpykhtin added inline comments to D30145: AMDGPU/SI: Fix SI scheduler LiveOut Refcount issue.
Mar 22 2017, 10:00 AM · Restricted Project

Mar 21 2017

vpykhtin committed rL298368: [AMDGPU] Iterative scheduling infrastructure + minimal registry scheduler.
[AMDGPU] Iterative scheduling infrastructure + minimal registry scheduler
Mar 21 2017, 6:28 AM
vpykhtin closed D31046: [AMDGPU] Iterative scheduling infrastructure + minimal registry scheduler by committing rL298368: [AMDGPU] Iterative scheduling infrastructure + minimal registry scheduler.
Mar 21 2017, 6:28 AM

Mar 20 2017

vpykhtin added inline comments to D31046: [AMDGPU] Iterative scheduling infrastructure + minimal registry scheduler.
Mar 20 2017, 10:43 AM
vpykhtin updated the diff for D31046: [AMDGPU] Iterative scheduling infrastructure + minimal registry scheduler.

Restored function order

Mar 20 2017, 10:06 AM
vpykhtin added a comment to D31046: [AMDGPU] Iterative scheduling infrastructure + minimal registry scheduler.

I optimistically moved dump function down in GCNRegPressure.cpp and all comments got out of sync with the source, sorry.

Mar 20 2017, 9:54 AM
vpykhtin updated the diff for D31046: [AMDGPU] Iterative scheduling infrastructure + minimal registry scheduler.

Added tests + per review updates.

Mar 20 2017, 9:49 AM

Mar 17 2017

vpykhtin accepted D31103: [AMDGPU] Add address space based alias analysis pass.

LGTM.

Mar 17 2017, 2:23 PM
vpykhtin added inline comments to D31103: [AMDGPU] Add address space based alias analysis pass.
Mar 17 2017, 2:23 PM
vpykhtin added a comment to D31046: [AMDGPU] Iterative scheduling infrastructure + minimal registry scheduler.

Can you please add more RUN lines with new strategies to the test/CodeGen/AMDGPU/schedule-regpressure-limit.ll

Mar 17 2017, 9:58 AM
vpykhtin added inline comments to D30626: MachineScheduler/ScheduleDAG: Add support for GetSubGraph.
Mar 17 2017, 9:38 AM
vpykhtin added a comment to D31046: [AMDGPU] Iterative scheduling infrastructure + minimal registry scheduler.

I think I should write a test and show how it works, but teoretically:

Before : all ready SUs are put to the ready queue with Priority = 0.

Step 1: 1, 2, 3, 4, 5 have one non ready successor (SU6) and lose. 7, 10, 13 ... SUs would be equivalent as they all have one ready successor and 7 will be selected by default order. This adds SU8 to the ready queue with priority = current step_no (1)
Step 2: We have the only SU8 with highest priority = 1 and it will be selected. Now that SU8 have non-ready successor SU9 it bumps the priority of every predecessor of SU9 in ready queue to step_no whichs is 2. This makes 1, 2, 3, 4, 5 SUs of priority 2
Step 3: We have 1, 2, 3, 4, 5 of highest priority (2) in the queue and as they are equivalent SU1 is selected as default. As SU1 has non-ready successor SU6 we bump the priority of predecessors of SU6 in ready queue to 3.
... continue until all predecessors of SU6 as selected and select SU6.

Continue with the rest of SUs.

I see. I didn't understand before that you were propagating the priority to non-direct predecessors.
In that case, the worst case scenario is then if I take exactly the same example with the numbers reversed.
That is equivalently if SUs with high NodeNum were selected first.

A good policy in my experience is to take the node with the maximum Height when you have several choices.
That is probably a better choice than relying on NodeNum.

Why? Lets assume 10, 11 and 12 are the last SUs in the sequence of summation and I select max nodenum first. This would select 10, 11 and would bump 1, 2, 3, 4, 5 again, and there will be 5, 4, 3, 2, 1, 6, 7, 8, 9

In the summation example, 12 depends on 9, thus 7, 8, 9 would get bumped as well, thus 7 taken first.

Mar 17 2017, 8:45 AM
vpykhtin added a comment to D31046: [AMDGPU] Iterative scheduling infrastructure + minimal registry scheduler.

I think I should write a test and show how it works, but teoretically:

Before : all ready SUs are put to the ready queue with Priority = 0.

Step 1: 1, 2, 3, 4, 5 have one non ready successor (SU6) and lose. 7, 10, 13 ... SUs would be equivalent as they all have one ready successor and 7 will be selected by default order. This adds SU8 to the ready queue with priority = current step_no (1)
Step 2: We have the only SU8 with highest priority = 1 and it will be selected. Now that SU8 have non-ready successor SU9 it bumps the priority of every predecessor of SU9 in ready queue to step_no whichs is 2. This makes 1, 2, 3, 4, 5 SUs of priority 2
Step 3: We have 1, 2, 3, 4, 5 of highest priority (2) in the queue and as they are equivalent SU1 is selected as default. As SU1 has non-ready successor SU6 we bump the priority of predecessors of SU6 in ready queue to 3.
... continue until all predecessors of SU6 as selected and select SU6.

Continue with the rest of SUs.

I see. I didn't understand before that you were propagating the priority to non-direct predecessors.
In that case, the worst case scenario is then if I take exactly the same example with the numbers reversed.
That is equivalently if SUs with high NodeNum were selected first.

A good policy in my experience is to take the node with the maximum Height when you have several choices.
That is probably a better choice than relying on NodeNum.

Mar 17 2017, 8:40 AM
vpykhtin added a comment to D31046: [AMDGPU] Iterative scheduling infrastructure + minimal registry scheduler.

Then in my example, what is the result of this strategy ? Does it avoid scheduling SU 6 late ?

From you example it's not clear how the following SUs relate: SU6 <-> SU7, SU9 <-> SU7, SU9 <-> SU8

Ok, I add more details to make it more realistics.

Initially, SUs 1, 2, 3, 4, 5, 7, 10, 13, 16 etc (up to 50) can be scheduled (no dependencies)
SU 6 depends on SUs 1 2 3 4 5 only
SU 8 depends only on SU 7.
SU 9 depends on SUs 6 and 8
SU 11 depends only on SU 10
SU 12 depends on SUs 6, 9 and 11
etc

A possible pseudocode giving that scenario is:
SU 1 to 5: loads from memory
SU 6: read from memory a constant b. (And we'll say that the load order is enforced in this schedule)
SU (7+3*i): read from memory a constant a_i
SU (8+3*i): compute the square of a_i
SU (9+3*i): current sum += a_i ^2

That is we have
b loaded from memory (SU 6)
b+= a_1^2 (SU 7 8 9)
b+= a_2^2 (SU 10 11 12)
etc

I think with the minReg policy, the schedule will be
SU 7 10 13 etc
then
SU 8 11 14 etc
then
SU 1 2 3 4 5 6 9 12 etc

SU 7 10 13 increases register usage, and the register usage is only reduced when 9, 12, etc are scheduled.

Mar 17 2017, 8:22 AM
vpykhtin added inline comments to D31046: [AMDGPU] Iterative scheduling infrastructure + minimal registry scheduler.
Mar 17 2017, 2:47 AM
vpykhtin added a comment to D31046: [AMDGPU] Iterative scheduling infrastructure + minimal registry scheduler.

Then in my example, what is the result of this strategy ? Does it avoid scheduling SU 6 late ?

From you example it's not clear how the following SUs relate: SU6 <-> SU7, SU9 <-> SU7, SU9 <-> SU8

As for including sisched I have patch to include it into this, though its a bit outdated and should be updated.

I think one blocker is sisched doesn't support yet when subRegLiveness is enabled. I'm on it.

I have several sisched patches pending review. Would be great if you could take a look in order to have them merged.

Mar 17 2017, 2:14 AM

Mar 16 2017

vpykhtin added inline comments to D31046: [AMDGPU] Iterative scheduling infrastructure + minimal registry scheduler.
Mar 16 2017, 2:19 PM
vpykhtin added a comment to D31046: [AMDGPU] Iterative scheduling infrastructure + minimal registry scheduler.

Hi Axel, thanks for reply!

Mar 16 2017, 2:04 PM
vpykhtin accepted D30796: Only unswitch loops with uniform conditions.

LGTM.

Mar 16 2017, 1:33 PM
vpykhtin created D31046: [AMDGPU] Iterative scheduling infrastructure + minimal registry scheduler.
Mar 16 2017, 11:31 AM
vpykhtin accepted D31016: [AMDGPU] Run always inliner early in opt.

LGTM.

Mar 16 2017, 3:45 AM

Feb 28 2017

vpykhtin accepted D30442: [AMDGPU] Add second pass of the scheduler.

Ok, it's just not that easy to follow this in GCNMaxOccupancySchedStrategy::initialize.

Feb 28 2017, 10:13 AM
vpykhtin added a comment to D30442: [AMDGPU] Add second pass of the scheduler.

I'm just a bit confused: what gives scheduler more registry freedom on rescheduling run?

Feb 28 2017, 9:57 AM
vpykhtin accepted D30439: [AMDGPU] New method to estimate register pressure.

LGTM.

Feb 28 2017, 9:15 AM
vpykhtin added inline comments to D30439: [AMDGPU] New method to estimate register pressure.
Feb 28 2017, 8:46 AM
vpykhtin added inline comments to D30439: [AMDGPU] New method to estimate register pressure.
Feb 28 2017, 8:24 AM
vpykhtin accepted D30428: [AMDGPU] Fix read-undef flags when schedule is reverted.

LGTM.

Feb 28 2017, 7:26 AM
vpykhtin added inline comments to D30439: [AMDGPU] New method to estimate register pressure.
Feb 28 2017, 5:55 AM

Feb 15 2017

vpykhtin accepted D29971: [AMDGPU] Revert failed scheduling.

LGTM.

Feb 15 2017, 9:13 AM