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[MIPS GlobalISel] Fix mul operands
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Authored by Petar.Avramovic on Feb 27 2019, 6:34 AM.

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Summary

Unsigned mul high for MIPS32 is selected into two PseudoInstructions:
PseudoMULTu and PseudoMFHI that use accumulator register class ACC64 for
some of its operands. Registers in this class have appropriate hi and lo
register as subregisters: $lo0 and $hi0 are subregisters of $ac0 etc.
mul instruction implicit-defs $lo0 and $hi0 according to MipsInstrInfo.td.
In functions where mul and PseudoMULTu are present fastRegisterAllocator
will "run out of registers during register allocation" because
'calcSpillCost' for $ac0 will return spillImpossible because subregisters
$lo0 and $hi0 of $ac0 are reserved by mul instruction above. A solution is
to mark implicit-defs of $lo0 and $hi0 as dead in mul instruction.

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Repository
rL LLVM

Event Timeline

This revision is now accepted and ready to land.Feb 28 2019, 6:50 AM
This revision was automatically updated to reflect the committed changes.
Herald added a project: Restricted Project. · View Herald TranscriptFeb 28 2019, 11:35 PM
Petar.Avramovic reopened this revision.Mar 6 2019, 1:31 AM

Reverted in https://reviews.llvm.org/rL355219
since it causes failure on bot that tests clang built with address sanitizer.

This revision is now accepted and ready to land.Mar 6 2019, 1:31 AM

selectImpl in some cases deletes I (using eraseFromParent()) and creates new instruction that is inserted in place of I in machine basic block.
In such cases I.getOpcode() accesses memory that was freed and can return unpredictable value.
For that reason we now select G_MUL manually before call to selectImpl.

Petar.Avramovic requested review of this revision.Mar 6 2019, 3:18 AM
This revision is now accepted and ready to land.Mar 7 2019, 4:45 AM
This revision was automatically updated to reflect the committed changes.